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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-2.6-block.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
967dd82f
FF		 20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio.h>
23#include <linux/kernel.h>
e39d14a7 24#include <linux/math.h>
75f4f7b2 25#include <linux/minmax.h>
967dd82f
FF		 26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
5e004460 29#include <linux/phylink.h>
1da6df85 30#include <linux/etherdevice.h>
ff39c2d6 31#include <linux/if_bridge.h>
680a8217 32#include <linux/if_vlan.h>
967dd82f
FF		 33#include <net/dsa.h>
34
35#include "b53_regs.h"
36#include "b53_priv.h"
37
38struct b53_mib_desc {
39 u8 size;
40 u8 offset;
41 const char *name;
42};
43
44/* BCM5365 MIB counters */
45static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78};
79
80#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
81
82/* BCM63xx MIB counters */
83static const struct b53_mib_desc b53_mibs_63xx[] = {
84 { 8, 0x00, "TxOctets" },
85 { 4, 0x08, "TxDropPkts" },
86 { 4, 0x0c, "TxQoSPkts" },
87 { 4, 0x10, "TxBroadcastPkts" },
88 { 4, 0x14, "TxMulticastPkts" },
89 { 4, 0x18, "TxUnicastPkts" },
90 { 4, 0x1c, "TxCollisions" },
91 { 4, 0x20, "TxSingleCollision" },
92 { 4, 0x24, "TxMultipleCollision" },
93 { 4, 0x28, "TxDeferredTransmit" },
94 { 4, 0x2c, "TxLateCollision" },
95 { 4, 0x30, "TxExcessiveCollision" },
96 { 4, 0x38, "TxPausePkts" },
97 { 8, 0x3c, "TxQoSOctets" },
98 { 8, 0x44, "RxOctets" },
99 { 4, 0x4c, "RxUndersizePkts" },
100 { 4, 0x50, "RxPausePkts" },
101 { 4, 0x54, "Pkts64Octets" },
102 { 4, 0x58, "Pkts65to127Octets" },
103 { 4, 0x5c, "Pkts128to255Octets" },
104 { 4, 0x60, "Pkts256to511Octets" },
105 { 4, 0x64, "Pkts512to1023Octets" },
106 { 4, 0x68, "Pkts1024to1522Octets" },
107 { 4, 0x6c, "RxOversizePkts" },
108 { 4, 0x70, "RxJabbers" },
109 { 4, 0x74, "RxAlignmentErrors" },
110 { 4, 0x78, "RxFCSErrors" },
111 { 8, 0x7c, "RxGoodOctets" },
112 { 4, 0x84, "RxDropPkts" },
113 { 4, 0x88, "RxUnicastPkts" },
114 { 4, 0x8c, "RxMulticastPkts" },
115 { 4, 0x90, "RxBroadcastPkts" },
116 { 4, 0x94, "RxSAChanges" },
117 { 4, 0x98, "RxFragments" },
118 { 4, 0xa0, "RxSymbolErrors" },
119 { 4, 0xa4, "RxQoSPkts" },
120 { 8, 0xa8, "RxQoSOctets" },
121 { 4, 0xb0, "Pkts1523to2047Octets" },
122 { 4, 0xb4, "Pkts2048to4095Octets" },
123 { 4, 0xb8, "Pkts4096to8191Octets" },
124 { 4, 0xbc, "Pkts8192to9728Octets" },
125 { 4, 0xc0, "RxDiscarded" },
126};
127
128#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
129
130/* MIB counters */
131static const struct b53_mib_desc b53_mibs[] = {
132 { 8, 0x00, "TxOctets" },
133 { 4, 0x08, "TxDropPkts" },
134 { 4, 0x10, "TxBroadcastPkts" },
135 { 4, 0x14, "TxMulticastPkts" },
136 { 4, 0x18, "TxUnicastPkts" },
137 { 4, 0x1c, "TxCollisions" },
138 { 4, 0x20, "TxSingleCollision" },
139 { 4, 0x24, "TxMultipleCollision" },
140 { 4, 0x28, "TxDeferredTransmit" },
141 { 4, 0x2c, "TxLateCollision" },
142 { 4, 0x30, "TxExcessiveCollision" },
143 { 4, 0x38, "TxPausePkts" },
144 { 8, 0x50, "RxOctets" },
145 { 4, 0x58, "RxUndersizePkts" },
146 { 4, 0x5c, "RxPausePkts" },
147 { 4, 0x60, "Pkts64Octets" },
148 { 4, 0x64, "Pkts65to127Octets" },
149 { 4, 0x68, "Pkts128to255Octets" },
150 { 4, 0x6c, "Pkts256to511Octets" },
151 { 4, 0x70, "Pkts512to1023Octets" },
152 { 4, 0x74, "Pkts1024to1522Octets" },
153 { 4, 0x78, "RxOversizePkts" },
154 { 4, 0x7c, "RxJabbers" },
155 { 4, 0x80, "RxAlignmentErrors" },
156 { 4, 0x84, "RxFCSErrors" },
157 { 8, 0x88, "RxGoodOctets" },
158 { 4, 0x90, "RxDropPkts" },
159 { 4, 0x94, "RxUnicastPkts" },
160 { 4, 0x98, "RxMulticastPkts" },
161 { 4, 0x9c, "RxBroadcastPkts" },
162 { 4, 0xa0, "RxSAChanges" },
163 { 4, 0xa4, "RxFragments" },
164 { 4, 0xa8, "RxJumboPkts" },
165 { 4, 0xac, "RxSymbolErrors" },
166 { 4, 0xc0, "RxDiscarded" },
167};
168
169#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
170
bde5d132
FF		 171static const struct b53_mib_desc b53_mibs_58xx[] = {
172 { 8, 0x00, "TxOctets" },
173 { 4, 0x08, "TxDropPkts" },
174 { 4, 0x0c, "TxQPKTQ0" },
175 { 4, 0x10, "TxBroadcastPkts" },
176 { 4, 0x14, "TxMulticastPkts" },
177 { 4, 0x18, "TxUnicastPKts" },
178 { 4, 0x1c, "TxCollisions" },
179 { 4, 0x20, "TxSingleCollision" },
180 { 4, 0x24, "TxMultipleCollision" },
181 { 4, 0x28, "TxDeferredCollision" },
182 { 4, 0x2c, "TxLateCollision" },
183 { 4, 0x30, "TxExcessiveCollision" },
184 { 4, 0x34, "TxFrameInDisc" },
185 { 4, 0x38, "TxPausePkts" },
186 { 4, 0x3c, "TxQPKTQ1" },
187 { 4, 0x40, "TxQPKTQ2" },
188 { 4, 0x44, "TxQPKTQ3" },
189 { 4, 0x48, "TxQPKTQ4" },
190 { 4, 0x4c, "TxQPKTQ5" },
191 { 8, 0x50, "RxOctets" },
192 { 4, 0x58, "RxUndersizePkts" },
193 { 4, 0x5c, "RxPausePkts" },
194 { 4, 0x60, "RxPkts64Octets" },
195 { 4, 0x64, "RxPkts65to127Octets" },
196 { 4, 0x68, "RxPkts128to255Octets" },
197 { 4, 0x6c, "RxPkts256to511Octets" },
198 { 4, 0x70, "RxPkts512to1023Octets" },
199 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
200 { 4, 0x78, "RxOversizePkts" },
201 { 4, 0x7c, "RxJabbers" },
202 { 4, 0x80, "RxAlignmentErrors" },
203 { 4, 0x84, "RxFCSErrors" },
204 { 8, 0x88, "RxGoodOctets" },
205 { 4, 0x90, "RxDropPkts" },
206 { 4, 0x94, "RxUnicastPkts" },
207 { 4, 0x98, "RxMulticastPkts" },
208 { 4, 0x9c, "RxBroadcastPkts" },
209 { 4, 0xa0, "RxSAChanges" },
210 { 4, 0xa4, "RxFragments" },
211 { 4, 0xa8, "RxJumboPkt" },
212 { 4, 0xac, "RxSymblErr" },
213 { 4, 0xb0, "InRangeErrCount" },
214 { 4, 0xb4, "OutRangeErrCount" },
215 { 4, 0xb8, "EEELpiEvent" },
216 { 4, 0xbc, "EEELpiDuration" },
217 { 4, 0xc0, "RxDiscard" },
218 { 4, 0xc8, "TxQPKTQ6" },
219 { 4, 0xcc, "TxQPKTQ7" },
220 { 4, 0xd0, "TxPkts64Octets" },
221 { 4, 0xd4, "TxPkts65to127Octets" },
222 { 4, 0xd8, "TxPkts128to255Octets" },
223 { 4, 0xdc, "TxPkts256to511Ocets" },
224 { 4, 0xe0, "TxPkts512to1023Ocets" },
225 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
226};
227
228#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
229
ca8c1f71 230#define B53_MAX_MTU_25 (1536 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
680a8217
JG		 231#define B53_MAX_MTU (9720 - ETH_HLEN - VLAN_HLEN - ETH_FCS_LEN)
232
967dd82f
FF		 233static int b53_do_vlan_op(struct b53_device *dev, u8 op)
234{
235 unsigned int i;
236
237 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
238
239 for (i = 0; i < 10; i++) {
240 u8 vta;
241
242 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
243 if (!(vta & VTA_START_CMD))
244 return 0;
245
246 usleep_range(100, 200);
247 }
248
249 return -EIO;
250}
251
a2482d2c
FF		 252static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
253 struct b53_vlan *vlan)
967dd82f
FF		 254{
255 if (is5325(dev)) {
256 u32 entry = 0;
257
a2482d2c
FF		 258 if (vlan->members) {
259 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
260 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 261 if (dev->core_rev >= 3)
262 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
263 else
264 entry |= VA_VALID_25;
265 }
266
267 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
268 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
269 VTA_RW_STATE_WR | VTA_RW_OP_EN);
270 } else if (is5365(dev)) {
271 u16 entry = 0;
272
a2482d2c
FF		 273 if (vlan->members)
274 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
275 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 276
277 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
278 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
279 VTA_RW_STATE_WR | VTA_RW_OP_EN);
280 } else {
281 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
282 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 283 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 284
285 b53_do_vlan_op(dev, VTA_CMD_WRITE);
286 }
a2482d2c
FF		 287
288 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
289 vid, vlan->members, vlan->untag);
290}
291
292static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
293 struct b53_vlan *vlan)
294{
295 if (is5325(dev)) {
296 u32 entry = 0;
297
298 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
299 VTA_RW_STATE_RD | VTA_RW_OP_EN);
300 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
301
302 if (dev->core_rev >= 3)
303 vlan->valid = !!(entry & VA_VALID_25_R4);
304 else
305 vlan->valid = !!(entry & VA_VALID_25);
306 vlan->members = entry & VA_MEMBER_MASK;
307 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
308
309 } else if (is5365(dev)) {
310 u16 entry = 0;
311
312 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
313 VTA_RW_STATE_WR | VTA_RW_OP_EN);
314 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
315
316 vlan->valid = !!(entry & VA_VALID_65);
317 vlan->members = entry & VA_MEMBER_MASK;
318 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
319 } else {
320 u32 entry = 0;
321
322 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
323 b53_do_vlan_op(dev, VTA_CMD_READ);
324 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
325 vlan->members = entry & VTE_MEMBERS;
326 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
327 vlan->valid = true;
328 }
967dd82f
FF		 329}
330
4227ea91
JG		 331static void b53_set_eap_mode(struct b53_device *dev, int port, int mode)
332{
333 u64 eap_conf;
334
335 if (is5325(dev) || is5365(dev) || dev->chip_id == BCM5389_DEVICE_ID)
336 return;
337
338 b53_read64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), &eap_conf);
339
340 if (is63xx(dev)) {
341 eap_conf &= ~EAP_MODE_MASK_63XX;
342 eap_conf |= (u64)mode << EAP_MODE_SHIFT_63XX;
343 } else {
344 eap_conf &= ~EAP_MODE_MASK;
345 eap_conf |= (u64)mode << EAP_MODE_SHIFT;
346 }
347
348 b53_write64(dev, B53_EAP_PAGE, B53_PORT_EAP_CONF(port), eap_conf);
349}
350
a2482d2c 351static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 352{
353 u8 mgmt;
354
355 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
356
357 if (enable)
358 mgmt |= SM_SW_FWD_EN;
359 else
360 mgmt &= ~SM_SW_FWD_EN;
361
362 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de 363
7edc58d6 364 /* Include IMP port in dumb forwarding mode
a424f0de 365 */
7edc58d6
FF		 366 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
367 mgmt |= B53_MII_DUMB_FWDG_EN;
368 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
53568438
FF		 369
370 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
371 * frames should be flooded or not.
372 */
373 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
63cc54a6 374 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
53568438 375 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
967dd82f
FF		 376}
377
ee47ed08 378static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
dad8d7c6 379 bool enable_filtering)
967dd82f
FF		 380{
381 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
382
383 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
384 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
385 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
386
387 if (is5325(dev) || is5365(dev)) {
388 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
389 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
390 } else if (is63xx(dev)) {
391 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
392 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
393 } else {
394 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
395 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
396 }
397
5f93185a
JG		 398 vc1 &= ~VC1_RX_MCST_FWD_EN;
399
967dd82f
FF		 400 if (enable) {
401 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
5f93185a 402 vc1 |= VC1_RX_MCST_UNTAG_EN;
967dd82f 403 vc4 &= ~VC4_ING_VID_CHECK_MASK;
dad8d7c6
FF		 404 if (enable_filtering) {
405 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
406 vc5 |= VC5_DROP_VTABLE_MISS;
407 } else {
9f34ad89 408 vc4 |= VC4_NO_ING_VID_CHK << VC4_ING_VID_CHECK_S;
dad8d7c6
FF		 409 vc5 &= ~VC5_DROP_VTABLE_MISS;
410 }
967dd82f
FF		 411
412 if (is5325(dev))
413 vc0 &= ~VC0_RESERVED_1;
414
415 if (is5325(dev) || is5365(dev))
416 vc1 |= VC1_RX_MCST_TAG_EN;
417
967dd82f
FF		 418 } else {
419 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
5f93185a 420 vc1 &= ~VC1_RX_MCST_UNTAG_EN;
967dd82f
FF		 421 vc4 &= ~VC4_ING_VID_CHECK_MASK;
422 vc5 &= ~VC5_DROP_VTABLE_MISS;
423
424 if (is5325(dev) || is5365(dev))
425 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
426 else
427 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
428
429 if (is5325(dev) || is5365(dev))
430 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 431 }
432
a2482d2c
FF		 433 if (!is5325(dev) && !is5365(dev))
434 vc5 &= ~VC5_VID_FFF_EN;
435
967dd82f
FF		 436 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
437 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
438
439 if (is5325(dev) || is5365(dev)) {
440 /* enable the high 8 bit vid check on 5325 */
441 if (is5325(dev) && enable)
442 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
443 VC3_HIGH_8BIT_EN);
444 else
445 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
446
447 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
448 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
449 } else if (is63xx(dev)) {
450 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
451 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
452 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
453 } else {
454 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
455 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
456 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
457 }
458
459 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
dad8d7c6
FF		 460
461 dev->vlan_enabled = enable;
ee47ed08
FF		 462
463 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
464 port, enable, enable_filtering);
967dd82f
FF		 465}
466
467static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
468{
469 u32 port_mask = 0;
470 u16 max_size = JMS_MIN_SIZE;
471
472 if (is5325(dev) || is5365(dev))
473 return -EINVAL;
474
475 if (enable) {
476 port_mask = dev->enabled_ports;
477 max_size = JMS_MAX_SIZE;
478 if (allow_10_100)
479 port_mask |= JPM_10_100_JUMBO_EN;
480 }
481
482 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
483 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
484}
485
ff39c2d6 486static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 487{
488 unsigned int i;
489
490 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 491 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 492
493 for (i = 0; i < 10; i++) {
494 u8 fast_age_ctrl;
495
496 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
497 &fast_age_ctrl);
498
499 if (!(fast_age_ctrl & FAST_AGE_DONE))
500 goto out;
501
502 msleep(1);
503 }
504
505 return -ETIMEDOUT;
506out:
507 /* Only age dynamic entries (default behavior) */
508 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
509 return 0;
510}
511
ff39c2d6
FF		 512static int b53_fast_age_port(struct b53_device *dev, int port)
513{
514 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
515
516 return b53_flush_arl(dev, FAST_AGE_PORT);
517}
518
a2482d2c
FF		 519static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
520{
521 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
522
523 return b53_flush_arl(dev, FAST_AGE_VLAN);
524}
525
aac02867 526void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 527{
04bed143 528 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 529 unsigned int i;
530 u16 pvlan;
531
532 /* Enable the IMP port to be in the same VLAN as the other ports
533 * on a per-port basis such that we only have Port i and IMP in
534 * the same VLAN.
535 */
536 b53_for_each_port(dev, i) {
537 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
538 pvlan |= BIT(cpu_port);
539 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
540 }
541}
aac02867 542EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 543
a8b659e7
VO		 544static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
545 bool unicast)
546{
547 u16 uc;
548
549 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
550 if (unicast)
551 uc |= BIT(port);
552 else
553 uc &= ~BIT(port);
554 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
555}
556
557static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
558 bool multicast)
559{
560 u16 mc;
561
562 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
563 if (multicast)
564 mc |= BIT(port);
565 else
566 mc &= ~BIT(port);
567 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
568
569 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
570 if (multicast)
571 mc |= BIT(port);
572 else
573 mc &= ~BIT(port);
574 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
575}
576
f9b3827e
FF		 577static void b53_port_set_learning(struct b53_device *dev, int port,
578 bool learning)
579{
580 u16 reg;
581
582 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, &reg);
583 if (learning)
584 reg &= ~BIT(port);
585 else
586 reg |= BIT(port);
587 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
588}
589
a2e52064
VO		 590static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
591{
592 struct b53_device *dev = ds->priv;
593 u16 reg;
594
595 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
596 if (enable)
597 reg |= BIT(port);
598 else
599 reg &= ~BIT(port);
600 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
601}
602
2e7179c6
JG		 603int b53_setup_port(struct dsa_switch *ds, int port)
604{
605 struct b53_device *dev = ds->priv;
606
607 b53_port_set_ucast_flood(dev, port, true);
608 b53_port_set_mcast_flood(dev, port, true);
609 b53_port_set_learning(dev, port, false);
610
4227ea91
JG		 611 /* Force all traffic to go to the CPU port to prevent the ASIC from
612 * trying to forward to bridged ports on matching FDB entries, then
613 * dropping frames because it isn't allowed to forward there.
614 */
615 if (dsa_is_user_port(ds, port))
616 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
617
2e7179c6
JG		 618 return 0;
619}
620EXPORT_SYMBOL(b53_setup_port);
621
f86ad77f 622int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 623{
04bed143 624 struct b53_device *dev = ds->priv;
74be4bab 625 unsigned int cpu_port;
8ca7c160 626 int ret = 0;
ff39c2d6 627 u16 pvlan;
967dd82f 628
74be4bab
VD		 629 if (!dsa_is_user_port(ds, port))
630 return 0;
631
68bb8ea8 632 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
74be4bab 633
8ca7c160
FF		 634 if (dev->ops->irq_enable)
635 ret = dev->ops->irq_enable(dev, port);
636 if (ret)
637 return ret;
638
967dd82f
FF		 639 /* Clear the Rx and Tx disable bits and set to no spanning tree */
640 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
641
ff39c2d6
FF		 642 /* Set this port, and only this one to be in the default VLAN,
643 * if member of a bridge, restore its membership prior to
644 * bringing down this port.
645 */
646 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
647 pvlan &= ~0x1ff;
648 pvlan |= BIT(port);
649 pvlan |= dev->ports[port].vlan_ctl_mask;
650 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
651
652 b53_imp_vlan_setup(ds, cpu_port);
653
f43a2dbe
FF		 654 /* If EEE was enabled, restore it */
655 if (dev->ports[port].eee.eee_enabled)
656 b53_eee_enable_set(ds, port, true);
657
967dd82f
FF		 658 return 0;
659}
f86ad77f 660EXPORT_SYMBOL(b53_enable_port);
967dd82f 661
75104db0 662void b53_disable_port(struct dsa_switch *ds, int port)
967dd82f 663{
04bed143 664 struct b53_device *dev = ds->priv;
967dd82f
FF		 665 u8 reg;
666
667 /* Disable Tx/Rx for the port */
668 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
669 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
670 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
8ca7c160
FF		 671
672 if (dev->ops->irq_disable)
673 dev->ops->irq_disable(dev, port);
967dd82f 674}
f86ad77f 675EXPORT_SYMBOL(b53_disable_port);
967dd82f 676
b409a9ef
FF		 677void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
678{
679 struct b53_device *dev = ds->priv;
4d776482 680 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
b409a9ef
FF		 681 u8 hdr_ctl, val;
682 u16 reg;
683
684 /* Resolve which bit controls the Broadcom tag */
685 switch (port) {
686 case 8:
687 val = BRCM_HDR_P8_EN;
688 break;
689 case 7:
690 val = BRCM_HDR_P7_EN;
691 break;
692 case 5:
693 val = BRCM_HDR_P5_EN;
694 break;
695 default:
696 val = 0;
697 break;
698 }
699
8fab459e
FF		 700 /* Enable management mode if tagging is requested */
701 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
702 if (tag_en)
703 hdr_ctl |= SM_SW_FWD_MODE;
704 else
705 hdr_ctl &= ~SM_SW_FWD_MODE;
706 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
707
708 /* Configure the appropriate IMP port */
709 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
710 if (port == 8)
711 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
712 else if (port == 5)
713 hdr_ctl |= GC_FRM_MGMT_PORT_M;
714 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
715
b409a9ef
FF		 716 /* Enable Broadcom tags for IMP port */
717 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 718 if (tag_en)
719 hdr_ctl |= val;
720 else
721 hdr_ctl &= ~val;
b409a9ef
FF		 722 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
723
724 /* Registers below are only accessible on newer devices */
725 if (!is58xx(dev))
726 return;
727
728 /* Enable reception Broadcom tag for CPU TX (switch RX) to
729 * allow us to tag outgoing frames
730 */
731 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 732 if (tag_en)
733 reg &= ~BIT(port);
734 else
735 reg |= BIT(port);
b409a9ef
FF		 736 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
737
738 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
739 * allow delivering frames to the per-port net_devices
740 */
741 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 742 if (tag_en)
743 reg &= ~BIT(port);
744 else
745 reg |= BIT(port);
b409a9ef
FF		 746 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
747}
748EXPORT_SYMBOL(b53_brcm_hdr_setup);
749
299752a7 750static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 751{
967dd82f
FF		 752 u8 port_ctrl;
753
754 /* BCM5325 CPU port is at 8 */
299752a7
FF		 755 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
756 port = B53_CPU_PORT;
967dd82f
FF		 757
758 port_ctrl = PORT_CTRL_RX_BCST_EN |
759 PORT_CTRL_RX_MCST_EN |
760 PORT_CTRL_RX_UCST_EN;
299752a7 761 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
7edc58d6
FF		 762
763 b53_brcm_hdr_setup(dev->ds, port);
967dd82f
FF		 764}
765
766static void b53_enable_mib(struct b53_device *dev)
767{
768 u8 gc;
769
770 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
771 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
772 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
773}
774
36355ddf
JG		 775static void b53_enable_stp(struct b53_device *dev)
776{
777 u8 gc;
778
779 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
780 gc |= GC_RX_BPDU_EN;
781 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
782}
783
fea83353
FF		 784static u16 b53_default_pvid(struct b53_device *dev)
785{
786 if (is5325(dev) || is5365(dev))
787 return 1;
788 else
789 return 0;
790}
791
64a81b24
FF		 792static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
793{
794 struct b53_device *dev = ds->priv;
795
796 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
797}
798
2dc2bd57
JG		 799static bool b53_vlan_port_may_join_untagged(struct dsa_switch *ds, int port)
800{
801 struct b53_device *dev = ds->priv;
802 struct dsa_port *dp;
803
804 if (!dev->vlan_filtering)
805 return true;
806
807 dp = dsa_to_port(ds, port);
808
809 if (dsa_port_is_cpu(dp))
810 return true;
811
812 return dp->bridge == NULL;
813}
814
5c1a6eaf 815int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 816{
5c1a6eaf 817 struct b53_device *dev = ds->priv;
a2482d2c 818 struct b53_vlan vl = { 0 };
d7a0b1f7 819 struct b53_vlan *v;
fea83353 820 int i, def_vid;
d7a0b1f7 821 u16 vid;
fea83353
FF		 822
823 def_vid = b53_default_pvid(dev);
967dd82f
FF		 824
825 /* clear all vlan entries */
826 if (is5325(dev) || is5365(dev)) {
fea83353 827 for (i = def_vid; i < dev->num_vlans; i++)
a2482d2c 828 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 829 } else {
830 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
831 }
832
2dc2bd57 833 b53_enable_vlan(dev, -1, dev->vlan_enabled, dev->vlan_filtering);
967dd82f 834
64a81b24
FF		 835 /* Create an untagged VLAN entry for the default PVID in case
836 * CONFIG_VLAN_8021Q is disabled and there are no calls to
6ca80638 837 * dsa_user_vlan_rx_add_vid() to create the default VLAN
64a81b24
FF		 838 * entry. Do this only when the tagging protocol is not
839 * DSA_TAG_PROTO_NONE
840 */
2dc2bd57 841 v = &dev->vlans[def_vid];
64a81b24 842 b53_for_each_port(dev, i) {
2dc2bd57
JG		 843 if (!b53_vlan_port_may_join_untagged(ds, i))
844 continue;
845
846 vl.members |= BIT(i);
64a81b24 847 if (!b53_vlan_port_needs_forced_tagged(ds, i))
2dc2bd57
JG		 848 vl.untag = vl.members;
849 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(i),
850 def_vid);
64a81b24 851 }
2dc2bd57 852 b53_set_vlan_entry(dev, def_vid, &vl);
967dd82f 853
2dc2bd57
JG		 854 if (dev->vlan_filtering) {
855 /* Upon initial call we have not set-up any VLANs, but upon
856 * system resume, we need to restore all VLAN entries.
857 */
858 for (vid = def_vid + 1; vid < dev->num_vlans; vid++) {
859 v = &dev->vlans[vid];
d7a0b1f7 860
2dc2bd57
JG		 861 if (!v->members)
862 continue;
863
864 b53_set_vlan_entry(dev, vid, v);
865 b53_fast_age_vlan(dev, vid);
866 }
d7a0b1f7 867
2dc2bd57
JG		 868 b53_for_each_port(dev, i) {
869 if (!dsa_is_cpu_port(ds, i))
870 b53_write16(dev, B53_VLAN_PAGE,
871 B53_VLAN_PORT_DEF_TAG(i),
872 dev->ports[i].pvid);
873 }
d7a0b1f7
FF		 874 }
875
967dd82f
FF		 876 return 0;
877}
5c1a6eaf 878EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 879
880static void b53_switch_reset_gpio(struct b53_device *dev)
881{
882 int gpio = dev->reset_gpio;
883
884 if (gpio < 0)
885 return;
886
887 /* Reset sequence: RESET low(50ms)->high(20ms)
888 */
889 gpio_set_value(gpio, 0);
890 mdelay(50);
891
892 gpio_set_value(gpio, 1);
893 mdelay(20);
894
895 dev->current_page = 0xff;
896}
897
898static int b53_switch_reset(struct b53_device *dev)
899{
3fb22b05
FF		 900 unsigned int timeout = 1000;
901 u8 mgmt, reg;
967dd82f
FF		 902
903 b53_switch_reset_gpio(dev);
904
905 if (is539x(dev)) {
906 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
907 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
908 }
909
3fb22b05
FF		 910 /* This is specific to 58xx devices here, do not use is58xx() which
911 * covers the larger Starfigther 2 family, including 7445/7278 which
912 * still use this driver as a library and need to perform the reset
913 * earlier.
914 */
5040cc99
AP		 915 if (dev->chip_id == BCM58XX_DEVICE_ID ||
916 dev->chip_id == BCM583XX_DEVICE_ID) {
3fb22b05
FF		 917 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
918 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
919 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
920
921 do {
922 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
923 if (!(reg & SW_RST))
924 break;
925
926 usleep_range(1000, 2000);
927 } while (timeout-- > 0);
928
434d2312
PB		 929 if (timeout == 0) {
930 dev_err(dev->dev,
931 "Timeout waiting for SW_RST to clear!\n");
3fb22b05 932 return -ETIMEDOUT;
434d2312 933 }
3fb22b05
FF		 934 }
935
967dd82f
FF		 936 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
937
938 if (!(mgmt & SM_SW_FWD_EN)) {
939 mgmt &= ~SM_SW_FWD_MODE;
940 mgmt |= SM_SW_FWD_EN;
941
942 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
943 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
944
945 if (!(mgmt & SM_SW_FWD_EN)) {
946 dev_err(dev->dev, "Failed to enable switch!\n");
947 return -EINVAL;
948 }
949 }
950
951 b53_enable_mib(dev);
36355ddf 952 b53_enable_stp(dev);
967dd82f 953
ff39c2d6 954 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 955}
956
957static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
958{
04bed143 959 struct b53_device *priv = ds->priv;
967dd82f
FF		 960 u16 value = 0;
961 int ret;
962
963 if (priv->ops->phy_read16)
964 ret = priv->ops->phy_read16(priv, addr, reg, &value);
965 else
966 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
967 reg * 2, &value);
968
969 return ret ? ret : value;
970}
971
972static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
973{
04bed143 974 struct b53_device *priv = ds->priv;
967dd82f
FF		 975
976 if (priv->ops->phy_write16)
977 return priv->ops->phy_write16(priv, addr, reg, val);
978
979 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
980}
981
982static int b53_reset_switch(struct b53_device *priv)
983{
984 /* reset vlans */
a2482d2c 985 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 986 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
987
0e01491d
FF		 988 priv->serdes_lane = B53_INVALID_LANE;
989
967dd82f
FF		 990 return b53_switch_reset(priv);
991}
992
993static int b53_apply_config(struct b53_device *priv)
994{
995 /* disable switching */
996 b53_set_forwarding(priv, 0);
997
5c1a6eaf 998 b53_configure_vlan(priv->ds);
967dd82f
FF		 999
1000 /* enable switching */
1001 b53_set_forwarding(priv, 1);
1002
1003 return 0;
1004}
1005
1006static void b53_reset_mib(struct b53_device *priv)
1007{
1008 u8 gc;
1009
1010 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
1011
1012 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1013 msleep(1);
1014 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1015 msleep(1);
1016}
1017
1018static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
1019{
1020 if (is5365(dev))
1021 return b53_mibs_65;
1022 else if (is63xx(dev))
1023 return b53_mibs_63xx;
bde5d132
FF		 1024 else if (is58xx(dev))
1025 return b53_mibs_58xx;
967dd82f
FF		 1026 else
1027 return b53_mibs;
1028}
1029
1030static unsigned int b53_get_mib_size(struct b53_device *dev)
1031{
1032 if (is5365(dev))
1033 return B53_MIBS_65_SIZE;
1034 else if (is63xx(dev))
1035 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 1036 else if (is58xx(dev))
1037 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 1038 else
1039 return B53_MIBS_SIZE;
1040}
1041
c7d28c9d
FF		 1042static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
1043{
1044 /* These ports typically do not have built-in PHYs */
1045 switch (port) {
1046 case B53_CPU_PORT_25:
1047 case 7:
1048 case B53_CPU_PORT:
1049 return NULL;
1050 }
1051
6ca80638 1052 return mdiobus_get_phy(ds->user_mii_bus, port);
c7d28c9d
FF		 1053}
1054
89f09048
FF		 1055void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
1056 uint8_t *data)
967dd82f 1057{
04bed143 1058 struct b53_device *dev = ds->priv;
967dd82f
FF		 1059 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1060 unsigned int mib_size = b53_get_mib_size(dev);
c7d28c9d 1061 struct phy_device *phydev;
967dd82f
FF		 1062 unsigned int i;
1063
c7d28c9d
FF		 1064 if (stringset == ETH_SS_STATS) {
1065 for (i = 0; i < mib_size; i++)
f12b3638 1066 ethtool_puts(&data, mibs[i].name);
c7d28c9d
FF		 1067 } else if (stringset == ETH_SS_PHY_STATS) {
1068 phydev = b53_get_phy_device(ds, port);
1069 if (!phydev)
1070 return;
89f09048 1071
c7d28c9d
FF		 1072 phy_ethtool_get_strings(phydev, data);
1073 }
967dd82f 1074}
3117455d 1075EXPORT_SYMBOL(b53_get_strings);
967dd82f 1076
3117455d 1077void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 1078{
04bed143 1079 struct b53_device *dev = ds->priv;
967dd82f
FF		 1080 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1081 unsigned int mib_size = b53_get_mib_size(dev);
1082 const struct b53_mib_desc *s;
1083 unsigned int i;
1084 u64 val = 0;
1085
1086 if (is5365(dev) && port == 5)
1087 port = 8;
1088
1089 mutex_lock(&dev->stats_mutex);
1090
1091 for (i = 0; i < mib_size; i++) {
1092 s = &mibs[i];
1093
51dca8a1 1094 if (s->size == 8) {
967dd82f
FF		 1095 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1096 } else {
1097 u32 val32;
1098
1099 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1100 &val32);
1101 val = val32;
1102 }
1103 data[i] = (u64)val;
1104 }
1105
1106 mutex_unlock(&dev->stats_mutex);
1107}
3117455d 1108EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 1109
c7d28c9d
FF		 1110void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1111{
1112 struct phy_device *phydev;
1113
1114 phydev = b53_get_phy_device(ds, port);
1115 if (!phydev)
1116 return;
1117
1118 phy_ethtool_get_stats(phydev, NULL, data);
1119}
1120EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1121
89f09048 1122int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
967dd82f 1123{
04bed143 1124 struct b53_device *dev = ds->priv;
c7d28c9d 1125 struct phy_device *phydev;
967dd82f 1126
c7d28c9d
FF		 1127 if (sset == ETH_SS_STATS) {
1128 return b53_get_mib_size(dev);
1129 } else if (sset == ETH_SS_PHY_STATS) {
1130 phydev = b53_get_phy_device(ds, port);
1131 if (!phydev)
1132 return 0;
1133
1134 return phy_ethtool_get_sset_count(phydev);
1135 }
89f09048 1136
c7d28c9d 1137 return 0;
967dd82f 1138}
3117455d 1139EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 1140
4f6a5caf
FF		 1141enum b53_devlink_resource_id {
1142 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1143};
1144
1145static u64 b53_devlink_vlan_table_get(void *priv)
1146{
1147 struct b53_device *dev = priv;
1148 struct b53_vlan *vl;
1149 unsigned int i;
1150 u64 count = 0;
1151
1152 for (i = 0; i < dev->num_vlans; i++) {
1153 vl = &dev->vlans[i];
1154 if (vl->members)
1155 count++;
1156 }
1157
1158 return count;
1159}
1160
1161int b53_setup_devlink_resources(struct dsa_switch *ds)
1162{
1163 struct devlink_resource_size_params size_params;
1164 struct b53_device *dev = ds->priv;
1165 int err;
1166
1167 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1168 dev->num_vlans,
1169 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1170
1171 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1172 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1173 DEVLINK_RESOURCE_ID_PARENT_TOP,
1174 &size_params);
1175 if (err)
1176 goto out;
1177
1178 dsa_devlink_resource_occ_get_register(ds,
1179 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1180 b53_devlink_vlan_table_get, dev);
1181
1182 return 0;
1183out:
1184 dsa_devlink_resources_unregister(ds);
1185 return err;
1186}
1187EXPORT_SYMBOL(b53_setup_devlink_resources);
1188
967dd82f
FF		 1189static int b53_setup(struct dsa_switch *ds)
1190{
04bed143 1191 struct b53_device *dev = ds->priv;
2dc2bd57 1192 struct b53_vlan *vl;
967dd82f 1193 unsigned int port;
2dc2bd57 1194 u16 pvid;
967dd82f
FF		 1195 int ret;
1196
2c32a3d3
FF		 1197 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1198 * which forces the CPU port to be tagged in all VLANs.
1199 */
1200 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1201
425f11d4
JG		 1202 /* The switch does not tell us the original VLAN for untagged
1203 * packets, so keep the CPU port always tagged.
1204 */
1205 ds->untag_vlan_aware_bridge_pvid = true;
1206
e39d14a7
JG		 1207 /* Ageing time is set in seconds */
1208 ds->ageing_time_min = 1 * 1000;
1209 ds->ageing_time_max = AGE_TIME_MAX * 1000;
1210
967dd82f
FF		 1211 ret = b53_reset_switch(dev);
1212 if (ret) {
1213 dev_err(ds->dev, "failed to reset switch\n");
1214 return ret;
1215 }
1216
2dc2bd57
JG		 1217 /* setup default vlan for filtering mode */
1218 pvid = b53_default_pvid(dev);
1219 vl = &dev->vlans[pvid];
1220 b53_for_each_port(dev, port) {
1221 vl->members |= BIT(port);
1222 if (!b53_vlan_port_needs_forced_tagged(ds, port))
1223 vl->untag |= BIT(port);
1224 }
1225
967dd82f
FF		 1226 b53_reset_mib(dev);
1227
1228 ret = b53_apply_config(dev);
4f6a5caf 1229 if (ret) {
967dd82f 1230 dev_err(ds->dev, "failed to apply configuration\n");
4f6a5caf
FF		 1231 return ret;
1232 }
967dd82f 1233
75dad252 1234 /* Configure IMP/CPU port, disable all other ports. Enabled
34c8befd
FF		 1235 * ports will be configured with .port_enable
1236 */
967dd82f 1237 for (port = 0; port < dev->num_ports; port++) {
34c8befd 1238 if (dsa_is_cpu_port(ds, port))
299752a7 1239 b53_enable_cpu_port(dev, port);
75dad252 1240 else
75104db0 1241 b53_disable_port(ds, port);
967dd82f
FF		 1242 }
1243
4f6a5caf
FF		 1244 return b53_setup_devlink_resources(ds);
1245}
1246
1247static void b53_teardown(struct dsa_switch *ds)
1248{
1249 dsa_devlink_resources_unregister(ds);
967dd82f
FF		 1250}
1251
5e004460 1252static void b53_force_link(struct b53_device *dev, int port, int link)
967dd82f 1253{
5e004460 1254 u8 reg, val, off;
967dd82f
FF		 1255
1256 /* Override the port settings */
63f8428b 1257 if (port == dev->imp_port) {
967dd82f 1258 off = B53_PORT_OVERRIDE_CTRL;
5e004460 1259 val = PORT_OVERRIDE_EN;
967dd82f
FF		 1260 } else {
1261 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
5e004460 1262 val = GMII_PO_EN;
967dd82f
FF		 1263 }
1264
5e004460
FF		 1265 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1266 reg |= val;
1267 if (link)
967dd82f 1268 reg |= PORT_OVERRIDE_LINK;
5e004460
FF		 1269 else
1270 reg &= ~PORT_OVERRIDE_LINK;
1271 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1272}
1273
1274static void b53_force_port_config(struct b53_device *dev, int port,
3cad1c8b
RK		 1275 int speed, int duplex,
1276 bool tx_pause, bool rx_pause)
5e004460
FF		 1277{
1278 u8 reg, val, off;
1279
1280 /* Override the port settings */
63f8428b 1281 if (port == dev->imp_port) {
5e004460
FF		 1282 off = B53_PORT_OVERRIDE_CTRL;
1283 val = PORT_OVERRIDE_EN;
1284 } else {
1285 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1286 val = GMII_PO_EN;
1287 }
967dd82f 1288
5e004460
FF		 1289 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1290 reg |= val;
1291 if (duplex == DUPLEX_FULL)
967dd82f 1292 reg |= PORT_OVERRIDE_FULL_DUPLEX;
5e004460
FF		 1293 else
1294 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
967dd82f 1295
5e004460 1296 switch (speed) {
967dd82f
FF		 1297 case 2000:
1298 reg |= PORT_OVERRIDE_SPEED_2000M;
df561f66 1299 fallthrough;
967dd82f
FF		 1300 case SPEED_1000:
1301 reg |= PORT_OVERRIDE_SPEED_1000M;
1302 break;
1303 case SPEED_100:
1304 reg |= PORT_OVERRIDE_SPEED_100M;
1305 break;
1306 case SPEED_10:
1307 reg |= PORT_OVERRIDE_SPEED_10M;
1308 break;
1309 default:
5e004460 1310 dev_err(dev->dev, "unknown speed: %d\n", speed);
967dd82f
FF		 1311 return;
1312 }
1313
3cad1c8b 1314 if (rx_pause)
5e004460 1315 reg |= PORT_OVERRIDE_RX_FLOW;
3cad1c8b 1316 if (tx_pause)
5e004460
FF		 1317 reg |= PORT_OVERRIDE_TX_FLOW;
1318
1319 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1320}
1321
ce3bf948
ÁFR		 1322static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1323 phy_interface_t interface)
1324{
1325 struct b53_device *dev = ds->priv;
75f4f7b2 1326 u8 rgmii_ctrl = 0;
ce3bf948 1327
75f4f7b2 1328 b53_read8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), &rgmii_ctrl);
4af52355 1329 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
ce3bf948 1330
75f4f7b2
JG		 1331 if (is63268(dev))
1332 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
594c6c2e 1333
75f4f7b2 1334 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
ce3bf948 1335
75f4f7b2 1336 b53_write8(dev, B53_CTRL_PAGE, B53_RGMII_CTRL_P(port), rgmii_ctrl);
ce3bf948
ÁFR		 1337
1338 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1339 phy_modes(interface));
1340}
1341
b3d06dc3
FF		 1342static void b53_adjust_531x5_rgmii(struct dsa_switch *ds, int port,
1343 phy_interface_t interface)
1344{
1345 struct b53_device *dev = ds->priv;
1346 u8 rgmii_ctrl = 0, off;
1347
1348 if (port == dev->imp_port)
1349 off = B53_RGMII_CTRL_IMP;
1350 else
1351 off = B53_RGMII_CTRL_P(port);
1352
1353 /* Configure the port RGMII clock delay by DLL disabled and
1354 * tx_clk aligned timing (restoring to reset defaults)
1355 */
1356 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
bc1a65eb 1357 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
b3d06dc3
FF		 1358
1359 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1360 * sure that we enable the port TX clock internal delay to
1361 * account for this internal delay that is inserted, otherwise
1362 * the switch won't be able to receive correctly.
1363 *
1364 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1365 * any delay neither on transmission nor reception, so the
1366 * BCM53125 must also be configured accordingly to account for
1367 * the lack of delay and introduce
1368 *
1369 * The BCM53125 switch has its RX clock and TX clock control
1370 * swapped, hence the reason why we modify the TX clock path in
1371 * the "RGMII" case
1372 */
1373 if (interface == PHY_INTERFACE_MODE_RGMII_TXID)
1374 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1375 if (interface == PHY_INTERFACE_MODE_RGMII)
1376 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
bc1a65eb
JG		 1377
1378 if (dev->chip_id != BCM53115_DEVICE_ID)
1379 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1380
b3d06dc3
FF		 1381 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1382
1383 dev_info(ds->dev, "Configured port %d for %s\n", port,
1384 phy_modes(interface));
1385}
1386
0d18dea4
FF		 1387static void b53_adjust_5325_mii(struct dsa_switch *ds, int port)
1388{
1389 struct b53_device *dev = ds->priv;
1390 u8 reg = 0;
1391
1392 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1393 &reg);
1394
1395 /* reverse mii needs to be enabled */
1396 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1397 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1398 reg | PORT_OVERRIDE_RV_MII_25);
1399 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1400 &reg);
1401
1402 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1403 dev_err(ds->dev,
1404 "Failed to enable reverse MII mode\n");
1405 return;
1406 }
1407 }
1408}
1409
a8e8b985
FF		 1410void b53_port_event(struct dsa_switch *ds, int port)
1411{
1412 struct b53_device *dev = ds->priv;
1413 bool link;
1414 u16 sts;
1415
1416 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1417 link = !!(sts & BIT(port));
1418 dsa_port_phylink_mac_change(ds, port, link);
1419}
1420EXPORT_SYMBOL(b53_port_event);
1421
dda1c257
RKO		 1422static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1423 struct phylink_config *config)
1424{
1425 struct b53_device *dev = ds->priv;
1426
1427 /* Internal ports need GMII for PHYLIB */
1428 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1429
1430 /* These switches appear to support MII and RevMII too, but beyond
1431 * this, the code gives very few clues. FIXME: We probably need more
1432 * interface modes here.
25179f8f
RKO		 1433 *
1434 * According to b53_srab_mux_init(), ports 3..5 can support:
1435 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1436 * However, the interface mode read from the MUX configuration is
1437 * not passed back to DSA, so phylink uses NA.
1438 * DT can specify RGMII for ports 0, 1.
1439 * For MDIO, port 8 can be RGMII_TXID.
dda1c257
RKO		 1440 */
1441 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1442 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1443
5ea0d42c
JG		 1444 /* BCM63xx RGMII ports support RGMII */
1445 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
1446 phy_interface_set_rgmii(config->supported_interfaces);
1447
dda1c257
RKO		 1448 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1449 MAC_10 | MAC_100;
1450
25179f8f
RKO		 1451 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1452 * Note: the original code also exclulded Gigagbit for MII, RevMII
1453 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1454 * so will be excluded by the generic validator implementation.
1455 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1456 */
dda1c257
RKO		 1457 if (!(is5325(dev) || is5365(dev)))
1458 config->mac_capabilities |= MAC_1000;
1459
1460 /* Get the implementation specific capabilities */
1461 if (dev->ops->phylink_get_caps)
1462 dev->ops->phylink_get_caps(dev, port, config);
1463}
1464
d0a35d29 1465static struct phylink_pcs *b53_phylink_mac_select_pcs(struct phylink_config *config,
79396934 1466 phy_interface_t interface)
a8e8b985 1467{
d0a35d29
FF		 1468 struct dsa_port *dp = dsa_phylink_to_port(config);
1469 struct b53_device *dev = dp->ds->priv;
a8e8b985 1470
79396934
RKO		 1471 if (!dev->ops->phylink_mac_select_pcs)
1472 return NULL;
0e01491d 1473
d0a35d29 1474 return dev->ops->phylink_mac_select_pcs(dev, dp->index, interface);
a8e8b985 1475}
a8e8b985 1476
d0a35d29 1477static void b53_phylink_mac_config(struct phylink_config *config,
65245197
FF		 1478 unsigned int mode,
1479 const struct phylink_link_state *state)
a8e8b985 1480{
d0a35d29 1481 struct dsa_port *dp = dsa_phylink_to_port(config);
536e5b2e 1482 phy_interface_t interface = state->interface;
d0a35d29 1483 struct dsa_switch *ds = dp->ds;
536e5b2e 1484 struct b53_device *dev = ds->priv;
d0a35d29 1485 int port = dp->index;
536e5b2e 1486
75f4f7b2 1487 if (is63xx(dev) && in_range(port, B53_63XX_RGMII0, 4))
536e5b2e
FF		 1488 b53_adjust_63xx_rgmii(ds, port, interface);
1489
1490 if (mode == MLO_AN_FIXED) {
1491 if (is531x5(dev) && phy_interface_mode_is_rgmii(interface))
1492 b53_adjust_531x5_rgmii(ds, port, interface);
1493
1494 /* configure MII port if necessary */
1495 if (is5325(dev))
1496 b53_adjust_5325_mii(ds, port);
1497 }
a8e8b985 1498}
a8e8b985 1499
d0a35d29 1500static void b53_phylink_mac_link_down(struct phylink_config *config,
65245197
FF		 1501 unsigned int mode,
1502 phy_interface_t interface)
a8e8b985 1503{
d0a35d29
FF		 1504 struct dsa_port *dp = dsa_phylink_to_port(config);
1505 struct b53_device *dev = dp->ds->priv;
1506 int port = dp->index;
a8e8b985
FF		 1507
1508 if (mode == MLO_AN_PHY)
1509 return;
1510
1511 if (mode == MLO_AN_FIXED) {
1512 b53_force_link(dev, port, false);
1513 return;
1514 }
0e01491d
FF		 1515
1516 if (phy_interface_mode_is_8023z(interface) &&
1517 dev->ops->serdes_link_set)
1518 dev->ops->serdes_link_set(dev, port, mode, interface, false);
a8e8b985 1519}
65245197 1520
d0a35d29
FF		 1521static void b53_phylink_mac_link_up(struct phylink_config *config,
1522 struct phy_device *phydev,
65245197
FF		 1523 unsigned int mode,
1524 phy_interface_t interface,
65245197
FF		 1525 int speed, int duplex,
1526 bool tx_pause, bool rx_pause)
a8e8b985 1527{
d0a35d29
FF		 1528 struct dsa_port *dp = dsa_phylink_to_port(config);
1529 struct dsa_switch *ds = dp->ds;
a8e8b985 1530 struct b53_device *dev = ds->priv;
d0a35d29
FF		 1531 struct ethtool_keee *p = &dev->ports[dp->index].eee;
1532 int port = dp->index;
a8e8b985 1533
888128f3
FF		 1534 if (mode == MLO_AN_PHY) {
1535 /* Re-negotiate EEE if it was enabled already */
1536 p->eee_enabled = b53_eee_init(ds, port, phydev);
a8e8b985 1537 return;
888128f3 1538 }
a8e8b985
FF		 1539
1540 if (mode == MLO_AN_FIXED) {
93a2579e
FF		 1541 /* Force flow control on BCM5301x's CPU port */
1542 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1543 tx_pause = rx_pause = true;
1544
ab017b79
RK		 1545 b53_force_port_config(dev, port, speed, duplex,
1546 tx_pause, rx_pause);
a8e8b985
FF		 1547 b53_force_link(dev, port, true);
1548 return;
1549 }
0e01491d
FF		 1550
1551 if (phy_interface_mode_is_8023z(interface) &&
1552 dev->ops->serdes_link_set)
1553 dev->ops->serdes_link_set(dev, port, mode, interface, true);
a8e8b985 1554}
a8e8b985 1555
89153ed6
VO		 1556int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1557 struct netlink_ext_ack *extack)
a2482d2c 1558{
dad8d7c6 1559 struct b53_device *dev = ds->priv;
dad8d7c6 1560
2dc2bd57
JG		 1561 if (dev->vlan_filtering != vlan_filtering) {
1562 dev->vlan_filtering = vlan_filtering;
1563 b53_apply_config(dev);
1564 }
dad8d7c6 1565
a2482d2c
FF		 1566 return 0;
1567}
3117455d 1568EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1569
1958d581
VO		 1570static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1571 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1572{
04bed143 1573 struct b53_device *dev = ds->priv;
a2482d2c 1574
b7a9e0da 1575 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
a2482d2c
FF		 1576 return -EOPNOTSUPP;
1577
88631864
FF		 1578 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1579 * receiving VLAN tagged frames at all, we can still allow the port to
1580 * be configured for egress untagged.
1581 */
1582 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1583 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1584 return -EINVAL;
1585
0fe2f273 1586 if (vlan->vid >= dev->num_vlans)
a2482d2c
FF		 1587 return -ERANGE;
1588
2dc2bd57 1589 b53_enable_vlan(dev, port, true, dev->vlan_filtering);
a2482d2c
FF		 1590
1591 return 0;
1592}
1593
1958d581 1594int b53_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1595 const struct switchdev_obj_port_vlan *vlan,
1596 struct netlink_ext_ack *extack)
a2482d2c 1597{
04bed143 1598 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1599 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1600 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c 1601 struct b53_vlan *vl;
f4808519 1602 u16 old_pvid, new_pvid;
1958d581
VO		 1603 int err;
1604
1605 err = b53_vlan_prepare(ds, port, vlan);
1606 if (err)
1607 return err;
a2482d2c 1608
45e9d59d
JG		 1609 if (vlan->vid == 0)
1610 return 0;
1611
2dc2bd57 1612 old_pvid = dev->ports[port].pvid;
f4808519
JG		 1613 if (pvid)
1614 new_pvid = vlan->vid;
1615 else if (!pvid && vlan->vid == old_pvid)
1616 new_pvid = b53_default_pvid(dev);
1617 else
1618 new_pvid = old_pvid;
2dc2bd57 1619 dev->ports[port].pvid = new_pvid;
f4808519 1620
b7a9e0da 1621 vl = &dev->vlans[vlan->vid];
a2482d2c 1622
45e9d59d 1623 if (dsa_is_cpu_port(ds, port))
425f11d4
JG		 1624 untagged = false;
1625
b7a9e0da 1626 vl->members |= BIT(port);
2c32a3d3 1627 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
b7a9e0da
VO		 1628 vl->untag |= BIT(port);
1629 else
1630 vl->untag &= ~BIT(port);
a2482d2c 1631
2dc2bd57
JG		 1632 if (!dev->vlan_filtering)
1633 return 0;
1634
b7a9e0da
VO		 1635 b53_set_vlan_entry(dev, vlan->vid, vl);
1636 b53_fast_age_vlan(dev, vlan->vid);
a2482d2c 1637
f4808519 1638 if (!dsa_is_cpu_port(ds, port) && new_pvid != old_pvid) {
a2482d2c 1639 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
f4808519 1640 new_pvid);
083c6b28 1641 b53_fast_age_vlan(dev, old_pvid);
a2482d2c 1642 }
1958d581
VO		 1643
1644 return 0;
a2482d2c 1645}
3117455d 1646EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1647
3117455d
FF		 1648int b53_vlan_del(struct dsa_switch *ds, int port,
1649 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1650{
04bed143 1651 struct b53_device *dev = ds->priv;
a2482d2c 1652 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c 1653 struct b53_vlan *vl;
a2482d2c
FF		 1654 u16 pvid;
1655
45e9d59d
JG		 1656 if (vlan->vid == 0)
1657 return 0;
1658
2dc2bd57 1659 pvid = dev->ports[port].pvid;
a2482d2c 1660
b7a9e0da 1661 vl = &dev->vlans[vlan->vid];
a2482d2c 1662
b7a9e0da 1663 vl->members &= ~BIT(port);
a2482d2c 1664
b7a9e0da
VO		 1665 if (pvid == vlan->vid)
1666 pvid = b53_default_pvid(dev);
2dc2bd57 1667 dev->ports[port].pvid = pvid;
a2482d2c 1668
2c32a3d3 1669 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
b7a9e0da 1670 vl->untag &= ~(BIT(port));
a2482d2c 1671
2dc2bd57
JG		 1672 if (!dev->vlan_filtering)
1673 return 0;
1674
b7a9e0da
VO		 1675 b53_set_vlan_entry(dev, vlan->vid, vl);
1676 b53_fast_age_vlan(dev, vlan->vid);
a2482d2c
FF		 1677
1678 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1679 b53_fast_age_vlan(dev, pvid);
1680
1681 return 0;
1682}
3117455d 1683EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1684
f7eb4a1c 1685/* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
1da6df85
FF		 1686static int b53_arl_op_wait(struct b53_device *dev)
1687{
1688 unsigned int timeout = 10;
1689 u8 reg;
1690
1691 do {
1692 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1693 if (!(reg & ARLTBL_START_DONE))
1694 return 0;
1695
1696 usleep_range(1000, 2000);
1697 } while (timeout--);
1698
1699 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1700
1701 return -ETIMEDOUT;
1702}
1703
1704static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1705{
1706 u8 reg;
1707
1708 if (op > ARLTBL_RW)
1709 return -EINVAL;
1710
1711 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1712 reg |= ARLTBL_START_DONE;
1713 if (op)
1714 reg |= ARLTBL_RW;
1715 else
1716 reg &= ~ARLTBL_RW;
64fec949
FF		 1717 if (dev->vlan_enabled)
1718 reg &= ~ARLTBL_IVL_SVL_SELECT;
1719 else
1720 reg |= ARLTBL_IVL_SVL_SELECT;
1da6df85
FF		 1721 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1722
1723 return b53_arl_op_wait(dev);
1724}
1725
1726static int b53_arl_read(struct b53_device *dev, u64 mac,
ef2a0bd9 1727 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1da6df85 1728{
6344dbde 1729 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1da6df85
FF		 1730 unsigned int i;
1731 int ret;
1732
1733 ret = b53_arl_op_wait(dev);
1734 if (ret)
1735 return ret;
1736
673e69a6 1737 bitmap_zero(free_bins, dev->num_arl_bins);
6344dbde 1738
1da6df85 1739 /* Read the bins */
673e69a6 1740 for (i = 0; i < dev->num_arl_bins; i++) {
1da6df85
FF		 1741 u64 mac_vid;
1742 u32 fwd_entry;
1743
1744 b53_read64(dev, B53_ARLIO_PAGE,
1745 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1746 b53_read32(dev, B53_ARLIO_PAGE,
1747 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1748 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1749
6344dbde
FF		 1750 if (!(fwd_entry & ARLTBL_VALID)) {
1751 set_bit(i, free_bins);
1da6df85 1752 continue;
6344dbde 1753 }
1da6df85
FF		 1754 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1755 continue;
2e97b0cd
FF		 1756 if (dev->vlan_enabled &&
1757 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1758 continue;
1da6df85 1759 *idx = i;
6344dbde 1760 return 0;
1da6df85
FF		 1761 }
1762
673e69a6 1763 *idx = find_first_bit(free_bins, dev->num_arl_bins);
e18e5cbc 1764 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1da6df85
FF		 1765}
1766
1767static int b53_arl_op(struct b53_device *dev, int op, int port,
1768 const unsigned char *addr, u16 vid, bool is_valid)
1769{
1770 struct b53_arl_entry ent;
1771 u32 fwd_entry;
1772 u64 mac, mac_vid = 0;
1773 u8 idx = 0;
1774 int ret;
1775
1776 /* Convert the array into a 64-bit MAC */
4b92ea81 1777 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1778
1779 /* Perform a read for the given MAC and VID */
1780 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1781 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1782
1783 /* Issue a read operation for this MAC */
1784 ret = b53_arl_rw_op(dev, 1);
1785 if (ret)
1786 return ret;
1787
ef2a0bd9
FF		 1788 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1789
1da6df85
FF		 1790 /* If this is a read, just finish now */
1791 if (op)
1792 return ret;
1793
6344dbde 1794 switch (ret) {
774d977a
TR		 1795 case -ETIMEDOUT:
1796 return ret;
6344dbde
FF		 1797 case -ENOSPC:
1798 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1799 addr, vid);
1800 return is_valid ? ret : 0;
1801 case -ENOENT:
1802 /* We could not find a matching MAC, so reset to a new entry */
1803 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1804 addr, vid, idx);
1da6df85 1805 fwd_entry = 0;
6344dbde
FF		 1806 break;
1807 default:
1808 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1809 addr, vid, idx);
1810 break;
1da6df85
FF		 1811 }
1812
5d65b64a
FF		 1813 /* For multicast address, the port is a bitmask and the validity
1814 * is determined by having at least one port being still active
1815 */
1816 if (!is_multicast_ether_addr(addr)) {
1817 ent.port = port;
1818 ent.is_valid = is_valid;
1819 } else {
1820 if (is_valid)
1821 ent.port |= BIT(port);
1822 else
1823 ent.port &= ~BIT(port);
1824
1825 ent.is_valid = !!(ent.port);
1826 }
1827
1da6df85
FF		 1828 ent.vid = vid;
1829 ent.is_static = true;
5d65b64a 1830 ent.is_age = false;
1da6df85
FF		 1831 memcpy(ent.mac, addr, ETH_ALEN);
1832 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1833
1834 b53_write64(dev, B53_ARLIO_PAGE,
1835 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1836 b53_write32(dev, B53_ARLIO_PAGE,
1837 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1838
1839 return b53_arl_rw_op(dev, 0);
1840}
1841
1b6dd556 1842int b53_fdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1843 const unsigned char *addr, u16 vid,
1844 struct dsa_db db)
1da6df85 1845{
04bed143 1846 struct b53_device *priv = ds->priv;
f7eb4a1c 1847 int ret;
1da6df85
FF		 1848
1849 /* 5325 and 5365 require some more massaging, but could
1850 * be supported eventually
1851 */
1852 if (is5325(priv) || is5365(priv))
1853 return -EOPNOTSUPP;
1854
f7eb4a1c
VO		 1855 mutex_lock(&priv->arl_mutex);
1856 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1857 mutex_unlock(&priv->arl_mutex);
1858
1859 return ret;
1da6df85 1860}
3117455d 1861EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1862
3117455d 1863int b53_fdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1864 const unsigned char *addr, u16 vid,
1865 struct dsa_db db)
1da6df85 1866{
04bed143 1867 struct b53_device *priv = ds->priv;
f7eb4a1c 1868 int ret;
1da6df85 1869
f7eb4a1c
VO		 1870 mutex_lock(&priv->arl_mutex);
1871 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1872 mutex_unlock(&priv->arl_mutex);
1873
1874 return ret;
1da6df85 1875}
3117455d 1876EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1877
1878static int b53_arl_search_wait(struct b53_device *dev)
1879{
1880 unsigned int timeout = 1000;
1881 u8 reg;
1882
1883 do {
1884 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1885 if (!(reg & ARL_SRCH_STDN))
1886 return 0;
1887
1888 if (reg & ARL_SRCH_VLID)
1889 return 0;
1890
1891 usleep_range(1000, 2000);
1892 } while (timeout--);
1893
1894 return -ETIMEDOUT;
1895}
1896
1897static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1898 struct b53_arl_entry *ent)
1899{
1900 u64 mac_vid;
1901 u32 fwd_entry;
1902
1903 b53_read64(dev, B53_ARLIO_PAGE,
1904 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1905 b53_read32(dev, B53_ARLIO_PAGE,
1906 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1907 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1908}
1909
e6cbef0c 1910static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1911 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1912{
1913 if (!ent->is_valid)
1914 return 0;
1915
1916 if (port != ent->port)
1917 return 0;
1918
2bedde1a 1919 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1920}
1921
3117455d 1922int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1923 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1924{
04bed143 1925 struct b53_device *priv = ds->priv;
1da6df85
FF		 1926 struct b53_arl_entry results[2];
1927 unsigned int count = 0;
1928 int ret;
1929 u8 reg;
1930
f7eb4a1c
VO		 1931 mutex_lock(&priv->arl_mutex);
1932
1da6df85
FF		 1933 /* Start search operation */
1934 reg = ARL_SRCH_STDN;
1935 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1936
1937 do {
1938 ret = b53_arl_search_wait(priv);
1939 if (ret)
f7eb4a1c 1940 break;
1da6df85
FF		 1941
1942 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1943 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85 1944 if (ret)
f7eb4a1c 1945 break;
1da6df85 1946
673e69a6 1947 if (priv->num_arl_bins > 2) {
1da6df85 1948 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1949 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85 1950 if (ret)
f7eb4a1c 1951 break;
1da6df85
FF		 1952
1953 if (!results[0].is_valid && !results[1].is_valid)
1954 break;
1955 }
1956
cd169d79 1957 } while (count++ < b53_max_arl_entries(priv) / 2);
1da6df85 1958
f7eb4a1c
VO		 1959 mutex_unlock(&priv->arl_mutex);
1960
1da6df85
FF		 1961 return 0;
1962}
3117455d 1963EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1964
a52b2da7 1965int b53_mdb_add(struct dsa_switch *ds, int port,
c2693363
VO		 1966 const struct switchdev_obj_port_mdb *mdb,
1967 struct dsa_db db)
5d65b64a
FF		 1968{
1969 struct b53_device *priv = ds->priv;
f7eb4a1c 1970 int ret;
5d65b64a
FF		 1971
1972 /* 5325 and 5365 require some more massaging, but could
1973 * be supported eventually
1974 */
1975 if (is5325(priv) || is5365(priv))
1976 return -EOPNOTSUPP;
1977
f7eb4a1c
VO		 1978 mutex_lock(&priv->arl_mutex);
1979 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1980 mutex_unlock(&priv->arl_mutex);
1981
1982 return ret;
5d65b64a
FF		 1983}
1984EXPORT_SYMBOL(b53_mdb_add);
1985
1986int b53_mdb_del(struct dsa_switch *ds, int port,
c2693363
VO		 1987 const struct switchdev_obj_port_mdb *mdb,
1988 struct dsa_db db)
5d65b64a
FF		 1989{
1990 struct b53_device *priv = ds->priv;
1991 int ret;
1992
f7eb4a1c 1993 mutex_lock(&priv->arl_mutex);
5d65b64a 1994 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
f7eb4a1c 1995 mutex_unlock(&priv->arl_mutex);
5d65b64a
FF		 1996 if (ret)
1997 dev_err(ds->dev, "failed to delete MDB entry\n");
1998
1999 return ret;
2000}
2001EXPORT_SYMBOL(b53_mdb_del);
2002
b079922b 2003int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
06b9cce4 2004 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
ff39c2d6 2005{
04bed143 2006 struct b53_device *dev = ds->priv;
45e9d59d 2007 struct b53_vlan *vl;
68bb8ea8 2008 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
45e9d59d 2009 u16 pvlan, reg, pvid;
ff39c2d6
FF		 2010 unsigned int i;
2011
31bfc2d4
FF		 2012 /* On 7278, port 7 which connects to the ASP should only receive
2013 * traffic from matching CFP rules.
2014 */
2015 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
2016 return -EINVAL;
2017
45e9d59d
JG		 2018 pvid = b53_default_pvid(dev);
2019 vl = &dev->vlans[pvid];
2020
2dc2bd57 2021 if (dev->vlan_filtering) {
f089652b
JG		 2022 /* Make this port leave the all VLANs join since we will have
2023 * proper VLAN entries from now on
2024 */
2025 if (is58xx(dev)) {
2026 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN,
2027 &reg);
2028 reg &= ~BIT(port);
2029 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
2030 reg &= ~BIT(cpu_port);
2031 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN,
2032 reg);
2033 }
2034
45e9d59d
JG		 2035 b53_get_vlan_entry(dev, pvid, vl);
2036 vl->members &= ~BIT(port);
45e9d59d
JG		 2037 b53_set_vlan_entry(dev, pvid, vl);
2038 }
2039
ff39c2d6
FF		 2040 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
2041
2042 b53_for_each_port(dev, i) {
d3eed0e5 2043 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
ff39c2d6
FF		 2044 continue;
2045
2046 /* Add this local port to the remote port VLAN control
2047 * membership and update the remote port bitmask
2048 */
2049 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
2050 reg |= BIT(port);
2051 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
2052 dev->ports[i].vlan_ctl_mask = reg;
2053
2054 pvlan |= BIT(i);
2055 }
2056
4227ea91
JG		 2057 /* Disable redirection of unknown SA to the CPU port */
2058 b53_set_eap_mode(dev, port, EAP_MODE_BASIC);
2059
ff39c2d6
FF		 2060 /* Configure the local port VLAN control membership to include
2061 * remote ports and update the local port bitmask
2062 */
2063 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
2064 dev->ports[port].vlan_ctl_mask = pvlan;
2065
2066 return 0;
2067}
3117455d 2068EXPORT_SYMBOL(b53_br_join);
ff39c2d6 2069
d3eed0e5 2070void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
ff39c2d6 2071{
04bed143 2072 struct b53_device *dev = ds->priv;
a1c1901c 2073 struct b53_vlan *vl;
68bb8ea8 2074 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
ff39c2d6 2075 unsigned int i;
a2482d2c 2076 u16 pvlan, reg, pvid;
ff39c2d6
FF		 2077
2078 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
2079
2080 b53_for_each_port(dev, i) {
2081 /* Don't touch the remaining ports */
d3eed0e5 2082 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
ff39c2d6
FF		 2083 continue;
2084
2085 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
2086 reg &= ~BIT(port);
2087 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
2088 dev->ports[port].vlan_ctl_mask = reg;
2089
2090 /* Prevent self removal to preserve isolation */
2091 if (port != i)
2092 pvlan &= ~BIT(i);
2093 }
2094
4227ea91
JG		 2095 /* Enable redirection of unknown SA to the CPU port */
2096 b53_set_eap_mode(dev, port, EAP_MODE_SIMPLIFIED);
2097
ff39c2d6
FF		 2098 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
2099 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c 2100
fea83353 2101 pvid = b53_default_pvid(dev);
a1c1901c 2102 vl = &dev->vlans[pvid];
a2482d2c 2103
2dc2bd57 2104 if (dev->vlan_filtering) {
f089652b
JG		 2105 /* Make this port join all VLANs without VLAN entries */
2106 if (is58xx(dev)) {
2107 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
2108 reg |= BIT(port);
2109 if (!(reg & BIT(cpu_port)))
2110 reg |= BIT(cpu_port);
2111 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
2112 }
2113
45e9d59d 2114 b53_get_vlan_entry(dev, pvid, vl);
692eb9f8 2115 vl->members |= BIT(port);
45e9d59d
JG		 2116 b53_set_vlan_entry(dev, pvid, vl);
2117 }
ff39c2d6 2118}
3117455d 2119EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 2120
3117455d 2121void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 2122{
04bed143 2123 struct b53_device *dev = ds->priv;
597698f1 2124 u8 hw_state;
ff39c2d6
FF		 2125 u8 reg;
2126
ff39c2d6
FF		 2127 switch (state) {
2128 case BR_STATE_DISABLED:
2129 hw_state = PORT_CTRL_DIS_STATE;
2130 break;
2131 case BR_STATE_LISTENING:
2132 hw_state = PORT_CTRL_LISTEN_STATE;
2133 break;
2134 case BR_STATE_LEARNING:
2135 hw_state = PORT_CTRL_LEARN_STATE;
2136 break;
2137 case BR_STATE_FORWARDING:
2138 hw_state = PORT_CTRL_FWD_STATE;
2139 break;
2140 case BR_STATE_BLOCKING:
2141 hw_state = PORT_CTRL_BLOCK_STATE;
2142 break;
2143 default:
2144 dev_err(ds->dev, "invalid STP state: %d\n", state);
2145 return;
2146 }
2147
ff39c2d6
FF		 2148 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
2149 reg &= ~PORT_CTRL_STP_STATE_MASK;
2150 reg |= hw_state;
2151 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2152}
3117455d 2153EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 2154
3117455d 2155void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 2156{
2157 struct b53_device *dev = ds->priv;
2158
2159 if (b53_fast_age_port(dev, port))
2160 dev_err(ds->dev, "fast ageing failed\n");
2161}
3117455d 2162EXPORT_SYMBOL(b53_br_fast_age);
597698f1 2163
e6dd86ed
FF		 2164int b53_br_flags_pre(struct dsa_switch *ds, int port,
2165 struct switchdev_brport_flags flags,
2166 struct netlink_ext_ack *extack)
53568438 2167{
f9b3827e 2168 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
a8b659e7 2169 return -EINVAL;
63cc54a6 2170
a8b659e7
VO		 2171 return 0;
2172}
e6dd86ed 2173EXPORT_SYMBOL(b53_br_flags_pre);
53568438 2174
e6dd86ed
FF		 2175int b53_br_flags(struct dsa_switch *ds, int port,
2176 struct switchdev_brport_flags flags,
2177 struct netlink_ext_ack *extack)
a8b659e7
VO		 2178{
2179 if (flags.mask & BR_FLOOD)
2180 b53_port_set_ucast_flood(ds->priv, port,
2181 !!(flags.val & BR_FLOOD));
2182 if (flags.mask & BR_MCAST_FLOOD)
2183 b53_port_set_mcast_flood(ds->priv, port,
2184 !!(flags.val & BR_MCAST_FLOOD));
f9b3827e
FF		 2185 if (flags.mask & BR_LEARNING)
2186 b53_port_set_learning(ds->priv, port,
2187 !!(flags.val & BR_LEARNING));
53568438
FF		 2188
2189 return 0;
a8b659e7 2190}
e6dd86ed 2191EXPORT_SYMBOL(b53_br_flags);
53568438 2192
c7d28c9d 2193static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
7edc58d6 2194{
7edc58d6
FF		 2195 /* Broadcom switches will accept enabling Broadcom tags on the
2196 * following ports: 5, 7 and 8, any other port is not supported
2197 */
5ed4e3eb
FF		 2198 switch (port) {
2199 case B53_CPU_PORT_25:
2200 case 7:
2201 case B53_CPU_PORT:
2202 return true;
7edc58d6
FF		 2203 }
2204
5ed4e3eb 2205 return false;
7edc58d6
FF		 2206}
2207
8fab459e
FF		 2208static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2209 enum dsa_tag_protocol tag_protocol)
c7d28c9d
FF		 2210{
2211 bool ret = b53_possible_cpu_port(ds, port);
2212
8fab459e 2213 if (!ret) {
c7d28c9d
FF		 2214 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2215 port);
8fab459e
FF		 2216 return ret;
2217 }
2218
2219 switch (tag_protocol) {
2220 case DSA_TAG_PROTO_BRCM:
2221 case DSA_TAG_PROTO_BRCM_PREPEND:
2222 dev_warn(ds->dev,
2223 "Port %d is stacked to Broadcom tag switch\n", port);
2224 ret = false;
2225 break;
2226 default:
2227 ret = true;
2228 break;
2229 }
2230
c7d28c9d
FF		 2231 return ret;
2232}
2233
4d776482
FF		 2234enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2235 enum dsa_tag_protocol mprot)
7b314362 2236{
7edc58d6
FF		 2237 struct b53_device *dev = ds->priv;
2238
46c5176c 2239 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
4d776482
FF		 2240 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2241 goto out;
46c5176c
ÁFR		 2242 }
2243
2244 /* Older models require a different 6 byte tag */
2245 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2246 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2247 goto out;
4d776482 2248 }
11606039
FF		 2249
2250 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2251 * which requires us to use the prepended Broadcom tag type
2252 */
4d776482
FF		 2253 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2254 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2255 goto out;
2256 }
11606039 2257
4d776482
FF		 2258 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2259out:
2260 return dev->tag_protocol;
7b314362 2261}
9f66816a 2262EXPORT_SYMBOL(b53_get_tag_protocol);
7b314362 2263
ed3af5fd 2264int b53_mirror_add(struct dsa_switch *ds, int port,
0148bb50
VO		 2265 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2266 struct netlink_ext_ack *extack)
ed3af5fd
FF		 2267{
2268 struct b53_device *dev = ds->priv;
2269 u16 reg, loc;
2270
2271 if (ingress)
2272 loc = B53_IG_MIR_CTL;
2273 else
2274 loc = B53_EG_MIR_CTL;
2275
2276 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
ed3af5fd
FF		 2277 reg |= BIT(port);
2278 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2279
2280 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2281 reg &= ~CAP_PORT_MASK;
2282 reg |= mirror->to_local_port;
2283 reg |= MIRROR_EN;
2284 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2285
2286 return 0;
2287}
2288EXPORT_SYMBOL(b53_mirror_add);
2289
2290void b53_mirror_del(struct dsa_switch *ds, int port,
2291 struct dsa_mall_mirror_tc_entry *mirror)
2292{
2293 struct b53_device *dev = ds->priv;
2294 bool loc_disable = false, other_loc_disable = false;
2295 u16 reg, loc;
2296
2297 if (mirror->ingress)
2298 loc = B53_IG_MIR_CTL;
2299 else
2300 loc = B53_EG_MIR_CTL;
2301
2302 /* Update the desired ingress/egress register */
2303 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2304 reg &= ~BIT(port);
2305 if (!(reg & MIRROR_MASK))
2306 loc_disable = true;
2307 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2308
2309 /* Now look at the other one to know if we can disable mirroring
2310 * entirely
2311 */
2312 if (mirror->ingress)
2313 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2314 else
2315 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2316 if (!(reg & MIRROR_MASK))
2317 other_loc_disable = true;
2318
2319 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2320 /* Both no longer have ports, let's disable mirroring */
2321 if (loc_disable && other_loc_disable) {
2322 reg &= ~MIRROR_EN;
2323 reg &= ~mirror->to_local_port;
2324 }
2325 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2326}
2327EXPORT_SYMBOL(b53_mirror_del);
2328
22256b0a
FF		 2329/* Returns 0 if EEE was not enabled, or 1 otherwise
2330 */
2331int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2332{
2333 int ret;
2334
1237c2d4
JG		 2335 if (!b53_support_eee(ds, port))
2336 return 0;
2337
53243d41 2338 ret = phy_init_eee(phy, false);
22256b0a
FF		 2339 if (ret)
2340 return 0;
2341
2342 b53_eee_enable_set(ds, port, true);
2343
2344 return 1;
2345}
2346EXPORT_SYMBOL(b53_eee_init);
2347
c86692fc 2348bool b53_support_eee(struct dsa_switch *ds, int port)
22256b0a
FF		 2349{
2350 struct b53_device *dev = ds->priv;
22256b0a 2351
1237c2d4 2352 return !is5325(dev) && !is5365(dev) && !is63xx(dev);
c86692fc
RKO		 2353}
2354EXPORT_SYMBOL(b53_support_eee);
22256b0a 2355
d80a5233 2356int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
22256b0a
FF		 2357{
2358 struct b53_device *dev = ds->priv;
d80a5233 2359 struct ethtool_keee *p = &dev->ports[port].eee;
22256b0a 2360
22256b0a
FF		 2361 p->eee_enabled = e->eee_enabled;
2362 b53_eee_enable_set(ds, port, e->eee_enabled);
2363
2364 return 0;
2365}
2366EXPORT_SYMBOL(b53_set_mac_eee);
2367
6ae5834b
MKP		 2368static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2369{
2370 struct b53_device *dev = ds->priv;
2371 bool enable_jumbo;
2372 bool allow_10_100;
2373
2374 if (is5325(dev) || is5365(dev))
e4b294f8 2375 return 0;
6ae5834b 2376
c5118072
MW		 2377 if (!dsa_is_cpu_port(ds, port))
2378 return 0;
2379
42fb3acf 2380 enable_jumbo = (mtu > ETH_DATA_LEN);
2f3dcd0d 2381 allow_10_100 = !is63xx(dev);
6ae5834b
MKP		 2382
2383 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2384}
2385
2386static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2387{
ca8c1f71
JG		 2388 struct b53_device *dev = ds->priv;
2389
2390 if (is5325(dev) || is5365(dev))
2391 return B53_MAX_MTU_25;
2392
680a8217 2393 return B53_MAX_MTU;
6ae5834b
MKP		 2394}
2395
e39d14a7
JG		 2396int b53_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2397{
2398 struct b53_device *dev = ds->priv;
2399 u32 atc;
2400 int reg;
2401
2402 if (is63xx(dev))
2403 reg = B53_AGING_TIME_CONTROL_63XX;
2404 else
2405 reg = B53_AGING_TIME_CONTROL;
2406
2407 atc = DIV_ROUND_CLOSEST(msecs, 1000);
2408
2409 if (!is5325(dev) && !is5365(dev))
2410 atc |= AGE_CHANGE;
2411
2412 b53_write32(dev, B53_MGMT_PAGE, reg, atc);
2413
2414 return 0;
2415}
2416EXPORT_SYMBOL_GPL(b53_set_ageing_time);
2417
d0a35d29
FF		 2418static const struct phylink_mac_ops b53_phylink_mac_ops = {
2419 .mac_select_pcs = b53_phylink_mac_select_pcs,
2420 .mac_config = b53_phylink_mac_config,
2421 .mac_link_down = b53_phylink_mac_link_down,
2422 .mac_link_up = b53_phylink_mac_link_up,
2423};
2424
a82f67af 2425static const struct dsa_switch_ops b53_switch_ops = {
7b314362 2426 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 2427 .setup = b53_setup,
4f6a5caf 2428 .teardown = b53_teardown,
967dd82f
FF		 2429 .get_strings = b53_get_strings,
2430 .get_ethtool_stats = b53_get_ethtool_stats,
2431 .get_sset_count = b53_get_sset_count,
c7d28c9d 2432 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
967dd82f
FF		 2433 .phy_read = b53_phy_read16,
2434 .phy_write = b53_phy_write16,
dda1c257 2435 .phylink_get_caps = b53_phylink_get_caps,
2e7179c6 2436 .port_setup = b53_setup_port,
967dd82f
FF		 2437 .port_enable = b53_enable_port,
2438 .port_disable = b53_disable_port,
c86692fc 2439 .support_eee = b53_support_eee,
f43a2dbe 2440 .set_mac_eee = b53_set_mac_eee,
e39d14a7 2441 .set_ageing_time = b53_set_ageing_time,
ff39c2d6
FF		 2442 .port_bridge_join = b53_br_join,
2443 .port_bridge_leave = b53_br_leave,
a8b659e7
VO		 2444 .port_pre_bridge_flags = b53_br_flags_pre,
2445 .port_bridge_flags = b53_br_flags,
ff39c2d6 2446 .port_stp_state_set = b53_br_set_stp_state,
597698f1 2447 .port_fast_age = b53_br_fast_age,
a2482d2c 2448 .port_vlan_filtering = b53_vlan_filtering,
a2482d2c
FF		 2449 .port_vlan_add = b53_vlan_add,
2450 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 2451 .port_fdb_dump = b53_fdb_dump,
2452 .port_fdb_add = b53_fdb_add,
2453 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 2454 .port_mirror_add = b53_mirror_add,
2455 .port_mirror_del = b53_mirror_del,
5d65b64a
FF		 2456 .port_mdb_add = b53_mdb_add,
2457 .port_mdb_del = b53_mdb_del,
6ae5834b
MKP		 2458 .port_max_mtu = b53_get_max_mtu,
2459 .port_change_mtu = b53_change_mtu,
967dd82f
FF		 2460};
2461
2462struct b53_chip_data {
2463 u32 chip_id;
2464 const char *dev_name;
2465 u16 vlans;
2466 u16 enabled_ports;
63f8428b 2467 u8 imp_port;
967dd82f
FF		 2468 u8 cpu_port;
2469 u8 vta_regs[3];
673e69a6 2470 u8 arl_bins;
e3da4038 2471 u16 arl_buckets;
967dd82f
FF		 2472 u8 duplex_reg;
2473 u8 jumbo_pm_reg;
2474 u8 jumbo_size_reg;
2475};
2476
2477#define B53_VTA_REGS \
2478 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2479#define B53_VTA_REGS_9798 \
2480 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2481#define B53_VTA_REGS_63XX \
2482 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2483
2484static const struct b53_chip_data b53_switch_chips[] = {
2485 {
2486 .chip_id = BCM5325_DEVICE_ID,
2487 .dev_name = "BCM5325",
2488 .vlans = 16,
983d96a9 2489 .enabled_ports = 0x3f,
673e69a6 2490 .arl_bins = 2,
e3da4038 2491 .arl_buckets = 1024,
63f8428b 2492 .imp_port = 5,
967dd82f
FF		 2493 .duplex_reg = B53_DUPLEX_STAT_FE,
2494 },
2495 {
2496 .chip_id = BCM5365_DEVICE_ID,
2497 .dev_name = "BCM5365",
2498 .vlans = 256,
983d96a9 2499 .enabled_ports = 0x3f,
673e69a6 2500 .arl_bins = 2,
e3da4038 2501 .arl_buckets = 1024,
63f8428b 2502 .imp_port = 5,
967dd82f
FF		 2503 .duplex_reg = B53_DUPLEX_STAT_FE,
2504 },
a95691bc
DT		 2505 {
2506 .chip_id = BCM5389_DEVICE_ID,
2507 .dev_name = "BCM5389",
2508 .vlans = 4096,
983d96a9 2509 .enabled_ports = 0x11f,
673e69a6 2510 .arl_bins = 4,
e3da4038 2511 .arl_buckets = 1024,
63f8428b 2512 .imp_port = 8,
a95691bc
DT		 2513 .vta_regs = B53_VTA_REGS,
2514 .duplex_reg = B53_DUPLEX_STAT_GE,
2515 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2516 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2517 },
967dd82f
FF		 2518 {
2519 .chip_id = BCM5395_DEVICE_ID,
2520 .dev_name = "BCM5395",
2521 .vlans = 4096,
983d96a9 2522 .enabled_ports = 0x11f,
673e69a6 2523 .arl_bins = 4,
e3da4038 2524 .arl_buckets = 1024,
63f8428b 2525 .imp_port = 8,
967dd82f
FF		 2526 .vta_regs = B53_VTA_REGS,
2527 .duplex_reg = B53_DUPLEX_STAT_GE,
2528 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2529 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2530 },
2531 {
2532 .chip_id = BCM5397_DEVICE_ID,
2533 .dev_name = "BCM5397",
2534 .vlans = 4096,
983d96a9 2535 .enabled_ports = 0x11f,
673e69a6 2536 .arl_bins = 4,
e3da4038 2537 .arl_buckets = 1024,
63f8428b 2538 .imp_port = 8,
967dd82f
FF		 2539 .vta_regs = B53_VTA_REGS_9798,
2540 .duplex_reg = B53_DUPLEX_STAT_GE,
2541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2543 },
2544 {
2545 .chip_id = BCM5398_DEVICE_ID,
2546 .dev_name = "BCM5398",
2547 .vlans = 4096,
983d96a9 2548 .enabled_ports = 0x17f,
673e69a6 2549 .arl_bins = 4,
e3da4038 2550 .arl_buckets = 1024,
63f8428b 2551 .imp_port = 8,
967dd82f
FF		 2552 .vta_regs = B53_VTA_REGS_9798,
2553 .duplex_reg = B53_DUPLEX_STAT_GE,
2554 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2555 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2556 },
c4f873c2
TN		 2557 {
2558 .chip_id = BCM53101_DEVICE_ID,
2559 .dev_name = "BCM53101",
2560 .vlans = 4096,
2561 .enabled_ports = 0x11f,
2562 .arl_bins = 4,
2563 .arl_buckets = 512,
2564 .vta_regs = B53_VTA_REGS,
2565 .imp_port = 8,
2566 .duplex_reg = B53_DUPLEX_STAT_GE,
2567 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2568 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2569 },
967dd82f
FF		 2570 {
2571 .chip_id = BCM53115_DEVICE_ID,
2572 .dev_name = "BCM53115",
2573 .vlans = 4096,
983d96a9 2574 .enabled_ports = 0x11f,
673e69a6 2575 .arl_bins = 4,
e3da4038 2576 .arl_buckets = 1024,
967dd82f 2577 .vta_regs = B53_VTA_REGS,
63f8428b 2578 .imp_port = 8,
967dd82f
FF		 2579 .duplex_reg = B53_DUPLEX_STAT_GE,
2580 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2581 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2582 },
2583 {
2584 .chip_id = BCM53125_DEVICE_ID,
2585 .dev_name = "BCM53125",
2586 .vlans = 4096,
983d96a9 2587 .enabled_ports = 0x1ff,
673e69a6 2588 .arl_bins = 4,
e3da4038 2589 .arl_buckets = 1024,
63f8428b 2590 .imp_port = 8,
967dd82f
FF		 2591 .vta_regs = B53_VTA_REGS,
2592 .duplex_reg = B53_DUPLEX_STAT_GE,
2593 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2594 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2595 },
2596 {
2597 .chip_id = BCM53128_DEVICE_ID,
2598 .dev_name = "BCM53128",
2599 .vlans = 4096,
2600 .enabled_ports = 0x1ff,
673e69a6 2601 .arl_bins = 4,
e3da4038 2602 .arl_buckets = 1024,
63f8428b 2603 .imp_port = 8,
967dd82f
FF		 2604 .vta_regs = B53_VTA_REGS,
2605 .duplex_reg = B53_DUPLEX_STAT_GE,
2606 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2607 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2608 },
2609 {
2610 .chip_id = BCM63XX_DEVICE_ID,
2611 .dev_name = "BCM63xx",
2612 .vlans = 4096,
2613 .enabled_ports = 0, /* pdata must provide them */
673e69a6 2614 .arl_bins = 4,
e3da4038 2615 .arl_buckets = 1024,
63f8428b 2616 .imp_port = 8,
967dd82f
FF		 2617 .vta_regs = B53_VTA_REGS_63XX,
2618 .duplex_reg = B53_DUPLEX_STAT_63XX,
2619 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2620 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2621 },
260887c7
ÁFR		 2622 {
2623 .chip_id = BCM63268_DEVICE_ID,
2624 .dev_name = "BCM63268",
2625 .vlans = 4096,
2626 .enabled_ports = 0, /* pdata must provide them */
2627 .arl_bins = 4,
2628 .arl_buckets = 1024,
2629 .imp_port = 8,
2630 .vta_regs = B53_VTA_REGS_63XX,
2631 .duplex_reg = B53_DUPLEX_STAT_63XX,
2632 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2633 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2634 },
967dd82f
FF		 2635 {
2636 .chip_id = BCM53010_DEVICE_ID,
2637 .dev_name = "BCM53010",
2638 .vlans = 4096,
983d96a9 2639 .enabled_ports = 0x1bf,
673e69a6 2640 .arl_bins = 4,
e3da4038 2641 .arl_buckets = 1024,
63f8428b 2642 .imp_port = 8,
967dd82f
FF		 2643 .vta_regs = B53_VTA_REGS,
2644 .duplex_reg = B53_DUPLEX_STAT_GE,
2645 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2646 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2647 },
2648 {
2649 .chip_id = BCM53011_DEVICE_ID,
2650 .dev_name = "BCM53011",
2651 .vlans = 4096,
2652 .enabled_ports = 0x1bf,
673e69a6 2653 .arl_bins = 4,
e3da4038 2654 .arl_buckets = 1024,
63f8428b 2655 .imp_port = 8,
967dd82f
FF		 2656 .vta_regs = B53_VTA_REGS,
2657 .duplex_reg = B53_DUPLEX_STAT_GE,
2658 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2659 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2660 },
2661 {
2662 .chip_id = BCM53012_DEVICE_ID,
2663 .dev_name = "BCM53012",
2664 .vlans = 4096,
2665 .enabled_ports = 0x1bf,
673e69a6 2666 .arl_bins = 4,
e3da4038 2667 .arl_buckets = 1024,
63f8428b 2668 .imp_port = 8,
967dd82f
FF		 2669 .vta_regs = B53_VTA_REGS,
2670 .duplex_reg = B53_DUPLEX_STAT_GE,
2671 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2672 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2673 },
2674 {
2675 .chip_id = BCM53018_DEVICE_ID,
2676 .dev_name = "BCM53018",
2677 .vlans = 4096,
983d96a9 2678 .enabled_ports = 0x1bf,
673e69a6 2679 .arl_bins = 4,
e3da4038 2680 .arl_buckets = 1024,
63f8428b 2681 .imp_port = 8,
967dd82f
FF		 2682 .vta_regs = B53_VTA_REGS,
2683 .duplex_reg = B53_DUPLEX_STAT_GE,
2684 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2685 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2686 },
2687 {
2688 .chip_id = BCM53019_DEVICE_ID,
2689 .dev_name = "BCM53019",
2690 .vlans = 4096,
983d96a9 2691 .enabled_ports = 0x1bf,
673e69a6 2692 .arl_bins = 4,
e3da4038 2693 .arl_buckets = 1024,
63f8428b 2694 .imp_port = 8,
967dd82f
FF		 2695 .vta_regs = B53_VTA_REGS,
2696 .duplex_reg = B53_DUPLEX_STAT_GE,
2697 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2698 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2699 },
991a36bb
FF		 2700 {
2701 .chip_id = BCM58XX_DEVICE_ID,
2702 .dev_name = "BCM585xx/586xx/88312",
2703 .vlans = 4096,
2704 .enabled_ports = 0x1ff,
673e69a6 2705 .arl_bins = 4,
e3da4038 2706 .arl_buckets = 1024,
63f8428b 2707 .imp_port = 8,
991a36bb
FF		 2708 .vta_regs = B53_VTA_REGS,
2709 .duplex_reg = B53_DUPLEX_STAT_GE,
2710 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2711 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2712 },
5040cc99
AP		 2713 {
2714 .chip_id = BCM583XX_DEVICE_ID,
2715 .dev_name = "BCM583xx/11360",
2716 .vlans = 4096,
2717 .enabled_ports = 0x103,
673e69a6 2718 .arl_bins = 4,
e3da4038 2719 .arl_buckets = 1024,
63f8428b 2720 .imp_port = 8,
5040cc99
AP		 2721 .vta_regs = B53_VTA_REGS,
2722 .duplex_reg = B53_DUPLEX_STAT_GE,
2723 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2724 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2725 },
73b7a604
RM		 2726 /* Starfighter 2 */
2727 {
2728 .chip_id = BCM4908_DEVICE_ID,
2729 .dev_name = "BCM4908",
2730 .vlans = 4096,
2731 .enabled_ports = 0x1bf,
2732 .arl_bins = 4,
2733 .arl_buckets = 256,
63f8428b 2734 .imp_port = 8,
73b7a604
RM		 2735 .vta_regs = B53_VTA_REGS,
2736 .duplex_reg = B53_DUPLEX_STAT_GE,
2737 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2738 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2739 },
130401d9
FF		 2740 {
2741 .chip_id = BCM7445_DEVICE_ID,
2742 .dev_name = "BCM7445",
2743 .vlans = 4096,
2744 .enabled_ports = 0x1ff,
673e69a6 2745 .arl_bins = 4,
e3da4038 2746 .arl_buckets = 1024,
63f8428b 2747 .imp_port = 8,
130401d9
FF		 2748 .vta_regs = B53_VTA_REGS,
2749 .duplex_reg = B53_DUPLEX_STAT_GE,
2750 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2751 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2752 },
0fe99338
FF		 2753 {
2754 .chip_id = BCM7278_DEVICE_ID,
2755 .dev_name = "BCM7278",
2756 .vlans = 4096,
2757 .enabled_ports = 0x1ff,
673e69a6 2758 .arl_bins = 4,
e3da4038 2759 .arl_buckets = 256,
63f8428b 2760 .imp_port = 8,
0fe99338
FF		 2761 .vta_regs = B53_VTA_REGS,
2762 .duplex_reg = B53_DUPLEX_STAT_GE,
2763 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2764 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2765 },
f927e8ef
PG		 2766 {
2767 .chip_id = BCM53134_DEVICE_ID,
2768 .dev_name = "BCM53134",
2769 .vlans = 4096,
2770 .enabled_ports = 0x12f,
2771 .imp_port = 8,
2772 .cpu_port = B53_CPU_PORT,
2773 .vta_regs = B53_VTA_REGS,
2774 .arl_bins = 4,
2775 .arl_buckets = 1024,
2776 .duplex_reg = B53_DUPLEX_STAT_GE,
2777 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2778 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2779 },
967dd82f
FF		 2780};
2781
2782static int b53_switch_init(struct b53_device *dev)
2783{
967dd82f
FF		 2784 unsigned int i;
2785 int ret;
2786
2787 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2788 const struct b53_chip_data *chip = &b53_switch_chips[i];
2789
2790 if (chip->chip_id == dev->chip_id) {
2791 if (!dev->enabled_ports)
2792 dev->enabled_ports = chip->enabled_ports;
2793 dev->name = chip->dev_name;
2794 dev->duplex_reg = chip->duplex_reg;
2795 dev->vta_regs[0] = chip->vta_regs[0];
2796 dev->vta_regs[1] = chip->vta_regs[1];
2797 dev->vta_regs[2] = chip->vta_regs[2];
2798 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
63f8428b 2799 dev->imp_port = chip->imp_port;
967dd82f 2800 dev->num_vlans = chip->vlans;
673e69a6 2801 dev->num_arl_bins = chip->arl_bins;
e3da4038 2802 dev->num_arl_buckets = chip->arl_buckets;
967dd82f
FF		 2803 break;
2804 }
2805 }
2806
2807 /* check which BCM5325x version we have */
2808 if (is5325(dev)) {
2809 u8 vc4;
2810
2811 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2812
2813 /* check reserved bits */
2814 switch (vc4 & 3) {
2815 case 1:
2816 /* BCM5325E */
2817 break;
2818 case 3:
2819 /* BCM5325F - do not use port 4 */
2820 dev->enabled_ports &= ~BIT(4);
2821 break;
2822 default:
2823/* On the BCM47XX SoCs this is the supported internal switch.*/
2824#ifndef CONFIG_BCM47XX
2825 /* BCM5325M */
2826 return -EINVAL;
2827#else
2828 break;
2829#endif
2830 }
967dd82f
FF		 2831 }
2832
cdb067d3 2833 dev->num_ports = fls(dev->enabled_ports);
967dd82f 2834
d12e1c46
RM		 2835 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2836
c7d28c9d
FF		 2837 /* Include non standard CPU port built-in PHYs to be probed */
2838 if (is539x(dev) || is531x5(dev)) {
2839 for (i = 0; i < dev->num_ports; i++) {
2840 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2841 !b53_possible_cpu_port(dev->ds, i))
2842 dev->ds->phys_mii_mask |= BIT(i);
2843 }
2844 }
2845
a86854d0
KC		 2846 dev->ports = devm_kcalloc(dev->dev,
2847 dev->num_ports, sizeof(struct b53_port),
967dd82f
FF		 2848 GFP_KERNEL);
2849 if (!dev->ports)
2850 return -ENOMEM;
2851
a86854d0
KC		 2852 dev->vlans = devm_kcalloc(dev->dev,
2853 dev->num_vlans, sizeof(struct b53_vlan),
a2482d2c
FF		 2854 GFP_KERNEL);
2855 if (!dev->vlans)
2856 return -ENOMEM;
2857
967dd82f
FF		 2858 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2859 if (dev->reset_gpio >= 0) {
2860 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2861 GPIOF_OUT_INIT_HIGH, "robo_reset");
2862 if (ret)
2863 return ret;
2864 }
2865
2866 return 0;
2867}
2868
0dff88d3
JL		 2869struct b53_device *b53_switch_alloc(struct device *base,
2870 const struct b53_io_ops *ops,
967dd82f
FF		 2871 void *priv)
2872{
2873 struct dsa_switch *ds;
2874 struct b53_device *dev;
2875
7e99e347 2876 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
967dd82f
FF		 2877 if (!ds)
2878 return NULL;
2879
7e99e347 2880 ds->dev = base;
7e99e347 2881
a0c02161
VD		 2882 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2883 if (!dev)
2884 return NULL;
967dd82f
FF		 2885
2886 ds->priv = dev;
967dd82f
FF		 2887 dev->dev = base;
2888
2889 dev->ds = ds;
2890 dev->priv = priv;
2891 dev->ops = ops;
485ebd61 2892 ds->ops = &b53_switch_ops;
d0a35d29 2893 ds->phylink_mac_ops = &b53_phylink_mac_ops;
0ee2af4e 2894 dev->vlan_enabled = true;
2dc2bd57 2895 dev->vlan_filtering = false;
d45c36ba
FF		 2896 /* Let DSA handle the case were multiple bridges span the same switch
2897 * device and different VLAN awareness settings are requested, which
2898 * would be breaking filtering semantics for any of the other bridge
2899 * devices. (not hardware supported)
2900 */
2901 ds->vlan_filtering_is_global = true;
2902
967dd82f
FF		 2903 mutex_init(&dev->reg_mutex);
2904 mutex_init(&dev->stats_mutex);
f7eb4a1c 2905 mutex_init(&dev->arl_mutex);
967dd82f
FF		 2906
2907 return dev;
2908}
2909EXPORT_SYMBOL(b53_switch_alloc);
2910
2911int b53_switch_detect(struct b53_device *dev)
2912{
2913 u32 id32;
2914 u16 tmp;
2915 u8 id8;
2916 int ret;
2917
2918 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2919 if (ret)
2920 return ret;
2921
2922 switch (id8) {
2923 case 0:
2924 /* BCM5325 and BCM5365 do not have this register so reads
2925 * return 0. But the read operation did succeed, so assume this
2926 * is one of them.
2927 *
2928 * Next check if we can write to the 5325's VTA register; for
2929 * 5365 it is read only.
2930 */
2931 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2932 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2933
2934 if (tmp == 0xf)
2935 dev->chip_id = BCM5325_DEVICE_ID;
2936 else
2937 dev->chip_id = BCM5365_DEVICE_ID;
2938 break;
a95691bc 2939 case BCM5389_DEVICE_ID:
967dd82f
FF		 2940 case BCM5395_DEVICE_ID:
2941 case BCM5397_DEVICE_ID:
2942 case BCM5398_DEVICE_ID:
2943 dev->chip_id = id8;
2944 break;
2945 default:
2946 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2947 if (ret)
2948 return ret;
2949
2950 switch (id32) {
c4f873c2 2951 case BCM53101_DEVICE_ID:
967dd82f
FF		 2952 case BCM53115_DEVICE_ID:
2953 case BCM53125_DEVICE_ID:
2954 case BCM53128_DEVICE_ID:
2955 case BCM53010_DEVICE_ID:
2956 case BCM53011_DEVICE_ID:
2957 case BCM53012_DEVICE_ID:
2958 case BCM53018_DEVICE_ID:
2959 case BCM53019_DEVICE_ID:
f927e8ef 2960 case BCM53134_DEVICE_ID:
967dd82f
FF		 2961 dev->chip_id = id32;
2962 break;
2963 default:
3b33438c
PB		 2964 dev_err(dev->dev,
2965 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2966 id8, id32);
967dd82f
FF		 2967 return -ENODEV;
2968 }
2969 }
2970
2971 if (dev->chip_id == BCM5325_DEVICE_ID)
2972 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2973 &dev->core_rev);
2974 else
2975 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2976 &dev->core_rev);
2977}
2978EXPORT_SYMBOL(b53_switch_detect);
2979
2980int b53_switch_register(struct b53_device *dev)
2981{
2982 int ret;
2983
2984 if (dev->pdata) {
2985 dev->chip_id = dev->pdata->chip_id;
2986 dev->enabled_ports = dev->pdata->enabled_ports;
2987 }
2988
2989 if (!dev->chip_id && b53_switch_detect(dev))
2990 return -EINVAL;
2991
2992 ret = b53_switch_init(dev);
2993 if (ret)
2994 return ret;
2995
3b33438c
PB		 2996 dev_info(dev->dev, "found switch: %s, rev %i\n",
2997 dev->name, dev->core_rev);
967dd82f 2998
23c9ee49 2999 return dsa_register_switch(dev->ds);
967dd82f
FF		 3000}
3001EXPORT_SYMBOL(b53_switch_register);
3002
3003MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
3004MODULE_DESCRIPTION("B53 switch library");
3005MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)