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net: dsa: b53: Wire-up EEE
[linux-2.6-block.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f 327{
a424f0de 328 struct dsa_switch *ds = dev->ds;
967dd82f
FF		 329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de
FF		 339
340 /* Include IMP port in dumb forwarding mode when no tagging protocol is
341 * set
342 */
343 if (ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_NONE) {
344 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
345 mgmt |= B53_MII_DUMB_FWDG_EN;
346 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
347 }
967dd82f
FF		 348}
349
a2482d2c 350static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 351{
352 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
353
354 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
357
358 if (is5325(dev) || is5365(dev)) {
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
360 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
361 } else if (is63xx(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
364 } else {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
367 }
368
369 mgmt &= ~SM_SW_FWD_MODE;
370
371 if (enable) {
372 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
373 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
374 vc4 &= ~VC4_ING_VID_CHECK_MASK;
375 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
376 vc5 |= VC5_DROP_VTABLE_MISS;
377
378 if (is5325(dev))
379 vc0 &= ~VC0_RESERVED_1;
380
381 if (is5325(dev) || is5365(dev))
382 vc1 |= VC1_RX_MCST_TAG_EN;
383
967dd82f
FF		 384 } else {
385 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
386 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
387 vc4 &= ~VC4_ING_VID_CHECK_MASK;
388 vc5 &= ~VC5_DROP_VTABLE_MISS;
389
390 if (is5325(dev) || is5365(dev))
391 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
392 else
393 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
394
395 if (is5325(dev) || is5365(dev))
396 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 397 }
398
a2482d2c
FF		 399 if (!is5325(dev) && !is5365(dev))
400 vc5 &= ~VC5_VID_FFF_EN;
401
967dd82f
FF		 402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
403 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
404
405 if (is5325(dev) || is5365(dev)) {
406 /* enable the high 8 bit vid check on 5325 */
407 if (is5325(dev) && enable)
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
409 VC3_HIGH_8BIT_EN);
410 else
411 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
415 } else if (is63xx(dev)) {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
419 } else {
420 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
421 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
422 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
423 }
424
425 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
426}
427
428static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
429{
430 u32 port_mask = 0;
431 u16 max_size = JMS_MIN_SIZE;
432
433 if (is5325(dev) || is5365(dev))
434 return -EINVAL;
435
436 if (enable) {
437 port_mask = dev->enabled_ports;
438 max_size = JMS_MAX_SIZE;
439 if (allow_10_100)
440 port_mask |= JPM_10_100_JUMBO_EN;
441 }
442
443 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
444 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
445}
446
ff39c2d6 447static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 448{
449 unsigned int i;
450
451 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 452 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 453
454 for (i = 0; i < 10; i++) {
455 u8 fast_age_ctrl;
456
457 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
458 &fast_age_ctrl);
459
460 if (!(fast_age_ctrl & FAST_AGE_DONE))
461 goto out;
462
463 msleep(1);
464 }
465
466 return -ETIMEDOUT;
467out:
468 /* Only age dynamic entries (default behavior) */
469 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
470 return 0;
471}
472
ff39c2d6
FF		 473static int b53_fast_age_port(struct b53_device *dev, int port)
474{
475 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
476
477 return b53_flush_arl(dev, FAST_AGE_PORT);
478}
479
a2482d2c
FF		 480static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
481{
482 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
483
484 return b53_flush_arl(dev, FAST_AGE_VLAN);
485}
486
ff39c2d6
FF		 487static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
488{
04bed143 489 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 490 unsigned int i;
491 u16 pvlan;
492
493 /* Enable the IMP port to be in the same VLAN as the other ports
494 * on a per-port basis such that we only have Port i and IMP in
495 * the same VLAN.
496 */
497 b53_for_each_port(dev, i) {
498 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
499 pvlan |= BIT(cpu_port);
500 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
501 }
502}
503
967dd82f
FF		 504static int b53_enable_port(struct dsa_switch *ds, int port,
505 struct phy_device *phy)
506{
04bed143 507 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 508 unsigned int cpu_port = dev->cpu_port;
509 u16 pvlan;
967dd82f
FF		 510
511 /* Clear the Rx and Tx disable bits and set to no spanning tree */
512 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
513
ff39c2d6
FF		 514 /* Set this port, and only this one to be in the default VLAN,
515 * if member of a bridge, restore its membership prior to
516 * bringing down this port.
517 */
518 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
519 pvlan &= ~0x1ff;
520 pvlan |= BIT(port);
521 pvlan |= dev->ports[port].vlan_ctl_mask;
522 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
523
524 b53_imp_vlan_setup(ds, cpu_port);
525
f43a2dbe
FF		 526 /* If EEE was enabled, restore it */
527 if (dev->ports[port].eee.eee_enabled)
528 b53_eee_enable_set(ds, port, true);
529
967dd82f
FF		 530 return 0;
531}
532
533static void b53_disable_port(struct dsa_switch *ds, int port,
534 struct phy_device *phy)
535{
04bed143 536 struct b53_device *dev = ds->priv;
967dd82f
FF		 537 u8 reg;
538
539 /* Disable Tx/Rx for the port */
540 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
541 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
542 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
543}
544
b409a9ef
FF		 545void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
546{
547 struct b53_device *dev = ds->priv;
548 u8 hdr_ctl, val;
549 u16 reg;
550
551 /* Resolve which bit controls the Broadcom tag */
552 switch (port) {
553 case 8:
554 val = BRCM_HDR_P8_EN;
555 break;
556 case 7:
557 val = BRCM_HDR_P7_EN;
558 break;
559 case 5:
560 val = BRCM_HDR_P5_EN;
561 break;
562 default:
563 val = 0;
564 break;
565 }
566
567 /* Enable Broadcom tags for IMP port */
568 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
569 hdr_ctl |= val;
570 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
571
572 /* Registers below are only accessible on newer devices */
573 if (!is58xx(dev))
574 return;
575
576 /* Enable reception Broadcom tag for CPU TX (switch RX) to
577 * allow us to tag outgoing frames
578 */
579 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
580 reg &= ~BIT(port);
581 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
582
583 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
584 * allow delivering frames to the per-port net_devices
585 */
586 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
587 reg &= ~BIT(port);
588 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
589}
590EXPORT_SYMBOL(b53_brcm_hdr_setup);
591
299752a7 592static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 593{
967dd82f
FF		 594 u8 port_ctrl;
595
596 /* BCM5325 CPU port is at 8 */
299752a7
FF		 597 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
598 port = B53_CPU_PORT;
967dd82f
FF		 599
600 port_ctrl = PORT_CTRL_RX_BCST_EN |
601 PORT_CTRL_RX_MCST_EN |
602 PORT_CTRL_RX_UCST_EN;
299752a7 603 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
967dd82f
FF		 604}
605
606static void b53_enable_mib(struct b53_device *dev)
607{
608 u8 gc;
609
610 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
611 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
612 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
613}
614
615static int b53_configure_vlan(struct b53_device *dev)
616{
a2482d2c 617 struct b53_vlan vl = { 0 };
967dd82f
FF		 618 int i;
619
620 /* clear all vlan entries */
621 if (is5325(dev) || is5365(dev)) {
622 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 623 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 624 } else {
625 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
626 }
627
628 b53_enable_vlan(dev, false);
629
630 b53_for_each_port(dev, i)
631 b53_write16(dev, B53_VLAN_PAGE,
632 B53_VLAN_PORT_DEF_TAG(i), 1);
633
634 if (!is5325(dev) && !is5365(dev))
635 b53_set_jumbo(dev, dev->enable_jumbo, false);
636
637 return 0;
638}
639
640static void b53_switch_reset_gpio(struct b53_device *dev)
641{
642 int gpio = dev->reset_gpio;
643
644 if (gpio < 0)
645 return;
646
647 /* Reset sequence: RESET low(50ms)->high(20ms)
648 */
649 gpio_set_value(gpio, 0);
650 mdelay(50);
651
652 gpio_set_value(gpio, 1);
653 mdelay(20);
654
655 dev->current_page = 0xff;
656}
657
658static int b53_switch_reset(struct b53_device *dev)
659{
3fb22b05
FF		 660 unsigned int timeout = 1000;
661 u8 mgmt, reg;
967dd82f
FF		 662
663 b53_switch_reset_gpio(dev);
664
665 if (is539x(dev)) {
666 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
667 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
668 }
669
3fb22b05
FF		 670 /* This is specific to 58xx devices here, do not use is58xx() which
671 * covers the larger Starfigther 2 family, including 7445/7278 which
672 * still use this driver as a library and need to perform the reset
673 * earlier.
674 */
675 if (dev->chip_id == BCM58XX_DEVICE_ID) {
676 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
677 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
679
680 do {
681 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
682 if (!(reg & SW_RST))
683 break;
684
685 usleep_range(1000, 2000);
686 } while (timeout-- > 0);
687
688 if (timeout == 0)
689 return -ETIMEDOUT;
690 }
691
967dd82f
FF		 692 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
693
694 if (!(mgmt & SM_SW_FWD_EN)) {
695 mgmt &= ~SM_SW_FWD_MODE;
696 mgmt |= SM_SW_FWD_EN;
697
698 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
699 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
700
701 if (!(mgmt & SM_SW_FWD_EN)) {
702 dev_err(dev->dev, "Failed to enable switch!\n");
703 return -EINVAL;
704 }
705 }
706
707 b53_enable_mib(dev);
708
ff39c2d6 709 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 710}
711
712static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
713{
04bed143 714 struct b53_device *priv = ds->priv;
967dd82f
FF		 715 u16 value = 0;
716 int ret;
717
718 if (priv->ops->phy_read16)
719 ret = priv->ops->phy_read16(priv, addr, reg, &value);
720 else
721 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
722 reg * 2, &value);
723
724 return ret ? ret : value;
725}
726
727static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
728{
04bed143 729 struct b53_device *priv = ds->priv;
967dd82f
FF		 730
731 if (priv->ops->phy_write16)
732 return priv->ops->phy_write16(priv, addr, reg, val);
733
734 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
735}
736
737static int b53_reset_switch(struct b53_device *priv)
738{
739 /* reset vlans */
740 priv->enable_jumbo = false;
741
a2482d2c 742 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 743 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
744
745 return b53_switch_reset(priv);
746}
747
748static int b53_apply_config(struct b53_device *priv)
749{
750 /* disable switching */
751 b53_set_forwarding(priv, 0);
752
753 b53_configure_vlan(priv);
754
755 /* enable switching */
756 b53_set_forwarding(priv, 1);
757
758 return 0;
759}
760
761static void b53_reset_mib(struct b53_device *priv)
762{
763 u8 gc;
764
765 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
766
767 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
768 msleep(1);
769 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
770 msleep(1);
771}
772
773static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
774{
775 if (is5365(dev))
776 return b53_mibs_65;
777 else if (is63xx(dev))
778 return b53_mibs_63xx;
bde5d132
FF		 779 else if (is58xx(dev))
780 return b53_mibs_58xx;
967dd82f
FF		 781 else
782 return b53_mibs;
783}
784
785static unsigned int b53_get_mib_size(struct b53_device *dev)
786{
787 if (is5365(dev))
788 return B53_MIBS_65_SIZE;
789 else if (is63xx(dev))
790 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 791 else if (is58xx(dev))
792 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 793 else
794 return B53_MIBS_SIZE;
795}
796
3117455d 797void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 798{
04bed143 799 struct b53_device *dev = ds->priv;
967dd82f
FF		 800 const struct b53_mib_desc *mibs = b53_get_mib(dev);
801 unsigned int mib_size = b53_get_mib_size(dev);
802 unsigned int i;
803
804 for (i = 0; i < mib_size; i++)
805 memcpy(data + i * ETH_GSTRING_LEN,
806 mibs[i].name, ETH_GSTRING_LEN);
807}
3117455d 808EXPORT_SYMBOL(b53_get_strings);
967dd82f 809
3117455d 810void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 811{
04bed143 812 struct b53_device *dev = ds->priv;
967dd82f
FF		 813 const struct b53_mib_desc *mibs = b53_get_mib(dev);
814 unsigned int mib_size = b53_get_mib_size(dev);
815 const struct b53_mib_desc *s;
816 unsigned int i;
817 u64 val = 0;
818
819 if (is5365(dev) && port == 5)
820 port = 8;
821
822 mutex_lock(&dev->stats_mutex);
823
824 for (i = 0; i < mib_size; i++) {
825 s = &mibs[i];
826
51dca8a1 827 if (s->size == 8) {
967dd82f
FF		 828 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
829 } else {
830 u32 val32;
831
832 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
833 &val32);
834 val = val32;
835 }
836 data[i] = (u64)val;
837 }
838
839 mutex_unlock(&dev->stats_mutex);
840}
3117455d 841EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 842
3117455d 843int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 844{
04bed143 845 struct b53_device *dev = ds->priv;
967dd82f
FF		 846
847 return b53_get_mib_size(dev);
848}
3117455d 849EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 850
967dd82f
FF		 851static int b53_setup(struct dsa_switch *ds)
852{
04bed143 853 struct b53_device *dev = ds->priv;
967dd82f
FF		 854 unsigned int port;
855 int ret;
856
857 ret = b53_reset_switch(dev);
858 if (ret) {
859 dev_err(ds->dev, "failed to reset switch\n");
860 return ret;
861 }
862
863 b53_reset_mib(dev);
864
865 ret = b53_apply_config(dev);
866 if (ret)
867 dev_err(ds->dev, "failed to apply configuration\n");
868
34c8befd
FF		 869 /* Configure IMP/CPU port, disable unused ports. Enabled
870 * ports will be configured with .port_enable
871 */
967dd82f 872 for (port = 0; port < dev->num_ports; port++) {
34c8befd 873 if (dsa_is_cpu_port(ds, port))
299752a7 874 b53_enable_cpu_port(dev, port);
34c8befd 875 else if (!(BIT(port) & ds->enabled_port_mask))
967dd82f
FF		 876 b53_disable_port(ds, port, NULL);
877 }
878
879 return ret;
880}
881
882static void b53_adjust_link(struct dsa_switch *ds, int port,
883 struct phy_device *phydev)
884{
04bed143 885 struct b53_device *dev = ds->priv;
f43a2dbe 886 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 887 u8 rgmii_ctrl = 0, reg = 0, off;
888
889 if (!phy_is_pseudo_fixed_link(phydev))
890 return;
891
892 /* Override the port settings */
893 if (port == dev->cpu_port) {
894 off = B53_PORT_OVERRIDE_CTRL;
895 reg = PORT_OVERRIDE_EN;
896 } else {
897 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
898 reg = GMII_PO_EN;
899 }
900
901 /* Set the link UP */
902 if (phydev->link)
903 reg |= PORT_OVERRIDE_LINK;
904
905 if (phydev->duplex == DUPLEX_FULL)
906 reg |= PORT_OVERRIDE_FULL_DUPLEX;
907
908 switch (phydev->speed) {
909 case 2000:
910 reg |= PORT_OVERRIDE_SPEED_2000M;
911 /* fallthrough */
912 case SPEED_1000:
913 reg |= PORT_OVERRIDE_SPEED_1000M;
914 break;
915 case SPEED_100:
916 reg |= PORT_OVERRIDE_SPEED_100M;
917 break;
918 case SPEED_10:
919 reg |= PORT_OVERRIDE_SPEED_10M;
920 break;
921 default:
922 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
923 return;
924 }
925
926 /* Enable flow control on BCM5301x's CPU port */
927 if (is5301x(dev) && port == dev->cpu_port)
928 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
929
930 if (phydev->pause) {
931 if (phydev->asym_pause)
932 reg |= PORT_OVERRIDE_TX_FLOW;
933 reg |= PORT_OVERRIDE_RX_FLOW;
934 }
935
936 b53_write8(dev, B53_CTRL_PAGE, off, reg);
937
938 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
939 if (port == 8)
940 off = B53_RGMII_CTRL_IMP;
941 else
942 off = B53_RGMII_CTRL_P(port);
943
944 /* Configure the port RGMII clock delay by DLL disabled and
945 * tx_clk aligned timing (restoring to reset defaults)
946 */
947 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
948 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
949 RGMII_CTRL_TIMING_SEL);
950
951 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
952 * sure that we enable the port TX clock internal delay to
953 * account for this internal delay that is inserted, otherwise
954 * the switch won't be able to receive correctly.
955 *
956 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
957 * any delay neither on transmission nor reception, so the
958 * BCM53125 must also be configured accordingly to account for
959 * the lack of delay and introduce
960 *
961 * The BCM53125 switch has its RX clock and TX clock control
962 * swapped, hence the reason why we modify the TX clock path in
963 * the "RGMII" case
964 */
965 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
966 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
967 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
968 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
969 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
970 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
971
972 dev_info(ds->dev, "Configured port %d for %s\n", port,
973 phy_modes(phydev->interface));
974 }
975
976 /* configure MII port if necessary */
977 if (is5325(dev)) {
978 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
979 &reg);
980
981 /* reverse mii needs to be enabled */
982 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
983 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
984 reg | PORT_OVERRIDE_RV_MII_25);
985 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
986 &reg);
987
988 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
989 dev_err(ds->dev,
990 "Failed to enable reverse MII mode\n");
991 return;
992 }
993 }
994 } else if (is5301x(dev)) {
995 if (port != dev->cpu_port) {
996 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
997 u8 gmii_po;
998
999 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1000 gmii_po |= GMII_PO_LINK |
1001 GMII_PO_RX_FLOW |
1002 GMII_PO_TX_FLOW |
1003 GMII_PO_EN |
1004 GMII_PO_SPEED_2000M;
1005 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1006 }
1007 }
f43a2dbe
FF		 1008
1009 /* Re-negotiate EEE if it was enabled already */
1010 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1011}
1012
3117455d 1013int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1014{
1015 return 0;
1016}
3117455d 1017EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1018
3117455d
FF		 1019int b53_vlan_prepare(struct dsa_switch *ds, int port,
1020 const struct switchdev_obj_port_vlan *vlan,
1021 struct switchdev_trans *trans)
a2482d2c 1022{
04bed143 1023 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1024
1025 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1026 return -EOPNOTSUPP;
1027
1028 if (vlan->vid_end > dev->num_vlans)
1029 return -ERANGE;
1030
1031 b53_enable_vlan(dev, true);
1032
1033 return 0;
1034}
3117455d 1035EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1036
3117455d
FF		 1037void b53_vlan_add(struct dsa_switch *ds, int port,
1038 const struct switchdev_obj_port_vlan *vlan,
1039 struct switchdev_trans *trans)
a2482d2c 1040{
04bed143 1041 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1042 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1043 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1044 unsigned int cpu_port = dev->cpu_port;
1045 struct b53_vlan *vl;
1046 u16 vid;
1047
1048 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1049 vl = &dev->vlans[vid];
1050
1051 b53_get_vlan_entry(dev, vid, vl);
1052
1053 vl->members |= BIT(port) | BIT(cpu_port);
1054 if (untagged)
e47112d9 1055 vl->untag |= BIT(port);
a2482d2c 1056 else
e47112d9
FF		 1057 vl->untag &= ~BIT(port);
1058 vl->untag &= ~BIT(cpu_port);
a2482d2c
FF		 1059
1060 b53_set_vlan_entry(dev, vid, vl);
1061 b53_fast_age_vlan(dev, vid);
1062 }
1063
1064 if (pvid) {
1065 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1066 vlan->vid_end);
a2482d2c
FF		 1067 b53_fast_age_vlan(dev, vid);
1068 }
1069}
3117455d 1070EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1071
3117455d
FF		 1072int b53_vlan_del(struct dsa_switch *ds, int port,
1073 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1074{
04bed143 1075 struct b53_device *dev = ds->priv;
a2482d2c 1076 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1077 struct b53_vlan *vl;
1078 u16 vid;
1079 u16 pvid;
1080
1081 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1082
1083 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1084 vl = &dev->vlans[vid];
1085
1086 b53_get_vlan_entry(dev, vid, vl);
1087
1088 vl->members &= ~BIT(port);
a2482d2c
FF		 1089
1090 if (pvid == vid) {
1091 if (is5325(dev) || is5365(dev))
1092 pvid = 1;
1093 else
1094 pvid = 0;
1095 }
1096
e47112d9 1097 if (untagged)
a2482d2c 1098 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1099
1100 b53_set_vlan_entry(dev, vid, vl);
1101 b53_fast_age_vlan(dev, vid);
1102 }
1103
1104 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1105 b53_fast_age_vlan(dev, pvid);
1106
1107 return 0;
1108}
3117455d 1109EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1110
1da6df85
FF		 1111/* Address Resolution Logic routines */
1112static int b53_arl_op_wait(struct b53_device *dev)
1113{
1114 unsigned int timeout = 10;
1115 u8 reg;
1116
1117 do {
1118 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1119 if (!(reg & ARLTBL_START_DONE))
1120 return 0;
1121
1122 usleep_range(1000, 2000);
1123 } while (timeout--);
1124
1125 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1126
1127 return -ETIMEDOUT;
1128}
1129
1130static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1131{
1132 u8 reg;
1133
1134 if (op > ARLTBL_RW)
1135 return -EINVAL;
1136
1137 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1138 reg |= ARLTBL_START_DONE;
1139 if (op)
1140 reg |= ARLTBL_RW;
1141 else
1142 reg &= ~ARLTBL_RW;
1143 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1144
1145 return b53_arl_op_wait(dev);
1146}
1147
1148static int b53_arl_read(struct b53_device *dev, u64 mac,
1149 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1150 bool is_valid)
1151{
1152 unsigned int i;
1153 int ret;
1154
1155 ret = b53_arl_op_wait(dev);
1156 if (ret)
1157 return ret;
1158
1159 /* Read the bins */
1160 for (i = 0; i < dev->num_arl_entries; i++) {
1161 u64 mac_vid;
1162 u32 fwd_entry;
1163
1164 b53_read64(dev, B53_ARLIO_PAGE,
1165 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1166 b53_read32(dev, B53_ARLIO_PAGE,
1167 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1168 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1169
1170 if (!(fwd_entry & ARLTBL_VALID))
1171 continue;
1172 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1173 continue;
1174 *idx = i;
1175 }
1176
1177 return -ENOENT;
1178}
1179
1180static int b53_arl_op(struct b53_device *dev, int op, int port,
1181 const unsigned char *addr, u16 vid, bool is_valid)
1182{
1183 struct b53_arl_entry ent;
1184 u32 fwd_entry;
1185 u64 mac, mac_vid = 0;
1186 u8 idx = 0;
1187 int ret;
1188
1189 /* Convert the array into a 64-bit MAC */
4b92ea81 1190 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1191
1192 /* Perform a read for the given MAC and VID */
1193 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1194 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1195
1196 /* Issue a read operation for this MAC */
1197 ret = b53_arl_rw_op(dev, 1);
1198 if (ret)
1199 return ret;
1200
1201 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1202 /* If this is a read, just finish now */
1203 if (op)
1204 return ret;
1205
1206 /* We could not find a matching MAC, so reset to a new entry */
1207 if (ret) {
1208 fwd_entry = 0;
1209 idx = 1;
1210 }
1211
1212 memset(&ent, 0, sizeof(ent));
1213 ent.port = port;
1214 ent.is_valid = is_valid;
1215 ent.vid = vid;
1216 ent.is_static = true;
1217 memcpy(ent.mac, addr, ETH_ALEN);
1218 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1219
1220 b53_write64(dev, B53_ARLIO_PAGE,
1221 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1222 b53_write32(dev, B53_ARLIO_PAGE,
1223 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1224
1225 return b53_arl_rw_op(dev, 0);
1226}
1227
1b6dd556
AS		 1228int b53_fdb_add(struct dsa_switch *ds, int port,
1229 const unsigned char *addr, u16 vid)
1da6df85 1230{
04bed143 1231 struct b53_device *priv = ds->priv;
1da6df85
FF		 1232
1233 /* 5325 and 5365 require some more massaging, but could
1234 * be supported eventually
1235 */
1236 if (is5325(priv) || is5365(priv))
1237 return -EOPNOTSUPP;
1238
1b6dd556 1239 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1240}
3117455d 1241EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1242
3117455d 1243int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1244 const unsigned char *addr, u16 vid)
1da6df85 1245{
04bed143 1246 struct b53_device *priv = ds->priv;
1da6df85 1247
6c2c1dcb 1248 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1249}
3117455d 1250EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1251
1252static int b53_arl_search_wait(struct b53_device *dev)
1253{
1254 unsigned int timeout = 1000;
1255 u8 reg;
1256
1257 do {
1258 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1259 if (!(reg & ARL_SRCH_STDN))
1260 return 0;
1261
1262 if (reg & ARL_SRCH_VLID)
1263 return 0;
1264
1265 usleep_range(1000, 2000);
1266 } while (timeout--);
1267
1268 return -ETIMEDOUT;
1269}
1270
1271static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1272 struct b53_arl_entry *ent)
1273{
1274 u64 mac_vid;
1275 u32 fwd_entry;
1276
1277 b53_read64(dev, B53_ARLIO_PAGE,
1278 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1279 b53_read32(dev, B53_ARLIO_PAGE,
1280 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1281 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1282}
1283
e6cbef0c 1284static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1285 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1286{
1287 if (!ent->is_valid)
1288 return 0;
1289
1290 if (port != ent->port)
1291 return 0;
1292
2bedde1a 1293 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1294}
1295
3117455d 1296int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1297 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1298{
04bed143 1299 struct b53_device *priv = ds->priv;
1da6df85
FF		 1300 struct b53_arl_entry results[2];
1301 unsigned int count = 0;
1302 int ret;
1303 u8 reg;
1304
1305 /* Start search operation */
1306 reg = ARL_SRCH_STDN;
1307 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1308
1309 do {
1310 ret = b53_arl_search_wait(priv);
1311 if (ret)
1312 return ret;
1313
1314 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1315 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1316 if (ret)
1317 return ret;
1318
1319 if (priv->num_arl_entries > 2) {
1320 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1321 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1322 if (ret)
1323 return ret;
1324
1325 if (!results[0].is_valid && !results[1].is_valid)
1326 break;
1327 }
1328
1329 } while (count++ < 1024);
1330
1331 return 0;
1332}
3117455d 1333EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1334
ddd3a0c8 1335int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1336{
04bed143 1337 struct b53_device *dev = ds->priv;
8b0d3ea5 1338 s8 cpu_port = ds->dst->cpu_dp->index;
ff39c2d6
FF		 1339 u16 pvlan, reg;
1340 unsigned int i;
1341
48aea33a
FF		 1342 /* Make this port leave the all VLANs join since we will have proper
1343 * VLAN entries from now on
1344 */
1345 if (is58xx(dev)) {
1346 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1347 reg &= ~BIT(port);
1348 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1349 reg &= ~BIT(cpu_port);
1350 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1351 }
1352
ff39c2d6
FF		 1353 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1354
1355 b53_for_each_port(dev, i) {
ddd3a0c8 1356 if (ds->ports[i].bridge_dev != br)
ff39c2d6
FF		 1357 continue;
1358
1359 /* Add this local port to the remote port VLAN control
1360 * membership and update the remote port bitmask
1361 */
1362 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1363 reg |= BIT(port);
1364 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1365 dev->ports[i].vlan_ctl_mask = reg;
1366
1367 pvlan |= BIT(i);
1368 }
1369
1370 /* Configure the local port VLAN control membership to include
1371 * remote ports and update the local port bitmask
1372 */
1373 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1374 dev->ports[port].vlan_ctl_mask = pvlan;
1375
1376 return 0;
1377}
3117455d 1378EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1379
f123f2fb 1380void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1381{
04bed143 1382 struct b53_device *dev = ds->priv;
a2482d2c 1383 struct b53_vlan *vl = &dev->vlans[0];
8b0d3ea5 1384 s8 cpu_port = ds->dst->cpu_dp->index;
ff39c2d6 1385 unsigned int i;
a2482d2c 1386 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1387
1388 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1389
1390 b53_for_each_port(dev, i) {
1391 /* Don't touch the remaining ports */
ddd3a0c8 1392 if (ds->ports[i].bridge_dev != br)
ff39c2d6
FF		 1393 continue;
1394
1395 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1396 reg &= ~BIT(port);
1397 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1398 dev->ports[port].vlan_ctl_mask = reg;
1399
1400 /* Prevent self removal to preserve isolation */
1401 if (port != i)
1402 pvlan &= ~BIT(i);
1403 }
1404
1405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1406 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1407
1408 if (is5325(dev) || is5365(dev))
1409 pvid = 1;
1410 else
1411 pvid = 0;
1412
48aea33a
FF		 1413 /* Make this port join all VLANs without VLAN entries */
1414 if (is58xx(dev)) {
1415 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1416 reg |= BIT(port);
1417 if (!(reg & BIT(cpu_port)))
1418 reg |= BIT(cpu_port);
1419 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1420 } else {
1421 b53_get_vlan_entry(dev, pvid, vl);
1422 vl->members |= BIT(port) | BIT(dev->cpu_port);
1423 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1424 b53_set_vlan_entry(dev, pvid, vl);
1425 }
ff39c2d6 1426}
3117455d 1427EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1428
3117455d 1429void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1430{
04bed143 1431 struct b53_device *dev = ds->priv;
597698f1 1432 u8 hw_state;
ff39c2d6
FF		 1433 u8 reg;
1434
ff39c2d6
FF		 1435 switch (state) {
1436 case BR_STATE_DISABLED:
1437 hw_state = PORT_CTRL_DIS_STATE;
1438 break;
1439 case BR_STATE_LISTENING:
1440 hw_state = PORT_CTRL_LISTEN_STATE;
1441 break;
1442 case BR_STATE_LEARNING:
1443 hw_state = PORT_CTRL_LEARN_STATE;
1444 break;
1445 case BR_STATE_FORWARDING:
1446 hw_state = PORT_CTRL_FWD_STATE;
1447 break;
1448 case BR_STATE_BLOCKING:
1449 hw_state = PORT_CTRL_BLOCK_STATE;
1450 break;
1451 default:
1452 dev_err(ds->dev, "invalid STP state: %d\n", state);
1453 return;
1454 }
1455
ff39c2d6
FF		 1456 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1457 reg &= ~PORT_CTRL_STP_STATE_MASK;
1458 reg |= hw_state;
1459 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1460}
3117455d 1461EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1462
3117455d 1463void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1464{
1465 struct b53_device *dev = ds->priv;
1466
1467 if (b53_fast_age_port(dev, port))
1468 dev_err(ds->dev, "fast ageing failed\n");
1469}
3117455d 1470EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1471
7b314362
AL		 1472static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1473{
1474 return DSA_TAG_PROTO_NONE;
1475}
1476
ed3af5fd
FF		 1477int b53_mirror_add(struct dsa_switch *ds, int port,
1478 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1479{
1480 struct b53_device *dev = ds->priv;
1481 u16 reg, loc;
1482
1483 if (ingress)
1484 loc = B53_IG_MIR_CTL;
1485 else
1486 loc = B53_EG_MIR_CTL;
1487
1488 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1489 reg &= ~MIRROR_MASK;
1490 reg |= BIT(port);
1491 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1492
1493 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1494 reg &= ~CAP_PORT_MASK;
1495 reg |= mirror->to_local_port;
1496 reg |= MIRROR_EN;
1497 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1498
1499 return 0;
1500}
1501EXPORT_SYMBOL(b53_mirror_add);
1502
1503void b53_mirror_del(struct dsa_switch *ds, int port,
1504 struct dsa_mall_mirror_tc_entry *mirror)
1505{
1506 struct b53_device *dev = ds->priv;
1507 bool loc_disable = false, other_loc_disable = false;
1508 u16 reg, loc;
1509
1510 if (mirror->ingress)
1511 loc = B53_IG_MIR_CTL;
1512 else
1513 loc = B53_EG_MIR_CTL;
1514
1515 /* Update the desired ingress/egress register */
1516 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1517 reg &= ~BIT(port);
1518 if (!(reg & MIRROR_MASK))
1519 loc_disable = true;
1520 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1521
1522 /* Now look at the other one to know if we can disable mirroring
1523 * entirely
1524 */
1525 if (mirror->ingress)
1526 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1527 else
1528 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1529 if (!(reg & MIRROR_MASK))
1530 other_loc_disable = true;
1531
1532 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1533 /* Both no longer have ports, let's disable mirroring */
1534 if (loc_disable && other_loc_disable) {
1535 reg &= ~MIRROR_EN;
1536 reg &= ~mirror->to_local_port;
1537 }
1538 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1539}
1540EXPORT_SYMBOL(b53_mirror_del);
1541
22256b0a
FF		 1542void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1543{
1544 struct b53_device *dev = ds->priv;
1545 u16 reg;
1546
1547 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1548 if (enable)
1549 reg |= BIT(port);
1550 else
1551 reg &= ~BIT(port);
1552 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1553}
1554EXPORT_SYMBOL(b53_eee_enable_set);
1555
1556
1557/* Returns 0 if EEE was not enabled, or 1 otherwise
1558 */
1559int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1560{
1561 int ret;
1562
1563 ret = phy_init_eee(phy, 0);
1564 if (ret)
1565 return 0;
1566
1567 b53_eee_enable_set(ds, port, true);
1568
1569 return 1;
1570}
1571EXPORT_SYMBOL(b53_eee_init);
1572
1573int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1574{
1575 struct b53_device *dev = ds->priv;
1576 struct ethtool_eee *p = &dev->ports[port].eee;
1577 u16 reg;
1578
1579 if (is5325(dev) || is5365(dev))
1580 return -EOPNOTSUPP;
1581
1582 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1583 e->eee_enabled = p->eee_enabled;
1584 e->eee_active = !!(reg & BIT(port));
1585
1586 return 0;
1587}
1588EXPORT_SYMBOL(b53_get_mac_eee);
1589
1590int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1591{
1592 struct b53_device *dev = ds->priv;
1593 struct ethtool_eee *p = &dev->ports[port].eee;
1594
1595 if (is5325(dev) || is5365(dev))
1596 return -EOPNOTSUPP;
1597
1598 p->eee_enabled = e->eee_enabled;
1599 b53_eee_enable_set(ds, port, e->eee_enabled);
1600
1601 return 0;
1602}
1603EXPORT_SYMBOL(b53_set_mac_eee);
1604
a82f67af 1605static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1606 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1607 .setup = b53_setup,
967dd82f
FF		 1608 .get_strings = b53_get_strings,
1609 .get_ethtool_stats = b53_get_ethtool_stats,
1610 .get_sset_count = b53_get_sset_count,
1611 .phy_read = b53_phy_read16,
1612 .phy_write = b53_phy_write16,
1613 .adjust_link = b53_adjust_link,
1614 .port_enable = b53_enable_port,
1615 .port_disable = b53_disable_port,
f43a2dbe
FF		 1616 .get_mac_eee = b53_get_mac_eee,
1617 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1618 .port_bridge_join = b53_br_join,
1619 .port_bridge_leave = b53_br_leave,
1620 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1621 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1622 .port_vlan_filtering = b53_vlan_filtering,
1623 .port_vlan_prepare = b53_vlan_prepare,
1624 .port_vlan_add = b53_vlan_add,
1625 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1626 .port_fdb_dump = b53_fdb_dump,
1627 .port_fdb_add = b53_fdb_add,
1628 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1629 .port_mirror_add = b53_mirror_add,
1630 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1631};
1632
1633struct b53_chip_data {
1634 u32 chip_id;
1635 const char *dev_name;
1636 u16 vlans;
1637 u16 enabled_ports;
1638 u8 cpu_port;
1639 u8 vta_regs[3];
1da6df85 1640 u8 arl_entries;
967dd82f
FF		 1641 u8 duplex_reg;
1642 u8 jumbo_pm_reg;
1643 u8 jumbo_size_reg;
1644};
1645
1646#define B53_VTA_REGS \
1647 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1648#define B53_VTA_REGS_9798 \
1649 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1650#define B53_VTA_REGS_63XX \
1651 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1652
1653static const struct b53_chip_data b53_switch_chips[] = {
1654 {
1655 .chip_id = BCM5325_DEVICE_ID,
1656 .dev_name = "BCM5325",
1657 .vlans = 16,
1658 .enabled_ports = 0x1f,
1da6df85 1659 .arl_entries = 2,
967dd82f
FF		 1660 .cpu_port = B53_CPU_PORT_25,
1661 .duplex_reg = B53_DUPLEX_STAT_FE,
1662 },
1663 {
1664 .chip_id = BCM5365_DEVICE_ID,
1665 .dev_name = "BCM5365",
1666 .vlans = 256,
1667 .enabled_ports = 0x1f,
1da6df85 1668 .arl_entries = 2,
967dd82f
FF		 1669 .cpu_port = B53_CPU_PORT_25,
1670 .duplex_reg = B53_DUPLEX_STAT_FE,
1671 },
1672 {
1673 .chip_id = BCM5395_DEVICE_ID,
1674 .dev_name = "BCM5395",
1675 .vlans = 4096,
1676 .enabled_ports = 0x1f,
1da6df85 1677 .arl_entries = 4,
967dd82f
FF		 1678 .cpu_port = B53_CPU_PORT,
1679 .vta_regs = B53_VTA_REGS,
1680 .duplex_reg = B53_DUPLEX_STAT_GE,
1681 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1682 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1683 },
1684 {
1685 .chip_id = BCM5397_DEVICE_ID,
1686 .dev_name = "BCM5397",
1687 .vlans = 4096,
1688 .enabled_ports = 0x1f,
1da6df85 1689 .arl_entries = 4,
967dd82f
FF		 1690 .cpu_port = B53_CPU_PORT,
1691 .vta_regs = B53_VTA_REGS_9798,
1692 .duplex_reg = B53_DUPLEX_STAT_GE,
1693 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1694 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1695 },
1696 {
1697 .chip_id = BCM5398_DEVICE_ID,
1698 .dev_name = "BCM5398",
1699 .vlans = 4096,
1700 .enabled_ports = 0x7f,
1da6df85 1701 .arl_entries = 4,
967dd82f
FF		 1702 .cpu_port = B53_CPU_PORT,
1703 .vta_regs = B53_VTA_REGS_9798,
1704 .duplex_reg = B53_DUPLEX_STAT_GE,
1705 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1706 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1707 },
1708 {
1709 .chip_id = BCM53115_DEVICE_ID,
1710 .dev_name = "BCM53115",
1711 .vlans = 4096,
1712 .enabled_ports = 0x1f,
1da6df85 1713 .arl_entries = 4,
967dd82f
FF		 1714 .vta_regs = B53_VTA_REGS,
1715 .cpu_port = B53_CPU_PORT,
1716 .duplex_reg = B53_DUPLEX_STAT_GE,
1717 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1718 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1719 },
1720 {
1721 .chip_id = BCM53125_DEVICE_ID,
1722 .dev_name = "BCM53125",
1723 .vlans = 4096,
1724 .enabled_ports = 0xff,
be35e8c5 1725 .arl_entries = 4,
967dd82f
FF		 1726 .cpu_port = B53_CPU_PORT,
1727 .vta_regs = B53_VTA_REGS,
1728 .duplex_reg = B53_DUPLEX_STAT_GE,
1729 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1730 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1731 },
1732 {
1733 .chip_id = BCM53128_DEVICE_ID,
1734 .dev_name = "BCM53128",
1735 .vlans = 4096,
1736 .enabled_ports = 0x1ff,
1da6df85 1737 .arl_entries = 4,
967dd82f
FF		 1738 .cpu_port = B53_CPU_PORT,
1739 .vta_regs = B53_VTA_REGS,
1740 .duplex_reg = B53_DUPLEX_STAT_GE,
1741 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1742 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1743 },
1744 {
1745 .chip_id = BCM63XX_DEVICE_ID,
1746 .dev_name = "BCM63xx",
1747 .vlans = 4096,
1748 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1749 .arl_entries = 4,
967dd82f
FF		 1750 .cpu_port = B53_CPU_PORT,
1751 .vta_regs = B53_VTA_REGS_63XX,
1752 .duplex_reg = B53_DUPLEX_STAT_63XX,
1753 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1754 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1755 },
1756 {
1757 .chip_id = BCM53010_DEVICE_ID,
1758 .dev_name = "BCM53010",
1759 .vlans = 4096,
1760 .enabled_ports = 0x1f,
1da6df85 1761 .arl_entries = 4,
967dd82f
FF		 1762 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1763 .vta_regs = B53_VTA_REGS,
1764 .duplex_reg = B53_DUPLEX_STAT_GE,
1765 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1766 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1767 },
1768 {
1769 .chip_id = BCM53011_DEVICE_ID,
1770 .dev_name = "BCM53011",
1771 .vlans = 4096,
1772 .enabled_ports = 0x1bf,
1da6df85 1773 .arl_entries = 4,
967dd82f
FF		 1774 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1775 .vta_regs = B53_VTA_REGS,
1776 .duplex_reg = B53_DUPLEX_STAT_GE,
1777 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1778 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1779 },
1780 {
1781 .chip_id = BCM53012_DEVICE_ID,
1782 .dev_name = "BCM53012",
1783 .vlans = 4096,
1784 .enabled_ports = 0x1bf,
1da6df85 1785 .arl_entries = 4,
967dd82f
FF		 1786 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1787 .vta_regs = B53_VTA_REGS,
1788 .duplex_reg = B53_DUPLEX_STAT_GE,
1789 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1790 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1791 },
1792 {
1793 .chip_id = BCM53018_DEVICE_ID,
1794 .dev_name = "BCM53018",
1795 .vlans = 4096,
1796 .enabled_ports = 0x1f,
1da6df85 1797 .arl_entries = 4,
967dd82f
FF		 1798 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1799 .vta_regs = B53_VTA_REGS,
1800 .duplex_reg = B53_DUPLEX_STAT_GE,
1801 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1802 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1803 },
1804 {
1805 .chip_id = BCM53019_DEVICE_ID,
1806 .dev_name = "BCM53019",
1807 .vlans = 4096,
1808 .enabled_ports = 0x1f,
1da6df85 1809 .arl_entries = 4,
967dd82f
FF		 1810 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1811 .vta_regs = B53_VTA_REGS,
1812 .duplex_reg = B53_DUPLEX_STAT_GE,
1813 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1814 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1815 },
991a36bb
FF		 1816 {
1817 .chip_id = BCM58XX_DEVICE_ID,
1818 .dev_name = "BCM585xx/586xx/88312",
1819 .vlans = 4096,
1820 .enabled_ports = 0x1ff,
1821 .arl_entries = 4,
bfcda65c 1822 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1823 .vta_regs = B53_VTA_REGS,
1824 .duplex_reg = B53_DUPLEX_STAT_GE,
1825 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1826 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1827 },
130401d9
FF		 1828 {
1829 .chip_id = BCM7445_DEVICE_ID,
1830 .dev_name = "BCM7445",
1831 .vlans = 4096,
1832 .enabled_ports = 0x1ff,
1833 .arl_entries = 4,
1834 .cpu_port = B53_CPU_PORT,
1835 .vta_regs = B53_VTA_REGS,
1836 .duplex_reg = B53_DUPLEX_STAT_GE,
1837 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1838 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1839 },
0fe99338
FF		 1840 {
1841 .chip_id = BCM7278_DEVICE_ID,
1842 .dev_name = "BCM7278",
1843 .vlans = 4096,
1844 .enabled_ports = 0x1ff,
1845 .arl_entries= 4,
1846 .cpu_port = B53_CPU_PORT,
1847 .vta_regs = B53_VTA_REGS,
1848 .duplex_reg = B53_DUPLEX_STAT_GE,
1849 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1850 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1851 },
967dd82f
FF		 1852};
1853
1854static int b53_switch_init(struct b53_device *dev)
1855{
967dd82f
FF		 1856 unsigned int i;
1857 int ret;
1858
1859 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1860 const struct b53_chip_data *chip = &b53_switch_chips[i];
1861
1862 if (chip->chip_id == dev->chip_id) {
1863 if (!dev->enabled_ports)
1864 dev->enabled_ports = chip->enabled_ports;
1865 dev->name = chip->dev_name;
1866 dev->duplex_reg = chip->duplex_reg;
1867 dev->vta_regs[0] = chip->vta_regs[0];
1868 dev->vta_regs[1] = chip->vta_regs[1];
1869 dev->vta_regs[2] = chip->vta_regs[2];
1870 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1871 dev->cpu_port = chip->cpu_port;
1872 dev->num_vlans = chip->vlans;
1da6df85 1873 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1874 break;
1875 }
1876 }
1877
1878 /* check which BCM5325x version we have */
1879 if (is5325(dev)) {
1880 u8 vc4;
1881
1882 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1883
1884 /* check reserved bits */
1885 switch (vc4 & 3) {
1886 case 1:
1887 /* BCM5325E */
1888 break;
1889 case 3:
1890 /* BCM5325F - do not use port 4 */
1891 dev->enabled_ports &= ~BIT(4);
1892 break;
1893 default:
1894/* On the BCM47XX SoCs this is the supported internal switch.*/
1895#ifndef CONFIG_BCM47XX
1896 /* BCM5325M */
1897 return -EINVAL;
1898#else
1899 break;
1900#endif
1901 }
1902 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1903 u64 strap_value;
1904
1905 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1906 /* use second IMP port if GMII is enabled */
1907 if (strap_value & SV_GMII_CTRL_115)
1908 dev->cpu_port = 5;
1909 }
1910
1911 /* cpu port is always last */
1912 dev->num_ports = dev->cpu_port + 1;
1913 dev->enabled_ports |= BIT(dev->cpu_port);
1914
1915 dev->ports = devm_kzalloc(dev->dev,
1916 sizeof(struct b53_port) * dev->num_ports,
1917 GFP_KERNEL);
1918 if (!dev->ports)
1919 return -ENOMEM;
1920
a2482d2c
FF		 1921 dev->vlans = devm_kzalloc(dev->dev,
1922 sizeof(struct b53_vlan) * dev->num_vlans,
1923 GFP_KERNEL);
1924 if (!dev->vlans)
1925 return -ENOMEM;
1926
967dd82f
FF		 1927 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1928 if (dev->reset_gpio >= 0) {
1929 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1930 GPIOF_OUT_INIT_HIGH, "robo_reset");
1931 if (ret)
1932 return ret;
1933 }
1934
1935 return 0;
1936}
1937
0dff88d3
JL		 1938struct b53_device *b53_switch_alloc(struct device *base,
1939 const struct b53_io_ops *ops,
967dd82f
FF		 1940 void *priv)
1941{
1942 struct dsa_switch *ds;
1943 struct b53_device *dev;
1944
a0c02161 1945 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1946 if (!ds)
1947 return NULL;
1948
a0c02161
VD		 1949 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1950 if (!dev)
1951 return NULL;
967dd82f
FF		 1952
1953 ds->priv = dev;
967dd82f
FF		 1954 dev->dev = base;
1955
1956 dev->ds = ds;
1957 dev->priv = priv;
1958 dev->ops = ops;
485ebd61 1959 ds->ops = &b53_switch_ops;
967dd82f
FF		 1960 mutex_init(&dev->reg_mutex);
1961 mutex_init(&dev->stats_mutex);
1962
1963 return dev;
1964}
1965EXPORT_SYMBOL(b53_switch_alloc);
1966
1967int b53_switch_detect(struct b53_device *dev)
1968{
1969 u32 id32;
1970 u16 tmp;
1971 u8 id8;
1972 int ret;
1973
1974 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1975 if (ret)
1976 return ret;
1977
1978 switch (id8) {
1979 case 0:
1980 /* BCM5325 and BCM5365 do not have this register so reads
1981 * return 0. But the read operation did succeed, so assume this
1982 * is one of them.
1983 *
1984 * Next check if we can write to the 5325's VTA register; for
1985 * 5365 it is read only.
1986 */
1987 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1988 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1989
1990 if (tmp == 0xf)
1991 dev->chip_id = BCM5325_DEVICE_ID;
1992 else
1993 dev->chip_id = BCM5365_DEVICE_ID;
1994 break;
1995 case BCM5395_DEVICE_ID:
1996 case BCM5397_DEVICE_ID:
1997 case BCM5398_DEVICE_ID:
1998 dev->chip_id = id8;
1999 break;
2000 default:
2001 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2002 if (ret)
2003 return ret;
2004
2005 switch (id32) {
2006 case BCM53115_DEVICE_ID:
2007 case BCM53125_DEVICE_ID:
2008 case BCM53128_DEVICE_ID:
2009 case BCM53010_DEVICE_ID:
2010 case BCM53011_DEVICE_ID:
2011 case BCM53012_DEVICE_ID:
2012 case BCM53018_DEVICE_ID:
2013 case BCM53019_DEVICE_ID:
2014 dev->chip_id = id32;
2015 break;
2016 default:
2017 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2018 id8, id32);
2019 return -ENODEV;
2020 }
2021 }
2022
2023 if (dev->chip_id == BCM5325_DEVICE_ID)
2024 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2025 &dev->core_rev);
2026 else
2027 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2028 &dev->core_rev);
2029}
2030EXPORT_SYMBOL(b53_switch_detect);
2031
2032int b53_switch_register(struct b53_device *dev)
2033{
2034 int ret;
2035
2036 if (dev->pdata) {
2037 dev->chip_id = dev->pdata->chip_id;
2038 dev->enabled_ports = dev->pdata->enabled_ports;
2039 }
2040
2041 if (!dev->chip_id && b53_switch_detect(dev))
2042 return -EINVAL;
2043
2044 ret = b53_switch_init(dev);
2045 if (ret)
2046 return ret;
2047
2048 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2049
23c9ee49 2050 return dsa_register_switch(dev->ds);
967dd82f
FF		 2051}
2052EXPORT_SYMBOL(b53_switch_register);
2053
2054MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2055MODULE_DESCRIPTION("B53 switch library");
2056MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)