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net/sched/sch_red.c: work around gcc-4.4.4 anon union initializer issue
[linux-2.6-block.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 327{
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de 338
7edc58d6 339 /* Include IMP port in dumb forwarding mode
a424f0de 340 */
7edc58d6
FF		 341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
967dd82f
FF		 344}
345
a2482d2c 346static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 347{
348 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
349
350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
353
354 if (is5325(dev) || is5365(dev)) {
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
357 } else if (is63xx(dev)) {
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
360 } else {
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
363 }
364
365 mgmt &= ~SM_SW_FWD_MODE;
366
367 if (enable) {
368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
370 vc4 &= ~VC4_ING_VID_CHECK_MASK;
371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
372 vc5 |= VC5_DROP_VTABLE_MISS;
373
374 if (is5325(dev))
375 vc0 &= ~VC0_RESERVED_1;
376
377 if (is5325(dev) || is5365(dev))
378 vc1 |= VC1_RX_MCST_TAG_EN;
379
967dd82f
FF		 380 } else {
381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
383 vc4 &= ~VC4_ING_VID_CHECK_MASK;
384 vc5 &= ~VC5_DROP_VTABLE_MISS;
385
386 if (is5325(dev) || is5365(dev))
387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
388 else
389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 393 }
394
a2482d2c
FF		 395 if (!is5325(dev) && !is5365(dev))
396 vc5 &= ~VC5_VID_FFF_EN;
397
967dd82f
FF		 398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
400
401 if (is5325(dev) || is5365(dev)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev) && enable)
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
405 VC3_HIGH_8BIT_EN);
406 else
407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
408
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
411 } else if (is63xx(dev)) {
412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
415 } else {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
419 }
420
421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
422}
423
424static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
425{
426 u32 port_mask = 0;
427 u16 max_size = JMS_MIN_SIZE;
428
429 if (is5325(dev) || is5365(dev))
430 return -EINVAL;
431
432 if (enable) {
433 port_mask = dev->enabled_ports;
434 max_size = JMS_MAX_SIZE;
435 if (allow_10_100)
436 port_mask |= JPM_10_100_JUMBO_EN;
437 }
438
439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
441}
442
ff39c2d6 443static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 444{
445 unsigned int i;
446
447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 449
450 for (i = 0; i < 10; i++) {
451 u8 fast_age_ctrl;
452
453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
454 &fast_age_ctrl);
455
456 if (!(fast_age_ctrl & FAST_AGE_DONE))
457 goto out;
458
459 msleep(1);
460 }
461
462 return -ETIMEDOUT;
463out:
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
466 return 0;
467}
468
ff39c2d6
FF		 469static int b53_fast_age_port(struct b53_device *dev, int port)
470{
471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
472
473 return b53_flush_arl(dev, FAST_AGE_PORT);
474}
475
a2482d2c
FF		 476static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
477{
478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
479
480 return b53_flush_arl(dev, FAST_AGE_VLAN);
481}
482
aac02867 483void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 484{
04bed143 485 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 486 unsigned int i;
487 u16 pvlan;
488
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
491 * the same VLAN.
492 */
493 b53_for_each_port(dev, i) {
494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
495 pvlan |= BIT(cpu_port);
496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
497 }
498}
aac02867 499EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 500
f86ad77f 501int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 502{
04bed143 503 struct b53_device *dev = ds->priv;
c499696e 504 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 505 u16 pvlan;
967dd82f
FF		 506
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
509
ff39c2d6
FF		 510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
513 */
514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
515 pvlan &= ~0x1ff;
516 pvlan |= BIT(port);
517 pvlan |= dev->ports[port].vlan_ctl_mask;
518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
519
520 b53_imp_vlan_setup(ds, cpu_port);
521
f43a2dbe
FF		 522 /* If EEE was enabled, restore it */
523 if (dev->ports[port].eee.eee_enabled)
524 b53_eee_enable_set(ds, port, true);
525
967dd82f
FF		 526 return 0;
527}
f86ad77f 528EXPORT_SYMBOL(b53_enable_port);
967dd82f 529
f86ad77f 530void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 531{
04bed143 532 struct b53_device *dev = ds->priv;
967dd82f
FF		 533 u8 reg;
534
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
539}
f86ad77f 540EXPORT_SYMBOL(b53_disable_port);
967dd82f 541
b409a9ef
FF		 542void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
543{
cdb583cf 544 bool tag_en = !!(ds->ops->get_tag_protocol(ds) == DSA_TAG_PROTO_BRCM);
b409a9ef
FF		 545 struct b53_device *dev = ds->priv;
546 u8 hdr_ctl, val;
547 u16 reg;
548
549 /* Resolve which bit controls the Broadcom tag */
550 switch (port) {
551 case 8:
552 val = BRCM_HDR_P8_EN;
553 break;
554 case 7:
555 val = BRCM_HDR_P7_EN;
556 break;
557 case 5:
558 val = BRCM_HDR_P5_EN;
559 break;
560 default:
561 val = 0;
562 break;
563 }
564
565 /* Enable Broadcom tags for IMP port */
566 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 567 if (tag_en)
568 hdr_ctl |= val;
569 else
570 hdr_ctl &= ~val;
b409a9ef
FF		 571 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
572
573 /* Registers below are only accessible on newer devices */
574 if (!is58xx(dev))
575 return;
576
577 /* Enable reception Broadcom tag for CPU TX (switch RX) to
578 * allow us to tag outgoing frames
579 */
580 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 581 if (tag_en)
582 reg &= ~BIT(port);
583 else
584 reg |= BIT(port);
b409a9ef
FF		 585 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
586
587 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
588 * allow delivering frames to the per-port net_devices
589 */
590 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 591 if (tag_en)
592 reg &= ~BIT(port);
593 else
594 reg |= BIT(port);
b409a9ef
FF		 595 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
596}
597EXPORT_SYMBOL(b53_brcm_hdr_setup);
598
299752a7 599static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 600{
967dd82f
FF		 601 u8 port_ctrl;
602
603 /* BCM5325 CPU port is at 8 */
299752a7
FF		 604 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
605 port = B53_CPU_PORT;
967dd82f
FF		 606
607 port_ctrl = PORT_CTRL_RX_BCST_EN |
608 PORT_CTRL_RX_MCST_EN |
609 PORT_CTRL_RX_UCST_EN;
299752a7 610 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
7edc58d6
FF		 611
612 b53_brcm_hdr_setup(dev->ds, port);
967dd82f
FF		 613}
614
615static void b53_enable_mib(struct b53_device *dev)
616{
617 u8 gc;
618
619 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
620 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
621 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
622}
623
5c1a6eaf 624int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 625{
5c1a6eaf 626 struct b53_device *dev = ds->priv;
a2482d2c 627 struct b53_vlan vl = { 0 };
967dd82f
FF		 628 int i;
629
630 /* clear all vlan entries */
631 if (is5325(dev) || is5365(dev)) {
632 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 633 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 634 } else {
635 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
636 }
637
638 b53_enable_vlan(dev, false);
639
640 b53_for_each_port(dev, i)
641 b53_write16(dev, B53_VLAN_PAGE,
642 B53_VLAN_PORT_DEF_TAG(i), 1);
643
644 if (!is5325(dev) && !is5365(dev))
645 b53_set_jumbo(dev, dev->enable_jumbo, false);
646
647 return 0;
648}
5c1a6eaf 649EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 650
651static void b53_switch_reset_gpio(struct b53_device *dev)
652{
653 int gpio = dev->reset_gpio;
654
655 if (gpio < 0)
656 return;
657
658 /* Reset sequence: RESET low(50ms)->high(20ms)
659 */
660 gpio_set_value(gpio, 0);
661 mdelay(50);
662
663 gpio_set_value(gpio, 1);
664 mdelay(20);
665
666 dev->current_page = 0xff;
667}
668
669static int b53_switch_reset(struct b53_device *dev)
670{
3fb22b05
FF		 671 unsigned int timeout = 1000;
672 u8 mgmt, reg;
967dd82f
FF		 673
674 b53_switch_reset_gpio(dev);
675
676 if (is539x(dev)) {
677 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
679 }
680
3fb22b05
FF		 681 /* This is specific to 58xx devices here, do not use is58xx() which
682 * covers the larger Starfigther 2 family, including 7445/7278 which
683 * still use this driver as a library and need to perform the reset
684 * earlier.
685 */
686 if (dev->chip_id == BCM58XX_DEVICE_ID) {
687 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
688 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
689 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
690
691 do {
692 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
693 if (!(reg & SW_RST))
694 break;
695
696 usleep_range(1000, 2000);
697 } while (timeout-- > 0);
698
699 if (timeout == 0)
700 return -ETIMEDOUT;
701 }
702
967dd82f
FF		 703 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
704
705 if (!(mgmt & SM_SW_FWD_EN)) {
706 mgmt &= ~SM_SW_FWD_MODE;
707 mgmt |= SM_SW_FWD_EN;
708
709 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
710 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
711
712 if (!(mgmt & SM_SW_FWD_EN)) {
713 dev_err(dev->dev, "Failed to enable switch!\n");
714 return -EINVAL;
715 }
716 }
717
718 b53_enable_mib(dev);
719
ff39c2d6 720 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 721}
722
723static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
724{
04bed143 725 struct b53_device *priv = ds->priv;
967dd82f
FF		 726 u16 value = 0;
727 int ret;
728
729 if (priv->ops->phy_read16)
730 ret = priv->ops->phy_read16(priv, addr, reg, &value);
731 else
732 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
733 reg * 2, &value);
734
735 return ret ? ret : value;
736}
737
738static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
739{
04bed143 740 struct b53_device *priv = ds->priv;
967dd82f
FF		 741
742 if (priv->ops->phy_write16)
743 return priv->ops->phy_write16(priv, addr, reg, val);
744
745 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
746}
747
748static int b53_reset_switch(struct b53_device *priv)
749{
750 /* reset vlans */
751 priv->enable_jumbo = false;
752
a2482d2c 753 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 754 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
755
756 return b53_switch_reset(priv);
757}
758
759static int b53_apply_config(struct b53_device *priv)
760{
761 /* disable switching */
762 b53_set_forwarding(priv, 0);
763
5c1a6eaf 764 b53_configure_vlan(priv->ds);
967dd82f
FF		 765
766 /* enable switching */
767 b53_set_forwarding(priv, 1);
768
769 return 0;
770}
771
772static void b53_reset_mib(struct b53_device *priv)
773{
774 u8 gc;
775
776 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
777
778 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
779 msleep(1);
780 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
781 msleep(1);
782}
783
784static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
785{
786 if (is5365(dev))
787 return b53_mibs_65;
788 else if (is63xx(dev))
789 return b53_mibs_63xx;
bde5d132
FF		 790 else if (is58xx(dev))
791 return b53_mibs_58xx;
967dd82f
FF		 792 else
793 return b53_mibs;
794}
795
796static unsigned int b53_get_mib_size(struct b53_device *dev)
797{
798 if (is5365(dev))
799 return B53_MIBS_65_SIZE;
800 else if (is63xx(dev))
801 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 802 else if (is58xx(dev))
803 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 804 else
805 return B53_MIBS_SIZE;
806}
807
3117455d 808void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
967dd82f 809{
04bed143 810 struct b53_device *dev = ds->priv;
967dd82f
FF		 811 const struct b53_mib_desc *mibs = b53_get_mib(dev);
812 unsigned int mib_size = b53_get_mib_size(dev);
813 unsigned int i;
814
815 for (i = 0; i < mib_size; i++)
816 memcpy(data + i * ETH_GSTRING_LEN,
817 mibs[i].name, ETH_GSTRING_LEN);
818}
3117455d 819EXPORT_SYMBOL(b53_get_strings);
967dd82f 820
3117455d 821void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 822{
04bed143 823 struct b53_device *dev = ds->priv;
967dd82f
FF		 824 const struct b53_mib_desc *mibs = b53_get_mib(dev);
825 unsigned int mib_size = b53_get_mib_size(dev);
826 const struct b53_mib_desc *s;
827 unsigned int i;
828 u64 val = 0;
829
830 if (is5365(dev) && port == 5)
831 port = 8;
832
833 mutex_lock(&dev->stats_mutex);
834
835 for (i = 0; i < mib_size; i++) {
836 s = &mibs[i];
837
51dca8a1 838 if (s->size == 8) {
967dd82f
FF		 839 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
840 } else {
841 u32 val32;
842
843 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
844 &val32);
845 val = val32;
846 }
847 data[i] = (u64)val;
848 }
849
850 mutex_unlock(&dev->stats_mutex);
851}
3117455d 852EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 853
3117455d 854int b53_get_sset_count(struct dsa_switch *ds)
967dd82f 855{
04bed143 856 struct b53_device *dev = ds->priv;
967dd82f
FF		 857
858 return b53_get_mib_size(dev);
859}
3117455d 860EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 861
967dd82f
FF		 862static int b53_setup(struct dsa_switch *ds)
863{
04bed143 864 struct b53_device *dev = ds->priv;
967dd82f
FF		 865 unsigned int port;
866 int ret;
867
868 ret = b53_reset_switch(dev);
869 if (ret) {
870 dev_err(ds->dev, "failed to reset switch\n");
871 return ret;
872 }
873
874 b53_reset_mib(dev);
875
876 ret = b53_apply_config(dev);
877 if (ret)
878 dev_err(ds->dev, "failed to apply configuration\n");
879
34c8befd
FF		 880 /* Configure IMP/CPU port, disable unused ports. Enabled
881 * ports will be configured with .port_enable
882 */
967dd82f 883 for (port = 0; port < dev->num_ports; port++) {
34c8befd 884 if (dsa_is_cpu_port(ds, port))
299752a7 885 b53_enable_cpu_port(dev, port);
bff7b688 886 else if (dsa_is_unused_port(ds, port))
967dd82f
FF		 887 b53_disable_port(ds, port, NULL);
888 }
889
890 return ret;
891}
892
893static void b53_adjust_link(struct dsa_switch *ds, int port,
894 struct phy_device *phydev)
895{
04bed143 896 struct b53_device *dev = ds->priv;
f43a2dbe 897 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 898 u8 rgmii_ctrl = 0, reg = 0, off;
899
900 if (!phy_is_pseudo_fixed_link(phydev))
901 return;
902
903 /* Override the port settings */
904 if (port == dev->cpu_port) {
905 off = B53_PORT_OVERRIDE_CTRL;
906 reg = PORT_OVERRIDE_EN;
907 } else {
908 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
909 reg = GMII_PO_EN;
910 }
911
912 /* Set the link UP */
913 if (phydev->link)
914 reg |= PORT_OVERRIDE_LINK;
915
916 if (phydev->duplex == DUPLEX_FULL)
917 reg |= PORT_OVERRIDE_FULL_DUPLEX;
918
919 switch (phydev->speed) {
920 case 2000:
921 reg |= PORT_OVERRIDE_SPEED_2000M;
922 /* fallthrough */
923 case SPEED_1000:
924 reg |= PORT_OVERRIDE_SPEED_1000M;
925 break;
926 case SPEED_100:
927 reg |= PORT_OVERRIDE_SPEED_100M;
928 break;
929 case SPEED_10:
930 reg |= PORT_OVERRIDE_SPEED_10M;
931 break;
932 default:
933 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
934 return;
935 }
936
937 /* Enable flow control on BCM5301x's CPU port */
938 if (is5301x(dev) && port == dev->cpu_port)
939 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
940
941 if (phydev->pause) {
942 if (phydev->asym_pause)
943 reg |= PORT_OVERRIDE_TX_FLOW;
944 reg |= PORT_OVERRIDE_RX_FLOW;
945 }
946
947 b53_write8(dev, B53_CTRL_PAGE, off, reg);
948
949 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
950 if (port == 8)
951 off = B53_RGMII_CTRL_IMP;
952 else
953 off = B53_RGMII_CTRL_P(port);
954
955 /* Configure the port RGMII clock delay by DLL disabled and
956 * tx_clk aligned timing (restoring to reset defaults)
957 */
958 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
959 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
960 RGMII_CTRL_TIMING_SEL);
961
962 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
963 * sure that we enable the port TX clock internal delay to
964 * account for this internal delay that is inserted, otherwise
965 * the switch won't be able to receive correctly.
966 *
967 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
968 * any delay neither on transmission nor reception, so the
969 * BCM53125 must also be configured accordingly to account for
970 * the lack of delay and introduce
971 *
972 * The BCM53125 switch has its RX clock and TX clock control
973 * swapped, hence the reason why we modify the TX clock path in
974 * the "RGMII" case
975 */
976 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
977 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
978 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
979 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
980 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
981 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
982
983 dev_info(ds->dev, "Configured port %d for %s\n", port,
984 phy_modes(phydev->interface));
985 }
986
987 /* configure MII port if necessary */
988 if (is5325(dev)) {
989 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
990 &reg);
991
992 /* reverse mii needs to be enabled */
993 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
994 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
995 reg | PORT_OVERRIDE_RV_MII_25);
996 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
997 &reg);
998
999 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1000 dev_err(ds->dev,
1001 "Failed to enable reverse MII mode\n");
1002 return;
1003 }
1004 }
1005 } else if (is5301x(dev)) {
1006 if (port != dev->cpu_port) {
1007 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1008 u8 gmii_po;
1009
1010 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1011 gmii_po |= GMII_PO_LINK |
1012 GMII_PO_RX_FLOW |
1013 GMII_PO_TX_FLOW |
1014 GMII_PO_EN |
1015 GMII_PO_SPEED_2000M;
1016 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1017 }
1018 }
f43a2dbe
FF		 1019
1020 /* Re-negotiate EEE if it was enabled already */
1021 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1022}
1023
3117455d 1024int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1025{
1026 return 0;
1027}
3117455d 1028EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1029
3117455d
FF		 1030int b53_vlan_prepare(struct dsa_switch *ds, int port,
1031 const struct switchdev_obj_port_vlan *vlan,
1032 struct switchdev_trans *trans)
a2482d2c 1033{
04bed143 1034 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1035
1036 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1037 return -EOPNOTSUPP;
1038
1039 if (vlan->vid_end > dev->num_vlans)
1040 return -ERANGE;
1041
1042 b53_enable_vlan(dev, true);
1043
1044 return 0;
1045}
3117455d 1046EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1047
3117455d
FF		 1048void b53_vlan_add(struct dsa_switch *ds, int port,
1049 const struct switchdev_obj_port_vlan *vlan,
1050 struct switchdev_trans *trans)
a2482d2c 1051{
04bed143 1052 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1053 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1054 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c
FF		 1055 struct b53_vlan *vl;
1056 u16 vid;
1057
1058 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1059 vl = &dev->vlans[vid];
1060
1061 b53_get_vlan_entry(dev, vid, vl);
1062
c499696e 1063 vl->members |= BIT(port);
a2482d2c 1064 if (untagged)
e47112d9 1065 vl->untag |= BIT(port);
a2482d2c 1066 else
e47112d9 1067 vl->untag &= ~BIT(port);
a2482d2c
FF		 1068
1069 b53_set_vlan_entry(dev, vid, vl);
1070 b53_fast_age_vlan(dev, vid);
1071 }
1072
1073 if (pvid) {
1074 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1075 vlan->vid_end);
a2482d2c
FF		 1076 b53_fast_age_vlan(dev, vid);
1077 }
1078}
3117455d 1079EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1080
3117455d
FF		 1081int b53_vlan_del(struct dsa_switch *ds, int port,
1082 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1083{
04bed143 1084 struct b53_device *dev = ds->priv;
a2482d2c 1085 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1086 struct b53_vlan *vl;
1087 u16 vid;
1088 u16 pvid;
1089
1090 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1091
1092 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1093 vl = &dev->vlans[vid];
1094
1095 b53_get_vlan_entry(dev, vid, vl);
1096
1097 vl->members &= ~BIT(port);
a2482d2c
FF		 1098
1099 if (pvid == vid) {
1100 if (is5325(dev) || is5365(dev))
1101 pvid = 1;
1102 else
1103 pvid = 0;
1104 }
1105
e47112d9 1106 if (untagged)
a2482d2c 1107 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1108
1109 b53_set_vlan_entry(dev, vid, vl);
1110 b53_fast_age_vlan(dev, vid);
1111 }
1112
1113 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1114 b53_fast_age_vlan(dev, pvid);
1115
1116 return 0;
1117}
3117455d 1118EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1119
1da6df85
FF		 1120/* Address Resolution Logic routines */
1121static int b53_arl_op_wait(struct b53_device *dev)
1122{
1123 unsigned int timeout = 10;
1124 u8 reg;
1125
1126 do {
1127 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1128 if (!(reg & ARLTBL_START_DONE))
1129 return 0;
1130
1131 usleep_range(1000, 2000);
1132 } while (timeout--);
1133
1134 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1135
1136 return -ETIMEDOUT;
1137}
1138
1139static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1140{
1141 u8 reg;
1142
1143 if (op > ARLTBL_RW)
1144 return -EINVAL;
1145
1146 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1147 reg |= ARLTBL_START_DONE;
1148 if (op)
1149 reg |= ARLTBL_RW;
1150 else
1151 reg &= ~ARLTBL_RW;
1152 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1153
1154 return b53_arl_op_wait(dev);
1155}
1156
1157static int b53_arl_read(struct b53_device *dev, u64 mac,
1158 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1159 bool is_valid)
1160{
1161 unsigned int i;
1162 int ret;
1163
1164 ret = b53_arl_op_wait(dev);
1165 if (ret)
1166 return ret;
1167
1168 /* Read the bins */
1169 for (i = 0; i < dev->num_arl_entries; i++) {
1170 u64 mac_vid;
1171 u32 fwd_entry;
1172
1173 b53_read64(dev, B53_ARLIO_PAGE,
1174 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1175 b53_read32(dev, B53_ARLIO_PAGE,
1176 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1177 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1178
1179 if (!(fwd_entry & ARLTBL_VALID))
1180 continue;
1181 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1182 continue;
1183 *idx = i;
1184 }
1185
1186 return -ENOENT;
1187}
1188
1189static int b53_arl_op(struct b53_device *dev, int op, int port,
1190 const unsigned char *addr, u16 vid, bool is_valid)
1191{
1192 struct b53_arl_entry ent;
1193 u32 fwd_entry;
1194 u64 mac, mac_vid = 0;
1195 u8 idx = 0;
1196 int ret;
1197
1198 /* Convert the array into a 64-bit MAC */
4b92ea81 1199 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1200
1201 /* Perform a read for the given MAC and VID */
1202 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1203 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1204
1205 /* Issue a read operation for this MAC */
1206 ret = b53_arl_rw_op(dev, 1);
1207 if (ret)
1208 return ret;
1209
1210 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1211 /* If this is a read, just finish now */
1212 if (op)
1213 return ret;
1214
1215 /* We could not find a matching MAC, so reset to a new entry */
1216 if (ret) {
1217 fwd_entry = 0;
1218 idx = 1;
1219 }
1220
1221 memset(&ent, 0, sizeof(ent));
1222 ent.port = port;
1223 ent.is_valid = is_valid;
1224 ent.vid = vid;
1225 ent.is_static = true;
1226 memcpy(ent.mac, addr, ETH_ALEN);
1227 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1228
1229 b53_write64(dev, B53_ARLIO_PAGE,
1230 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1231 b53_write32(dev, B53_ARLIO_PAGE,
1232 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1233
1234 return b53_arl_rw_op(dev, 0);
1235}
1236
1b6dd556
AS		 1237int b53_fdb_add(struct dsa_switch *ds, int port,
1238 const unsigned char *addr, u16 vid)
1da6df85 1239{
04bed143 1240 struct b53_device *priv = ds->priv;
1da6df85
FF		 1241
1242 /* 5325 and 5365 require some more massaging, but could
1243 * be supported eventually
1244 */
1245 if (is5325(priv) || is5365(priv))
1246 return -EOPNOTSUPP;
1247
1b6dd556 1248 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1249}
3117455d 1250EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1251
3117455d 1252int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1253 const unsigned char *addr, u16 vid)
1da6df85 1254{
04bed143 1255 struct b53_device *priv = ds->priv;
1da6df85 1256
6c2c1dcb 1257 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1258}
3117455d 1259EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1260
1261static int b53_arl_search_wait(struct b53_device *dev)
1262{
1263 unsigned int timeout = 1000;
1264 u8 reg;
1265
1266 do {
1267 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1268 if (!(reg & ARL_SRCH_STDN))
1269 return 0;
1270
1271 if (reg & ARL_SRCH_VLID)
1272 return 0;
1273
1274 usleep_range(1000, 2000);
1275 } while (timeout--);
1276
1277 return -ETIMEDOUT;
1278}
1279
1280static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1281 struct b53_arl_entry *ent)
1282{
1283 u64 mac_vid;
1284 u32 fwd_entry;
1285
1286 b53_read64(dev, B53_ARLIO_PAGE,
1287 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1288 b53_read32(dev, B53_ARLIO_PAGE,
1289 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1290 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1291}
1292
e6cbef0c 1293static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1294 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1295{
1296 if (!ent->is_valid)
1297 return 0;
1298
1299 if (port != ent->port)
1300 return 0;
1301
2bedde1a 1302 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1303}
1304
3117455d 1305int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1306 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1307{
04bed143 1308 struct b53_device *priv = ds->priv;
1da6df85
FF		 1309 struct b53_arl_entry results[2];
1310 unsigned int count = 0;
1311 int ret;
1312 u8 reg;
1313
1314 /* Start search operation */
1315 reg = ARL_SRCH_STDN;
1316 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1317
1318 do {
1319 ret = b53_arl_search_wait(priv);
1320 if (ret)
1321 return ret;
1322
1323 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1324 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1325 if (ret)
1326 return ret;
1327
1328 if (priv->num_arl_entries > 2) {
1329 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1330 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1331 if (ret)
1332 return ret;
1333
1334 if (!results[0].is_valid && !results[1].is_valid)
1335 break;
1336 }
1337
1338 } while (count++ < 1024);
1339
1340 return 0;
1341}
3117455d 1342EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1343
ddd3a0c8 1344int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1345{
04bed143 1346 struct b53_device *dev = ds->priv;
0abfd494 1347 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1348 u16 pvlan, reg;
1349 unsigned int i;
1350
48aea33a
FF		 1351 /* Make this port leave the all VLANs join since we will have proper
1352 * VLAN entries from now on
1353 */
1354 if (is58xx(dev)) {
1355 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1356 reg &= ~BIT(port);
1357 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1358 reg &= ~BIT(cpu_port);
1359 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1360 }
1361
ff39c2d6
FF		 1362 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1363
1364 b53_for_each_port(dev, i) {
c8652c83 1365 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1366 continue;
1367
1368 /* Add this local port to the remote port VLAN control
1369 * membership and update the remote port bitmask
1370 */
1371 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1372 reg |= BIT(port);
1373 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1374 dev->ports[i].vlan_ctl_mask = reg;
1375
1376 pvlan |= BIT(i);
1377 }
1378
1379 /* Configure the local port VLAN control membership to include
1380 * remote ports and update the local port bitmask
1381 */
1382 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1383 dev->ports[port].vlan_ctl_mask = pvlan;
1384
1385 return 0;
1386}
3117455d 1387EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1388
f123f2fb 1389void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1390{
04bed143 1391 struct b53_device *dev = ds->priv;
a2482d2c 1392 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1393 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1394 unsigned int i;
a2482d2c 1395 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1396
1397 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1398
1399 b53_for_each_port(dev, i) {
1400 /* Don't touch the remaining ports */
c8652c83 1401 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1402 continue;
1403
1404 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1405 reg &= ~BIT(port);
1406 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1407 dev->ports[port].vlan_ctl_mask = reg;
1408
1409 /* Prevent self removal to preserve isolation */
1410 if (port != i)
1411 pvlan &= ~BIT(i);
1412 }
1413
1414 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1415 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1416
1417 if (is5325(dev) || is5365(dev))
1418 pvid = 1;
1419 else
1420 pvid = 0;
1421
48aea33a
FF		 1422 /* Make this port join all VLANs without VLAN entries */
1423 if (is58xx(dev)) {
1424 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1425 reg |= BIT(port);
1426 if (!(reg & BIT(cpu_port)))
1427 reg |= BIT(cpu_port);
1428 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1429 } else {
1430 b53_get_vlan_entry(dev, pvid, vl);
c499696e
FF		 1431 vl->members |= BIT(port) | BIT(cpu_port);
1432 vl->untag |= BIT(port) | BIT(cpu_port);
48aea33a
FF		 1433 b53_set_vlan_entry(dev, pvid, vl);
1434 }
ff39c2d6 1435}
3117455d 1436EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1437
3117455d 1438void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1439{
04bed143 1440 struct b53_device *dev = ds->priv;
597698f1 1441 u8 hw_state;
ff39c2d6
FF		 1442 u8 reg;
1443
ff39c2d6
FF		 1444 switch (state) {
1445 case BR_STATE_DISABLED:
1446 hw_state = PORT_CTRL_DIS_STATE;
1447 break;
1448 case BR_STATE_LISTENING:
1449 hw_state = PORT_CTRL_LISTEN_STATE;
1450 break;
1451 case BR_STATE_LEARNING:
1452 hw_state = PORT_CTRL_LEARN_STATE;
1453 break;
1454 case BR_STATE_FORWARDING:
1455 hw_state = PORT_CTRL_FWD_STATE;
1456 break;
1457 case BR_STATE_BLOCKING:
1458 hw_state = PORT_CTRL_BLOCK_STATE;
1459 break;
1460 default:
1461 dev_err(ds->dev, "invalid STP state: %d\n", state);
1462 return;
1463 }
1464
ff39c2d6
FF		 1465 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1466 reg &= ~PORT_CTRL_STP_STATE_MASK;
1467 reg |= hw_state;
1468 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1469}
3117455d 1470EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1471
3117455d 1472void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1473{
1474 struct b53_device *dev = ds->priv;
1475
1476 if (b53_fast_age_port(dev, port))
1477 dev_err(ds->dev, "fast ageing failed\n");
1478}
3117455d 1479EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1480
7edc58d6
FF		 1481static bool b53_can_enable_brcm_tags(struct dsa_switch *ds)
1482{
1483 unsigned int brcm_tag_mask;
1484 unsigned int i;
1485
1486 /* Broadcom switches will accept enabling Broadcom tags on the
1487 * following ports: 5, 7 and 8, any other port is not supported
1488 */
1489 brcm_tag_mask = BIT(B53_CPU_PORT_25) | BIT(7) | BIT(B53_CPU_PORT);
1490
1491 for (i = 0; i < ds->num_ports; i++) {
1492 if (dsa_is_cpu_port(ds, i)) {
1493 if (!(BIT(i) & brcm_tag_mask)) {
1494 dev_warn(ds->dev,
1495 "Port %d is not Broadcom tag capable\n",
1496 i);
1497 return false;
1498 }
1499 }
1500 }
1501
1502 return true;
1503}
1504
7b314362
AL		 1505static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1506{
7edc58d6
FF		 1507 struct b53_device *dev = ds->priv;
1508
1509 /* Older models support a different tag format that we do not
1510 * support in net/dsa/tag_brcm.c yet.
1511 */
1512 if (is5325(dev) || is5365(dev) || !b53_can_enable_brcm_tags(ds))
1513 return DSA_TAG_PROTO_NONE;
1514 else
1515 return DSA_TAG_PROTO_BRCM;
7b314362
AL		 1516}
1517
ed3af5fd
FF		 1518int b53_mirror_add(struct dsa_switch *ds, int port,
1519 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1520{
1521 struct b53_device *dev = ds->priv;
1522 u16 reg, loc;
1523
1524 if (ingress)
1525 loc = B53_IG_MIR_CTL;
1526 else
1527 loc = B53_EG_MIR_CTL;
1528
1529 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1530 reg &= ~MIRROR_MASK;
1531 reg |= BIT(port);
1532 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1533
1534 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1535 reg &= ~CAP_PORT_MASK;
1536 reg |= mirror->to_local_port;
1537 reg |= MIRROR_EN;
1538 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1539
1540 return 0;
1541}
1542EXPORT_SYMBOL(b53_mirror_add);
1543
1544void b53_mirror_del(struct dsa_switch *ds, int port,
1545 struct dsa_mall_mirror_tc_entry *mirror)
1546{
1547 struct b53_device *dev = ds->priv;
1548 bool loc_disable = false, other_loc_disable = false;
1549 u16 reg, loc;
1550
1551 if (mirror->ingress)
1552 loc = B53_IG_MIR_CTL;
1553 else
1554 loc = B53_EG_MIR_CTL;
1555
1556 /* Update the desired ingress/egress register */
1557 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1558 reg &= ~BIT(port);
1559 if (!(reg & MIRROR_MASK))
1560 loc_disable = true;
1561 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1562
1563 /* Now look at the other one to know if we can disable mirroring
1564 * entirely
1565 */
1566 if (mirror->ingress)
1567 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1568 else
1569 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1570 if (!(reg & MIRROR_MASK))
1571 other_loc_disable = true;
1572
1573 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1574 /* Both no longer have ports, let's disable mirroring */
1575 if (loc_disable && other_loc_disable) {
1576 reg &= ~MIRROR_EN;
1577 reg &= ~mirror->to_local_port;
1578 }
1579 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1580}
1581EXPORT_SYMBOL(b53_mirror_del);
1582
22256b0a
FF		 1583void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1584{
1585 struct b53_device *dev = ds->priv;
1586 u16 reg;
1587
1588 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1589 if (enable)
1590 reg |= BIT(port);
1591 else
1592 reg &= ~BIT(port);
1593 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1594}
1595EXPORT_SYMBOL(b53_eee_enable_set);
1596
1597
1598/* Returns 0 if EEE was not enabled, or 1 otherwise
1599 */
1600int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1601{
1602 int ret;
1603
1604 ret = phy_init_eee(phy, 0);
1605 if (ret)
1606 return 0;
1607
1608 b53_eee_enable_set(ds, port, true);
1609
1610 return 1;
1611}
1612EXPORT_SYMBOL(b53_eee_init);
1613
1614int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1615{
1616 struct b53_device *dev = ds->priv;
1617 struct ethtool_eee *p = &dev->ports[port].eee;
1618 u16 reg;
1619
1620 if (is5325(dev) || is5365(dev))
1621 return -EOPNOTSUPP;
1622
1623 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1624 e->eee_enabled = p->eee_enabled;
1625 e->eee_active = !!(reg & BIT(port));
1626
1627 return 0;
1628}
1629EXPORT_SYMBOL(b53_get_mac_eee);
1630
1631int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1632{
1633 struct b53_device *dev = ds->priv;
1634 struct ethtool_eee *p = &dev->ports[port].eee;
1635
1636 if (is5325(dev) || is5365(dev))
1637 return -EOPNOTSUPP;
1638
1639 p->eee_enabled = e->eee_enabled;
1640 b53_eee_enable_set(ds, port, e->eee_enabled);
1641
1642 return 0;
1643}
1644EXPORT_SYMBOL(b53_set_mac_eee);
1645
a82f67af 1646static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1647 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1648 .setup = b53_setup,
967dd82f
FF		 1649 .get_strings = b53_get_strings,
1650 .get_ethtool_stats = b53_get_ethtool_stats,
1651 .get_sset_count = b53_get_sset_count,
1652 .phy_read = b53_phy_read16,
1653 .phy_write = b53_phy_write16,
1654 .adjust_link = b53_adjust_link,
1655 .port_enable = b53_enable_port,
1656 .port_disable = b53_disable_port,
f43a2dbe
FF		 1657 .get_mac_eee = b53_get_mac_eee,
1658 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1659 .port_bridge_join = b53_br_join,
1660 .port_bridge_leave = b53_br_leave,
1661 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1662 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1663 .port_vlan_filtering = b53_vlan_filtering,
1664 .port_vlan_prepare = b53_vlan_prepare,
1665 .port_vlan_add = b53_vlan_add,
1666 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1667 .port_fdb_dump = b53_fdb_dump,
1668 .port_fdb_add = b53_fdb_add,
1669 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1670 .port_mirror_add = b53_mirror_add,
1671 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1672};
1673
1674struct b53_chip_data {
1675 u32 chip_id;
1676 const char *dev_name;
1677 u16 vlans;
1678 u16 enabled_ports;
1679 u8 cpu_port;
1680 u8 vta_regs[3];
1da6df85 1681 u8 arl_entries;
967dd82f
FF		 1682 u8 duplex_reg;
1683 u8 jumbo_pm_reg;
1684 u8 jumbo_size_reg;
1685};
1686
1687#define B53_VTA_REGS \
1688 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1689#define B53_VTA_REGS_9798 \
1690 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1691#define B53_VTA_REGS_63XX \
1692 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1693
1694static const struct b53_chip_data b53_switch_chips[] = {
1695 {
1696 .chip_id = BCM5325_DEVICE_ID,
1697 .dev_name = "BCM5325",
1698 .vlans = 16,
1699 .enabled_ports = 0x1f,
1da6df85 1700 .arl_entries = 2,
967dd82f
FF		 1701 .cpu_port = B53_CPU_PORT_25,
1702 .duplex_reg = B53_DUPLEX_STAT_FE,
1703 },
1704 {
1705 .chip_id = BCM5365_DEVICE_ID,
1706 .dev_name = "BCM5365",
1707 .vlans = 256,
1708 .enabled_ports = 0x1f,
1da6df85 1709 .arl_entries = 2,
967dd82f
FF		 1710 .cpu_port = B53_CPU_PORT_25,
1711 .duplex_reg = B53_DUPLEX_STAT_FE,
1712 },
1713 {
1714 .chip_id = BCM5395_DEVICE_ID,
1715 .dev_name = "BCM5395",
1716 .vlans = 4096,
1717 .enabled_ports = 0x1f,
1da6df85 1718 .arl_entries = 4,
967dd82f
FF		 1719 .cpu_port = B53_CPU_PORT,
1720 .vta_regs = B53_VTA_REGS,
1721 .duplex_reg = B53_DUPLEX_STAT_GE,
1722 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1723 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1724 },
1725 {
1726 .chip_id = BCM5397_DEVICE_ID,
1727 .dev_name = "BCM5397",
1728 .vlans = 4096,
1729 .enabled_ports = 0x1f,
1da6df85 1730 .arl_entries = 4,
967dd82f
FF		 1731 .cpu_port = B53_CPU_PORT,
1732 .vta_regs = B53_VTA_REGS_9798,
1733 .duplex_reg = B53_DUPLEX_STAT_GE,
1734 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1735 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1736 },
1737 {
1738 .chip_id = BCM5398_DEVICE_ID,
1739 .dev_name = "BCM5398",
1740 .vlans = 4096,
1741 .enabled_ports = 0x7f,
1da6df85 1742 .arl_entries = 4,
967dd82f
FF		 1743 .cpu_port = B53_CPU_PORT,
1744 .vta_regs = B53_VTA_REGS_9798,
1745 .duplex_reg = B53_DUPLEX_STAT_GE,
1746 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1747 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1748 },
1749 {
1750 .chip_id = BCM53115_DEVICE_ID,
1751 .dev_name = "BCM53115",
1752 .vlans = 4096,
1753 .enabled_ports = 0x1f,
1da6df85 1754 .arl_entries = 4,
967dd82f
FF		 1755 .vta_regs = B53_VTA_REGS,
1756 .cpu_port = B53_CPU_PORT,
1757 .duplex_reg = B53_DUPLEX_STAT_GE,
1758 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1759 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1760 },
1761 {
1762 .chip_id = BCM53125_DEVICE_ID,
1763 .dev_name = "BCM53125",
1764 .vlans = 4096,
1765 .enabled_ports = 0xff,
be35e8c5 1766 .arl_entries = 4,
967dd82f
FF		 1767 .cpu_port = B53_CPU_PORT,
1768 .vta_regs = B53_VTA_REGS,
1769 .duplex_reg = B53_DUPLEX_STAT_GE,
1770 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1771 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1772 },
1773 {
1774 .chip_id = BCM53128_DEVICE_ID,
1775 .dev_name = "BCM53128",
1776 .vlans = 4096,
1777 .enabled_ports = 0x1ff,
1da6df85 1778 .arl_entries = 4,
967dd82f
FF		 1779 .cpu_port = B53_CPU_PORT,
1780 .vta_regs = B53_VTA_REGS,
1781 .duplex_reg = B53_DUPLEX_STAT_GE,
1782 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1783 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1784 },
1785 {
1786 .chip_id = BCM63XX_DEVICE_ID,
1787 .dev_name = "BCM63xx",
1788 .vlans = 4096,
1789 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1790 .arl_entries = 4,
967dd82f
FF		 1791 .cpu_port = B53_CPU_PORT,
1792 .vta_regs = B53_VTA_REGS_63XX,
1793 .duplex_reg = B53_DUPLEX_STAT_63XX,
1794 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1795 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1796 },
1797 {
1798 .chip_id = BCM53010_DEVICE_ID,
1799 .dev_name = "BCM53010",
1800 .vlans = 4096,
1801 .enabled_ports = 0x1f,
1da6df85 1802 .arl_entries = 4,
967dd82f
FF		 1803 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1804 .vta_regs = B53_VTA_REGS,
1805 .duplex_reg = B53_DUPLEX_STAT_GE,
1806 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1807 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1808 },
1809 {
1810 .chip_id = BCM53011_DEVICE_ID,
1811 .dev_name = "BCM53011",
1812 .vlans = 4096,
1813 .enabled_ports = 0x1bf,
1da6df85 1814 .arl_entries = 4,
967dd82f
FF		 1815 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1816 .vta_regs = B53_VTA_REGS,
1817 .duplex_reg = B53_DUPLEX_STAT_GE,
1818 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1819 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1820 },
1821 {
1822 .chip_id = BCM53012_DEVICE_ID,
1823 .dev_name = "BCM53012",
1824 .vlans = 4096,
1825 .enabled_ports = 0x1bf,
1da6df85 1826 .arl_entries = 4,
967dd82f
FF		 1827 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1828 .vta_regs = B53_VTA_REGS,
1829 .duplex_reg = B53_DUPLEX_STAT_GE,
1830 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1831 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1832 },
1833 {
1834 .chip_id = BCM53018_DEVICE_ID,
1835 .dev_name = "BCM53018",
1836 .vlans = 4096,
1837 .enabled_ports = 0x1f,
1da6df85 1838 .arl_entries = 4,
967dd82f
FF		 1839 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1840 .vta_regs = B53_VTA_REGS,
1841 .duplex_reg = B53_DUPLEX_STAT_GE,
1842 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1843 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1844 },
1845 {
1846 .chip_id = BCM53019_DEVICE_ID,
1847 .dev_name = "BCM53019",
1848 .vlans = 4096,
1849 .enabled_ports = 0x1f,
1da6df85 1850 .arl_entries = 4,
967dd82f
FF		 1851 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1852 .vta_regs = B53_VTA_REGS,
1853 .duplex_reg = B53_DUPLEX_STAT_GE,
1854 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1855 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1856 },
991a36bb
FF		 1857 {
1858 .chip_id = BCM58XX_DEVICE_ID,
1859 .dev_name = "BCM585xx/586xx/88312",
1860 .vlans = 4096,
1861 .enabled_ports = 0x1ff,
1862 .arl_entries = 4,
bfcda65c 1863 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1864 .vta_regs = B53_VTA_REGS,
1865 .duplex_reg = B53_DUPLEX_STAT_GE,
1866 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1867 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1868 },
130401d9
FF		 1869 {
1870 .chip_id = BCM7445_DEVICE_ID,
1871 .dev_name = "BCM7445",
1872 .vlans = 4096,
1873 .enabled_ports = 0x1ff,
1874 .arl_entries = 4,
1875 .cpu_port = B53_CPU_PORT,
1876 .vta_regs = B53_VTA_REGS,
1877 .duplex_reg = B53_DUPLEX_STAT_GE,
1878 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1879 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1880 },
0fe99338
FF		 1881 {
1882 .chip_id = BCM7278_DEVICE_ID,
1883 .dev_name = "BCM7278",
1884 .vlans = 4096,
1885 .enabled_ports = 0x1ff,
1886 .arl_entries= 4,
1887 .cpu_port = B53_CPU_PORT,
1888 .vta_regs = B53_VTA_REGS,
1889 .duplex_reg = B53_DUPLEX_STAT_GE,
1890 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1891 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1892 },
967dd82f
FF		 1893};
1894
1895static int b53_switch_init(struct b53_device *dev)
1896{
967dd82f
FF		 1897 unsigned int i;
1898 int ret;
1899
1900 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1901 const struct b53_chip_data *chip = &b53_switch_chips[i];
1902
1903 if (chip->chip_id == dev->chip_id) {
1904 if (!dev->enabled_ports)
1905 dev->enabled_ports = chip->enabled_ports;
1906 dev->name = chip->dev_name;
1907 dev->duplex_reg = chip->duplex_reg;
1908 dev->vta_regs[0] = chip->vta_regs[0];
1909 dev->vta_regs[1] = chip->vta_regs[1];
1910 dev->vta_regs[2] = chip->vta_regs[2];
1911 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1912 dev->cpu_port = chip->cpu_port;
1913 dev->num_vlans = chip->vlans;
1da6df85 1914 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1915 break;
1916 }
1917 }
1918
1919 /* check which BCM5325x version we have */
1920 if (is5325(dev)) {
1921 u8 vc4;
1922
1923 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1924
1925 /* check reserved bits */
1926 switch (vc4 & 3) {
1927 case 1:
1928 /* BCM5325E */
1929 break;
1930 case 3:
1931 /* BCM5325F - do not use port 4 */
1932 dev->enabled_ports &= ~BIT(4);
1933 break;
1934 default:
1935/* On the BCM47XX SoCs this is the supported internal switch.*/
1936#ifndef CONFIG_BCM47XX
1937 /* BCM5325M */
1938 return -EINVAL;
1939#else
1940 break;
1941#endif
1942 }
1943 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1944 u64 strap_value;
1945
1946 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1947 /* use second IMP port if GMII is enabled */
1948 if (strap_value & SV_GMII_CTRL_115)
1949 dev->cpu_port = 5;
1950 }
1951
1952 /* cpu port is always last */
1953 dev->num_ports = dev->cpu_port + 1;
1954 dev->enabled_ports |= BIT(dev->cpu_port);
1955
1956 dev->ports = devm_kzalloc(dev->dev,
1957 sizeof(struct b53_port) * dev->num_ports,
1958 GFP_KERNEL);
1959 if (!dev->ports)
1960 return -ENOMEM;
1961
a2482d2c
FF		 1962 dev->vlans = devm_kzalloc(dev->dev,
1963 sizeof(struct b53_vlan) * dev->num_vlans,
1964 GFP_KERNEL);
1965 if (!dev->vlans)
1966 return -ENOMEM;
1967
967dd82f
FF		 1968 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1969 if (dev->reset_gpio >= 0) {
1970 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1971 GPIOF_OUT_INIT_HIGH, "robo_reset");
1972 if (ret)
1973 return ret;
1974 }
1975
1976 return 0;
1977}
1978
0dff88d3
JL		 1979struct b53_device *b53_switch_alloc(struct device *base,
1980 const struct b53_io_ops *ops,
967dd82f
FF		 1981 void *priv)
1982{
1983 struct dsa_switch *ds;
1984 struct b53_device *dev;
1985
a0c02161 1986 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 1987 if (!ds)
1988 return NULL;
1989
a0c02161
VD		 1990 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1991 if (!dev)
1992 return NULL;
967dd82f
FF		 1993
1994 ds->priv = dev;
967dd82f
FF		 1995 dev->dev = base;
1996
1997 dev->ds = ds;
1998 dev->priv = priv;
1999 dev->ops = ops;
485ebd61 2000 ds->ops = &b53_switch_ops;
967dd82f
FF		 2001 mutex_init(&dev->reg_mutex);
2002 mutex_init(&dev->stats_mutex);
2003
2004 return dev;
2005}
2006EXPORT_SYMBOL(b53_switch_alloc);
2007
2008int b53_switch_detect(struct b53_device *dev)
2009{
2010 u32 id32;
2011 u16 tmp;
2012 u8 id8;
2013 int ret;
2014
2015 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2016 if (ret)
2017 return ret;
2018
2019 switch (id8) {
2020 case 0:
2021 /* BCM5325 and BCM5365 do not have this register so reads
2022 * return 0. But the read operation did succeed, so assume this
2023 * is one of them.
2024 *
2025 * Next check if we can write to the 5325's VTA register; for
2026 * 5365 it is read only.
2027 */
2028 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2029 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2030
2031 if (tmp == 0xf)
2032 dev->chip_id = BCM5325_DEVICE_ID;
2033 else
2034 dev->chip_id = BCM5365_DEVICE_ID;
2035 break;
2036 case BCM5395_DEVICE_ID:
2037 case BCM5397_DEVICE_ID:
2038 case BCM5398_DEVICE_ID:
2039 dev->chip_id = id8;
2040 break;
2041 default:
2042 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2043 if (ret)
2044 return ret;
2045
2046 switch (id32) {
2047 case BCM53115_DEVICE_ID:
2048 case BCM53125_DEVICE_ID:
2049 case BCM53128_DEVICE_ID:
2050 case BCM53010_DEVICE_ID:
2051 case BCM53011_DEVICE_ID:
2052 case BCM53012_DEVICE_ID:
2053 case BCM53018_DEVICE_ID:
2054 case BCM53019_DEVICE_ID:
2055 dev->chip_id = id32;
2056 break;
2057 default:
2058 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2059 id8, id32);
2060 return -ENODEV;
2061 }
2062 }
2063
2064 if (dev->chip_id == BCM5325_DEVICE_ID)
2065 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2066 &dev->core_rev);
2067 else
2068 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2069 &dev->core_rev);
2070}
2071EXPORT_SYMBOL(b53_switch_detect);
2072
2073int b53_switch_register(struct b53_device *dev)
2074{
2075 int ret;
2076
2077 if (dev->pdata) {
2078 dev->chip_id = dev->pdata->chip_id;
2079 dev->enabled_ports = dev->pdata->enabled_ports;
2080 }
2081
2082 if (!dev->chip_id && b53_switch_detect(dev))
2083 return -EINVAL;
2084
2085 ret = b53_switch_init(dev);
2086 if (ret)
2087 return ret;
2088
2089 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2090
23c9ee49 2091 return dsa_register_switch(dev->ds);
967dd82f
FF		 2092}
2093EXPORT_SYMBOL(b53_switch_register);
2094
2095MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2096MODULE_DESCRIPTION("B53 switch library");
2097MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)