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net: dsa: propagate extack to .port_vlan_filtering
[linux-2.6-block.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
967dd82f
FF		 20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/platform_data/b53.h>
26#include <linux/phy.h>
5e004460 27#include <linux/phylink.h>
1da6df85 28#include <linux/etherdevice.h>
ff39c2d6 29#include <linux/if_bridge.h>
967dd82f
FF		 30#include <net/dsa.h>
31
32#include "b53_regs.h"
33#include "b53_priv.h"
34
35struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39};
40
41/* BCM5365 MIB counters */
42static const struct b53_mib_desc b53_mibs_65[] = {
43 { 8, 0x00, "TxOctets" },
44 { 4, 0x08, "TxDropPkts" },
45 { 4, 0x10, "TxBroadcastPkts" },
46 { 4, 0x14, "TxMulticastPkts" },
47 { 4, 0x18, "TxUnicastPkts" },
48 { 4, 0x1c, "TxCollisions" },
49 { 4, 0x20, "TxSingleCollision" },
50 { 4, 0x24, "TxMultipleCollision" },
51 { 4, 0x28, "TxDeferredTransmit" },
52 { 4, 0x2c, "TxLateCollision" },
53 { 4, 0x30, "TxExcessiveCollision" },
54 { 4, 0x38, "TxPausePkts" },
55 { 8, 0x44, "RxOctets" },
56 { 4, 0x4c, "RxUndersizePkts" },
57 { 4, 0x50, "RxPausePkts" },
58 { 4, 0x54, "Pkts64Octets" },
59 { 4, 0x58, "Pkts65to127Octets" },
60 { 4, 0x5c, "Pkts128to255Octets" },
61 { 4, 0x60, "Pkts256to511Octets" },
62 { 4, 0x64, "Pkts512to1023Octets" },
63 { 4, 0x68, "Pkts1024to1522Octets" },
64 { 4, 0x6c, "RxOversizePkts" },
65 { 4, 0x70, "RxJabbers" },
66 { 4, 0x74, "RxAlignmentErrors" },
67 { 4, 0x78, "RxFCSErrors" },
68 { 8, 0x7c, "RxGoodOctets" },
69 { 4, 0x84, "RxDropPkts" },
70 { 4, 0x88, "RxUnicastPkts" },
71 { 4, 0x8c, "RxMulticastPkts" },
72 { 4, 0x90, "RxBroadcastPkts" },
73 { 4, 0x94, "RxSAChanges" },
74 { 4, 0x98, "RxFragments" },
75};
76
77#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
78
79/* BCM63xx MIB counters */
80static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123};
124
125#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
126
127/* MIB counters */
128static const struct b53_mib_desc b53_mibs[] = {
129 { 8, 0x00, "TxOctets" },
130 { 4, 0x08, "TxDropPkts" },
131 { 4, 0x10, "TxBroadcastPkts" },
132 { 4, 0x14, "TxMulticastPkts" },
133 { 4, 0x18, "TxUnicastPkts" },
134 { 4, 0x1c, "TxCollisions" },
135 { 4, 0x20, "TxSingleCollision" },
136 { 4, 0x24, "TxMultipleCollision" },
137 { 4, 0x28, "TxDeferredTransmit" },
138 { 4, 0x2c, "TxLateCollision" },
139 { 4, 0x30, "TxExcessiveCollision" },
140 { 4, 0x38, "TxPausePkts" },
141 { 8, 0x50, "RxOctets" },
142 { 4, 0x58, "RxUndersizePkts" },
143 { 4, 0x5c, "RxPausePkts" },
144 { 4, 0x60, "Pkts64Octets" },
145 { 4, 0x64, "Pkts65to127Octets" },
146 { 4, 0x68, "Pkts128to255Octets" },
147 { 4, 0x6c, "Pkts256to511Octets" },
148 { 4, 0x70, "Pkts512to1023Octets" },
149 { 4, 0x74, "Pkts1024to1522Octets" },
150 { 4, 0x78, "RxOversizePkts" },
151 { 4, 0x7c, "RxJabbers" },
152 { 4, 0x80, "RxAlignmentErrors" },
153 { 4, 0x84, "RxFCSErrors" },
154 { 8, 0x88, "RxGoodOctets" },
155 { 4, 0x90, "RxDropPkts" },
156 { 4, 0x94, "RxUnicastPkts" },
157 { 4, 0x98, "RxMulticastPkts" },
158 { 4, 0x9c, "RxBroadcastPkts" },
159 { 4, 0xa0, "RxSAChanges" },
160 { 4, 0xa4, "RxFragments" },
161 { 4, 0xa8, "RxJumboPkts" },
162 { 4, 0xac, "RxSymbolErrors" },
163 { 4, 0xc0, "RxDiscarded" },
164};
165
166#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
167
bde5d132
FF		 168static const struct b53_mib_desc b53_mibs_58xx[] = {
169 { 8, 0x00, "TxOctets" },
170 { 4, 0x08, "TxDropPkts" },
171 { 4, 0x0c, "TxQPKTQ0" },
172 { 4, 0x10, "TxBroadcastPkts" },
173 { 4, 0x14, "TxMulticastPkts" },
174 { 4, 0x18, "TxUnicastPKts" },
175 { 4, 0x1c, "TxCollisions" },
176 { 4, 0x20, "TxSingleCollision" },
177 { 4, 0x24, "TxMultipleCollision" },
178 { 4, 0x28, "TxDeferredCollision" },
179 { 4, 0x2c, "TxLateCollision" },
180 { 4, 0x30, "TxExcessiveCollision" },
181 { 4, 0x34, "TxFrameInDisc" },
182 { 4, 0x38, "TxPausePkts" },
183 { 4, 0x3c, "TxQPKTQ1" },
184 { 4, 0x40, "TxQPKTQ2" },
185 { 4, 0x44, "TxQPKTQ3" },
186 { 4, 0x48, "TxQPKTQ4" },
187 { 4, 0x4c, "TxQPKTQ5" },
188 { 8, 0x50, "RxOctets" },
189 { 4, 0x58, "RxUndersizePkts" },
190 { 4, 0x5c, "RxPausePkts" },
191 { 4, 0x60, "RxPkts64Octets" },
192 { 4, 0x64, "RxPkts65to127Octets" },
193 { 4, 0x68, "RxPkts128to255Octets" },
194 { 4, 0x6c, "RxPkts256to511Octets" },
195 { 4, 0x70, "RxPkts512to1023Octets" },
196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
197 { 4, 0x78, "RxOversizePkts" },
198 { 4, 0x7c, "RxJabbers" },
199 { 4, 0x80, "RxAlignmentErrors" },
200 { 4, 0x84, "RxFCSErrors" },
201 { 8, 0x88, "RxGoodOctets" },
202 { 4, 0x90, "RxDropPkts" },
203 { 4, 0x94, "RxUnicastPkts" },
204 { 4, 0x98, "RxMulticastPkts" },
205 { 4, 0x9c, "RxBroadcastPkts" },
206 { 4, 0xa0, "RxSAChanges" },
207 { 4, 0xa4, "RxFragments" },
208 { 4, 0xa8, "RxJumboPkt" },
209 { 4, 0xac, "RxSymblErr" },
210 { 4, 0xb0, "InRangeErrCount" },
211 { 4, 0xb4, "OutRangeErrCount" },
212 { 4, 0xb8, "EEELpiEvent" },
213 { 4, 0xbc, "EEELpiDuration" },
214 { 4, 0xc0, "RxDiscard" },
215 { 4, 0xc8, "TxQPKTQ6" },
216 { 4, 0xcc, "TxQPKTQ7" },
217 { 4, 0xd0, "TxPkts64Octets" },
218 { 4, 0xd4, "TxPkts65to127Octets" },
219 { 4, 0xd8, "TxPkts128to255Octets" },
220 { 4, 0xdc, "TxPkts256to511Ocets" },
221 { 4, 0xe0, "TxPkts512to1023Ocets" },
222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
223};
224
225#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
226
967dd82f
FF		 227static int b53_do_vlan_op(struct b53_device *dev, u8 op)
228{
229 unsigned int i;
230
231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
232
233 for (i = 0; i < 10; i++) {
234 u8 vta;
235
236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
237 if (!(vta & VTA_START_CMD))
238 return 0;
239
240 usleep_range(100, 200);
241 }
242
243 return -EIO;
244}
245
a2482d2c
FF		 246static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
247 struct b53_vlan *vlan)
967dd82f
FF		 248{
249 if (is5325(dev)) {
250 u32 entry = 0;
251
a2482d2c
FF		 252 if (vlan->members) {
253 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
254 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 255 if (dev->core_rev >= 3)
256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
257 else
258 entry |= VA_VALID_25;
259 }
260
261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
263 VTA_RW_STATE_WR | VTA_RW_OP_EN);
264 } else if (is5365(dev)) {
265 u16 entry = 0;
266
a2482d2c
FF		 267 if (vlan->members)
268 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 270
271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
273 VTA_RW_STATE_WR | VTA_RW_OP_EN);
274 } else {
275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 277 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 278
279 b53_do_vlan_op(dev, VTA_CMD_WRITE);
280 }
a2482d2c
FF		 281
282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
283 vid, vlan->members, vlan->untag);
284}
285
286static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
287 struct b53_vlan *vlan)
288{
289 if (is5325(dev)) {
290 u32 entry = 0;
291
292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
293 VTA_RW_STATE_RD | VTA_RW_OP_EN);
294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
295
296 if (dev->core_rev >= 3)
297 vlan->valid = !!(entry & VA_VALID_25_R4);
298 else
299 vlan->valid = !!(entry & VA_VALID_25);
300 vlan->members = entry & VA_MEMBER_MASK;
301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
302
303 } else if (is5365(dev)) {
304 u16 entry = 0;
305
306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
307 VTA_RW_STATE_WR | VTA_RW_OP_EN);
308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
309
310 vlan->valid = !!(entry & VA_VALID_65);
311 vlan->members = entry & VA_MEMBER_MASK;
312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
313 } else {
314 u32 entry = 0;
315
316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
317 b53_do_vlan_op(dev, VTA_CMD_READ);
318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
319 vlan->members = entry & VTE_MEMBERS;
320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
321 vlan->valid = true;
322 }
967dd82f
FF		 323}
324
a2482d2c 325static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 326{
327 u8 mgmt;
328
329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
330
331 if (enable)
332 mgmt |= SM_SW_FWD_EN;
333 else
334 mgmt &= ~SM_SW_FWD_EN;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de 337
7edc58d6 338 /* Include IMP port in dumb forwarding mode
a424f0de 339 */
7edc58d6
FF		 340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
341 mgmt |= B53_MII_DUMB_FWDG_EN;
342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
53568438
FF		 343
344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
345 * frames should be flooded or not.
346 */
347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
63cc54a6 348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
53568438 349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
967dd82f
FF		 350}
351
dad8d7c6
FF		 352static void b53_enable_vlan(struct b53_device *dev, bool enable,
353 bool enable_filtering)
967dd82f
FF		 354{
355 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
360
361 if (is5325(dev) || is5365(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
364 } else if (is63xx(dev)) {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
367 } else {
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 }
371
967dd82f
FF		 372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
dad8d7c6
FF		 376 if (enable_filtering) {
377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
378 vc5 |= VC5_DROP_VTABLE_MISS;
379 } else {
380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
381 vc5 &= ~VC5_DROP_VTABLE_MISS;
382 }
967dd82f
FF		 383
384 if (is5325(dev))
385 vc0 &= ~VC0_RESERVED_1;
386
387 if (is5325(dev) || is5365(dev))
388 vc1 |= VC1_RX_MCST_TAG_EN;
389
967dd82f
FF		 390 } else {
391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
393 vc4 &= ~VC4_ING_VID_CHECK_MASK;
394 vc5 &= ~VC5_DROP_VTABLE_MISS;
395
396 if (is5325(dev) || is5365(dev))
397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
398 else
399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
400
401 if (is5325(dev) || is5365(dev))
402 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 403 }
404
a2482d2c
FF		 405 if (!is5325(dev) && !is5365(dev))
406 vc5 &= ~VC5_VID_FFF_EN;
407
967dd82f
FF		 408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
410
411 if (is5325(dev) || is5365(dev)) {
412 /* enable the high 8 bit vid check on 5325 */
413 if (is5325(dev) && enable)
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
415 VC3_HIGH_8BIT_EN);
416 else
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
418
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
421 } else if (is63xx(dev)) {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
425 } else {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
429 }
430
431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
dad8d7c6
FF		 432
433 dev->vlan_enabled = enable;
967dd82f
FF		 434}
435
436static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
437{
438 u32 port_mask = 0;
439 u16 max_size = JMS_MIN_SIZE;
440
441 if (is5325(dev) || is5365(dev))
442 return -EINVAL;
443
444 if (enable) {
445 port_mask = dev->enabled_ports;
446 max_size = JMS_MAX_SIZE;
447 if (allow_10_100)
448 port_mask |= JPM_10_100_JUMBO_EN;
449 }
450
451 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
452 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
453}
454
ff39c2d6 455static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 456{
457 unsigned int i;
458
459 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 460 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 461
462 for (i = 0; i < 10; i++) {
463 u8 fast_age_ctrl;
464
465 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
466 &fast_age_ctrl);
467
468 if (!(fast_age_ctrl & FAST_AGE_DONE))
469 goto out;
470
471 msleep(1);
472 }
473
474 return -ETIMEDOUT;
475out:
476 /* Only age dynamic entries (default behavior) */
477 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
478 return 0;
479}
480
ff39c2d6
FF		 481static int b53_fast_age_port(struct b53_device *dev, int port)
482{
483 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
484
485 return b53_flush_arl(dev, FAST_AGE_PORT);
486}
487
a2482d2c
FF		 488static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
489{
490 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
491
492 return b53_flush_arl(dev, FAST_AGE_VLAN);
493}
494
aac02867 495void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 496{
04bed143 497 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 498 unsigned int i;
499 u16 pvlan;
500
501 /* Enable the IMP port to be in the same VLAN as the other ports
502 * on a per-port basis such that we only have Port i and IMP in
503 * the same VLAN.
504 */
505 b53_for_each_port(dev, i) {
506 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
507 pvlan |= BIT(cpu_port);
508 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
509 }
510}
aac02867 511EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 512
a8b659e7
VO		 513static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
514 bool unicast)
515{
516 u16 uc;
517
518 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
519 if (unicast)
520 uc |= BIT(port);
521 else
522 uc &= ~BIT(port);
523 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
524}
525
526static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
527 bool multicast)
528{
529 u16 mc;
530
531 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
532 if (multicast)
533 mc |= BIT(port);
534 else
535 mc &= ~BIT(port);
536 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
537
538 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
539 if (multicast)
540 mc |= BIT(port);
541 else
542 mc &= ~BIT(port);
543 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
544}
545
f86ad77f 546int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 547{
04bed143 548 struct b53_device *dev = ds->priv;
74be4bab 549 unsigned int cpu_port;
8ca7c160 550 int ret = 0;
ff39c2d6 551 u16 pvlan;
967dd82f 552
74be4bab
VD		 553 if (!dsa_is_user_port(ds, port))
554 return 0;
555
68bb8ea8 556 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
74be4bab 557
a8b659e7
VO		 558 b53_port_set_ucast_flood(dev, port, true);
559 b53_port_set_mcast_flood(dev, port, true);
63cc54a6 560
8ca7c160
FF		 561 if (dev->ops->irq_enable)
562 ret = dev->ops->irq_enable(dev, port);
563 if (ret)
564 return ret;
565
967dd82f
FF		 566 /* Clear the Rx and Tx disable bits and set to no spanning tree */
567 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
568
ff39c2d6
FF		 569 /* Set this port, and only this one to be in the default VLAN,
570 * if member of a bridge, restore its membership prior to
571 * bringing down this port.
572 */
573 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
574 pvlan &= ~0x1ff;
575 pvlan |= BIT(port);
576 pvlan |= dev->ports[port].vlan_ctl_mask;
577 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
578
579 b53_imp_vlan_setup(ds, cpu_port);
580
f43a2dbe
FF		 581 /* If EEE was enabled, restore it */
582 if (dev->ports[port].eee.eee_enabled)
583 b53_eee_enable_set(ds, port, true);
584
967dd82f
FF		 585 return 0;
586}
f86ad77f 587EXPORT_SYMBOL(b53_enable_port);
967dd82f 588
75104db0 589void b53_disable_port(struct dsa_switch *ds, int port)
967dd82f 590{
04bed143 591 struct b53_device *dev = ds->priv;
967dd82f
FF		 592 u8 reg;
593
594 /* Disable Tx/Rx for the port */
595 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
596 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
597 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
8ca7c160
FF		 598
599 if (dev->ops->irq_disable)
600 dev->ops->irq_disable(dev, port);
967dd82f 601}
f86ad77f 602EXPORT_SYMBOL(b53_disable_port);
967dd82f 603
b409a9ef
FF		 604void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
605{
606 struct b53_device *dev = ds->priv;
4d776482 607 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
b409a9ef
FF		 608 u8 hdr_ctl, val;
609 u16 reg;
610
611 /* Resolve which bit controls the Broadcom tag */
612 switch (port) {
613 case 8:
614 val = BRCM_HDR_P8_EN;
615 break;
616 case 7:
617 val = BRCM_HDR_P7_EN;
618 break;
619 case 5:
620 val = BRCM_HDR_P5_EN;
621 break;
622 default:
623 val = 0;
624 break;
625 }
626
8fab459e
FF		 627 /* Enable management mode if tagging is requested */
628 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
629 if (tag_en)
630 hdr_ctl |= SM_SW_FWD_MODE;
631 else
632 hdr_ctl &= ~SM_SW_FWD_MODE;
633 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
634
635 /* Configure the appropriate IMP port */
636 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
637 if (port == 8)
638 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
639 else if (port == 5)
640 hdr_ctl |= GC_FRM_MGMT_PORT_M;
641 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
642
b409a9ef
FF		 643 /* Enable Broadcom tags for IMP port */
644 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 645 if (tag_en)
646 hdr_ctl |= val;
647 else
648 hdr_ctl &= ~val;
b409a9ef
FF		 649 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
650
651 /* Registers below are only accessible on newer devices */
652 if (!is58xx(dev))
653 return;
654
655 /* Enable reception Broadcom tag for CPU TX (switch RX) to
656 * allow us to tag outgoing frames
657 */
658 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 659 if (tag_en)
660 reg &= ~BIT(port);
661 else
662 reg |= BIT(port);
b409a9ef
FF		 663 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
664
665 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
666 * allow delivering frames to the per-port net_devices
667 */
668 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 669 if (tag_en)
670 reg &= ~BIT(port);
671 else
672 reg |= BIT(port);
b409a9ef
FF		 673 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
674}
675EXPORT_SYMBOL(b53_brcm_hdr_setup);
676
299752a7 677static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 678{
967dd82f
FF		 679 u8 port_ctrl;
680
681 /* BCM5325 CPU port is at 8 */
299752a7
FF		 682 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
683 port = B53_CPU_PORT;
967dd82f
FF		 684
685 port_ctrl = PORT_CTRL_RX_BCST_EN |
686 PORT_CTRL_RX_MCST_EN |
687 PORT_CTRL_RX_UCST_EN;
299752a7 688 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
7edc58d6
FF		 689
690 b53_brcm_hdr_setup(dev->ds, port);
63cc54a6 691
a8b659e7
VO		 692 b53_port_set_ucast_flood(dev, port, true);
693 b53_port_set_mcast_flood(dev, port, true);
967dd82f
FF		 694}
695
696static void b53_enable_mib(struct b53_device *dev)
697{
698 u8 gc;
699
700 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
701 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
702 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
703}
704
fea83353
FF		 705static u16 b53_default_pvid(struct b53_device *dev)
706{
707 if (is5325(dev) || is5365(dev))
708 return 1;
709 else
710 return 0;
711}
712
5c1a6eaf 713int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 714{
5c1a6eaf 715 struct b53_device *dev = ds->priv;
a2482d2c 716 struct b53_vlan vl = { 0 };
d7a0b1f7 717 struct b53_vlan *v;
fea83353 718 int i, def_vid;
d7a0b1f7 719 u16 vid;
fea83353
FF		 720
721 def_vid = b53_default_pvid(dev);
967dd82f
FF		 722
723 /* clear all vlan entries */
724 if (is5325(dev) || is5365(dev)) {
fea83353 725 for (i = def_vid; i < dev->num_vlans; i++)
a2482d2c 726 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 727 } else {
728 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
729 }
730
df373702 731 b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);
967dd82f
FF		 732
733 b53_for_each_port(dev, i)
734 b53_write16(dev, B53_VLAN_PAGE,
fea83353 735 B53_VLAN_PORT_DEF_TAG(i), def_vid);
967dd82f 736
d7a0b1f7
FF		 737 /* Upon initial call we have not set-up any VLANs, but upon
738 * system resume, we need to restore all VLAN entries.
739 */
740 for (vid = def_vid; vid < dev->num_vlans; vid++) {
741 v = &dev->vlans[vid];
742
743 if (!v->members)
744 continue;
745
746 b53_set_vlan_entry(dev, vid, v);
747 b53_fast_age_vlan(dev, vid);
748 }
749
967dd82f
FF		 750 return 0;
751}
5c1a6eaf 752EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 753
754static void b53_switch_reset_gpio(struct b53_device *dev)
755{
756 int gpio = dev->reset_gpio;
757
758 if (gpio < 0)
759 return;
760
761 /* Reset sequence: RESET low(50ms)->high(20ms)
762 */
763 gpio_set_value(gpio, 0);
764 mdelay(50);
765
766 gpio_set_value(gpio, 1);
767 mdelay(20);
768
769 dev->current_page = 0xff;
770}
771
772static int b53_switch_reset(struct b53_device *dev)
773{
3fb22b05
FF		 774 unsigned int timeout = 1000;
775 u8 mgmt, reg;
967dd82f
FF		 776
777 b53_switch_reset_gpio(dev);
778
779 if (is539x(dev)) {
780 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
781 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
782 }
783
3fb22b05
FF		 784 /* This is specific to 58xx devices here, do not use is58xx() which
785 * covers the larger Starfigther 2 family, including 7445/7278 which
786 * still use this driver as a library and need to perform the reset
787 * earlier.
788 */
5040cc99
AP		 789 if (dev->chip_id == BCM58XX_DEVICE_ID ||
790 dev->chip_id == BCM583XX_DEVICE_ID) {
3fb22b05
FF		 791 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
792 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
793 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
794
795 do {
796 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
797 if (!(reg & SW_RST))
798 break;
799
800 usleep_range(1000, 2000);
801 } while (timeout-- > 0);
802
434d2312
PB		 803 if (timeout == 0) {
804 dev_err(dev->dev,
805 "Timeout waiting for SW_RST to clear!\n");
3fb22b05 806 return -ETIMEDOUT;
434d2312 807 }
3fb22b05
FF		 808 }
809
967dd82f
FF		 810 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
811
812 if (!(mgmt & SM_SW_FWD_EN)) {
813 mgmt &= ~SM_SW_FWD_MODE;
814 mgmt |= SM_SW_FWD_EN;
815
816 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
817 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
818
819 if (!(mgmt & SM_SW_FWD_EN)) {
820 dev_err(dev->dev, "Failed to enable switch!\n");
821 return -EINVAL;
822 }
823 }
824
825 b53_enable_mib(dev);
826
ff39c2d6 827 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 828}
829
830static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
831{
04bed143 832 struct b53_device *priv = ds->priv;
967dd82f
FF		 833 u16 value = 0;
834 int ret;
835
836 if (priv->ops->phy_read16)
837 ret = priv->ops->phy_read16(priv, addr, reg, &value);
838 else
839 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
840 reg * 2, &value);
841
842 return ret ? ret : value;
843}
844
845static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
846{
04bed143 847 struct b53_device *priv = ds->priv;
967dd82f
FF		 848
849 if (priv->ops->phy_write16)
850 return priv->ops->phy_write16(priv, addr, reg, val);
851
852 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
853}
854
855static int b53_reset_switch(struct b53_device *priv)
856{
857 /* reset vlans */
a2482d2c 858 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 859 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
860
0e01491d
FF		 861 priv->serdes_lane = B53_INVALID_LANE;
862
967dd82f
FF		 863 return b53_switch_reset(priv);
864}
865
866static int b53_apply_config(struct b53_device *priv)
867{
868 /* disable switching */
869 b53_set_forwarding(priv, 0);
870
5c1a6eaf 871 b53_configure_vlan(priv->ds);
967dd82f
FF		 872
873 /* enable switching */
874 b53_set_forwarding(priv, 1);
875
876 return 0;
877}
878
879static void b53_reset_mib(struct b53_device *priv)
880{
881 u8 gc;
882
883 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
884
885 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
886 msleep(1);
887 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
888 msleep(1);
889}
890
891static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
892{
893 if (is5365(dev))
894 return b53_mibs_65;
895 else if (is63xx(dev))
896 return b53_mibs_63xx;
bde5d132
FF		 897 else if (is58xx(dev))
898 return b53_mibs_58xx;
967dd82f
FF		 899 else
900 return b53_mibs;
901}
902
903static unsigned int b53_get_mib_size(struct b53_device *dev)
904{
905 if (is5365(dev))
906 return B53_MIBS_65_SIZE;
907 else if (is63xx(dev))
908 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 909 else if (is58xx(dev))
910 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 911 else
912 return B53_MIBS_SIZE;
913}
914
c7d28c9d
FF		 915static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
916{
917 /* These ports typically do not have built-in PHYs */
918 switch (port) {
919 case B53_CPU_PORT_25:
920 case 7:
921 case B53_CPU_PORT:
922 return NULL;
923 }
924
925 return mdiobus_get_phy(ds->slave_mii_bus, port);
926}
927
89f09048
FF		 928void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
929 uint8_t *data)
967dd82f 930{
04bed143 931 struct b53_device *dev = ds->priv;
967dd82f
FF		 932 const struct b53_mib_desc *mibs = b53_get_mib(dev);
933 unsigned int mib_size = b53_get_mib_size(dev);
c7d28c9d 934 struct phy_device *phydev;
967dd82f
FF		 935 unsigned int i;
936
c7d28c9d
FF		 937 if (stringset == ETH_SS_STATS) {
938 for (i = 0; i < mib_size; i++)
939 strlcpy(data + i * ETH_GSTRING_LEN,
940 mibs[i].name, ETH_GSTRING_LEN);
941 } else if (stringset == ETH_SS_PHY_STATS) {
942 phydev = b53_get_phy_device(ds, port);
943 if (!phydev)
944 return;
89f09048 945
c7d28c9d
FF		 946 phy_ethtool_get_strings(phydev, data);
947 }
967dd82f 948}
3117455d 949EXPORT_SYMBOL(b53_get_strings);
967dd82f 950
3117455d 951void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 952{
04bed143 953 struct b53_device *dev = ds->priv;
967dd82f
FF		 954 const struct b53_mib_desc *mibs = b53_get_mib(dev);
955 unsigned int mib_size = b53_get_mib_size(dev);
956 const struct b53_mib_desc *s;
957 unsigned int i;
958 u64 val = 0;
959
960 if (is5365(dev) && port == 5)
961 port = 8;
962
963 mutex_lock(&dev->stats_mutex);
964
965 for (i = 0; i < mib_size; i++) {
966 s = &mibs[i];
967
51dca8a1 968 if (s->size == 8) {
967dd82f
FF		 969 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
970 } else {
971 u32 val32;
972
973 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
974 &val32);
975 val = val32;
976 }
977 data[i] = (u64)val;
978 }
979
980 mutex_unlock(&dev->stats_mutex);
981}
3117455d 982EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 983
c7d28c9d
FF		 984void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
985{
986 struct phy_device *phydev;
987
988 phydev = b53_get_phy_device(ds, port);
989 if (!phydev)
990 return;
991
992 phy_ethtool_get_stats(phydev, NULL, data);
993}
994EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
995
89f09048 996int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
967dd82f 997{
04bed143 998 struct b53_device *dev = ds->priv;
c7d28c9d 999 struct phy_device *phydev;
967dd82f 1000
c7d28c9d
FF		 1001 if (sset == ETH_SS_STATS) {
1002 return b53_get_mib_size(dev);
1003 } else if (sset == ETH_SS_PHY_STATS) {
1004 phydev = b53_get_phy_device(ds, port);
1005 if (!phydev)
1006 return 0;
1007
1008 return phy_ethtool_get_sset_count(phydev);
1009 }
89f09048 1010
c7d28c9d 1011 return 0;
967dd82f 1012}
3117455d 1013EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 1014
4f6a5caf
FF		 1015enum b53_devlink_resource_id {
1016 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1017};
1018
1019static u64 b53_devlink_vlan_table_get(void *priv)
1020{
1021 struct b53_device *dev = priv;
1022 struct b53_vlan *vl;
1023 unsigned int i;
1024 u64 count = 0;
1025
1026 for (i = 0; i < dev->num_vlans; i++) {
1027 vl = &dev->vlans[i];
1028 if (vl->members)
1029 count++;
1030 }
1031
1032 return count;
1033}
1034
1035int b53_setup_devlink_resources(struct dsa_switch *ds)
1036{
1037 struct devlink_resource_size_params size_params;
1038 struct b53_device *dev = ds->priv;
1039 int err;
1040
1041 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1042 dev->num_vlans,
1043 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1044
1045 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1046 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1047 DEVLINK_RESOURCE_ID_PARENT_TOP,
1048 &size_params);
1049 if (err)
1050 goto out;
1051
1052 dsa_devlink_resource_occ_get_register(ds,
1053 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1054 b53_devlink_vlan_table_get, dev);
1055
1056 return 0;
1057out:
1058 dsa_devlink_resources_unregister(ds);
1059 return err;
1060}
1061EXPORT_SYMBOL(b53_setup_devlink_resources);
1062
967dd82f
FF		 1063static int b53_setup(struct dsa_switch *ds)
1064{
04bed143 1065 struct b53_device *dev = ds->priv;
967dd82f
FF		 1066 unsigned int port;
1067 int ret;
1068
1069 ret = b53_reset_switch(dev);
1070 if (ret) {
1071 dev_err(ds->dev, "failed to reset switch\n");
1072 return ret;
1073 }
1074
1075 b53_reset_mib(dev);
1076
1077 ret = b53_apply_config(dev);
4f6a5caf 1078 if (ret) {
967dd82f 1079 dev_err(ds->dev, "failed to apply configuration\n");
4f6a5caf
FF		 1080 return ret;
1081 }
967dd82f 1082
75dad252 1083 /* Configure IMP/CPU port, disable all other ports. Enabled
34c8befd
FF		 1084 * ports will be configured with .port_enable
1085 */
967dd82f 1086 for (port = 0; port < dev->num_ports; port++) {
34c8befd 1087 if (dsa_is_cpu_port(ds, port))
299752a7 1088 b53_enable_cpu_port(dev, port);
75dad252 1089 else
75104db0 1090 b53_disable_port(ds, port);
967dd82f
FF		 1091 }
1092
7228b23e
VO		 1093 /* Let DSA handle the case were multiple bridges span the same switch
1094 * device and different VLAN awareness settings are requested, which
1095 * would be breaking filtering semantics for any of the other bridge
1096 * devices. (not hardware supported)
1097 */
1098 ds->vlan_filtering_is_global = true;
1099
4f6a5caf
FF		 1100 return b53_setup_devlink_resources(ds);
1101}
1102
1103static void b53_teardown(struct dsa_switch *ds)
1104{
1105 dsa_devlink_resources_unregister(ds);
967dd82f
FF		 1106}
1107
5e004460 1108static void b53_force_link(struct b53_device *dev, int port, int link)
967dd82f 1109{
5e004460 1110 u8 reg, val, off;
967dd82f
FF		 1111
1112 /* Override the port settings */
1113 if (port == dev->cpu_port) {
1114 off = B53_PORT_OVERRIDE_CTRL;
5e004460 1115 val = PORT_OVERRIDE_EN;
967dd82f
FF		 1116 } else {
1117 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
5e004460 1118 val = GMII_PO_EN;
967dd82f
FF		 1119 }
1120
5e004460
FF		 1121 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1122 reg |= val;
1123 if (link)
967dd82f 1124 reg |= PORT_OVERRIDE_LINK;
5e004460
FF		 1125 else
1126 reg &= ~PORT_OVERRIDE_LINK;
1127 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1128}
1129
1130static void b53_force_port_config(struct b53_device *dev, int port,
3cad1c8b
RK		 1131 int speed, int duplex,
1132 bool tx_pause, bool rx_pause)
5e004460
FF		 1133{
1134 u8 reg, val, off;
1135
1136 /* Override the port settings */
1137 if (port == dev->cpu_port) {
1138 off = B53_PORT_OVERRIDE_CTRL;
1139 val = PORT_OVERRIDE_EN;
1140 } else {
1141 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1142 val = GMII_PO_EN;
1143 }
967dd82f 1144
5e004460
FF		 1145 b53_read8(dev, B53_CTRL_PAGE, off, &reg);
1146 reg |= val;
1147 if (duplex == DUPLEX_FULL)
967dd82f 1148 reg |= PORT_OVERRIDE_FULL_DUPLEX;
5e004460
FF		 1149 else
1150 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
967dd82f 1151
5e004460 1152 switch (speed) {
967dd82f
FF		 1153 case 2000:
1154 reg |= PORT_OVERRIDE_SPEED_2000M;
df561f66 1155 fallthrough;
967dd82f
FF		 1156 case SPEED_1000:
1157 reg |= PORT_OVERRIDE_SPEED_1000M;
1158 break;
1159 case SPEED_100:
1160 reg |= PORT_OVERRIDE_SPEED_100M;
1161 break;
1162 case SPEED_10:
1163 reg |= PORT_OVERRIDE_SPEED_10M;
1164 break;
1165 default:
5e004460 1166 dev_err(dev->dev, "unknown speed: %d\n", speed);
967dd82f
FF		 1167 return;
1168 }
1169
3cad1c8b 1170 if (rx_pause)
5e004460 1171 reg |= PORT_OVERRIDE_RX_FLOW;
3cad1c8b 1172 if (tx_pause)
5e004460
FF		 1173 reg |= PORT_OVERRIDE_TX_FLOW;
1174
1175 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1176}
1177
1178static void b53_adjust_link(struct dsa_switch *ds, int port,
1179 struct phy_device *phydev)
1180{
1181 struct b53_device *dev = ds->priv;
1182 struct ethtool_eee *p = &dev->ports[port].eee;
1183 u8 rgmii_ctrl = 0, reg = 0, off;
3cad1c8b
RK		 1184 bool tx_pause = false;
1185 bool rx_pause = false;
5e004460
FF		 1186
1187 if (!phy_is_pseudo_fixed_link(phydev))
1188 return;
1189
967dd82f
FF		 1190 /* Enable flow control on BCM5301x's CPU port */
1191 if (is5301x(dev) && port == dev->cpu_port)
3cad1c8b 1192 tx_pause = rx_pause = true;
967dd82f
FF		 1193
1194 if (phydev->pause) {
1195 if (phydev->asym_pause)
3cad1c8b
RK		 1196 tx_pause = true;
1197 rx_pause = true;
967dd82f
FF		 1198 }
1199
3cad1c8b
RK		 1200 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1201 tx_pause, rx_pause);
5e004460 1202 b53_force_link(dev, port, phydev->link);
967dd82f
FF		 1203
1204 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1205 if (port == 8)
1206 off = B53_RGMII_CTRL_IMP;
1207 else
1208 off = B53_RGMII_CTRL_P(port);
1209
1210 /* Configure the port RGMII clock delay by DLL disabled and
1211 * tx_clk aligned timing (restoring to reset defaults)
1212 */
1213 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1214 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1215 RGMII_CTRL_TIMING_SEL);
1216
1217 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1218 * sure that we enable the port TX clock internal delay to
1219 * account for this internal delay that is inserted, otherwise
1220 * the switch won't be able to receive correctly.
1221 *
1222 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1223 * any delay neither on transmission nor reception, so the
1224 * BCM53125 must also be configured accordingly to account for
1225 * the lack of delay and introduce
1226 *
1227 * The BCM53125 switch has its RX clock and TX clock control
1228 * swapped, hence the reason why we modify the TX clock path in
1229 * the "RGMII" case
1230 */
1231 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1232 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1233 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1234 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1235 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1236 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1237
1238 dev_info(ds->dev, "Configured port %d for %s\n", port,
1239 phy_modes(phydev->interface));
1240 }
1241
1242 /* configure MII port if necessary */
1243 if (is5325(dev)) {
1244 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1245 &reg);
1246
1247 /* reverse mii needs to be enabled */
1248 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1249 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1250 reg | PORT_OVERRIDE_RV_MII_25);
1251 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1252 &reg);
1253
1254 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1255 dev_err(ds->dev,
1256 "Failed to enable reverse MII mode\n");
1257 return;
1258 }
1259 }
1260 } else if (is5301x(dev)) {
1261 if (port != dev->cpu_port) {
5e004460 1262 b53_force_port_config(dev, dev->cpu_port, 2000,
3cad1c8b 1263 DUPLEX_FULL, true, true);
5e004460 1264 b53_force_link(dev, dev->cpu_port, 1);
967dd82f
FF		 1265 }
1266 }
f43a2dbe
FF		 1267
1268 /* Re-negotiate EEE if it was enabled already */
1269 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1270}
1271
a8e8b985
FF		 1272void b53_port_event(struct dsa_switch *ds, int port)
1273{
1274 struct b53_device *dev = ds->priv;
1275 bool link;
1276 u16 sts;
1277
1278 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1279 link = !!(sts & BIT(port));
1280 dsa_port_phylink_mac_change(ds, port, link);
1281}
1282EXPORT_SYMBOL(b53_port_event);
1283
1284void b53_phylink_validate(struct dsa_switch *ds, int port,
1285 unsigned long *supported,
1286 struct phylink_link_state *state)
1287{
1288 struct b53_device *dev = ds->priv;
1289 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1290
0e01491d
FF		 1291 if (dev->ops->serdes_phylink_validate)
1292 dev->ops->serdes_phylink_validate(dev, port, mask, state);
1293
a8e8b985
FF		 1294 /* Allow all the expected bits */
1295 phylink_set(mask, Autoneg);
1296 phylink_set_port_modes(mask);
1297 phylink_set(mask, Pause);
1298 phylink_set(mask, Asym_Pause);
1299
1300 /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1301 * support Gigabit, including Half duplex.
1302 */
1303 if (state->interface != PHY_INTERFACE_MODE_MII &&
1304 state->interface != PHY_INTERFACE_MODE_REVMII &&
1305 !phy_interface_mode_is_8023z(state->interface) &&
1306 !(is5325(dev) || is5365(dev))) {
1307 phylink_set(mask, 1000baseT_Full);
1308 phylink_set(mask, 1000baseT_Half);
1309 }
1310
1311 if (!phy_interface_mode_is_8023z(state->interface)) {
1312 phylink_set(mask, 10baseT_Half);
1313 phylink_set(mask, 10baseT_Full);
1314 phylink_set(mask, 100baseT_Half);
1315 phylink_set(mask, 100baseT_Full);
1316 }
1317
1318 bitmap_and(supported, supported, mask,
1319 __ETHTOOL_LINK_MODE_MASK_NBITS);
1320 bitmap_and(state->advertising, state->advertising, mask,
1321 __ETHTOOL_LINK_MODE_MASK_NBITS);
1322
1323 phylink_helper_basex_speed(state);
1324}
1325EXPORT_SYMBOL(b53_phylink_validate);
1326
1327int b53_phylink_mac_link_state(struct dsa_switch *ds, int port,
1328 struct phylink_link_state *state)
1329{
0e01491d 1330 struct b53_device *dev = ds->priv;
a8e8b985
FF		 1331 int ret = -EOPNOTSUPP;
1332
55a4d2ea
FF		 1333 if ((phy_interface_mode_is_8023z(state->interface) ||
1334 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1335 dev->ops->serdes_link_state)
0e01491d
FF		 1336 ret = dev->ops->serdes_link_state(dev, port, state);
1337
a8e8b985
FF		 1338 return ret;
1339}
1340EXPORT_SYMBOL(b53_phylink_mac_link_state);
1341
1342void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1343 unsigned int mode,
1344 const struct phylink_link_state *state)
1345{
1346 struct b53_device *dev = ds->priv;
1347
ab017b79 1348 if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED)
a8e8b985
FF		 1349 return;
1350
55a4d2ea
FF		 1351 if ((phy_interface_mode_is_8023z(state->interface) ||
1352 state->interface == PHY_INTERFACE_MODE_SGMII) &&
1353 dev->ops->serdes_config)
0e01491d 1354 dev->ops->serdes_config(dev, port, mode, state);
a8e8b985
FF		 1355}
1356EXPORT_SYMBOL(b53_phylink_mac_config);
1357
1358void b53_phylink_mac_an_restart(struct dsa_switch *ds, int port)
1359{
0e01491d
FF		 1360 struct b53_device *dev = ds->priv;
1361
1362 if (dev->ops->serdes_an_restart)
1363 dev->ops->serdes_an_restart(dev, port);
a8e8b985
FF		 1364}
1365EXPORT_SYMBOL(b53_phylink_mac_an_restart);
1366
1367void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1368 unsigned int mode,
1369 phy_interface_t interface)
1370{
1371 struct b53_device *dev = ds->priv;
1372
1373 if (mode == MLO_AN_PHY)
1374 return;
1375
1376 if (mode == MLO_AN_FIXED) {
1377 b53_force_link(dev, port, false);
1378 return;
1379 }
0e01491d
FF		 1380
1381 if (phy_interface_mode_is_8023z(interface) &&
1382 dev->ops->serdes_link_set)
1383 dev->ops->serdes_link_set(dev, port, mode, interface, false);
a8e8b985
FF		 1384}
1385EXPORT_SYMBOL(b53_phylink_mac_link_down);
1386
1387void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1388 unsigned int mode,
1389 phy_interface_t interface,
5b502a7b
RK		 1390 struct phy_device *phydev,
1391 int speed, int duplex,
1392 bool tx_pause, bool rx_pause)
a8e8b985
FF		 1393{
1394 struct b53_device *dev = ds->priv;
1395
1396 if (mode == MLO_AN_PHY)
1397 return;
1398
1399 if (mode == MLO_AN_FIXED) {
ab017b79
RK		 1400 b53_force_port_config(dev, port, speed, duplex,
1401 tx_pause, rx_pause);
a8e8b985
FF		 1402 b53_force_link(dev, port, true);
1403 return;
1404 }
0e01491d
FF		 1405
1406 if (phy_interface_mode_is_8023z(interface) &&
1407 dev->ops->serdes_link_set)
1408 dev->ops->serdes_link_set(dev, port, mode, interface, true);
a8e8b985
FF		 1409}
1410EXPORT_SYMBOL(b53_phylink_mac_link_up);
1411
89153ed6
VO		 1412int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1413 struct netlink_ext_ack *extack)
a2482d2c 1414{
dad8d7c6 1415 struct b53_device *dev = ds->priv;
dad8d7c6
FF		 1416
1417 b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);
1418
a2482d2c
FF		 1419 return 0;
1420}
3117455d 1421EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1422
1958d581
VO		 1423static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1424 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1425{
04bed143 1426 struct b53_device *dev = ds->priv;
a2482d2c 1427
b7a9e0da 1428 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
a2482d2c
FF		 1429 return -EOPNOTSUPP;
1430
88631864
FF		 1431 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1432 * receiving VLAN tagged frames at all, we can still allow the port to
1433 * be configured for egress untagged.
1434 */
1435 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1436 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1437 return -EINVAL;
1438
0fe2f273 1439 if (vlan->vid >= dev->num_vlans)
a2482d2c
FF		 1440 return -ERANGE;
1441
e74f014e 1442 b53_enable_vlan(dev, true, ds->vlan_filtering);
a2482d2c
FF		 1443
1444 return 0;
1445}
1446
1958d581 1447int b53_vlan_add(struct dsa_switch *ds, int port,
31046a5f
VO		 1448 const struct switchdev_obj_port_vlan *vlan,
1449 struct netlink_ext_ack *extack)
a2482d2c 1450{
04bed143 1451 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1452 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1453 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c 1454 struct b53_vlan *vl;
1958d581
VO		 1455 int err;
1456
1457 err = b53_vlan_prepare(ds, port, vlan);
1458 if (err)
1459 return err;
a2482d2c 1460
b7a9e0da 1461 vl = &dev->vlans[vlan->vid];
a2482d2c 1462
b7a9e0da 1463 b53_get_vlan_entry(dev, vlan->vid, vl);
a2482d2c 1464
b7a9e0da
VO		 1465 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1466 untagged = true;
d965a543 1467
b7a9e0da
VO		 1468 vl->members |= BIT(port);
1469 if (untagged && !dsa_is_cpu_port(ds, port))
1470 vl->untag |= BIT(port);
1471 else
1472 vl->untag &= ~BIT(port);
a2482d2c 1473
b7a9e0da
VO		 1474 b53_set_vlan_entry(dev, vlan->vid, vl);
1475 b53_fast_age_vlan(dev, vlan->vid);
a2482d2c 1476
10163aae 1477 if (pvid && !dsa_is_cpu_port(ds, port)) {
a2482d2c 1478 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
b7a9e0da
VO		 1479 vlan->vid);
1480 b53_fast_age_vlan(dev, vlan->vid);
a2482d2c 1481 }
1958d581
VO		 1482
1483 return 0;
a2482d2c 1484}
3117455d 1485EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1486
3117455d
FF		 1487int b53_vlan_del(struct dsa_switch *ds, int port,
1488 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1489{
04bed143 1490 struct b53_device *dev = ds->priv;
a2482d2c 1491 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c 1492 struct b53_vlan *vl;
a2482d2c
FF		 1493 u16 pvid;
1494
1495 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1496
b7a9e0da 1497 vl = &dev->vlans[vlan->vid];
a2482d2c 1498
b7a9e0da 1499 b53_get_vlan_entry(dev, vlan->vid, vl);
a2482d2c 1500
b7a9e0da 1501 vl->members &= ~BIT(port);
a2482d2c 1502
b7a9e0da
VO		 1503 if (pvid == vlan->vid)
1504 pvid = b53_default_pvid(dev);
a2482d2c 1505
b7a9e0da
VO		 1506 if (untagged && !dsa_is_cpu_port(ds, port))
1507 vl->untag &= ~(BIT(port));
a2482d2c 1508
b7a9e0da
VO		 1509 b53_set_vlan_entry(dev, vlan->vid, vl);
1510 b53_fast_age_vlan(dev, vlan->vid);
a2482d2c
FF		 1511
1512 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1513 b53_fast_age_vlan(dev, pvid);
1514
1515 return 0;
1516}
3117455d 1517EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1518
1da6df85
FF		 1519/* Address Resolution Logic routines */
1520static int b53_arl_op_wait(struct b53_device *dev)
1521{
1522 unsigned int timeout = 10;
1523 u8 reg;
1524
1525 do {
1526 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1527 if (!(reg & ARLTBL_START_DONE))
1528 return 0;
1529
1530 usleep_range(1000, 2000);
1531 } while (timeout--);
1532
1533 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1534
1535 return -ETIMEDOUT;
1536}
1537
1538static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1539{
1540 u8 reg;
1541
1542 if (op > ARLTBL_RW)
1543 return -EINVAL;
1544
1545 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1546 reg |= ARLTBL_START_DONE;
1547 if (op)
1548 reg |= ARLTBL_RW;
1549 else
1550 reg &= ~ARLTBL_RW;
64fec949
FF		 1551 if (dev->vlan_enabled)
1552 reg &= ~ARLTBL_IVL_SVL_SELECT;
1553 else
1554 reg |= ARLTBL_IVL_SVL_SELECT;
1da6df85
FF		 1555 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1556
1557 return b53_arl_op_wait(dev);
1558}
1559
1560static int b53_arl_read(struct b53_device *dev, u64 mac,
ef2a0bd9 1561 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1da6df85 1562{
6344dbde 1563 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1da6df85
FF		 1564 unsigned int i;
1565 int ret;
1566
1567 ret = b53_arl_op_wait(dev);
1568 if (ret)
1569 return ret;
1570
673e69a6 1571 bitmap_zero(free_bins, dev->num_arl_bins);
6344dbde 1572
1da6df85 1573 /* Read the bins */
673e69a6 1574 for (i = 0; i < dev->num_arl_bins; i++) {
1da6df85
FF		 1575 u64 mac_vid;
1576 u32 fwd_entry;
1577
1578 b53_read64(dev, B53_ARLIO_PAGE,
1579 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1580 b53_read32(dev, B53_ARLIO_PAGE,
1581 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1582 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1583
6344dbde
FF		 1584 if (!(fwd_entry & ARLTBL_VALID)) {
1585 set_bit(i, free_bins);
1da6df85 1586 continue;
6344dbde 1587 }
1da6df85
FF		 1588 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1589 continue;
2e97b0cd
FF		 1590 if (dev->vlan_enabled &&
1591 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1592 continue;
1da6df85 1593 *idx = i;
6344dbde 1594 return 0;
1da6df85
FF		 1595 }
1596
673e69a6 1597 if (bitmap_weight(free_bins, dev->num_arl_bins) == 0)
6344dbde
FF		 1598 return -ENOSPC;
1599
673e69a6 1600 *idx = find_first_bit(free_bins, dev->num_arl_bins);
6344dbde 1601
1da6df85
FF		 1602 return -ENOENT;
1603}
1604
1605static int b53_arl_op(struct b53_device *dev, int op, int port,
1606 const unsigned char *addr, u16 vid, bool is_valid)
1607{
1608 struct b53_arl_entry ent;
1609 u32 fwd_entry;
1610 u64 mac, mac_vid = 0;
1611 u8 idx = 0;
1612 int ret;
1613
1614 /* Convert the array into a 64-bit MAC */
4b92ea81 1615 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1616
1617 /* Perform a read for the given MAC and VID */
1618 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1619 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1620
1621 /* Issue a read operation for this MAC */
1622 ret = b53_arl_rw_op(dev, 1);
1623 if (ret)
1624 return ret;
1625
ef2a0bd9
FF		 1626 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1627
1da6df85
FF		 1628 /* If this is a read, just finish now */
1629 if (op)
1630 return ret;
1631
6344dbde 1632 switch (ret) {
774d977a
TR		 1633 case -ETIMEDOUT:
1634 return ret;
6344dbde
FF		 1635 case -ENOSPC:
1636 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1637 addr, vid);
1638 return is_valid ? ret : 0;
1639 case -ENOENT:
1640 /* We could not find a matching MAC, so reset to a new entry */
1641 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1642 addr, vid, idx);
1da6df85 1643 fwd_entry = 0;
6344dbde
FF		 1644 break;
1645 default:
1646 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1647 addr, vid, idx);
1648 break;
1da6df85
FF		 1649 }
1650
5d65b64a
FF		 1651 /* For multicast address, the port is a bitmask and the validity
1652 * is determined by having at least one port being still active
1653 */
1654 if (!is_multicast_ether_addr(addr)) {
1655 ent.port = port;
1656 ent.is_valid = is_valid;
1657 } else {
1658 if (is_valid)
1659 ent.port |= BIT(port);
1660 else
1661 ent.port &= ~BIT(port);
1662
1663 ent.is_valid = !!(ent.port);
1664 }
1665
1da6df85
FF		 1666 ent.vid = vid;
1667 ent.is_static = true;
5d65b64a 1668 ent.is_age = false;
1da6df85
FF		 1669 memcpy(ent.mac, addr, ETH_ALEN);
1670 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1671
1672 b53_write64(dev, B53_ARLIO_PAGE,
1673 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1674 b53_write32(dev, B53_ARLIO_PAGE,
1675 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1676
1677 return b53_arl_rw_op(dev, 0);
1678}
1679
1b6dd556
AS		 1680int b53_fdb_add(struct dsa_switch *ds, int port,
1681 const unsigned char *addr, u16 vid)
1da6df85 1682{
04bed143 1683 struct b53_device *priv = ds->priv;
1da6df85
FF		 1684
1685 /* 5325 and 5365 require some more massaging, but could
1686 * be supported eventually
1687 */
1688 if (is5325(priv) || is5365(priv))
1689 return -EOPNOTSUPP;
1690
1b6dd556 1691 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1692}
3117455d 1693EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1694
3117455d 1695int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1696 const unsigned char *addr, u16 vid)
1da6df85 1697{
04bed143 1698 struct b53_device *priv = ds->priv;
1da6df85 1699
6c2c1dcb 1700 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1701}
3117455d 1702EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1703
1704static int b53_arl_search_wait(struct b53_device *dev)
1705{
1706 unsigned int timeout = 1000;
1707 u8 reg;
1708
1709 do {
1710 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1711 if (!(reg & ARL_SRCH_STDN))
1712 return 0;
1713
1714 if (reg & ARL_SRCH_VLID)
1715 return 0;
1716
1717 usleep_range(1000, 2000);
1718 } while (timeout--);
1719
1720 return -ETIMEDOUT;
1721}
1722
1723static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1724 struct b53_arl_entry *ent)
1725{
1726 u64 mac_vid;
1727 u32 fwd_entry;
1728
1729 b53_read64(dev, B53_ARLIO_PAGE,
1730 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1731 b53_read32(dev, B53_ARLIO_PAGE,
1732 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1733 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1734}
1735
e6cbef0c 1736static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1737 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1738{
1739 if (!ent->is_valid)
1740 return 0;
1741
1742 if (port != ent->port)
1743 return 0;
1744
2bedde1a 1745 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1746}
1747
3117455d 1748int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1749 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1750{
04bed143 1751 struct b53_device *priv = ds->priv;
1da6df85
FF		 1752 struct b53_arl_entry results[2];
1753 unsigned int count = 0;
1754 int ret;
1755 u8 reg;
1756
1757 /* Start search operation */
1758 reg = ARL_SRCH_STDN;
1759 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1760
1761 do {
1762 ret = b53_arl_search_wait(priv);
1763 if (ret)
1764 return ret;
1765
1766 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1767 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1768 if (ret)
1769 return ret;
1770
673e69a6 1771 if (priv->num_arl_bins > 2) {
1da6df85 1772 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1773 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1774 if (ret)
1775 return ret;
1776
1777 if (!results[0].is_valid && !results[1].is_valid)
1778 break;
1779 }
1780
cd169d79 1781 } while (count++ < b53_max_arl_entries(priv) / 2);
1da6df85
FF		 1782
1783 return 0;
1784}
3117455d 1785EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1786
a52b2da7
VO		 1787int b53_mdb_add(struct dsa_switch *ds, int port,
1788 const struct switchdev_obj_port_mdb *mdb)
5d65b64a
FF		 1789{
1790 struct b53_device *priv = ds->priv;
1791
1792 /* 5325 and 5365 require some more massaging, but could
1793 * be supported eventually
1794 */
1795 if (is5325(priv) || is5365(priv))
1796 return -EOPNOTSUPP;
1797
a52b2da7 1798 return b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
5d65b64a
FF		 1799}
1800EXPORT_SYMBOL(b53_mdb_add);
1801
1802int b53_mdb_del(struct dsa_switch *ds, int port,
1803 const struct switchdev_obj_port_mdb *mdb)
1804{
1805 struct b53_device *priv = ds->priv;
1806 int ret;
1807
1808 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1809 if (ret)
1810 dev_err(ds->dev, "failed to delete MDB entry\n");
1811
1812 return ret;
1813}
1814EXPORT_SYMBOL(b53_mdb_del);
1815
ddd3a0c8 1816int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1817{
04bed143 1818 struct b53_device *dev = ds->priv;
68bb8ea8 1819 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
ff39c2d6
FF		 1820 u16 pvlan, reg;
1821 unsigned int i;
1822
31bfc2d4
FF		 1823 /* On 7278, port 7 which connects to the ASP should only receive
1824 * traffic from matching CFP rules.
1825 */
1826 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1827 return -EINVAL;
1828
48aea33a
FF		 1829 /* Make this port leave the all VLANs join since we will have proper
1830 * VLAN entries from now on
1831 */
1832 if (is58xx(dev)) {
1833 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1834 reg &= ~BIT(port);
1835 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1836 reg &= ~BIT(cpu_port);
1837 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1838 }
1839
ff39c2d6
FF		 1840 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1841
1842 b53_for_each_port(dev, i) {
c8652c83 1843 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1844 continue;
1845
1846 /* Add this local port to the remote port VLAN control
1847 * membership and update the remote port bitmask
1848 */
1849 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1850 reg |= BIT(port);
1851 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1852 dev->ports[i].vlan_ctl_mask = reg;
1853
1854 pvlan |= BIT(i);
1855 }
1856
1857 /* Configure the local port VLAN control membership to include
1858 * remote ports and update the local port bitmask
1859 */
1860 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1861 dev->ports[port].vlan_ctl_mask = pvlan;
1862
1863 return 0;
1864}
3117455d 1865EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1866
f123f2fb 1867void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1868{
04bed143 1869 struct b53_device *dev = ds->priv;
a2482d2c 1870 struct b53_vlan *vl = &dev->vlans[0];
68bb8ea8 1871 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
ff39c2d6 1872 unsigned int i;
a2482d2c 1873 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1874
1875 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1876
1877 b53_for_each_port(dev, i) {
1878 /* Don't touch the remaining ports */
c8652c83 1879 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1880 continue;
1881
1882 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1883 reg &= ~BIT(port);
1884 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1885 dev->ports[port].vlan_ctl_mask = reg;
1886
1887 /* Prevent self removal to preserve isolation */
1888 if (port != i)
1889 pvlan &= ~BIT(i);
1890 }
1891
1892 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1893 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c 1894
fea83353 1895 pvid = b53_default_pvid(dev);
a2482d2c 1896
48aea33a
FF		 1897 /* Make this port join all VLANs without VLAN entries */
1898 if (is58xx(dev)) {
1899 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1900 reg |= BIT(port);
1901 if (!(reg & BIT(cpu_port)))
1902 reg |= BIT(cpu_port);
1903 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1904 } else {
1905 b53_get_vlan_entry(dev, pvid, vl);
c499696e
FF		 1906 vl->members |= BIT(port) | BIT(cpu_port);
1907 vl->untag |= BIT(port) | BIT(cpu_port);
48aea33a
FF		 1908 b53_set_vlan_entry(dev, pvid, vl);
1909 }
ff39c2d6 1910}
3117455d 1911EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1912
3117455d 1913void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1914{
04bed143 1915 struct b53_device *dev = ds->priv;
597698f1 1916 u8 hw_state;
ff39c2d6
FF		 1917 u8 reg;
1918
ff39c2d6
FF		 1919 switch (state) {
1920 case BR_STATE_DISABLED:
1921 hw_state = PORT_CTRL_DIS_STATE;
1922 break;
1923 case BR_STATE_LISTENING:
1924 hw_state = PORT_CTRL_LISTEN_STATE;
1925 break;
1926 case BR_STATE_LEARNING:
1927 hw_state = PORT_CTRL_LEARN_STATE;
1928 break;
1929 case BR_STATE_FORWARDING:
1930 hw_state = PORT_CTRL_FWD_STATE;
1931 break;
1932 case BR_STATE_BLOCKING:
1933 hw_state = PORT_CTRL_BLOCK_STATE;
1934 break;
1935 default:
1936 dev_err(ds->dev, "invalid STP state: %d\n", state);
1937 return;
1938 }
1939
ff39c2d6
FF		 1940 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1941 reg &= ~PORT_CTRL_STP_STATE_MASK;
1942 reg |= hw_state;
1943 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1944}
3117455d 1945EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1946
3117455d 1947void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1948{
1949 struct b53_device *dev = ds->priv;
1950
1951 if (b53_fast_age_port(dev, port))
1952 dev_err(ds->dev, "fast ageing failed\n");
1953}
3117455d 1954EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1955
a8b659e7
VO		 1956static int b53_br_flags_pre(struct dsa_switch *ds, int port,
1957 struct switchdev_brport_flags flags,
1958 struct netlink_ext_ack *extack)
53568438 1959{
a8b659e7
VO		 1960 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD))
1961 return -EINVAL;
63cc54a6 1962
a8b659e7
VO		 1963 return 0;
1964}
53568438 1965
a8b659e7
VO		 1966static int b53_br_flags(struct dsa_switch *ds, int port,
1967 struct switchdev_brport_flags flags,
1968 struct netlink_ext_ack *extack)
1969{
1970 if (flags.mask & BR_FLOOD)
1971 b53_port_set_ucast_flood(ds->priv, port,
1972 !!(flags.val & BR_FLOOD));
1973 if (flags.mask & BR_MCAST_FLOOD)
1974 b53_port_set_mcast_flood(ds->priv, port,
1975 !!(flags.val & BR_MCAST_FLOOD));
53568438
FF		 1976
1977 return 0;
a8b659e7 1978}
53568438 1979
a8b659e7
VO		 1980static int b53_set_mrouter(struct dsa_switch *ds, int port, bool mrouter,
1981 struct netlink_ext_ack *extack)
1982{
1983 b53_port_set_mcast_flood(ds->priv, port, mrouter);
1984
1985 return 0;
53568438 1986}
53568438 1987
c7d28c9d 1988static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
7edc58d6 1989{
7edc58d6
FF		 1990 /* Broadcom switches will accept enabling Broadcom tags on the
1991 * following ports: 5, 7 and 8, any other port is not supported
1992 */
5ed4e3eb
FF		 1993 switch (port) {
1994 case B53_CPU_PORT_25:
1995 case 7:
1996 case B53_CPU_PORT:
1997 return true;
7edc58d6
FF		 1998 }
1999
5ed4e3eb 2000 return false;
7edc58d6
FF		 2001}
2002
8fab459e
FF		 2003static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2004 enum dsa_tag_protocol tag_protocol)
c7d28c9d
FF		 2005{
2006 bool ret = b53_possible_cpu_port(ds, port);
2007
8fab459e 2008 if (!ret) {
c7d28c9d
FF		 2009 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2010 port);
8fab459e
FF		 2011 return ret;
2012 }
2013
2014 switch (tag_protocol) {
2015 case DSA_TAG_PROTO_BRCM:
2016 case DSA_TAG_PROTO_BRCM_PREPEND:
2017 dev_warn(ds->dev,
2018 "Port %d is stacked to Broadcom tag switch\n", port);
2019 ret = false;
2020 break;
2021 default:
2022 ret = true;
2023 break;
2024 }
2025
c7d28c9d
FF		 2026 return ret;
2027}
2028
4d776482
FF		 2029enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2030 enum dsa_tag_protocol mprot)
7b314362 2031{
7edc58d6
FF		 2032 struct b53_device *dev = ds->priv;
2033
54e98b5d 2034 /* Older models (5325, 5365) support a different tag format that we do
8fab459e 2035 * not support in net/dsa/tag_brcm.c yet.
7edc58d6 2036 */
8fab459e
FF		 2037 if (is5325(dev) || is5365(dev) ||
2038 !b53_can_enable_brcm_tags(ds, port, mprot)) {
4d776482
FF		 2039 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2040 goto out;
2041 }
11606039
FF		 2042
2043 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2044 * which requires us to use the prepended Broadcom tag type
2045 */
4d776482
FF		 2046 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2047 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2048 goto out;
2049 }
11606039 2050
4d776482
FF		 2051 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2052out:
2053 return dev->tag_protocol;
7b314362 2054}
9f66816a 2055EXPORT_SYMBOL(b53_get_tag_protocol);
7b314362 2056
ed3af5fd
FF		 2057int b53_mirror_add(struct dsa_switch *ds, int port,
2058 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
2059{
2060 struct b53_device *dev = ds->priv;
2061 u16 reg, loc;
2062
2063 if (ingress)
2064 loc = B53_IG_MIR_CTL;
2065 else
2066 loc = B53_EG_MIR_CTL;
2067
2068 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
ed3af5fd
FF		 2069 reg |= BIT(port);
2070 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2071
2072 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2073 reg &= ~CAP_PORT_MASK;
2074 reg |= mirror->to_local_port;
2075 reg |= MIRROR_EN;
2076 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2077
2078 return 0;
2079}
2080EXPORT_SYMBOL(b53_mirror_add);
2081
2082void b53_mirror_del(struct dsa_switch *ds, int port,
2083 struct dsa_mall_mirror_tc_entry *mirror)
2084{
2085 struct b53_device *dev = ds->priv;
2086 bool loc_disable = false, other_loc_disable = false;
2087 u16 reg, loc;
2088
2089 if (mirror->ingress)
2090 loc = B53_IG_MIR_CTL;
2091 else
2092 loc = B53_EG_MIR_CTL;
2093
2094 /* Update the desired ingress/egress register */
2095 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
2096 reg &= ~BIT(port);
2097 if (!(reg & MIRROR_MASK))
2098 loc_disable = true;
2099 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2100
2101 /* Now look at the other one to know if we can disable mirroring
2102 * entirely
2103 */
2104 if (mirror->ingress)
2105 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
2106 else
2107 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
2108 if (!(reg & MIRROR_MASK))
2109 other_loc_disable = true;
2110
2111 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
2112 /* Both no longer have ports, let's disable mirroring */
2113 if (loc_disable && other_loc_disable) {
2114 reg &= ~MIRROR_EN;
2115 reg &= ~mirror->to_local_port;
2116 }
2117 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2118}
2119EXPORT_SYMBOL(b53_mirror_del);
2120
22256b0a
FF		 2121void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
2122{
2123 struct b53_device *dev = ds->priv;
2124 u16 reg;
2125
2126 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
2127 if (enable)
2128 reg |= BIT(port);
2129 else
2130 reg &= ~BIT(port);
2131 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
2132}
2133EXPORT_SYMBOL(b53_eee_enable_set);
2134
2135
2136/* Returns 0 if EEE was not enabled, or 1 otherwise
2137 */
2138int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2139{
2140 int ret;
2141
2142 ret = phy_init_eee(phy, 0);
2143 if (ret)
2144 return 0;
2145
2146 b53_eee_enable_set(ds, port, true);
2147
2148 return 1;
2149}
2150EXPORT_SYMBOL(b53_eee_init);
2151
2152int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2153{
2154 struct b53_device *dev = ds->priv;
2155 struct ethtool_eee *p = &dev->ports[port].eee;
2156 u16 reg;
2157
2158 if (is5325(dev) || is5365(dev))
2159 return -EOPNOTSUPP;
2160
2161 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
2162 e->eee_enabled = p->eee_enabled;
2163 e->eee_active = !!(reg & BIT(port));
2164
2165 return 0;
2166}
2167EXPORT_SYMBOL(b53_get_mac_eee);
2168
2169int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2170{
2171 struct b53_device *dev = ds->priv;
2172 struct ethtool_eee *p = &dev->ports[port].eee;
2173
2174 if (is5325(dev) || is5365(dev))
2175 return -EOPNOTSUPP;
2176
2177 p->eee_enabled = e->eee_enabled;
2178 b53_eee_enable_set(ds, port, e->eee_enabled);
2179
2180 return 0;
2181}
2182EXPORT_SYMBOL(b53_set_mac_eee);
2183
6ae5834b
MKP		 2184static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2185{
2186 struct b53_device *dev = ds->priv;
2187 bool enable_jumbo;
2188 bool allow_10_100;
2189
2190 if (is5325(dev) || is5365(dev))
2191 return -EOPNOTSUPP;
2192
2193 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2194 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2195
2196 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2197}
2198
2199static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2200{
2201 return JMS_MAX_SIZE;
2202}
2203
a82f67af 2204static const struct dsa_switch_ops b53_switch_ops = {
7b314362 2205 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 2206 .setup = b53_setup,
4f6a5caf 2207 .teardown = b53_teardown,
967dd82f
FF		 2208 .get_strings = b53_get_strings,
2209 .get_ethtool_stats = b53_get_ethtool_stats,
2210 .get_sset_count = b53_get_sset_count,
c7d28c9d 2211 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
967dd82f
FF		 2212 .phy_read = b53_phy_read16,
2213 .phy_write = b53_phy_write16,
2214 .adjust_link = b53_adjust_link,
a8e8b985
FF		 2215 .phylink_validate = b53_phylink_validate,
2216 .phylink_mac_link_state = b53_phylink_mac_link_state,
2217 .phylink_mac_config = b53_phylink_mac_config,
2218 .phylink_mac_an_restart = b53_phylink_mac_an_restart,
2219 .phylink_mac_link_down = b53_phylink_mac_link_down,
2220 .phylink_mac_link_up = b53_phylink_mac_link_up,
967dd82f
FF		 2221 .port_enable = b53_enable_port,
2222 .port_disable = b53_disable_port,
f43a2dbe
FF		 2223 .get_mac_eee = b53_get_mac_eee,
2224 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 2225 .port_bridge_join = b53_br_join,
2226 .port_bridge_leave = b53_br_leave,
a8b659e7
VO		 2227 .port_pre_bridge_flags = b53_br_flags_pre,
2228 .port_bridge_flags = b53_br_flags,
2229 .port_set_mrouter = b53_set_mrouter,
ff39c2d6 2230 .port_stp_state_set = b53_br_set_stp_state,
597698f1 2231 .port_fast_age = b53_br_fast_age,
a2482d2c 2232 .port_vlan_filtering = b53_vlan_filtering,
a2482d2c
FF		 2233 .port_vlan_add = b53_vlan_add,
2234 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 2235 .port_fdb_dump = b53_fdb_dump,
2236 .port_fdb_add = b53_fdb_add,
2237 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 2238 .port_mirror_add = b53_mirror_add,
2239 .port_mirror_del = b53_mirror_del,
5d65b64a
FF		 2240 .port_mdb_add = b53_mdb_add,
2241 .port_mdb_del = b53_mdb_del,
6ae5834b
MKP		 2242 .port_max_mtu = b53_get_max_mtu,
2243 .port_change_mtu = b53_change_mtu,
967dd82f
FF		 2244};
2245
2246struct b53_chip_data {
2247 u32 chip_id;
2248 const char *dev_name;
2249 u16 vlans;
2250 u16 enabled_ports;
2251 u8 cpu_port;
2252 u8 vta_regs[3];
673e69a6 2253 u8 arl_bins;
e3da4038 2254 u16 arl_buckets;
967dd82f
FF		 2255 u8 duplex_reg;
2256 u8 jumbo_pm_reg;
2257 u8 jumbo_size_reg;
2258};
2259
2260#define B53_VTA_REGS \
2261 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2262#define B53_VTA_REGS_9798 \
2263 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2264#define B53_VTA_REGS_63XX \
2265 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2266
2267static const struct b53_chip_data b53_switch_chips[] = {
2268 {
2269 .chip_id = BCM5325_DEVICE_ID,
2270 .dev_name = "BCM5325",
2271 .vlans = 16,
2272 .enabled_ports = 0x1f,
673e69a6 2273 .arl_bins = 2,
e3da4038 2274 .arl_buckets = 1024,
967dd82f
FF		 2275 .cpu_port = B53_CPU_PORT_25,
2276 .duplex_reg = B53_DUPLEX_STAT_FE,
2277 },
2278 {
2279 .chip_id = BCM5365_DEVICE_ID,
2280 .dev_name = "BCM5365",
2281 .vlans = 256,
2282 .enabled_ports = 0x1f,
673e69a6 2283 .arl_bins = 2,
e3da4038 2284 .arl_buckets = 1024,
967dd82f
FF		 2285 .cpu_port = B53_CPU_PORT_25,
2286 .duplex_reg = B53_DUPLEX_STAT_FE,
2287 },
a95691bc
DT		 2288 {
2289 .chip_id = BCM5389_DEVICE_ID,
2290 .dev_name = "BCM5389",
2291 .vlans = 4096,
2292 .enabled_ports = 0x1f,
673e69a6 2293 .arl_bins = 4,
e3da4038 2294 .arl_buckets = 1024,
a95691bc
DT		 2295 .cpu_port = B53_CPU_PORT,
2296 .vta_regs = B53_VTA_REGS,
2297 .duplex_reg = B53_DUPLEX_STAT_GE,
2298 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2299 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2300 },
967dd82f
FF		 2301 {
2302 .chip_id = BCM5395_DEVICE_ID,
2303 .dev_name = "BCM5395",
2304 .vlans = 4096,
2305 .enabled_ports = 0x1f,
673e69a6 2306 .arl_bins = 4,
e3da4038 2307 .arl_buckets = 1024,
967dd82f
FF		 2308 .cpu_port = B53_CPU_PORT,
2309 .vta_regs = B53_VTA_REGS,
2310 .duplex_reg = B53_DUPLEX_STAT_GE,
2311 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2312 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2313 },
2314 {
2315 .chip_id = BCM5397_DEVICE_ID,
2316 .dev_name = "BCM5397",
2317 .vlans = 4096,
2318 .enabled_ports = 0x1f,
673e69a6 2319 .arl_bins = 4,
e3da4038 2320 .arl_buckets = 1024,
967dd82f
FF		 2321 .cpu_port = B53_CPU_PORT,
2322 .vta_regs = B53_VTA_REGS_9798,
2323 .duplex_reg = B53_DUPLEX_STAT_GE,
2324 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2325 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2326 },
2327 {
2328 .chip_id = BCM5398_DEVICE_ID,
2329 .dev_name = "BCM5398",
2330 .vlans = 4096,
2331 .enabled_ports = 0x7f,
673e69a6 2332 .arl_bins = 4,
e3da4038 2333 .arl_buckets = 1024,
967dd82f
FF		 2334 .cpu_port = B53_CPU_PORT,
2335 .vta_regs = B53_VTA_REGS_9798,
2336 .duplex_reg = B53_DUPLEX_STAT_GE,
2337 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2338 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2339 },
2340 {
2341 .chip_id = BCM53115_DEVICE_ID,
2342 .dev_name = "BCM53115",
2343 .vlans = 4096,
2344 .enabled_ports = 0x1f,
673e69a6 2345 .arl_bins = 4,
e3da4038 2346 .arl_buckets = 1024,
967dd82f
FF		 2347 .vta_regs = B53_VTA_REGS,
2348 .cpu_port = B53_CPU_PORT,
2349 .duplex_reg = B53_DUPLEX_STAT_GE,
2350 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2351 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2352 },
2353 {
2354 .chip_id = BCM53125_DEVICE_ID,
2355 .dev_name = "BCM53125",
2356 .vlans = 4096,
2357 .enabled_ports = 0xff,
673e69a6 2358 .arl_bins = 4,
e3da4038 2359 .arl_buckets = 1024,
967dd82f
FF		 2360 .cpu_port = B53_CPU_PORT,
2361 .vta_regs = B53_VTA_REGS,
2362 .duplex_reg = B53_DUPLEX_STAT_GE,
2363 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2364 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2365 },
2366 {
2367 .chip_id = BCM53128_DEVICE_ID,
2368 .dev_name = "BCM53128",
2369 .vlans = 4096,
2370 .enabled_ports = 0x1ff,
673e69a6 2371 .arl_bins = 4,
e3da4038 2372 .arl_buckets = 1024,
967dd82f
FF		 2373 .cpu_port = B53_CPU_PORT,
2374 .vta_regs = B53_VTA_REGS,
2375 .duplex_reg = B53_DUPLEX_STAT_GE,
2376 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2377 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2378 },
2379 {
2380 .chip_id = BCM63XX_DEVICE_ID,
2381 .dev_name = "BCM63xx",
2382 .vlans = 4096,
2383 .enabled_ports = 0, /* pdata must provide them */
673e69a6 2384 .arl_bins = 4,
e3da4038 2385 .arl_buckets = 1024,
967dd82f
FF		 2386 .cpu_port = B53_CPU_PORT,
2387 .vta_regs = B53_VTA_REGS_63XX,
2388 .duplex_reg = B53_DUPLEX_STAT_63XX,
2389 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2390 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2391 },
2392 {
2393 .chip_id = BCM53010_DEVICE_ID,
2394 .dev_name = "BCM53010",
2395 .vlans = 4096,
2396 .enabled_ports = 0x1f,
673e69a6 2397 .arl_bins = 4,
e3da4038 2398 .arl_buckets = 1024,
967dd82f
FF		 2399 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2400 .vta_regs = B53_VTA_REGS,
2401 .duplex_reg = B53_DUPLEX_STAT_GE,
2402 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2403 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2404 },
2405 {
2406 .chip_id = BCM53011_DEVICE_ID,
2407 .dev_name = "BCM53011",
2408 .vlans = 4096,
2409 .enabled_ports = 0x1bf,
673e69a6 2410 .arl_bins = 4,
e3da4038 2411 .arl_buckets = 1024,
967dd82f
FF		 2412 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2413 .vta_regs = B53_VTA_REGS,
2414 .duplex_reg = B53_DUPLEX_STAT_GE,
2415 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2416 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2417 },
2418 {
2419 .chip_id = BCM53012_DEVICE_ID,
2420 .dev_name = "BCM53012",
2421 .vlans = 4096,
2422 .enabled_ports = 0x1bf,
673e69a6 2423 .arl_bins = 4,
e3da4038 2424 .arl_buckets = 1024,
967dd82f
FF		 2425 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2426 .vta_regs = B53_VTA_REGS,
2427 .duplex_reg = B53_DUPLEX_STAT_GE,
2428 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2429 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2430 },
2431 {
2432 .chip_id = BCM53018_DEVICE_ID,
2433 .dev_name = "BCM53018",
2434 .vlans = 4096,
2435 .enabled_ports = 0x1f,
673e69a6 2436 .arl_bins = 4,
e3da4038 2437 .arl_buckets = 1024,
967dd82f
FF		 2438 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2439 .vta_regs = B53_VTA_REGS,
2440 .duplex_reg = B53_DUPLEX_STAT_GE,
2441 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2442 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2443 },
2444 {
2445 .chip_id = BCM53019_DEVICE_ID,
2446 .dev_name = "BCM53019",
2447 .vlans = 4096,
2448 .enabled_ports = 0x1f,
673e69a6 2449 .arl_bins = 4,
e3da4038 2450 .arl_buckets = 1024,
967dd82f
FF		 2451 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
2452 .vta_regs = B53_VTA_REGS,
2453 .duplex_reg = B53_DUPLEX_STAT_GE,
2454 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2455 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2456 },
991a36bb
FF		 2457 {
2458 .chip_id = BCM58XX_DEVICE_ID,
2459 .dev_name = "BCM585xx/586xx/88312",
2460 .vlans = 4096,
2461 .enabled_ports = 0x1ff,
673e69a6 2462 .arl_bins = 4,
e3da4038 2463 .arl_buckets = 1024,
bfcda65c 2464 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 2465 .vta_regs = B53_VTA_REGS,
2466 .duplex_reg = B53_DUPLEX_STAT_GE,
2467 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2468 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2469 },
5040cc99
AP		 2470 {
2471 .chip_id = BCM583XX_DEVICE_ID,
2472 .dev_name = "BCM583xx/11360",
2473 .vlans = 4096,
2474 .enabled_ports = 0x103,
673e69a6 2475 .arl_bins = 4,
e3da4038 2476 .arl_buckets = 1024,
5040cc99
AP		 2477 .cpu_port = B53_CPU_PORT,
2478 .vta_regs = B53_VTA_REGS,
2479 .duplex_reg = B53_DUPLEX_STAT_GE,
2480 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2481 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2482 },
73b7a604
RM		 2483 /* Starfighter 2 */
2484 {
2485 .chip_id = BCM4908_DEVICE_ID,
2486 .dev_name = "BCM4908",
2487 .vlans = 4096,
2488 .enabled_ports = 0x1bf,
2489 .arl_bins = 4,
2490 .arl_buckets = 256,
2491 .cpu_port = 8, /* TODO: ports 4, 5, 8 */
2492 .vta_regs = B53_VTA_REGS,
2493 .duplex_reg = B53_DUPLEX_STAT_GE,
2494 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2495 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2496 },
130401d9
FF		 2497 {
2498 .chip_id = BCM7445_DEVICE_ID,
2499 .dev_name = "BCM7445",
2500 .vlans = 4096,
2501 .enabled_ports = 0x1ff,
673e69a6 2502 .arl_bins = 4,
e3da4038 2503 .arl_buckets = 1024,
130401d9
FF		 2504 .cpu_port = B53_CPU_PORT,
2505 .vta_regs = B53_VTA_REGS,
2506 .duplex_reg = B53_DUPLEX_STAT_GE,
2507 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2508 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2509 },
0fe99338
FF		 2510 {
2511 .chip_id = BCM7278_DEVICE_ID,
2512 .dev_name = "BCM7278",
2513 .vlans = 4096,
2514 .enabled_ports = 0x1ff,
673e69a6 2515 .arl_bins = 4,
e3da4038 2516 .arl_buckets = 256,
0fe99338
FF		 2517 .cpu_port = B53_CPU_PORT,
2518 .vta_regs = B53_VTA_REGS,
2519 .duplex_reg = B53_DUPLEX_STAT_GE,
2520 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2521 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2522 },
967dd82f
FF		 2523};
2524
2525static int b53_switch_init(struct b53_device *dev)
2526{
967dd82f
FF		 2527 unsigned int i;
2528 int ret;
2529
2530 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2531 const struct b53_chip_data *chip = &b53_switch_chips[i];
2532
2533 if (chip->chip_id == dev->chip_id) {
2534 if (!dev->enabled_ports)
2535 dev->enabled_ports = chip->enabled_ports;
2536 dev->name = chip->dev_name;
2537 dev->duplex_reg = chip->duplex_reg;
2538 dev->vta_regs[0] = chip->vta_regs[0];
2539 dev->vta_regs[1] = chip->vta_regs[1];
2540 dev->vta_regs[2] = chip->vta_regs[2];
2541 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 2542 dev->cpu_port = chip->cpu_port;
2543 dev->num_vlans = chip->vlans;
673e69a6 2544 dev->num_arl_bins = chip->arl_bins;
e3da4038 2545 dev->num_arl_buckets = chip->arl_buckets;
967dd82f
FF		 2546 break;
2547 }
2548 }
2549
2550 /* check which BCM5325x version we have */
2551 if (is5325(dev)) {
2552 u8 vc4;
2553
2554 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2555
2556 /* check reserved bits */
2557 switch (vc4 & 3) {
2558 case 1:
2559 /* BCM5325E */
2560 break;
2561 case 3:
2562 /* BCM5325F - do not use port 4 */
2563 dev->enabled_ports &= ~BIT(4);
2564 break;
2565 default:
2566/* On the BCM47XX SoCs this is the supported internal switch.*/
2567#ifndef CONFIG_BCM47XX
2568 /* BCM5325M */
2569 return -EINVAL;
2570#else
2571 break;
2572#endif
2573 }
2574 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2575 u64 strap_value;
2576
2577 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2578 /* use second IMP port if GMII is enabled */
2579 if (strap_value & SV_GMII_CTRL_115)
2580 dev->cpu_port = 5;
2581 }
2582
2583 /* cpu port is always last */
2584 dev->num_ports = dev->cpu_port + 1;
2585 dev->enabled_ports |= BIT(dev->cpu_port);
2586
c7d28c9d
FF		 2587 /* Include non standard CPU port built-in PHYs to be probed */
2588 if (is539x(dev) || is531x5(dev)) {
2589 for (i = 0; i < dev->num_ports; i++) {
2590 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2591 !b53_possible_cpu_port(dev->ds, i))
2592 dev->ds->phys_mii_mask |= BIT(i);
2593 }
2594 }
2595
a86854d0
KC		 2596 dev->ports = devm_kcalloc(dev->dev,
2597 dev->num_ports, sizeof(struct b53_port),
967dd82f
FF		 2598 GFP_KERNEL);
2599 if (!dev->ports)
2600 return -ENOMEM;
2601
a86854d0
KC		 2602 dev->vlans = devm_kcalloc(dev->dev,
2603 dev->num_vlans, sizeof(struct b53_vlan),
a2482d2c
FF		 2604 GFP_KERNEL);
2605 if (!dev->vlans)
2606 return -ENOMEM;
2607
967dd82f
FF		 2608 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2609 if (dev->reset_gpio >= 0) {
2610 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2611 GPIOF_OUT_INIT_HIGH, "robo_reset");
2612 if (ret)
2613 return ret;
2614 }
2615
2616 return 0;
2617}
2618
0dff88d3
JL		 2619struct b53_device *b53_switch_alloc(struct device *base,
2620 const struct b53_io_ops *ops,
967dd82f
FF		 2621 void *priv)
2622{
2623 struct dsa_switch *ds;
2624 struct b53_device *dev;
2625
7e99e347 2626 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
967dd82f
FF		 2627 if (!ds)
2628 return NULL;
2629
7e99e347
VD		 2630 ds->dev = base;
2631 ds->num_ports = DSA_MAX_PORTS;
2632
a0c02161
VD		 2633 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2634 if (!dev)
2635 return NULL;
967dd82f
FF		 2636
2637 ds->priv = dev;
967dd82f
FF		 2638 dev->dev = base;
2639
2640 dev->ds = ds;
2641 dev->priv = priv;
2642 dev->ops = ops;
485ebd61 2643 ds->ops = &b53_switch_ops;
1c5ad5a9 2644 ds->untag_bridge_pvid = true;
0ee2af4e 2645 dev->vlan_enabled = true;
967dd82f
FF		 2646 mutex_init(&dev->reg_mutex);
2647 mutex_init(&dev->stats_mutex);
2648
2649 return dev;
2650}
2651EXPORT_SYMBOL(b53_switch_alloc);
2652
2653int b53_switch_detect(struct b53_device *dev)
2654{
2655 u32 id32;
2656 u16 tmp;
2657 u8 id8;
2658 int ret;
2659
2660 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2661 if (ret)
2662 return ret;
2663
2664 switch (id8) {
2665 case 0:
2666 /* BCM5325 and BCM5365 do not have this register so reads
2667 * return 0. But the read operation did succeed, so assume this
2668 * is one of them.
2669 *
2670 * Next check if we can write to the 5325's VTA register; for
2671 * 5365 it is read only.
2672 */
2673 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2674 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2675
2676 if (tmp == 0xf)
2677 dev->chip_id = BCM5325_DEVICE_ID;
2678 else
2679 dev->chip_id = BCM5365_DEVICE_ID;
2680 break;
a95691bc 2681 case BCM5389_DEVICE_ID:
967dd82f
FF		 2682 case BCM5395_DEVICE_ID:
2683 case BCM5397_DEVICE_ID:
2684 case BCM5398_DEVICE_ID:
2685 dev->chip_id = id8;
2686 break;
2687 default:
2688 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2689 if (ret)
2690 return ret;
2691
2692 switch (id32) {
2693 case BCM53115_DEVICE_ID:
2694 case BCM53125_DEVICE_ID:
2695 case BCM53128_DEVICE_ID:
2696 case BCM53010_DEVICE_ID:
2697 case BCM53011_DEVICE_ID:
2698 case BCM53012_DEVICE_ID:
2699 case BCM53018_DEVICE_ID:
2700 case BCM53019_DEVICE_ID:
2701 dev->chip_id = id32;
2702 break;
2703 default:
3b33438c
PB		 2704 dev_err(dev->dev,
2705 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2706 id8, id32);
967dd82f
FF		 2707 return -ENODEV;
2708 }
2709 }
2710
2711 if (dev->chip_id == BCM5325_DEVICE_ID)
2712 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2713 &dev->core_rev);
2714 else
2715 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2716 &dev->core_rev);
2717}
2718EXPORT_SYMBOL(b53_switch_detect);
2719
2720int b53_switch_register(struct b53_device *dev)
2721{
2722 int ret;
2723
2724 if (dev->pdata) {
2725 dev->chip_id = dev->pdata->chip_id;
2726 dev->enabled_ports = dev->pdata->enabled_ports;
2727 }
2728
2729 if (!dev->chip_id && b53_switch_detect(dev))
2730 return -EINVAL;
2731
2732 ret = b53_switch_init(dev);
2733 if (ret)
2734 return ret;
2735
3b33438c
PB		 2736 dev_info(dev->dev, "found switch: %s, rev %i\n",
2737 dev->name, dev->core_rev);
967dd82f 2738
23c9ee49 2739 return dsa_register_switch(dev->ds);
967dd82f
FF		 2740}
2741EXPORT_SYMBOL(b53_switch_register);
2742
2743MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2744MODULE_DESCRIPTION("B53 switch library");
2745MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)