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enic: fix UDP rss bits
[linux-2.6-block.git] / drivers / net / dsa / b53 / b53_common.c
CommitLineData
967dd82f
FF		 1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
1da6df85 29#include <linux/etherdevice.h>
ff39c2d6 30#include <linux/if_bridge.h>
967dd82f
FF		 31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
bde5d132
FF		 169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
967dd82f
FF		 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
a2482d2c
FF		 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
967dd82f
FF		 249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
a2482d2c
FF		 253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
967dd82f
FF		 256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
a2482d2c
FF		 268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
967dd82f
FF		 271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
a2482d2c 278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
967dd82f
FF		 279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
a2482d2c
FF		 282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
967dd82f
FF		 324}
325
a2482d2c 326static void b53_set_forwarding(struct b53_device *dev, int enable)
967dd82f
FF		 327{
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
a424f0de 338
7edc58d6 339 /* Include IMP port in dumb forwarding mode
a424f0de 340 */
7edc58d6
FF		 341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
967dd82f
FF		 344}
345
a2482d2c 346static void b53_enable_vlan(struct b53_device *dev, bool enable)
967dd82f
FF		 347{
348 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
349
350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
353
354 if (is5325(dev) || is5365(dev)) {
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
357 } else if (is63xx(dev)) {
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
360 } else {
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
363 }
364
365 mgmt &= ~SM_SW_FWD_MODE;
366
367 if (enable) {
368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
370 vc4 &= ~VC4_ING_VID_CHECK_MASK;
371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
372 vc5 |= VC5_DROP_VTABLE_MISS;
373
374 if (is5325(dev))
375 vc0 &= ~VC0_RESERVED_1;
376
377 if (is5325(dev) || is5365(dev))
378 vc1 |= VC1_RX_MCST_TAG_EN;
379
967dd82f
FF		 380 } else {
381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
383 vc4 &= ~VC4_ING_VID_CHECK_MASK;
384 vc5 &= ~VC5_DROP_VTABLE_MISS;
385
386 if (is5325(dev) || is5365(dev))
387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
388 else
389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 &= ~VC1_RX_MCST_TAG_EN;
967dd82f
FF		 393 }
394
a2482d2c
FF		 395 if (!is5325(dev) && !is5365(dev))
396 vc5 &= ~VC5_VID_FFF_EN;
397
967dd82f
FF		 398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
400
401 if (is5325(dev) || is5365(dev)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev) && enable)
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
405 VC3_HIGH_8BIT_EN);
406 else
407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
408
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
411 } else if (is63xx(dev)) {
412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
415 } else {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
419 }
420
421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
422}
423
424static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
425{
426 u32 port_mask = 0;
427 u16 max_size = JMS_MIN_SIZE;
428
429 if (is5325(dev) || is5365(dev))
430 return -EINVAL;
431
432 if (enable) {
433 port_mask = dev->enabled_ports;
434 max_size = JMS_MAX_SIZE;
435 if (allow_10_100)
436 port_mask |= JPM_10_100_JUMBO_EN;
437 }
438
439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
441}
442
ff39c2d6 443static int b53_flush_arl(struct b53_device *dev, u8 mask)
967dd82f
FF		 444{
445 unsigned int i;
446
447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
ff39c2d6 448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
967dd82f
FF		 449
450 for (i = 0; i < 10; i++) {
451 u8 fast_age_ctrl;
452
453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
454 &fast_age_ctrl);
455
456 if (!(fast_age_ctrl & FAST_AGE_DONE))
457 goto out;
458
459 msleep(1);
460 }
461
462 return -ETIMEDOUT;
463out:
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
466 return 0;
467}
468
ff39c2d6
FF		 469static int b53_fast_age_port(struct b53_device *dev, int port)
470{
471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
472
473 return b53_flush_arl(dev, FAST_AGE_PORT);
474}
475
a2482d2c
FF		 476static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
477{
478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
479
480 return b53_flush_arl(dev, FAST_AGE_VLAN);
481}
482
aac02867 483void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
ff39c2d6 484{
04bed143 485 struct b53_device *dev = ds->priv;
ff39c2d6
FF		 486 unsigned int i;
487 u16 pvlan;
488
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
491 * the same VLAN.
492 */
493 b53_for_each_port(dev, i) {
494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
495 pvlan |= BIT(cpu_port);
496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
497 }
498}
aac02867 499EXPORT_SYMBOL(b53_imp_vlan_setup);
ff39c2d6 500
f86ad77f 501int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 502{
04bed143 503 struct b53_device *dev = ds->priv;
c499696e 504 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 505 u16 pvlan;
967dd82f
FF		 506
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
509
ff39c2d6
FF		 510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
513 */
514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
515 pvlan &= ~0x1ff;
516 pvlan |= BIT(port);
517 pvlan |= dev->ports[port].vlan_ctl_mask;
518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
519
520 b53_imp_vlan_setup(ds, cpu_port);
521
f43a2dbe
FF		 522 /* If EEE was enabled, restore it */
523 if (dev->ports[port].eee.eee_enabled)
524 b53_eee_enable_set(ds, port, true);
525
967dd82f
FF		 526 return 0;
527}
f86ad77f 528EXPORT_SYMBOL(b53_enable_port);
967dd82f 529
f86ad77f 530void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
967dd82f 531{
04bed143 532 struct b53_device *dev = ds->priv;
967dd82f
FF		 533 u8 reg;
534
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
539}
f86ad77f 540EXPORT_SYMBOL(b53_disable_port);
967dd82f 541
b409a9ef
FF		 542void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
543{
11606039
FF		 544 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
545 DSA_TAG_PROTO_NONE);
b409a9ef
FF		 546 struct b53_device *dev = ds->priv;
547 u8 hdr_ctl, val;
548 u16 reg;
549
550 /* Resolve which bit controls the Broadcom tag */
551 switch (port) {
552 case 8:
553 val = BRCM_HDR_P8_EN;
554 break;
555 case 7:
556 val = BRCM_HDR_P7_EN;
557 break;
558 case 5:
559 val = BRCM_HDR_P5_EN;
560 break;
561 default:
562 val = 0;
563 break;
564 }
565
566 /* Enable Broadcom tags for IMP port */
567 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
cdb583cf
FF		 568 if (tag_en)
569 hdr_ctl |= val;
570 else
571 hdr_ctl &= ~val;
b409a9ef
FF		 572 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
573
574 /* Registers below are only accessible on newer devices */
575 if (!is58xx(dev))
576 return;
577
578 /* Enable reception Broadcom tag for CPU TX (switch RX) to
579 * allow us to tag outgoing frames
580 */
581 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
cdb583cf
FF		 582 if (tag_en)
583 reg &= ~BIT(port);
584 else
585 reg |= BIT(port);
b409a9ef
FF		 586 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
587
588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
589 * allow delivering frames to the per-port net_devices
590 */
591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
cdb583cf
FF		 592 if (tag_en)
593 reg &= ~BIT(port);
594 else
595 reg |= BIT(port);
b409a9ef
FF		 596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
597}
598EXPORT_SYMBOL(b53_brcm_hdr_setup);
599
299752a7 600static void b53_enable_cpu_port(struct b53_device *dev, int port)
967dd82f 601{
967dd82f
FF		 602 u8 port_ctrl;
603
604 /* BCM5325 CPU port is at 8 */
299752a7
FF		 605 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
606 port = B53_CPU_PORT;
967dd82f
FF		 607
608 port_ctrl = PORT_CTRL_RX_BCST_EN |
609 PORT_CTRL_RX_MCST_EN |
610 PORT_CTRL_RX_UCST_EN;
299752a7 611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
7edc58d6
FF		 612
613 b53_brcm_hdr_setup(dev->ds, port);
967dd82f
FF		 614}
615
616static void b53_enable_mib(struct b53_device *dev)
617{
618 u8 gc;
619
620 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
621 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
622 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
623}
624
5c1a6eaf 625int b53_configure_vlan(struct dsa_switch *ds)
967dd82f 626{
5c1a6eaf 627 struct b53_device *dev = ds->priv;
a2482d2c 628 struct b53_vlan vl = { 0 };
967dd82f
FF		 629 int i;
630
631 /* clear all vlan entries */
632 if (is5325(dev) || is5365(dev)) {
633 for (i = 1; i < dev->num_vlans; i++)
a2482d2c 634 b53_set_vlan_entry(dev, i, &vl);
967dd82f
FF		 635 } else {
636 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
637 }
638
639 b53_enable_vlan(dev, false);
640
641 b53_for_each_port(dev, i)
642 b53_write16(dev, B53_VLAN_PAGE,
643 B53_VLAN_PORT_DEF_TAG(i), 1);
644
645 if (!is5325(dev) && !is5365(dev))
646 b53_set_jumbo(dev, dev->enable_jumbo, false);
647
648 return 0;
649}
5c1a6eaf 650EXPORT_SYMBOL(b53_configure_vlan);
967dd82f
FF		 651
652static void b53_switch_reset_gpio(struct b53_device *dev)
653{
654 int gpio = dev->reset_gpio;
655
656 if (gpio < 0)
657 return;
658
659 /* Reset sequence: RESET low(50ms)->high(20ms)
660 */
661 gpio_set_value(gpio, 0);
662 mdelay(50);
663
664 gpio_set_value(gpio, 1);
665 mdelay(20);
666
667 dev->current_page = 0xff;
668}
669
670static int b53_switch_reset(struct b53_device *dev)
671{
3fb22b05
FF		 672 unsigned int timeout = 1000;
673 u8 mgmt, reg;
967dd82f
FF		 674
675 b53_switch_reset_gpio(dev);
676
677 if (is539x(dev)) {
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
680 }
681
3fb22b05
FF		 682 /* This is specific to 58xx devices here, do not use is58xx() which
683 * covers the larger Starfigther 2 family, including 7445/7278 which
684 * still use this driver as a library and need to perform the reset
685 * earlier.
686 */
687 if (dev->chip_id == BCM58XX_DEVICE_ID) {
688 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
689 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
690 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
691
692 do {
693 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
694 if (!(reg & SW_RST))
695 break;
696
697 usleep_range(1000, 2000);
698 } while (timeout-- > 0);
699
700 if (timeout == 0)
701 return -ETIMEDOUT;
702 }
703
967dd82f
FF		 704 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
705
706 if (!(mgmt & SM_SW_FWD_EN)) {
707 mgmt &= ~SM_SW_FWD_MODE;
708 mgmt |= SM_SW_FWD_EN;
709
710 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
711 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
712
713 if (!(mgmt & SM_SW_FWD_EN)) {
714 dev_err(dev->dev, "Failed to enable switch!\n");
715 return -EINVAL;
716 }
717 }
718
719 b53_enable_mib(dev);
720
ff39c2d6 721 return b53_flush_arl(dev, FAST_AGE_STATIC);
967dd82f
FF		 722}
723
724static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
725{
04bed143 726 struct b53_device *priv = ds->priv;
967dd82f
FF		 727 u16 value = 0;
728 int ret;
729
730 if (priv->ops->phy_read16)
731 ret = priv->ops->phy_read16(priv, addr, reg, &value);
732 else
733 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
734 reg * 2, &value);
735
736 return ret ? ret : value;
737}
738
739static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
740{
04bed143 741 struct b53_device *priv = ds->priv;
967dd82f
FF		 742
743 if (priv->ops->phy_write16)
744 return priv->ops->phy_write16(priv, addr, reg, val);
745
746 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
747}
748
749static int b53_reset_switch(struct b53_device *priv)
750{
751 /* reset vlans */
752 priv->enable_jumbo = false;
753
a2482d2c 754 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
967dd82f
FF		 755 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
756
757 return b53_switch_reset(priv);
758}
759
760static int b53_apply_config(struct b53_device *priv)
761{
762 /* disable switching */
763 b53_set_forwarding(priv, 0);
764
5c1a6eaf 765 b53_configure_vlan(priv->ds);
967dd82f
FF		 766
767 /* enable switching */
768 b53_set_forwarding(priv, 1);
769
770 return 0;
771}
772
773static void b53_reset_mib(struct b53_device *priv)
774{
775 u8 gc;
776
777 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
778
779 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
780 msleep(1);
781 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
782 msleep(1);
783}
784
785static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
786{
787 if (is5365(dev))
788 return b53_mibs_65;
789 else if (is63xx(dev))
790 return b53_mibs_63xx;
bde5d132
FF		 791 else if (is58xx(dev))
792 return b53_mibs_58xx;
967dd82f
FF		 793 else
794 return b53_mibs;
795}
796
797static unsigned int b53_get_mib_size(struct b53_device *dev)
798{
799 if (is5365(dev))
800 return B53_MIBS_65_SIZE;
801 else if (is63xx(dev))
802 return B53_MIBS_63XX_SIZE;
bde5d132
FF		 803 else if (is58xx(dev))
804 return B53_MIBS_58XX_SIZE;
967dd82f
FF		 805 else
806 return B53_MIBS_SIZE;
807}
808
c7d28c9d
FF		 809static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
810{
811 /* These ports typically do not have built-in PHYs */
812 switch (port) {
813 case B53_CPU_PORT_25:
814 case 7:
815 case B53_CPU_PORT:
816 return NULL;
817 }
818
819 return mdiobus_get_phy(ds->slave_mii_bus, port);
820}
821
89f09048
FF		 822void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
823 uint8_t *data)
967dd82f 824{
04bed143 825 struct b53_device *dev = ds->priv;
967dd82f
FF		 826 const struct b53_mib_desc *mibs = b53_get_mib(dev);
827 unsigned int mib_size = b53_get_mib_size(dev);
c7d28c9d 828 struct phy_device *phydev;
967dd82f
FF		 829 unsigned int i;
830
c7d28c9d
FF		 831 if (stringset == ETH_SS_STATS) {
832 for (i = 0; i < mib_size; i++)
833 strlcpy(data + i * ETH_GSTRING_LEN,
834 mibs[i].name, ETH_GSTRING_LEN);
835 } else if (stringset == ETH_SS_PHY_STATS) {
836 phydev = b53_get_phy_device(ds, port);
837 if (!phydev)
838 return;
89f09048 839
c7d28c9d
FF		 840 phy_ethtool_get_strings(phydev, data);
841 }
967dd82f 842}
3117455d 843EXPORT_SYMBOL(b53_get_strings);
967dd82f 844
3117455d 845void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
967dd82f 846{
04bed143 847 struct b53_device *dev = ds->priv;
967dd82f
FF		 848 const struct b53_mib_desc *mibs = b53_get_mib(dev);
849 unsigned int mib_size = b53_get_mib_size(dev);
850 const struct b53_mib_desc *s;
851 unsigned int i;
852 u64 val = 0;
853
854 if (is5365(dev) && port == 5)
855 port = 8;
856
857 mutex_lock(&dev->stats_mutex);
858
859 for (i = 0; i < mib_size; i++) {
860 s = &mibs[i];
861
51dca8a1 862 if (s->size == 8) {
967dd82f
FF		 863 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
864 } else {
865 u32 val32;
866
867 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
868 &val32);
869 val = val32;
870 }
871 data[i] = (u64)val;
872 }
873
874 mutex_unlock(&dev->stats_mutex);
875}
3117455d 876EXPORT_SYMBOL(b53_get_ethtool_stats);
967dd82f 877
c7d28c9d
FF		 878void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
879{
880 struct phy_device *phydev;
881
882 phydev = b53_get_phy_device(ds, port);
883 if (!phydev)
884 return;
885
886 phy_ethtool_get_stats(phydev, NULL, data);
887}
888EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
889
89f09048 890int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
967dd82f 891{
04bed143 892 struct b53_device *dev = ds->priv;
c7d28c9d 893 struct phy_device *phydev;
967dd82f 894
c7d28c9d
FF		 895 if (sset == ETH_SS_STATS) {
896 return b53_get_mib_size(dev);
897 } else if (sset == ETH_SS_PHY_STATS) {
898 phydev = b53_get_phy_device(ds, port);
899 if (!phydev)
900 return 0;
901
902 return phy_ethtool_get_sset_count(phydev);
903 }
89f09048 904
c7d28c9d 905 return 0;
967dd82f 906}
3117455d 907EXPORT_SYMBOL(b53_get_sset_count);
967dd82f 908
967dd82f
FF		 909static int b53_setup(struct dsa_switch *ds)
910{
04bed143 911 struct b53_device *dev = ds->priv;
967dd82f
FF		 912 unsigned int port;
913 int ret;
914
915 ret = b53_reset_switch(dev);
916 if (ret) {
917 dev_err(ds->dev, "failed to reset switch\n");
918 return ret;
919 }
920
921 b53_reset_mib(dev);
922
923 ret = b53_apply_config(dev);
924 if (ret)
925 dev_err(ds->dev, "failed to apply configuration\n");
926
34c8befd
FF		 927 /* Configure IMP/CPU port, disable unused ports. Enabled
928 * ports will be configured with .port_enable
929 */
967dd82f 930 for (port = 0; port < dev->num_ports; port++) {
34c8befd 931 if (dsa_is_cpu_port(ds, port))
299752a7 932 b53_enable_cpu_port(dev, port);
bff7b688 933 else if (dsa_is_unused_port(ds, port))
967dd82f
FF		 934 b53_disable_port(ds, port, NULL);
935 }
936
937 return ret;
938}
939
940static void b53_adjust_link(struct dsa_switch *ds, int port,
941 struct phy_device *phydev)
942{
04bed143 943 struct b53_device *dev = ds->priv;
f43a2dbe 944 struct ethtool_eee *p = &dev->ports[port].eee;
967dd82f
FF		 945 u8 rgmii_ctrl = 0, reg = 0, off;
946
947 if (!phy_is_pseudo_fixed_link(phydev))
948 return;
949
950 /* Override the port settings */
951 if (port == dev->cpu_port) {
952 off = B53_PORT_OVERRIDE_CTRL;
953 reg = PORT_OVERRIDE_EN;
954 } else {
955 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
956 reg = GMII_PO_EN;
957 }
958
959 /* Set the link UP */
960 if (phydev->link)
961 reg |= PORT_OVERRIDE_LINK;
962
963 if (phydev->duplex == DUPLEX_FULL)
964 reg |= PORT_OVERRIDE_FULL_DUPLEX;
965
966 switch (phydev->speed) {
967 case 2000:
968 reg |= PORT_OVERRIDE_SPEED_2000M;
969 /* fallthrough */
970 case SPEED_1000:
971 reg |= PORT_OVERRIDE_SPEED_1000M;
972 break;
973 case SPEED_100:
974 reg |= PORT_OVERRIDE_SPEED_100M;
975 break;
976 case SPEED_10:
977 reg |= PORT_OVERRIDE_SPEED_10M;
978 break;
979 default:
980 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
981 return;
982 }
983
984 /* Enable flow control on BCM5301x's CPU port */
985 if (is5301x(dev) && port == dev->cpu_port)
986 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
987
988 if (phydev->pause) {
989 if (phydev->asym_pause)
990 reg |= PORT_OVERRIDE_TX_FLOW;
991 reg |= PORT_OVERRIDE_RX_FLOW;
992 }
993
994 b53_write8(dev, B53_CTRL_PAGE, off, reg);
995
996 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
997 if (port == 8)
998 off = B53_RGMII_CTRL_IMP;
999 else
1000 off = B53_RGMII_CTRL_P(port);
1001
1002 /* Configure the port RGMII clock delay by DLL disabled and
1003 * tx_clk aligned timing (restoring to reset defaults)
1004 */
1005 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1006 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1007 RGMII_CTRL_TIMING_SEL);
1008
1009 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1010 * sure that we enable the port TX clock internal delay to
1011 * account for this internal delay that is inserted, otherwise
1012 * the switch won't be able to receive correctly.
1013 *
1014 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1015 * any delay neither on transmission nor reception, so the
1016 * BCM53125 must also be configured accordingly to account for
1017 * the lack of delay and introduce
1018 *
1019 * The BCM53125 switch has its RX clock and TX clock control
1020 * swapped, hence the reason why we modify the TX clock path in
1021 * the "RGMII" case
1022 */
1023 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1024 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1025 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1026 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1027 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1028 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1029
1030 dev_info(ds->dev, "Configured port %d for %s\n", port,
1031 phy_modes(phydev->interface));
1032 }
1033
1034 /* configure MII port if necessary */
1035 if (is5325(dev)) {
1036 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1037 &reg);
1038
1039 /* reverse mii needs to be enabled */
1040 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1041 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1042 reg | PORT_OVERRIDE_RV_MII_25);
1043 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1044 &reg);
1045
1046 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1047 dev_err(ds->dev,
1048 "Failed to enable reverse MII mode\n");
1049 return;
1050 }
1051 }
1052 } else if (is5301x(dev)) {
1053 if (port != dev->cpu_port) {
1054 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1055 u8 gmii_po;
1056
1057 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1058 gmii_po |= GMII_PO_LINK |
1059 GMII_PO_RX_FLOW |
1060 GMII_PO_TX_FLOW |
1061 GMII_PO_EN |
1062 GMII_PO_SPEED_2000M;
1063 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1064 }
1065 }
f43a2dbe
FF		 1066
1067 /* Re-negotiate EEE if it was enabled already */
1068 p->eee_enabled = b53_eee_init(ds, port, phydev);
967dd82f
FF		 1069}
1070
3117455d 1071int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
a2482d2c
FF		 1072{
1073 return 0;
1074}
3117455d 1075EXPORT_SYMBOL(b53_vlan_filtering);
a2482d2c 1076
3117455d 1077int b53_vlan_prepare(struct dsa_switch *ds, int port,
80e02360 1078 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1079{
04bed143 1080 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1081
1082 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1083 return -EOPNOTSUPP;
1084
1085 if (vlan->vid_end > dev->num_vlans)
1086 return -ERANGE;
1087
1088 b53_enable_vlan(dev, true);
1089
1090 return 0;
1091}
3117455d 1092EXPORT_SYMBOL(b53_vlan_prepare);
a2482d2c 1093
3117455d 1094void b53_vlan_add(struct dsa_switch *ds, int port,
80e02360 1095 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1096{
04bed143 1097 struct b53_device *dev = ds->priv;
a2482d2c
FF		 1098 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1099 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
a2482d2c
FF		 1100 struct b53_vlan *vl;
1101 u16 vid;
1102
1103 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1104 vl = &dev->vlans[vid];
1105
1106 b53_get_vlan_entry(dev, vid, vl);
1107
c499696e 1108 vl->members |= BIT(port);
a2482d2c 1109 if (untagged)
e47112d9 1110 vl->untag |= BIT(port);
a2482d2c 1111 else
e47112d9 1112 vl->untag &= ~BIT(port);
a2482d2c
FF		 1113
1114 b53_set_vlan_entry(dev, vid, vl);
1115 b53_fast_age_vlan(dev, vid);
1116 }
1117
1118 if (pvid) {
1119 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1120 vlan->vid_end);
a2482d2c
FF		 1121 b53_fast_age_vlan(dev, vid);
1122 }
1123}
3117455d 1124EXPORT_SYMBOL(b53_vlan_add);
a2482d2c 1125
3117455d
FF		 1126int b53_vlan_del(struct dsa_switch *ds, int port,
1127 const struct switchdev_obj_port_vlan *vlan)
a2482d2c 1128{
04bed143 1129 struct b53_device *dev = ds->priv;
a2482d2c 1130 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
a2482d2c
FF		 1131 struct b53_vlan *vl;
1132 u16 vid;
1133 u16 pvid;
1134
1135 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1136
1137 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1138 vl = &dev->vlans[vid];
1139
1140 b53_get_vlan_entry(dev, vid, vl);
1141
1142 vl->members &= ~BIT(port);
a2482d2c
FF		 1143
1144 if (pvid == vid) {
1145 if (is5325(dev) || is5365(dev))
1146 pvid = 1;
1147 else
1148 pvid = 0;
1149 }
1150
e47112d9 1151 if (untagged)
a2482d2c 1152 vl->untag &= ~(BIT(port));
a2482d2c
FF		 1153
1154 b53_set_vlan_entry(dev, vid, vl);
1155 b53_fast_age_vlan(dev, vid);
1156 }
1157
1158 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
a2482d2c
FF		 1159 b53_fast_age_vlan(dev, pvid);
1160
1161 return 0;
1162}
3117455d 1163EXPORT_SYMBOL(b53_vlan_del);
a2482d2c 1164
1da6df85
FF		 1165/* Address Resolution Logic routines */
1166static int b53_arl_op_wait(struct b53_device *dev)
1167{
1168 unsigned int timeout = 10;
1169 u8 reg;
1170
1171 do {
1172 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1173 if (!(reg & ARLTBL_START_DONE))
1174 return 0;
1175
1176 usleep_range(1000, 2000);
1177 } while (timeout--);
1178
1179 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1180
1181 return -ETIMEDOUT;
1182}
1183
1184static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1185{
1186 u8 reg;
1187
1188 if (op > ARLTBL_RW)
1189 return -EINVAL;
1190
1191 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1192 reg |= ARLTBL_START_DONE;
1193 if (op)
1194 reg |= ARLTBL_RW;
1195 else
1196 reg &= ~ARLTBL_RW;
1197 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1198
1199 return b53_arl_op_wait(dev);
1200}
1201
1202static int b53_arl_read(struct b53_device *dev, u64 mac,
1203 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1204 bool is_valid)
1205{
1206 unsigned int i;
1207 int ret;
1208
1209 ret = b53_arl_op_wait(dev);
1210 if (ret)
1211 return ret;
1212
1213 /* Read the bins */
1214 for (i = 0; i < dev->num_arl_entries; i++) {
1215 u64 mac_vid;
1216 u32 fwd_entry;
1217
1218 b53_read64(dev, B53_ARLIO_PAGE,
1219 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1220 b53_read32(dev, B53_ARLIO_PAGE,
1221 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1222 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1223
1224 if (!(fwd_entry & ARLTBL_VALID))
1225 continue;
1226 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1227 continue;
1228 *idx = i;
1229 }
1230
1231 return -ENOENT;
1232}
1233
1234static int b53_arl_op(struct b53_device *dev, int op, int port,
1235 const unsigned char *addr, u16 vid, bool is_valid)
1236{
1237 struct b53_arl_entry ent;
1238 u32 fwd_entry;
1239 u64 mac, mac_vid = 0;
1240 u8 idx = 0;
1241 int ret;
1242
1243 /* Convert the array into a 64-bit MAC */
4b92ea81 1244 mac = ether_addr_to_u64(addr);
1da6df85
FF		 1245
1246 /* Perform a read for the given MAC and VID */
1247 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1248 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1249
1250 /* Issue a read operation for this MAC */
1251 ret = b53_arl_rw_op(dev, 1);
1252 if (ret)
1253 return ret;
1254
1255 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1256 /* If this is a read, just finish now */
1257 if (op)
1258 return ret;
1259
1260 /* We could not find a matching MAC, so reset to a new entry */
1261 if (ret) {
1262 fwd_entry = 0;
1263 idx = 1;
1264 }
1265
1266 memset(&ent, 0, sizeof(ent));
1267 ent.port = port;
1268 ent.is_valid = is_valid;
1269 ent.vid = vid;
1270 ent.is_static = true;
1271 memcpy(ent.mac, addr, ETH_ALEN);
1272 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1273
1274 b53_write64(dev, B53_ARLIO_PAGE,
1275 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1276 b53_write32(dev, B53_ARLIO_PAGE,
1277 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1278
1279 return b53_arl_rw_op(dev, 0);
1280}
1281
1b6dd556
AS		 1282int b53_fdb_add(struct dsa_switch *ds, int port,
1283 const unsigned char *addr, u16 vid)
1da6df85 1284{
04bed143 1285 struct b53_device *priv = ds->priv;
1da6df85
FF		 1286
1287 /* 5325 and 5365 require some more massaging, but could
1288 * be supported eventually
1289 */
1290 if (is5325(priv) || is5365(priv))
1291 return -EOPNOTSUPP;
1292
1b6dd556 1293 return b53_arl_op(priv, 0, port, addr, vid, true);
1da6df85 1294}
3117455d 1295EXPORT_SYMBOL(b53_fdb_add);
1da6df85 1296
3117455d 1297int b53_fdb_del(struct dsa_switch *ds, int port,
6c2c1dcb 1298 const unsigned char *addr, u16 vid)
1da6df85 1299{
04bed143 1300 struct b53_device *priv = ds->priv;
1da6df85 1301
6c2c1dcb 1302 return b53_arl_op(priv, 0, port, addr, vid, false);
1da6df85 1303}
3117455d 1304EXPORT_SYMBOL(b53_fdb_del);
1da6df85
FF		 1305
1306static int b53_arl_search_wait(struct b53_device *dev)
1307{
1308 unsigned int timeout = 1000;
1309 u8 reg;
1310
1311 do {
1312 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1313 if (!(reg & ARL_SRCH_STDN))
1314 return 0;
1315
1316 if (reg & ARL_SRCH_VLID)
1317 return 0;
1318
1319 usleep_range(1000, 2000);
1320 } while (timeout--);
1321
1322 return -ETIMEDOUT;
1323}
1324
1325static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1326 struct b53_arl_entry *ent)
1327{
1328 u64 mac_vid;
1329 u32 fwd_entry;
1330
1331 b53_read64(dev, B53_ARLIO_PAGE,
1332 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1333 b53_read32(dev, B53_ARLIO_PAGE,
1334 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1335 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1336}
1337
e6cbef0c 1338static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
2bedde1a 1339 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85
FF		 1340{
1341 if (!ent->is_valid)
1342 return 0;
1343
1344 if (port != ent->port)
1345 return 0;
1346
2bedde1a 1347 return cb(ent->mac, ent->vid, ent->is_static, data);
1da6df85
FF		 1348}
1349
3117455d 1350int b53_fdb_dump(struct dsa_switch *ds, int port,
2bedde1a 1351 dsa_fdb_dump_cb_t *cb, void *data)
1da6df85 1352{
04bed143 1353 struct b53_device *priv = ds->priv;
1da6df85
FF		 1354 struct b53_arl_entry results[2];
1355 unsigned int count = 0;
1356 int ret;
1357 u8 reg;
1358
1359 /* Start search operation */
1360 reg = ARL_SRCH_STDN;
1361 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1362
1363 do {
1364 ret = b53_arl_search_wait(priv);
1365 if (ret)
1366 return ret;
1367
1368 b53_arl_search_rd(priv, 0, &results[0]);
2bedde1a 1369 ret = b53_fdb_copy(port, &results[0], cb, data);
1da6df85
FF		 1370 if (ret)
1371 return ret;
1372
1373 if (priv->num_arl_entries > 2) {
1374 b53_arl_search_rd(priv, 1, &results[1]);
2bedde1a 1375 ret = b53_fdb_copy(port, &results[1], cb, data);
1da6df85
FF		 1376 if (ret)
1377 return ret;
1378
1379 if (!results[0].is_valid && !results[1].is_valid)
1380 break;
1381 }
1382
1383 } while (count++ < 1024);
1384
1385 return 0;
1386}
3117455d 1387EXPORT_SYMBOL(b53_fdb_dump);
1da6df85 1388
ddd3a0c8 1389int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1390{
04bed143 1391 struct b53_device *dev = ds->priv;
0abfd494 1392 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6
FF		 1393 u16 pvlan, reg;
1394 unsigned int i;
1395
48aea33a
FF		 1396 /* Make this port leave the all VLANs join since we will have proper
1397 * VLAN entries from now on
1398 */
1399 if (is58xx(dev)) {
1400 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1401 reg &= ~BIT(port);
1402 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1403 reg &= ~BIT(cpu_port);
1404 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1405 }
1406
ff39c2d6
FF		 1407 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1408
1409 b53_for_each_port(dev, i) {
c8652c83 1410 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1411 continue;
1412
1413 /* Add this local port to the remote port VLAN control
1414 * membership and update the remote port bitmask
1415 */
1416 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1417 reg |= BIT(port);
1418 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1419 dev->ports[i].vlan_ctl_mask = reg;
1420
1421 pvlan |= BIT(i);
1422 }
1423
1424 /* Configure the local port VLAN control membership to include
1425 * remote ports and update the local port bitmask
1426 */
1427 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1428 dev->ports[port].vlan_ctl_mask = pvlan;
1429
1430 return 0;
1431}
3117455d 1432EXPORT_SYMBOL(b53_br_join);
ff39c2d6 1433
f123f2fb 1434void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
ff39c2d6 1435{
04bed143 1436 struct b53_device *dev = ds->priv;
a2482d2c 1437 struct b53_vlan *vl = &dev->vlans[0];
0abfd494 1438 s8 cpu_port = ds->ports[port].cpu_dp->index;
ff39c2d6 1439 unsigned int i;
a2482d2c 1440 u16 pvlan, reg, pvid;
ff39c2d6
FF		 1441
1442 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1443
1444 b53_for_each_port(dev, i) {
1445 /* Don't touch the remaining ports */
c8652c83 1446 if (dsa_to_port(ds, i)->bridge_dev != br)
ff39c2d6
FF		 1447 continue;
1448
1449 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1450 reg &= ~BIT(port);
1451 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1452 dev->ports[port].vlan_ctl_mask = reg;
1453
1454 /* Prevent self removal to preserve isolation */
1455 if (port != i)
1456 pvlan &= ~BIT(i);
1457 }
1458
1459 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1460 dev->ports[port].vlan_ctl_mask = pvlan;
a2482d2c
FF		 1461
1462 if (is5325(dev) || is5365(dev))
1463 pvid = 1;
1464 else
1465 pvid = 0;
1466
48aea33a
FF		 1467 /* Make this port join all VLANs without VLAN entries */
1468 if (is58xx(dev)) {
1469 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1470 reg |= BIT(port);
1471 if (!(reg & BIT(cpu_port)))
1472 reg |= BIT(cpu_port);
1473 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1474 } else {
1475 b53_get_vlan_entry(dev, pvid, vl);
c499696e
FF		 1476 vl->members |= BIT(port) | BIT(cpu_port);
1477 vl->untag |= BIT(port) | BIT(cpu_port);
48aea33a
FF		 1478 b53_set_vlan_entry(dev, pvid, vl);
1479 }
ff39c2d6 1480}
3117455d 1481EXPORT_SYMBOL(b53_br_leave);
ff39c2d6 1482
3117455d 1483void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
ff39c2d6 1484{
04bed143 1485 struct b53_device *dev = ds->priv;
597698f1 1486 u8 hw_state;
ff39c2d6
FF		 1487 u8 reg;
1488
ff39c2d6
FF		 1489 switch (state) {
1490 case BR_STATE_DISABLED:
1491 hw_state = PORT_CTRL_DIS_STATE;
1492 break;
1493 case BR_STATE_LISTENING:
1494 hw_state = PORT_CTRL_LISTEN_STATE;
1495 break;
1496 case BR_STATE_LEARNING:
1497 hw_state = PORT_CTRL_LEARN_STATE;
1498 break;
1499 case BR_STATE_FORWARDING:
1500 hw_state = PORT_CTRL_FWD_STATE;
1501 break;
1502 case BR_STATE_BLOCKING:
1503 hw_state = PORT_CTRL_BLOCK_STATE;
1504 break;
1505 default:
1506 dev_err(ds->dev, "invalid STP state: %d\n", state);
1507 return;
1508 }
1509
ff39c2d6
FF		 1510 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1511 reg &= ~PORT_CTRL_STP_STATE_MASK;
1512 reg |= hw_state;
1513 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1514}
3117455d 1515EXPORT_SYMBOL(b53_br_set_stp_state);
ff39c2d6 1516
3117455d 1517void b53_br_fast_age(struct dsa_switch *ds, int port)
597698f1
VD		 1518{
1519 struct b53_device *dev = ds->priv;
1520
1521 if (b53_fast_age_port(dev, port))
1522 dev_err(ds->dev, "fast ageing failed\n");
1523}
3117455d 1524EXPORT_SYMBOL(b53_br_fast_age);
597698f1 1525
c7d28c9d 1526static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
7edc58d6 1527{
7edc58d6
FF		 1528 /* Broadcom switches will accept enabling Broadcom tags on the
1529 * following ports: 5, 7 and 8, any other port is not supported
1530 */
5ed4e3eb
FF		 1531 switch (port) {
1532 case B53_CPU_PORT_25:
1533 case 7:
1534 case B53_CPU_PORT:
1535 return true;
7edc58d6
FF		 1536 }
1537
5ed4e3eb 1538 return false;
7edc58d6
FF		 1539}
1540
c7d28c9d
FF		 1541static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1542{
1543 bool ret = b53_possible_cpu_port(ds, port);
1544
1545 if (!ret)
1546 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
1547 port);
1548 return ret;
1549}
1550
9f66816a 1551enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
7b314362 1552{
7edc58d6
FF		 1553 struct b53_device *dev = ds->priv;
1554
54e98b5d
FF		 1555 /* Older models (5325, 5365) support a different tag format that we do
1556 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1557 * mode to be turned on which means we need to specifically manage ARL
1558 * misses on multicast addresses (TBD).
7edc58d6 1559 */
54e98b5d
FF		 1560 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1561 !b53_can_enable_brcm_tags(ds, port))
7edc58d6 1562 return DSA_TAG_PROTO_NONE;
11606039
FF		 1563
1564 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1565 * which requires us to use the prepended Broadcom tag type
1566 */
1567 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1568 return DSA_TAG_PROTO_BRCM_PREPEND;
1569
1570 return DSA_TAG_PROTO_BRCM;
7b314362 1571}
9f66816a 1572EXPORT_SYMBOL(b53_get_tag_protocol);
7b314362 1573
ed3af5fd
FF		 1574int b53_mirror_add(struct dsa_switch *ds, int port,
1575 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1576{
1577 struct b53_device *dev = ds->priv;
1578 u16 reg, loc;
1579
1580 if (ingress)
1581 loc = B53_IG_MIR_CTL;
1582 else
1583 loc = B53_EG_MIR_CTL;
1584
1585 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1586 reg &= ~MIRROR_MASK;
1587 reg |= BIT(port);
1588 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1589
1590 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1591 reg &= ~CAP_PORT_MASK;
1592 reg |= mirror->to_local_port;
1593 reg |= MIRROR_EN;
1594 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1595
1596 return 0;
1597}
1598EXPORT_SYMBOL(b53_mirror_add);
1599
1600void b53_mirror_del(struct dsa_switch *ds, int port,
1601 struct dsa_mall_mirror_tc_entry *mirror)
1602{
1603 struct b53_device *dev = ds->priv;
1604 bool loc_disable = false, other_loc_disable = false;
1605 u16 reg, loc;
1606
1607 if (mirror->ingress)
1608 loc = B53_IG_MIR_CTL;
1609 else
1610 loc = B53_EG_MIR_CTL;
1611
1612 /* Update the desired ingress/egress register */
1613 b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1614 reg &= ~BIT(port);
1615 if (!(reg & MIRROR_MASK))
1616 loc_disable = true;
1617 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1618
1619 /* Now look at the other one to know if we can disable mirroring
1620 * entirely
1621 */
1622 if (mirror->ingress)
1623 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1624 else
1625 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1626 if (!(reg & MIRROR_MASK))
1627 other_loc_disable = true;
1628
1629 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1630 /* Both no longer have ports, let's disable mirroring */
1631 if (loc_disable && other_loc_disable) {
1632 reg &= ~MIRROR_EN;
1633 reg &= ~mirror->to_local_port;
1634 }
1635 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1636}
1637EXPORT_SYMBOL(b53_mirror_del);
1638
22256b0a
FF		 1639void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1640{
1641 struct b53_device *dev = ds->priv;
1642 u16 reg;
1643
1644 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1645 if (enable)
1646 reg |= BIT(port);
1647 else
1648 reg &= ~BIT(port);
1649 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1650}
1651EXPORT_SYMBOL(b53_eee_enable_set);
1652
1653
1654/* Returns 0 if EEE was not enabled, or 1 otherwise
1655 */
1656int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1657{
1658 int ret;
1659
1660 ret = phy_init_eee(phy, 0);
1661 if (ret)
1662 return 0;
1663
1664 b53_eee_enable_set(ds, port, true);
1665
1666 return 1;
1667}
1668EXPORT_SYMBOL(b53_eee_init);
1669
1670int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1671{
1672 struct b53_device *dev = ds->priv;
1673 struct ethtool_eee *p = &dev->ports[port].eee;
1674 u16 reg;
1675
1676 if (is5325(dev) || is5365(dev))
1677 return -EOPNOTSUPP;
1678
1679 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1680 e->eee_enabled = p->eee_enabled;
1681 e->eee_active = !!(reg & BIT(port));
1682
1683 return 0;
1684}
1685EXPORT_SYMBOL(b53_get_mac_eee);
1686
1687int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1688{
1689 struct b53_device *dev = ds->priv;
1690 struct ethtool_eee *p = &dev->ports[port].eee;
1691
1692 if (is5325(dev) || is5365(dev))
1693 return -EOPNOTSUPP;
1694
1695 p->eee_enabled = e->eee_enabled;
1696 b53_eee_enable_set(ds, port, e->eee_enabled);
1697
1698 return 0;
1699}
1700EXPORT_SYMBOL(b53_set_mac_eee);
1701
a82f67af 1702static const struct dsa_switch_ops b53_switch_ops = {
7b314362 1703 .get_tag_protocol = b53_get_tag_protocol,
967dd82f 1704 .setup = b53_setup,
967dd82f
FF		 1705 .get_strings = b53_get_strings,
1706 .get_ethtool_stats = b53_get_ethtool_stats,
1707 .get_sset_count = b53_get_sset_count,
c7d28c9d 1708 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
967dd82f
FF		 1709 .phy_read = b53_phy_read16,
1710 .phy_write = b53_phy_write16,
1711 .adjust_link = b53_adjust_link,
1712 .port_enable = b53_enable_port,
1713 .port_disable = b53_disable_port,
f43a2dbe
FF		 1714 .get_mac_eee = b53_get_mac_eee,
1715 .set_mac_eee = b53_set_mac_eee,
ff39c2d6
FF		 1716 .port_bridge_join = b53_br_join,
1717 .port_bridge_leave = b53_br_leave,
1718 .port_stp_state_set = b53_br_set_stp_state,
597698f1 1719 .port_fast_age = b53_br_fast_age,
a2482d2c
FF		 1720 .port_vlan_filtering = b53_vlan_filtering,
1721 .port_vlan_prepare = b53_vlan_prepare,
1722 .port_vlan_add = b53_vlan_add,
1723 .port_vlan_del = b53_vlan_del,
1da6df85
FF		 1724 .port_fdb_dump = b53_fdb_dump,
1725 .port_fdb_add = b53_fdb_add,
1726 .port_fdb_del = b53_fdb_del,
ed3af5fd
FF		 1727 .port_mirror_add = b53_mirror_add,
1728 .port_mirror_del = b53_mirror_del,
967dd82f
FF		 1729};
1730
1731struct b53_chip_data {
1732 u32 chip_id;
1733 const char *dev_name;
1734 u16 vlans;
1735 u16 enabled_ports;
1736 u8 cpu_port;
1737 u8 vta_regs[3];
1da6df85 1738 u8 arl_entries;
967dd82f
FF		 1739 u8 duplex_reg;
1740 u8 jumbo_pm_reg;
1741 u8 jumbo_size_reg;
1742};
1743
1744#define B53_VTA_REGS \
1745 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1746#define B53_VTA_REGS_9798 \
1747 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1748#define B53_VTA_REGS_63XX \
1749 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1750
1751static const struct b53_chip_data b53_switch_chips[] = {
1752 {
1753 .chip_id = BCM5325_DEVICE_ID,
1754 .dev_name = "BCM5325",
1755 .vlans = 16,
1756 .enabled_ports = 0x1f,
1da6df85 1757 .arl_entries = 2,
967dd82f
FF		 1758 .cpu_port = B53_CPU_PORT_25,
1759 .duplex_reg = B53_DUPLEX_STAT_FE,
1760 },
1761 {
1762 .chip_id = BCM5365_DEVICE_ID,
1763 .dev_name = "BCM5365",
1764 .vlans = 256,
1765 .enabled_ports = 0x1f,
1da6df85 1766 .arl_entries = 2,
967dd82f
FF		 1767 .cpu_port = B53_CPU_PORT_25,
1768 .duplex_reg = B53_DUPLEX_STAT_FE,
1769 },
a95691bc
DT		 1770 {
1771 .chip_id = BCM5389_DEVICE_ID,
1772 .dev_name = "BCM5389",
1773 .vlans = 4096,
1774 .enabled_ports = 0x1f,
1775 .arl_entries = 4,
1776 .cpu_port = B53_CPU_PORT,
1777 .vta_regs = B53_VTA_REGS,
1778 .duplex_reg = B53_DUPLEX_STAT_GE,
1779 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1780 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1781 },
967dd82f
FF		 1782 {
1783 .chip_id = BCM5395_DEVICE_ID,
1784 .dev_name = "BCM5395",
1785 .vlans = 4096,
1786 .enabled_ports = 0x1f,
1da6df85 1787 .arl_entries = 4,
967dd82f
FF		 1788 .cpu_port = B53_CPU_PORT,
1789 .vta_regs = B53_VTA_REGS,
1790 .duplex_reg = B53_DUPLEX_STAT_GE,
1791 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1792 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1793 },
1794 {
1795 .chip_id = BCM5397_DEVICE_ID,
1796 .dev_name = "BCM5397",
1797 .vlans = 4096,
1798 .enabled_ports = 0x1f,
1da6df85 1799 .arl_entries = 4,
967dd82f
FF		 1800 .cpu_port = B53_CPU_PORT,
1801 .vta_regs = B53_VTA_REGS_9798,
1802 .duplex_reg = B53_DUPLEX_STAT_GE,
1803 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1804 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1805 },
1806 {
1807 .chip_id = BCM5398_DEVICE_ID,
1808 .dev_name = "BCM5398",
1809 .vlans = 4096,
1810 .enabled_ports = 0x7f,
1da6df85 1811 .arl_entries = 4,
967dd82f
FF		 1812 .cpu_port = B53_CPU_PORT,
1813 .vta_regs = B53_VTA_REGS_9798,
1814 .duplex_reg = B53_DUPLEX_STAT_GE,
1815 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1816 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1817 },
1818 {
1819 .chip_id = BCM53115_DEVICE_ID,
1820 .dev_name = "BCM53115",
1821 .vlans = 4096,
1822 .enabled_ports = 0x1f,
1da6df85 1823 .arl_entries = 4,
967dd82f
FF		 1824 .vta_regs = B53_VTA_REGS,
1825 .cpu_port = B53_CPU_PORT,
1826 .duplex_reg = B53_DUPLEX_STAT_GE,
1827 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1828 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1829 },
1830 {
1831 .chip_id = BCM53125_DEVICE_ID,
1832 .dev_name = "BCM53125",
1833 .vlans = 4096,
1834 .enabled_ports = 0xff,
be35e8c5 1835 .arl_entries = 4,
967dd82f
FF		 1836 .cpu_port = B53_CPU_PORT,
1837 .vta_regs = B53_VTA_REGS,
1838 .duplex_reg = B53_DUPLEX_STAT_GE,
1839 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1840 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1841 },
1842 {
1843 .chip_id = BCM53128_DEVICE_ID,
1844 .dev_name = "BCM53128",
1845 .vlans = 4096,
1846 .enabled_ports = 0x1ff,
1da6df85 1847 .arl_entries = 4,
967dd82f
FF		 1848 .cpu_port = B53_CPU_PORT,
1849 .vta_regs = B53_VTA_REGS,
1850 .duplex_reg = B53_DUPLEX_STAT_GE,
1851 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1852 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1853 },
1854 {
1855 .chip_id = BCM63XX_DEVICE_ID,
1856 .dev_name = "BCM63xx",
1857 .vlans = 4096,
1858 .enabled_ports = 0, /* pdata must provide them */
1da6df85 1859 .arl_entries = 4,
967dd82f
FF		 1860 .cpu_port = B53_CPU_PORT,
1861 .vta_regs = B53_VTA_REGS_63XX,
1862 .duplex_reg = B53_DUPLEX_STAT_63XX,
1863 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1864 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1865 },
1866 {
1867 .chip_id = BCM53010_DEVICE_ID,
1868 .dev_name = "BCM53010",
1869 .vlans = 4096,
1870 .enabled_ports = 0x1f,
1da6df85 1871 .arl_entries = 4,
967dd82f
FF		 1872 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1873 .vta_regs = B53_VTA_REGS,
1874 .duplex_reg = B53_DUPLEX_STAT_GE,
1875 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1876 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1877 },
1878 {
1879 .chip_id = BCM53011_DEVICE_ID,
1880 .dev_name = "BCM53011",
1881 .vlans = 4096,
1882 .enabled_ports = 0x1bf,
1da6df85 1883 .arl_entries = 4,
967dd82f
FF		 1884 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1885 .vta_regs = B53_VTA_REGS,
1886 .duplex_reg = B53_DUPLEX_STAT_GE,
1887 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1888 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1889 },
1890 {
1891 .chip_id = BCM53012_DEVICE_ID,
1892 .dev_name = "BCM53012",
1893 .vlans = 4096,
1894 .enabled_ports = 0x1bf,
1da6df85 1895 .arl_entries = 4,
967dd82f
FF		 1896 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1897 .vta_regs = B53_VTA_REGS,
1898 .duplex_reg = B53_DUPLEX_STAT_GE,
1899 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1900 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1901 },
1902 {
1903 .chip_id = BCM53018_DEVICE_ID,
1904 .dev_name = "BCM53018",
1905 .vlans = 4096,
1906 .enabled_ports = 0x1f,
1da6df85 1907 .arl_entries = 4,
967dd82f
FF		 1908 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1909 .vta_regs = B53_VTA_REGS,
1910 .duplex_reg = B53_DUPLEX_STAT_GE,
1911 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1912 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1913 },
1914 {
1915 .chip_id = BCM53019_DEVICE_ID,
1916 .dev_name = "BCM53019",
1917 .vlans = 4096,
1918 .enabled_ports = 0x1f,
1da6df85 1919 .arl_entries = 4,
967dd82f
FF		 1920 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1921 .vta_regs = B53_VTA_REGS,
1922 .duplex_reg = B53_DUPLEX_STAT_GE,
1923 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1924 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1925 },
991a36bb
FF		 1926 {
1927 .chip_id = BCM58XX_DEVICE_ID,
1928 .dev_name = "BCM585xx/586xx/88312",
1929 .vlans = 4096,
1930 .enabled_ports = 0x1ff,
1931 .arl_entries = 4,
bfcda65c 1932 .cpu_port = B53_CPU_PORT,
991a36bb
FF		 1933 .vta_regs = B53_VTA_REGS,
1934 .duplex_reg = B53_DUPLEX_STAT_GE,
1935 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1936 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1937 },
130401d9
FF		 1938 {
1939 .chip_id = BCM7445_DEVICE_ID,
1940 .dev_name = "BCM7445",
1941 .vlans = 4096,
1942 .enabled_ports = 0x1ff,
1943 .arl_entries = 4,
1944 .cpu_port = B53_CPU_PORT,
1945 .vta_regs = B53_VTA_REGS,
1946 .duplex_reg = B53_DUPLEX_STAT_GE,
1947 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1948 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1949 },
0fe99338
FF		 1950 {
1951 .chip_id = BCM7278_DEVICE_ID,
1952 .dev_name = "BCM7278",
1953 .vlans = 4096,
1954 .enabled_ports = 0x1ff,
1955 .arl_entries= 4,
1956 .cpu_port = B53_CPU_PORT,
1957 .vta_regs = B53_VTA_REGS,
1958 .duplex_reg = B53_DUPLEX_STAT_GE,
1959 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1960 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1961 },
967dd82f
FF		 1962};
1963
1964static int b53_switch_init(struct b53_device *dev)
1965{
967dd82f
FF		 1966 unsigned int i;
1967 int ret;
1968
1969 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1970 const struct b53_chip_data *chip = &b53_switch_chips[i];
1971
1972 if (chip->chip_id == dev->chip_id) {
1973 if (!dev->enabled_ports)
1974 dev->enabled_ports = chip->enabled_ports;
1975 dev->name = chip->dev_name;
1976 dev->duplex_reg = chip->duplex_reg;
1977 dev->vta_regs[0] = chip->vta_regs[0];
1978 dev->vta_regs[1] = chip->vta_regs[1];
1979 dev->vta_regs[2] = chip->vta_regs[2];
1980 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
967dd82f
FF		 1981 dev->cpu_port = chip->cpu_port;
1982 dev->num_vlans = chip->vlans;
1da6df85 1983 dev->num_arl_entries = chip->arl_entries;
967dd82f
FF		 1984 break;
1985 }
1986 }
1987
1988 /* check which BCM5325x version we have */
1989 if (is5325(dev)) {
1990 u8 vc4;
1991
1992 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1993
1994 /* check reserved bits */
1995 switch (vc4 & 3) {
1996 case 1:
1997 /* BCM5325E */
1998 break;
1999 case 3:
2000 /* BCM5325F - do not use port 4 */
2001 dev->enabled_ports &= ~BIT(4);
2002 break;
2003 default:
2004/* On the BCM47XX SoCs this is the supported internal switch.*/
2005#ifndef CONFIG_BCM47XX
2006 /* BCM5325M */
2007 return -EINVAL;
2008#else
2009 break;
2010#endif
2011 }
2012 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
2013 u64 strap_value;
2014
2015 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
2016 /* use second IMP port if GMII is enabled */
2017 if (strap_value & SV_GMII_CTRL_115)
2018 dev->cpu_port = 5;
2019 }
2020
2021 /* cpu port is always last */
2022 dev->num_ports = dev->cpu_port + 1;
2023 dev->enabled_ports |= BIT(dev->cpu_port);
2024
c7d28c9d
FF		 2025 /* Include non standard CPU port built-in PHYs to be probed */
2026 if (is539x(dev) || is531x5(dev)) {
2027 for (i = 0; i < dev->num_ports; i++) {
2028 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2029 !b53_possible_cpu_port(dev->ds, i))
2030 dev->ds->phys_mii_mask |= BIT(i);
2031 }
2032 }
2033
967dd82f
FF		 2034 dev->ports = devm_kzalloc(dev->dev,
2035 sizeof(struct b53_port) * dev->num_ports,
2036 GFP_KERNEL);
2037 if (!dev->ports)
2038 return -ENOMEM;
2039
a2482d2c
FF		 2040 dev->vlans = devm_kzalloc(dev->dev,
2041 sizeof(struct b53_vlan) * dev->num_vlans,
2042 GFP_KERNEL);
2043 if (!dev->vlans)
2044 return -ENOMEM;
2045
967dd82f
FF		 2046 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2047 if (dev->reset_gpio >= 0) {
2048 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2049 GPIOF_OUT_INIT_HIGH, "robo_reset");
2050 if (ret)
2051 return ret;
2052 }
2053
2054 return 0;
2055}
2056
0dff88d3
JL		 2057struct b53_device *b53_switch_alloc(struct device *base,
2058 const struct b53_io_ops *ops,
967dd82f
FF		 2059 void *priv)
2060{
2061 struct dsa_switch *ds;
2062 struct b53_device *dev;
2063
a0c02161 2064 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
967dd82f
FF		 2065 if (!ds)
2066 return NULL;
2067
a0c02161
VD		 2068 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2069 if (!dev)
2070 return NULL;
967dd82f
FF		 2071
2072 ds->priv = dev;
967dd82f
FF		 2073 dev->dev = base;
2074
2075 dev->ds = ds;
2076 dev->priv = priv;
2077 dev->ops = ops;
485ebd61 2078 ds->ops = &b53_switch_ops;
967dd82f
FF		 2079 mutex_init(&dev->reg_mutex);
2080 mutex_init(&dev->stats_mutex);
2081
2082 return dev;
2083}
2084EXPORT_SYMBOL(b53_switch_alloc);
2085
2086int b53_switch_detect(struct b53_device *dev)
2087{
2088 u32 id32;
2089 u16 tmp;
2090 u8 id8;
2091 int ret;
2092
2093 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2094 if (ret)
2095 return ret;
2096
2097 switch (id8) {
2098 case 0:
2099 /* BCM5325 and BCM5365 do not have this register so reads
2100 * return 0. But the read operation did succeed, so assume this
2101 * is one of them.
2102 *
2103 * Next check if we can write to the 5325's VTA register; for
2104 * 5365 it is read only.
2105 */
2106 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2107 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2108
2109 if (tmp == 0xf)
2110 dev->chip_id = BCM5325_DEVICE_ID;
2111 else
2112 dev->chip_id = BCM5365_DEVICE_ID;
2113 break;
a95691bc 2114 case BCM5389_DEVICE_ID:
967dd82f
FF		 2115 case BCM5395_DEVICE_ID:
2116 case BCM5397_DEVICE_ID:
2117 case BCM5398_DEVICE_ID:
2118 dev->chip_id = id8;
2119 break;
2120 default:
2121 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2122 if (ret)
2123 return ret;
2124
2125 switch (id32) {
2126 case BCM53115_DEVICE_ID:
2127 case BCM53125_DEVICE_ID:
2128 case BCM53128_DEVICE_ID:
2129 case BCM53010_DEVICE_ID:
2130 case BCM53011_DEVICE_ID:
2131 case BCM53012_DEVICE_ID:
2132 case BCM53018_DEVICE_ID:
2133 case BCM53019_DEVICE_ID:
2134 dev->chip_id = id32;
2135 break;
2136 default:
2137 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2138 id8, id32);
2139 return -ENODEV;
2140 }
2141 }
2142
2143 if (dev->chip_id == BCM5325_DEVICE_ID)
2144 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2145 &dev->core_rev);
2146 else
2147 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2148 &dev->core_rev);
2149}
2150EXPORT_SYMBOL(b53_switch_detect);
2151
2152int b53_switch_register(struct b53_device *dev)
2153{
2154 int ret;
2155
2156 if (dev->pdata) {
2157 dev->chip_id = dev->pdata->chip_id;
2158 dev->enabled_ports = dev->pdata->enabled_ports;
2159 }
2160
2161 if (!dev->chip_id && b53_switch_detect(dev))
2162 return -EINVAL;
2163
2164 ret = b53_switch_init(dev);
2165 if (ret)
2166 return ret;
2167
2168 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2169
23c9ee49 2170 return dsa_register_switch(dev->ds);
967dd82f
FF		 2171}
2172EXPORT_SYMBOL(b53_switch_register);
2173
2174MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2175MODULE_DESCRIPTION("B53 switch library");
2176MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)