Commit | Line | Data |
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a1365275 | 1 | /* |
41c340f0 | 2 | * Davicom DM9000 Fast Ethernet driver for Linux. |
a1365275 SH |
3 | * Copyright (C) 1997 Sten Wang |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
41c340f0 | 15 | * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. |
9ef9ac51 | 16 | * |
41c340f0 BD |
17 | * Additional updates, Copyright: |
18 | * Ben Dooks <ben@simtec.co.uk> | |
19 | * Sascha Hauer <s.hauer@pengutronix.de> | |
a1365275 SH |
20 | */ |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/skbuff.h> | |
a1365275 SH |
28 | #include <linux/spinlock.h> |
29 | #include <linux/crc32.h> | |
30 | #include <linux/mii.h> | |
7da99859 | 31 | #include <linux/ethtool.h> |
a1365275 SH |
32 | #include <linux/dm9000.h> |
33 | #include <linux/delay.h> | |
d052d1be | 34 | #include <linux/platform_device.h> |
4e4fc05a | 35 | #include <linux/irq.h> |
a1365275 SH |
36 | |
37 | #include <asm/delay.h> | |
38 | #include <asm/irq.h> | |
39 | #include <asm/io.h> | |
40 | ||
41 | #include "dm9000.h" | |
42 | ||
43 | /* Board/System/Debug information/definition ---------------- */ | |
44 | ||
45 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
46 | ||
59eae1fa BD |
47 | #define CARDNAME "dm9000" |
48 | #define DRV_VERSION "1.31" | |
a1365275 | 49 | |
f40d24d9 AL |
50 | #ifdef CONFIG_BLACKFIN |
51 | #define readsb insb | |
52 | #define readsw insw | |
53 | #define readsl insl | |
54 | #define writesb outsb | |
55 | #define writesw outsw | |
56 | #define writesl outsl | |
1a5f1c4f | 57 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 58 | #else |
1a5f1c4f | 59 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
60 | #endif |
61 | ||
a1365275 SH |
62 | /* |
63 | * Transmit timeout, default 5 seconds. | |
64 | */ | |
65 | static int watchdog = 5000; | |
66 | module_param(watchdog, int, 0400); | |
67 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
68 | ||
9a2f037c BD |
69 | /* DM9000 register address locking. |
70 | * | |
71 | * The DM9000 uses an address register to control where data written | |
72 | * to the data register goes. This means that the address register | |
73 | * must be preserved over interrupts or similar calls. | |
74 | * | |
75 | * During interrupt and other critical calls, a spinlock is used to | |
76 | * protect the system, but the calls themselves save the address | |
77 | * in the address register in case they are interrupting another | |
78 | * access to the device. | |
79 | * | |
80 | * For general accesses a lock is provided so that calls which are | |
81 | * allowed to sleep are serialised so that the address register does | |
82 | * not need to be saved. This lock also serves to serialise access | |
83 | * to the EEPROM and PHY access registers which are shared between | |
84 | * these two devices. | |
85 | */ | |
86 | ||
6d406b3c BD |
87 | /* The driver supports the original DM9000E, and now the two newer |
88 | * devices, DM9000A and DM9000B. | |
89 | */ | |
90 | ||
91 | enum dm9000_type { | |
92 | TYPE_DM9000E, /* original DM9000 */ | |
93 | TYPE_DM9000A, | |
94 | TYPE_DM9000B | |
95 | }; | |
96 | ||
a1365275 SH |
97 | /* Structure/enum declaration ------------------------------- */ |
98 | typedef struct board_info { | |
99 | ||
59eae1fa BD |
100 | void __iomem *io_addr; /* Register I/O base address */ |
101 | void __iomem *io_data; /* Data I/O address */ | |
102 | u16 irq; /* IRQ */ | |
a1365275 | 103 | |
59eae1fa BD |
104 | u16 tx_pkt_cnt; |
105 | u16 queue_pkt_len; | |
106 | u16 queue_start_addr; | |
107 | u16 dbug_cnt; | |
108 | u8 io_mode; /* 0:word, 2:byte */ | |
109 | u8 phy_addr; | |
110 | u8 imr_all; | |
111 | ||
112 | unsigned int flags; | |
113 | unsigned int in_suspend :1; | |
114 | int debug_level; | |
a1365275 | 115 | |
6d406b3c | 116 | enum dm9000_type type; |
5b2b4ff0 | 117 | |
a1365275 SH |
118 | void (*inblk)(void __iomem *port, void *data, int length); |
119 | void (*outblk)(void __iomem *port, void *data, int length); | |
120 | void (*dumpblk)(void __iomem *port, int length); | |
121 | ||
a76836f9 BD |
122 | struct device *dev; /* parent device */ |
123 | ||
a1365275 SH |
124 | struct resource *addr_res; /* resources found */ |
125 | struct resource *data_res; | |
126 | struct resource *addr_req; /* resources requested */ | |
127 | struct resource *data_req; | |
128 | struct resource *irq_res; | |
129 | ||
9a2f037c BD |
130 | struct mutex addr_lock; /* phy and eeprom access lock */ |
131 | ||
8f5bf5f2 BD |
132 | struct delayed_work phy_poll; |
133 | struct net_device *ndev; | |
134 | ||
59eae1fa | 135 | spinlock_t lock; |
a1365275 SH |
136 | |
137 | struct mii_if_info mii; | |
59eae1fa | 138 | u32 msg_enable; |
a1365275 SH |
139 | } board_info_t; |
140 | ||
5b2b4ff0 BD |
141 | /* debug code */ |
142 | ||
143 | #define dm9000_dbg(db, lev, msg...) do { \ | |
144 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
145 | (lev) < db->debug_level) { \ | |
146 | dev_dbg(db->dev, msg); \ | |
147 | } \ | |
148 | } while (0) | |
149 | ||
7da99859 BD |
150 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
151 | { | |
152 | return dev->priv; | |
153 | } | |
154 | ||
a1365275 SH |
155 | /* DM9000 network board routine ---------------------------- */ |
156 | ||
157 | static void | |
158 | dm9000_reset(board_info_t * db) | |
159 | { | |
a76836f9 BD |
160 | dev_dbg(db->dev, "resetting device\n"); |
161 | ||
a1365275 SH |
162 | /* RESET device */ |
163 | writeb(DM9000_NCR, db->io_addr); | |
164 | udelay(200); | |
165 | writeb(NCR_RST, db->io_data); | |
166 | udelay(200); | |
167 | } | |
168 | ||
169 | /* | |
170 | * Read a byte from I/O port | |
171 | */ | |
172 | static u8 | |
173 | ior(board_info_t * db, int reg) | |
174 | { | |
175 | writeb(reg, db->io_addr); | |
176 | return readb(db->io_data); | |
177 | } | |
178 | ||
179 | /* | |
180 | * Write a byte to I/O port | |
181 | */ | |
182 | ||
183 | static void | |
184 | iow(board_info_t * db, int reg, int value) | |
185 | { | |
186 | writeb(reg, db->io_addr); | |
187 | writeb(value, db->io_data); | |
188 | } | |
189 | ||
190 | /* routines for sending block to chip */ | |
191 | ||
192 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
193 | { | |
194 | writesb(reg, data, count); | |
195 | } | |
196 | ||
197 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
198 | { | |
199 | writesw(reg, data, (count+1) >> 1); | |
200 | } | |
201 | ||
202 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
203 | { | |
204 | writesl(reg, data, (count+3) >> 2); | |
205 | } | |
206 | ||
207 | /* input block from chip to memory */ | |
208 | ||
209 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
210 | { | |
5f6b5517 | 211 | readsb(reg, data, count); |
a1365275 SH |
212 | } |
213 | ||
214 | ||
215 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
216 | { | |
217 | readsw(reg, data, (count+1) >> 1); | |
218 | } | |
219 | ||
220 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
221 | { | |
222 | readsl(reg, data, (count+3) >> 2); | |
223 | } | |
224 | ||
225 | /* dump block from chip to null */ | |
226 | ||
227 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
228 | { | |
229 | int i; | |
230 | int tmp; | |
231 | ||
232 | for (i = 0; i < count; i++) | |
233 | tmp = readb(reg); | |
234 | } | |
235 | ||
236 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
237 | { | |
238 | int i; | |
239 | int tmp; | |
240 | ||
241 | count = (count + 1) >> 1; | |
242 | ||
243 | for (i = 0; i < count; i++) | |
244 | tmp = readw(reg); | |
245 | } | |
246 | ||
247 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
248 | { | |
249 | int i; | |
250 | int tmp; | |
251 | ||
252 | count = (count + 3) >> 2; | |
253 | ||
254 | for (i = 0; i < count; i++) | |
255 | tmp = readl(reg); | |
256 | } | |
257 | ||
258 | /* dm9000_set_io | |
259 | * | |
260 | * select the specified set of io routines to use with the | |
261 | * device | |
262 | */ | |
263 | ||
264 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
265 | { | |
266 | /* use the size of the data resource to work out what IO | |
267 | * routines we want to use | |
268 | */ | |
269 | ||
270 | switch (byte_width) { | |
271 | case 1: | |
272 | db->dumpblk = dm9000_dumpblk_8bit; | |
273 | db->outblk = dm9000_outblk_8bit; | |
274 | db->inblk = dm9000_inblk_8bit; | |
275 | break; | |
276 | ||
a1365275 SH |
277 | |
278 | case 3: | |
a76836f9 BD |
279 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
280 | case 2: | |
a1365275 SH |
281 | db->dumpblk = dm9000_dumpblk_16bit; |
282 | db->outblk = dm9000_outblk_16bit; | |
283 | db->inblk = dm9000_inblk_16bit; | |
284 | break; | |
285 | ||
286 | case 4: | |
287 | default: | |
288 | db->dumpblk = dm9000_dumpblk_32bit; | |
289 | db->outblk = dm9000_outblk_32bit; | |
290 | db->inblk = dm9000_inblk_32bit; | |
291 | break; | |
292 | } | |
293 | } | |
294 | ||
8f5bf5f2 BD |
295 | static void dm9000_schedule_poll(board_info_t *db) |
296 | { | |
6d406b3c BD |
297 | if (db->type == TYPE_DM9000E) |
298 | schedule_delayed_work(&db->phy_poll, HZ * 2); | |
8f5bf5f2 | 299 | } |
a1365275 | 300 | |
f8d79e79 BD |
301 | static int dm9000_ioctl(struct net_device *dev, struct ifreq *req, int cmd) |
302 | { | |
303 | board_info_t *dm = to_dm9000_board(dev); | |
304 | ||
305 | if (!netif_running(dev)) | |
306 | return -EINVAL; | |
307 | ||
308 | return generic_mii_ioctl(&dm->mii, if_mii(req), cmd, NULL); | |
309 | } | |
310 | ||
311 | static unsigned int | |
312 | dm9000_read_locked(board_info_t *db, int reg) | |
a1365275 | 313 | { |
a1365275 | 314 | unsigned long flags; |
f8d79e79 | 315 | unsigned int ret; |
a1365275 | 316 | |
f8d79e79 BD |
317 | spin_lock_irqsave(&db->lock, flags); |
318 | ret = ior(db, reg); | |
319 | spin_unlock_irqrestore(&db->lock, flags); | |
a1365275 | 320 | |
f8d79e79 BD |
321 | return ret; |
322 | } | |
a1365275 | 323 | |
f8d79e79 BD |
324 | static int dm9000_wait_eeprom(board_info_t *db) |
325 | { | |
326 | unsigned int status; | |
327 | int timeout = 8; /* wait max 8msec */ | |
328 | ||
329 | /* The DM9000 data sheets say we should be able to | |
330 | * poll the ERRE bit in EPCR to wait for the EEPROM | |
331 | * operation. From testing several chips, this bit | |
332 | * does not seem to work. | |
333 | * | |
334 | * We attempt to use the bit, but fall back to the | |
335 | * timeout (which is why we do not return an error | |
336 | * on expiry) to say that the EEPROM operation has | |
337 | * completed. | |
338 | */ | |
339 | ||
340 | while (1) { | |
341 | status = dm9000_read_locked(db, DM9000_EPCR); | |
342 | ||
343 | if ((status & EPCR_ERRE) == 0) | |
344 | break; | |
345 | ||
2fcf06ca BD |
346 | msleep(1); |
347 | ||
f8d79e79 BD |
348 | if (timeout-- < 0) { |
349 | dev_dbg(db->dev, "timeout waiting EEPROM\n"); | |
350 | break; | |
351 | } | |
352 | } | |
353 | ||
354 | return 0; | |
a1365275 SH |
355 | } |
356 | ||
2fd0e33f | 357 | /* |
f8d79e79 | 358 | * Read a word data from EEPROM |
2fd0e33f | 359 | */ |
f8d79e79 BD |
360 | static void |
361 | dm9000_read_eeprom(board_info_t *db, int offset, u8 *to) | |
2fd0e33f | 362 | { |
f8d79e79 BD |
363 | unsigned long flags; |
364 | ||
365 | if (db->flags & DM9000_PLATF_NO_EEPROM) { | |
366 | to[0] = 0xff; | |
367 | to[1] = 0xff; | |
368 | return; | |
369 | } | |
370 | ||
371 | mutex_lock(&db->addr_lock); | |
372 | ||
373 | spin_lock_irqsave(&db->lock, flags); | |
374 | ||
375 | iow(db, DM9000_EPAR, offset); | |
376 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
377 | ||
378 | spin_unlock_irqrestore(&db->lock, flags); | |
379 | ||
380 | dm9000_wait_eeprom(db); | |
381 | ||
382 | /* delay for at-least 150uS */ | |
383 | msleep(1); | |
384 | ||
385 | spin_lock_irqsave(&db->lock, flags); | |
386 | ||
387 | iow(db, DM9000_EPCR, 0x0); | |
388 | ||
389 | to[0] = ior(db, DM9000_EPDRL); | |
390 | to[1] = ior(db, DM9000_EPDRH); | |
391 | ||
392 | spin_unlock_irqrestore(&db->lock, flags); | |
393 | ||
394 | mutex_unlock(&db->addr_lock); | |
2fd0e33f | 395 | } |
a1365275 | 396 | |
f8d79e79 BD |
397 | /* |
398 | * Write a word data to SROM | |
399 | */ | |
400 | static void | |
401 | dm9000_write_eeprom(board_info_t *db, int offset, u8 *data) | |
f42d8aea | 402 | { |
f8d79e79 | 403 | unsigned long flags; |
f42d8aea | 404 | |
f8d79e79 BD |
405 | if (db->flags & DM9000_PLATF_NO_EEPROM) |
406 | return; | |
f42d8aea | 407 | |
f8d79e79 BD |
408 | mutex_lock(&db->addr_lock); |
409 | ||
410 | spin_lock_irqsave(&db->lock, flags); | |
411 | iow(db, DM9000_EPAR, offset); | |
412 | iow(db, DM9000_EPDRH, data[1]); | |
413 | iow(db, DM9000_EPDRL, data[0]); | |
414 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
415 | spin_unlock_irqrestore(&db->lock, flags); | |
416 | ||
417 | dm9000_wait_eeprom(db); | |
418 | ||
419 | mdelay(1); /* wait at least 150uS to clear */ | |
420 | ||
421 | spin_lock_irqsave(&db->lock, flags); | |
422 | iow(db, DM9000_EPCR, 0); | |
423 | spin_unlock_irqrestore(&db->lock, flags); | |
424 | ||
425 | mutex_unlock(&db->addr_lock); | |
f42d8aea BD |
426 | } |
427 | ||
7da99859 BD |
428 | /* ethtool ops */ |
429 | ||
430 | static void dm9000_get_drvinfo(struct net_device *dev, | |
431 | struct ethtool_drvinfo *info) | |
432 | { | |
433 | board_info_t *dm = to_dm9000_board(dev); | |
434 | ||
435 | strcpy(info->driver, CARDNAME); | |
436 | strcpy(info->version, DRV_VERSION); | |
437 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
438 | } | |
439 | ||
e662ee02 BD |
440 | static u32 dm9000_get_msglevel(struct net_device *dev) |
441 | { | |
442 | board_info_t *dm = to_dm9000_board(dev); | |
443 | ||
444 | return dm->msg_enable; | |
445 | } | |
446 | ||
447 | static void dm9000_set_msglevel(struct net_device *dev, u32 value) | |
448 | { | |
449 | board_info_t *dm = to_dm9000_board(dev); | |
450 | ||
451 | dm->msg_enable = value; | |
452 | } | |
453 | ||
7da99859 BD |
454 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
455 | { | |
456 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 457 | |
7da99859 | 458 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
459 | return 0; |
460 | } | |
461 | ||
462 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
463 | { | |
464 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 465 | |
9a2f037c | 466 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
467 | } |
468 | ||
469 | static int dm9000_nway_reset(struct net_device *dev) | |
470 | { | |
471 | board_info_t *dm = to_dm9000_board(dev); | |
472 | return mii_nway_restart(&dm->mii); | |
473 | } | |
474 | ||
475 | static u32 dm9000_get_link(struct net_device *dev) | |
476 | { | |
477 | board_info_t *dm = to_dm9000_board(dev); | |
aa1eb452 BD |
478 | u32 ret; |
479 | ||
480 | if (dm->flags & DM9000_PLATF_EXT_PHY) | |
481 | ret = mii_link_ok(&dm->mii); | |
482 | else | |
483 | ret = dm9000_read_locked(dm, DM9000_NSR) & NSR_LINKST ? 1 : 0; | |
484 | ||
485 | return ret; | |
7da99859 BD |
486 | } |
487 | ||
29d52e54 BD |
488 | #define DM_EEPROM_MAGIC (0x444D394B) |
489 | ||
490 | static int dm9000_get_eeprom_len(struct net_device *dev) | |
491 | { | |
492 | return 128; | |
493 | } | |
494 | ||
495 | static int dm9000_get_eeprom(struct net_device *dev, | |
496 | struct ethtool_eeprom *ee, u8 *data) | |
497 | { | |
498 | board_info_t *dm = to_dm9000_board(dev); | |
499 | int offset = ee->offset; | |
500 | int len = ee->len; | |
501 | int i; | |
502 | ||
503 | /* EEPROM access is aligned to two bytes */ | |
504 | ||
505 | if ((len & 1) != 0 || (offset & 1) != 0) | |
506 | return -EINVAL; | |
507 | ||
bb44fb70 BD |
508 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
509 | return -ENOENT; | |
510 | ||
29d52e54 BD |
511 | ee->magic = DM_EEPROM_MAGIC; |
512 | ||
513 | for (i = 0; i < len; i += 2) | |
514 | dm9000_read_eeprom(dm, (offset + i) / 2, data + i); | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | static int dm9000_set_eeprom(struct net_device *dev, | |
520 | struct ethtool_eeprom *ee, u8 *data) | |
521 | { | |
522 | board_info_t *dm = to_dm9000_board(dev); | |
523 | int offset = ee->offset; | |
524 | int len = ee->len; | |
525 | int i; | |
526 | ||
527 | /* EEPROM access is aligned to two bytes */ | |
528 | ||
529 | if ((len & 1) != 0 || (offset & 1) != 0) | |
530 | return -EINVAL; | |
531 | ||
bb44fb70 BD |
532 | if (dm->flags & DM9000_PLATF_NO_EEPROM) |
533 | return -ENOENT; | |
534 | ||
29d52e54 BD |
535 | if (ee->magic != DM_EEPROM_MAGIC) |
536 | return -EINVAL; | |
537 | ||
538 | for (i = 0; i < len; i += 2) | |
539 | dm9000_write_eeprom(dm, (offset + i) / 2, data + i); | |
540 | ||
541 | return 0; | |
542 | } | |
543 | ||
7da99859 BD |
544 | static const struct ethtool_ops dm9000_ethtool_ops = { |
545 | .get_drvinfo = dm9000_get_drvinfo, | |
546 | .get_settings = dm9000_get_settings, | |
547 | .set_settings = dm9000_set_settings, | |
e662ee02 BD |
548 | .get_msglevel = dm9000_get_msglevel, |
549 | .set_msglevel = dm9000_set_msglevel, | |
7da99859 BD |
550 | .nway_reset = dm9000_nway_reset, |
551 | .get_link = dm9000_get_link, | |
29d52e54 BD |
552 | .get_eeprom_len = dm9000_get_eeprom_len, |
553 | .get_eeprom = dm9000_get_eeprom, | |
554 | .set_eeprom = dm9000_set_eeprom, | |
7da99859 BD |
555 | }; |
556 | ||
f8dd0ecb BD |
557 | static void dm9000_show_carrier(board_info_t *db, |
558 | unsigned carrier, unsigned nsr) | |
559 | { | |
560 | struct net_device *ndev = db->ndev; | |
561 | unsigned ncr = dm9000_read_locked(db, DM9000_NCR); | |
562 | ||
563 | if (carrier) | |
564 | dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n", | |
565 | ndev->name, (nsr & NSR_SPEED) ? 10 : 100, | |
566 | (ncr & NCR_FDX) ? "full" : "half"); | |
567 | else | |
568 | dev_info(db->dev, "%s: link down\n", ndev->name); | |
569 | } | |
570 | ||
8f5bf5f2 BD |
571 | static void |
572 | dm9000_poll_work(struct work_struct *w) | |
573 | { | |
574 | struct delayed_work *dw = container_of(w, struct delayed_work, work); | |
575 | board_info_t *db = container_of(dw, board_info_t, phy_poll); | |
f8dd0ecb BD |
576 | struct net_device *ndev = db->ndev; |
577 | ||
578 | if (db->flags & DM9000_PLATF_SIMPLE_PHY && | |
579 | !(db->flags & DM9000_PLATF_EXT_PHY)) { | |
580 | unsigned nsr = dm9000_read_locked(db, DM9000_NSR); | |
581 | unsigned old_carrier = netif_carrier_ok(ndev) ? 1 : 0; | |
582 | unsigned new_carrier; | |
8f5bf5f2 | 583 | |
f8dd0ecb BD |
584 | new_carrier = (nsr & NSR_LINKST) ? 1 : 0; |
585 | ||
586 | if (old_carrier != new_carrier) { | |
587 | if (netif_msg_link(db)) | |
588 | dm9000_show_carrier(db, new_carrier, nsr); | |
589 | ||
590 | if (!new_carrier) | |
591 | netif_carrier_off(ndev); | |
592 | else | |
593 | netif_carrier_on(ndev); | |
594 | } | |
595 | } else | |
596 | mii_check_media(&db->mii, netif_msg_link(db), 0); | |
8f5bf5f2 | 597 | |
f8dd0ecb | 598 | if (netif_running(ndev)) |
8f5bf5f2 BD |
599 | dm9000_schedule_poll(db); |
600 | } | |
7da99859 | 601 | |
a1365275 SH |
602 | /* dm9000_release_board |
603 | * | |
604 | * release a board, and any mapped resources | |
605 | */ | |
606 | ||
607 | static void | |
608 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
609 | { | |
a1365275 SH |
610 | /* unmap our resources */ |
611 | ||
612 | iounmap(db->io_addr); | |
613 | iounmap(db->io_data); | |
614 | ||
615 | /* release the resources */ | |
616 | ||
9088fa4f BD |
617 | release_resource(db->data_req); |
618 | kfree(db->data_req); | |
a1365275 | 619 | |
9088fa4f BD |
620 | release_resource(db->addr_req); |
621 | kfree(db->addr_req); | |
a1365275 SH |
622 | } |
623 | ||
6d406b3c BD |
624 | static unsigned char dm9000_type_to_char(enum dm9000_type type) |
625 | { | |
626 | switch (type) { | |
627 | case TYPE_DM9000E: return 'e'; | |
628 | case TYPE_DM9000A: return 'a'; | |
629 | case TYPE_DM9000B: return 'b'; | |
630 | } | |
631 | ||
632 | return '?'; | |
633 | } | |
634 | ||
a1365275 | 635 | /* |
f8d79e79 | 636 | * Set DM9000 multicast address |
a1365275 | 637 | */ |
f8d79e79 BD |
638 | static void |
639 | dm9000_hash_table(struct net_device *dev) | |
a1365275 | 640 | { |
f8d79e79 BD |
641 | board_info_t *db = (board_info_t *) dev->priv; |
642 | struct dev_mc_list *mcptr = dev->mc_list; | |
643 | int mc_cnt = dev->mc_count; | |
644 | int i, oft; | |
645 | u32 hash_val; | |
646 | u16 hash_table[4]; | |
647 | u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN; | |
648 | unsigned long flags; | |
a1365275 | 649 | |
f8d79e79 | 650 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 651 | |
f8d79e79 | 652 | spin_lock_irqsave(&db->lock, flags); |
a1365275 | 653 | |
f8d79e79 BD |
654 | for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) |
655 | iow(db, oft, dev->dev_addr[i]); | |
a1365275 | 656 | |
f8d79e79 BD |
657 | /* Clear Hash Table */ |
658 | for (i = 0; i < 4; i++) | |
659 | hash_table[i] = 0x0; | |
a76836f9 | 660 | |
f8d79e79 BD |
661 | /* broadcast address */ |
662 | hash_table[3] = 0x8000; | |
9ef9ac51 | 663 | |
f8d79e79 BD |
664 | if (dev->flags & IFF_PROMISC) |
665 | rcr |= RCR_PRMSC; | |
8f5bf5f2 | 666 | |
f8d79e79 BD |
667 | if (dev->flags & IFF_ALLMULTI) |
668 | rcr |= RCR_ALL; | |
08c3f57c | 669 | |
f8d79e79 BD |
670 | /* the multicast address in Hash Table : 64 bits */ |
671 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
672 | hash_val = ether_crc_le(6, mcptr->dmi_addr) & 0x3f; | |
673 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
08c3f57c LP |
674 | } |
675 | ||
f8d79e79 BD |
676 | /* Write the hash table to MAC MD table */ |
677 | for (i = 0, oft = DM9000_MAR; i < 4; i++) { | |
678 | iow(db, oft++, hash_table[i]); | |
679 | iow(db, oft++, hash_table[i] >> 8); | |
08c3f57c LP |
680 | } |
681 | ||
f8d79e79 BD |
682 | iow(db, DM9000_RCR, rcr); |
683 | spin_unlock_irqrestore(&db->lock, flags); | |
684 | } | |
08c3f57c | 685 | |
f8d79e79 BD |
686 | /* |
687 | * Initilize dm9000 board | |
688 | */ | |
689 | static void | |
690 | dm9000_init_dm9000(struct net_device *dev) | |
691 | { | |
692 | board_info_t *db = dev->priv; | |
693 | unsigned int imr; | |
08c3f57c | 694 | |
f8d79e79 | 695 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
08c3f57c | 696 | |
f8d79e79 BD |
697 | /* I/O mode */ |
698 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
08c3f57c | 699 | |
f8d79e79 BD |
700 | /* GPIO0 on pre-activate PHY */ |
701 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
702 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
703 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
08c3f57c | 704 | |
f8d79e79 BD |
705 | if (db->flags & DM9000_PLATF_EXT_PHY) |
706 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
33ba5091 | 707 | |
a1365275 SH |
708 | /* Program operating register */ |
709 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
710 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
711 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
712 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
713 | /* clear TX status */ | |
714 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
715 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
716 | ||
717 | /* Set address filter table */ | |
718 | dm9000_hash_table(dev); | |
719 | ||
6d406b3c BD |
720 | imr = IMR_PAR | IMR_PTM | IMR_PRM; |
721 | if (db->type != TYPE_DM9000E) | |
722 | imr |= IMR_LNKCHNG; | |
723 | ||
724 | db->imr_all = imr; | |
725 | ||
a1365275 | 726 | /* Enable TX/RX interrupt mask */ |
6d406b3c | 727 | iow(db, DM9000_IMR, imr); |
a1365275 SH |
728 | |
729 | /* Init Driver variable */ | |
730 | db->tx_pkt_cnt = 0; | |
731 | db->queue_pkt_len = 0; | |
732 | dev->trans_start = 0; | |
a1365275 SH |
733 | } |
734 | ||
f8d79e79 BD |
735 | /* Our watchdog timed out. Called by the networking layer */ |
736 | static void dm9000_timeout(struct net_device *dev) | |
737 | { | |
738 | board_info_t *db = (board_info_t *) dev->priv; | |
739 | u8 reg_save; | |
740 | unsigned long flags; | |
741 | ||
742 | /* Save previous register address */ | |
743 | reg_save = readb(db->io_addr); | |
744 | spin_lock_irqsave(&db->lock, flags); | |
745 | ||
746 | netif_stop_queue(dev); | |
747 | dm9000_reset(db); | |
748 | dm9000_init_dm9000(dev); | |
749 | /* We can accept TX packets again */ | |
750 | dev->trans_start = jiffies; | |
751 | netif_wake_queue(dev); | |
752 | ||
753 | /* Restore previous register address */ | |
754 | writeb(reg_save, db->io_addr); | |
755 | spin_unlock_irqrestore(&db->lock, flags); | |
756 | } | |
757 | ||
a1365275 SH |
758 | /* |
759 | * Hardware start transmission. | |
760 | * Send a packet to media from the upper layer. | |
761 | */ | |
762 | static int | |
763 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
764 | { | |
c46ac946 | 765 | unsigned long flags; |
59eae1fa | 766 | board_info_t *db = dev->priv; |
a1365275 | 767 | |
5b2b4ff0 | 768 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
769 | |
770 | if (db->tx_pkt_cnt > 1) | |
771 | return 1; | |
772 | ||
c46ac946 | 773 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
774 | |
775 | /* Move data to DM9000 TX RAM */ | |
776 | writeb(DM9000_MWCMD, db->io_addr); | |
777 | ||
778 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 779 | dev->stats.tx_bytes += skb->len; |
a1365275 | 780 | |
c46ac946 | 781 | db->tx_pkt_cnt++; |
a1365275 | 782 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 783 | if (db->tx_pkt_cnt == 1) { |
a1365275 | 784 | /* Set TX length to DM9000 */ |
073d3f46 BD |
785 | iow(db, DM9000_TXPLL, skb->len); |
786 | iow(db, DM9000_TXPLH, skb->len >> 8); | |
a1365275 SH |
787 | |
788 | /* Issue TX polling command */ | |
789 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
790 | ||
791 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
792 | } else { |
793 | /* Second packet */ | |
a1365275 | 794 | db->queue_pkt_len = skb->len; |
c46ac946 | 795 | netif_stop_queue(dev); |
a1365275 SH |
796 | } |
797 | ||
c46ac946 FW |
798 | spin_unlock_irqrestore(&db->lock, flags); |
799 | ||
a1365275 SH |
800 | /* free this SKB */ |
801 | dev_kfree_skb(skb); | |
802 | ||
a1365275 SH |
803 | return 0; |
804 | } | |
805 | ||
a1365275 | 806 | /* |
f8d79e79 BD |
807 | * DM9000 interrupt handler |
808 | * receive the packet to upper layer, free the transmitted packet | |
a1365275 | 809 | */ |
f8d79e79 BD |
810 | |
811 | static void dm9000_tx_done(struct net_device *dev, board_info_t *db) | |
a1365275 | 812 | { |
f8d79e79 | 813 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ |
a1365275 | 814 | |
f8d79e79 BD |
815 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { |
816 | /* One packet sent complete */ | |
817 | db->tx_pkt_cnt--; | |
818 | dev->stats.tx_packets++; | |
a1365275 | 819 | |
f8d79e79 BD |
820 | if (netif_msg_tx_done(db)) |
821 | dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); | |
c991d168 | 822 | |
a1365275 SH |
823 | /* Queue packet check & send */ |
824 | if (db->tx_pkt_cnt > 0) { | |
073d3f46 BD |
825 | iow(db, DM9000_TXPLL, db->queue_pkt_len); |
826 | iow(db, DM9000_TXPLH, db->queue_pkt_len >> 8); | |
a1365275 SH |
827 | iow(db, DM9000_TCR, TCR_TXREQ); |
828 | dev->trans_start = jiffies; | |
829 | } | |
830 | netif_wake_queue(dev); | |
831 | } | |
832 | } | |
833 | ||
a1365275 | 834 | struct dm9000_rxhdr { |
93116573 BD |
835 | u8 RxPktReady; |
836 | u8 RxStatus; | |
8b9fc8ae | 837 | __le16 RxLen; |
a1365275 SH |
838 | } __attribute__((__packed__)); |
839 | ||
840 | /* | |
841 | * Received a packet and pass to upper layer | |
842 | */ | |
843 | static void | |
844 | dm9000_rx(struct net_device *dev) | |
845 | { | |
846 | board_info_t *db = (board_info_t *) dev->priv; | |
847 | struct dm9000_rxhdr rxhdr; | |
848 | struct sk_buff *skb; | |
849 | u8 rxbyte, *rdptr; | |
6478fac6 | 850 | bool GoodPacket; |
a1365275 SH |
851 | int RxLen; |
852 | ||
853 | /* Check packet ready or not */ | |
854 | do { | |
855 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
856 | ||
857 | /* Get most updated data */ | |
858 | rxbyte = readb(db->io_data); | |
859 | ||
860 | /* Status check: this byte must be 0 or 1 */ | |
861 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 862 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
863 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
864 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
865 | return; | |
866 | } | |
867 | ||
868 | if (rxbyte != DM9000_PKT_RDY) | |
869 | return; | |
870 | ||
871 | /* A packet ready now & Get status/length */ | |
6478fac6 | 872 | GoodPacket = true; |
a1365275 SH |
873 | writeb(DM9000_MRCMD, db->io_addr); |
874 | ||
875 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
876 | ||
93116573 | 877 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 | 878 | |
c991d168 BD |
879 | if (netif_msg_rx_status(db)) |
880 | dev_dbg(db->dev, "RX: status %02x, length %04x\n", | |
881 | rxhdr.RxStatus, RxLen); | |
882 | ||
a1365275 SH |
883 | /* Packet Status check */ |
884 | if (RxLen < 0x40) { | |
6478fac6 | 885 | GoodPacket = false; |
c991d168 BD |
886 | if (netif_msg_rx_err(db)) |
887 | dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); | |
a1365275 SH |
888 | } |
889 | ||
890 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 891 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
892 | } |
893 | ||
93116573 | 894 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 895 | GoodPacket = false; |
93116573 | 896 | if (rxhdr.RxStatus & 0x01) { |
c991d168 BD |
897 | if (netif_msg_rx_err(db)) |
898 | dev_dbg(db->dev, "fifo error\n"); | |
09f75cd7 | 899 | dev->stats.rx_fifo_errors++; |
a1365275 | 900 | } |
93116573 | 901 | if (rxhdr.RxStatus & 0x02) { |
c991d168 BD |
902 | if (netif_msg_rx_err(db)) |
903 | dev_dbg(db->dev, "crc error\n"); | |
09f75cd7 | 904 | dev->stats.rx_crc_errors++; |
a1365275 | 905 | } |
93116573 | 906 | if (rxhdr.RxStatus & 0x80) { |
c991d168 BD |
907 | if (netif_msg_rx_err(db)) |
908 | dev_dbg(db->dev, "length error\n"); | |
09f75cd7 | 909 | dev->stats.rx_length_errors++; |
a1365275 SH |
910 | } |
911 | } | |
912 | ||
913 | /* Move data from DM9000 */ | |
914 | if (GoodPacket | |
915 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
916 | skb_reserve(skb, 2); |
917 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
918 | ||
919 | /* Read received packet from RX SRAM */ | |
920 | ||
921 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 922 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
923 | |
924 | /* Pass to upper layer */ | |
925 | skb->protocol = eth_type_trans(skb, dev); | |
926 | netif_rx(skb); | |
09f75cd7 | 927 | dev->stats.rx_packets++; |
a1365275 SH |
928 | |
929 | } else { | |
930 | /* need to dump the packet's data */ | |
931 | ||
932 | (db->dumpblk)(db->io_data, RxLen); | |
933 | } | |
934 | } while (rxbyte == DM9000_PKT_RDY); | |
935 | } | |
936 | ||
f8d79e79 | 937 | static irqreturn_t dm9000_interrupt(int irq, void *dev_id) |
39c341a8 | 938 | { |
f8d79e79 BD |
939 | struct net_device *dev = dev_id; |
940 | board_info_t *db = dev->priv; | |
941 | int int_status; | |
942 | u8 reg_save; | |
39c341a8 | 943 | |
f8d79e79 | 944 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
39c341a8 | 945 | |
f8d79e79 | 946 | /* A real interrupt coming */ |
39c341a8 | 947 | |
f8d79e79 | 948 | spin_lock(&db->lock); |
39c341a8 | 949 | |
f8d79e79 BD |
950 | /* Save previous register address */ |
951 | reg_save = readb(db->io_addr); | |
39c341a8 | 952 | |
f8d79e79 BD |
953 | /* Disable all interrupts */ |
954 | iow(db, DM9000_IMR, IMR_PAR); | |
39c341a8 | 955 | |
f8d79e79 BD |
956 | /* Got DM9000 interrupt status */ |
957 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
958 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
39c341a8 | 959 | |
f8d79e79 BD |
960 | if (netif_msg_intr(db)) |
961 | dev_dbg(db->dev, "interrupt status %02x\n", int_status); | |
962 | ||
963 | /* Received the coming packet */ | |
964 | if (int_status & ISR_PRS) | |
965 | dm9000_rx(dev); | |
966 | ||
967 | /* Trnasmit Interrupt check */ | |
968 | if (int_status & ISR_PTS) | |
969 | dm9000_tx_done(dev, db); | |
970 | ||
971 | if (db->type != TYPE_DM9000E) { | |
972 | if (int_status & ISR_LNKCHNG) { | |
973 | /* fire a link-change request */ | |
974 | schedule_delayed_work(&db->phy_poll, 1); | |
39c341a8 BD |
975 | } |
976 | } | |
977 | ||
f8d79e79 BD |
978 | /* Re-enable interrupt mask */ |
979 | iow(db, DM9000_IMR, db->imr_all); | |
980 | ||
981 | /* Restore previous register address */ | |
982 | writeb(reg_save, db->io_addr); | |
983 | ||
984 | spin_unlock(&db->lock); | |
985 | ||
986 | return IRQ_HANDLED; | |
39c341a8 BD |
987 | } |
988 | ||
f8d79e79 | 989 | #ifdef CONFIG_NET_POLL_CONTROLLER |
a1365275 | 990 | /* |
f8d79e79 | 991 | *Used by netconsole |
a1365275 | 992 | */ |
f8d79e79 | 993 | static void dm9000_poll_controller(struct net_device *dev) |
a1365275 | 994 | { |
f8d79e79 BD |
995 | disable_irq(dev->irq); |
996 | dm9000_interrupt(dev->irq, dev); | |
997 | enable_irq(dev->irq); | |
998 | } | |
999 | #endif | |
9a2f037c | 1000 | |
f8d79e79 BD |
1001 | /* |
1002 | * Open the interface. | |
1003 | * The interface is opened whenever "ifconfig" actives it. | |
1004 | */ | |
1005 | static int | |
1006 | dm9000_open(struct net_device *dev) | |
1007 | { | |
1008 | board_info_t *db = dev->priv; | |
1009 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; | |
621ddcb0 | 1010 | |
f8d79e79 BD |
1011 | if (netif_msg_ifup(db)) |
1012 | dev_dbg(db->dev, "enabling %s\n", dev->name); | |
621ddcb0 | 1013 | |
f8d79e79 BD |
1014 | /* If there is no IRQ type specified, default to something that |
1015 | * may work, and tell the user that this is a problem */ | |
621ddcb0 | 1016 | |
f8d79e79 BD |
1017 | if (irqflags == IRQF_TRIGGER_NONE) { |
1018 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
1019 | irqflags = DEFAULT_TRIGGER; | |
1020 | } | |
1021 | ||
1022 | irqflags |= IRQF_SHARED; | |
39c341a8 | 1023 | |
f8d79e79 BD |
1024 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) |
1025 | return -EAGAIN; | |
621ddcb0 | 1026 | |
f8d79e79 BD |
1027 | /* Initialize DM9000 board */ |
1028 | dm9000_reset(db); | |
1029 | dm9000_init_dm9000(dev); | |
621ddcb0 | 1030 | |
f8d79e79 BD |
1031 | /* Init driver variable */ |
1032 | db->dbug_cnt = 0; | |
86c62fab | 1033 | |
f8d79e79 BD |
1034 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
1035 | netif_start_queue(dev); | |
1036 | ||
1037 | dm9000_schedule_poll(db); | |
9a2f037c | 1038 | |
f8d79e79 BD |
1039 | return 0; |
1040 | } | |
621ddcb0 | 1041 | |
f8d79e79 BD |
1042 | /* |
1043 | * Sleep, either by using msleep() or if we are suspending, then | |
1044 | * use mdelay() to sleep. | |
1045 | */ | |
1046 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1047 | { | |
1048 | if (db->in_suspend) | |
1049 | mdelay(ms); | |
1050 | else | |
1051 | msleep(ms); | |
a1365275 SH |
1052 | } |
1053 | ||
a1365275 | 1054 | /* |
f8d79e79 | 1055 | * Read a word from phyxcer |
a1365275 | 1056 | */ |
f8d79e79 BD |
1057 | static int |
1058 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
a1365275 | 1059 | { |
f8d79e79 | 1060 | board_info_t *db = (board_info_t *) dev->priv; |
621ddcb0 | 1061 | unsigned long flags; |
f8d79e79 BD |
1062 | unsigned int reg_save; |
1063 | int ret; | |
bb44fb70 | 1064 | |
9a2f037c BD |
1065 | mutex_lock(&db->addr_lock); |
1066 | ||
f8d79e79 | 1067 | spin_lock_irqsave(&db->lock,flags); |
621ddcb0 | 1068 | |
f8d79e79 BD |
1069 | /* Save previous register address */ |
1070 | reg_save = readb(db->io_addr); | |
39c341a8 | 1071 | |
f8d79e79 BD |
1072 | /* Fill the phyxcer register into REG_0C */ |
1073 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
621ddcb0 | 1074 | |
f8d79e79 | 1075 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ |
9a2f037c | 1076 | |
f8d79e79 BD |
1077 | writeb(reg_save, db->io_addr); |
1078 | spin_unlock_irqrestore(&db->lock,flags); | |
89c8b0e6 | 1079 | |
321f69a4 | 1080 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1081 | |
1082 | spin_lock_irqsave(&db->lock,flags); | |
1083 | reg_save = readb(db->io_addr); | |
1084 | ||
a1365275 SH |
1085 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1086 | ||
1087 | /* The read data keeps on REG_0D & REG_0E */ | |
1088 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1089 | ||
9ef9ac51 BD |
1090 | /* restore the previous address */ |
1091 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1092 | spin_unlock_irqrestore(&db->lock,flags); |
1093 | ||
9a2f037c | 1094 | mutex_unlock(&db->addr_lock); |
37d5dca6 ES |
1095 | |
1096 | dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret); | |
a1365275 SH |
1097 | return ret; |
1098 | } | |
1099 | ||
1100 | /* | |
1101 | * Write a word to phyxcer | |
1102 | */ | |
1103 | static void | |
59eae1fa BD |
1104 | dm9000_phy_write(struct net_device *dev, |
1105 | int phyaddr_unused, int reg, int value) | |
a1365275 SH |
1106 | { |
1107 | board_info_t *db = (board_info_t *) dev->priv; | |
1108 | unsigned long flags; | |
9ef9ac51 | 1109 | unsigned long reg_save; |
a1365275 | 1110 | |
37d5dca6 | 1111 | dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value); |
9a2f037c BD |
1112 | mutex_lock(&db->addr_lock); |
1113 | ||
a1365275 SH |
1114 | spin_lock_irqsave(&db->lock,flags); |
1115 | ||
9ef9ac51 BD |
1116 | /* Save previous register address */ |
1117 | reg_save = readb(db->io_addr); | |
1118 | ||
a1365275 SH |
1119 | /* Fill the phyxcer register into REG_0C */ |
1120 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1121 | ||
1122 | /* Fill the written data into REG_0D & REG_0E */ | |
073d3f46 BD |
1123 | iow(db, DM9000_EPDRL, value); |
1124 | iow(db, DM9000_EPDRH, value >> 8); | |
a1365275 SH |
1125 | |
1126 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1127 | |
1128 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1129 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1130 | |
321f69a4 | 1131 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1132 | |
1133 | spin_lock_irqsave(&db->lock,flags); | |
1134 | reg_save = readb(db->io_addr); | |
1135 | ||
a1365275 SH |
1136 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1137 | ||
9ef9ac51 BD |
1138 | /* restore the previous address */ |
1139 | writeb(reg_save, db->io_addr); | |
1140 | ||
9a2f037c BD |
1141 | spin_unlock_irqrestore(&db->lock, flags); |
1142 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1143 | } |
1144 | ||
f8d79e79 BD |
1145 | static void |
1146 | dm9000_shutdown(struct net_device *dev) | |
1147 | { | |
1148 | board_info_t *db = dev->priv; | |
1149 | ||
1150 | /* RESET device */ | |
1151 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
1152 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
1153 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
1154 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * Stop the interface. | |
1159 | * The interface is stopped when it is brought. | |
1160 | */ | |
1161 | static int | |
1162 | dm9000_stop(struct net_device *ndev) | |
1163 | { | |
1164 | board_info_t *db = ndev->priv; | |
1165 | ||
1166 | if (netif_msg_ifdown(db)) | |
1167 | dev_dbg(db->dev, "shutting down %s\n", ndev->name); | |
1168 | ||
1169 | cancel_delayed_work_sync(&db->phy_poll); | |
1170 | ||
1171 | netif_stop_queue(ndev); | |
1172 | netif_carrier_off(ndev); | |
1173 | ||
1174 | /* free interrupt */ | |
1175 | free_irq(ndev->irq, ndev); | |
1176 | ||
1177 | dm9000_shutdown(ndev); | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
1183 | ||
1184 | /* | |
1185 | * Search DM9000 board, allocate space and register it | |
1186 | */ | |
1187 | static int __devinit | |
1188 | dm9000_probe(struct platform_device *pdev) | |
1189 | { | |
1190 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; | |
1191 | struct board_info *db; /* Point a board information structure */ | |
1192 | struct net_device *ndev; | |
1193 | const unsigned char *mac_src; | |
1194 | int ret = 0; | |
1195 | int iosize; | |
1196 | int i; | |
1197 | u32 id_val; | |
1198 | ||
1199 | /* Init network device */ | |
1200 | ndev = alloc_etherdev(sizeof(struct board_info)); | |
1201 | if (!ndev) { | |
1202 | dev_err(&pdev->dev, "could not allocate device.\n"); | |
1203 | return -ENOMEM; | |
1204 | } | |
1205 | ||
1206 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1207 | ||
1208 | dev_dbg(&pdev->dev, "dm9000_probe()\n"); | |
1209 | ||
1210 | /* setup board info structure */ | |
1211 | db = ndev->priv; | |
1212 | memset(db, 0, sizeof(*db)); | |
1213 | ||
1214 | db->dev = &pdev->dev; | |
1215 | db->ndev = ndev; | |
1216 | ||
1217 | spin_lock_init(&db->lock); | |
1218 | mutex_init(&db->addr_lock); | |
1219 | ||
1220 | INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); | |
1221 | ||
1222 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1223 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1224 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1225 | ||
1226 | if (db->addr_res == NULL || db->data_res == NULL || | |
1227 | db->irq_res == NULL) { | |
1228 | dev_err(db->dev, "insufficient resources\n"); | |
1229 | ret = -ENOENT; | |
1230 | goto out; | |
1231 | } | |
1232 | ||
1233 | iosize = res_size(db->addr_res); | |
1234 | db->addr_req = request_mem_region(db->addr_res->start, iosize, | |
1235 | pdev->name); | |
1236 | ||
1237 | if (db->addr_req == NULL) { | |
1238 | dev_err(db->dev, "cannot claim address reg area\n"); | |
1239 | ret = -EIO; | |
1240 | goto out; | |
1241 | } | |
1242 | ||
1243 | db->io_addr = ioremap(db->addr_res->start, iosize); | |
1244 | ||
1245 | if (db->io_addr == NULL) { | |
1246 | dev_err(db->dev, "failed to ioremap address reg\n"); | |
1247 | ret = -EINVAL; | |
1248 | goto out; | |
1249 | } | |
1250 | ||
1251 | iosize = res_size(db->data_res); | |
1252 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
1253 | pdev->name); | |
1254 | ||
1255 | if (db->data_req == NULL) { | |
1256 | dev_err(db->dev, "cannot claim data reg area\n"); | |
1257 | ret = -EIO; | |
1258 | goto out; | |
1259 | } | |
1260 | ||
1261 | db->io_data = ioremap(db->data_res->start, iosize); | |
1262 | ||
1263 | if (db->io_data == NULL) { | |
1264 | dev_err(db->dev, "failed to ioremap data reg\n"); | |
1265 | ret = -EINVAL; | |
1266 | goto out; | |
1267 | } | |
1268 | ||
1269 | /* fill in parameters for net-dev structure */ | |
1270 | ndev->base_addr = (unsigned long)db->io_addr; | |
1271 | ndev->irq = db->irq_res->start; | |
1272 | ||
1273 | /* ensure at least we have a default set of IO routines */ | |
1274 | dm9000_set_io(db, iosize); | |
1275 | ||
1276 | /* check to see if anything is being over-ridden */ | |
1277 | if (pdata != NULL) { | |
1278 | /* check to see if the driver wants to over-ride the | |
1279 | * default IO width */ | |
1280 | ||
1281 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
1282 | dm9000_set_io(db, 1); | |
1283 | ||
1284 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
1285 | dm9000_set_io(db, 2); | |
1286 | ||
1287 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
1288 | dm9000_set_io(db, 4); | |
1289 | ||
1290 | /* check to see if there are any IO routine | |
1291 | * over-rides */ | |
1292 | ||
1293 | if (pdata->inblk != NULL) | |
1294 | db->inblk = pdata->inblk; | |
1295 | ||
1296 | if (pdata->outblk != NULL) | |
1297 | db->outblk = pdata->outblk; | |
1298 | ||
1299 | if (pdata->dumpblk != NULL) | |
1300 | db->dumpblk = pdata->dumpblk; | |
1301 | ||
1302 | db->flags = pdata->flags; | |
1303 | } | |
1304 | ||
f8dd0ecb BD |
1305 | #ifdef CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL |
1306 | db->flags |= DM9000_PLATF_SIMPLE_PHY; | |
1307 | #endif | |
1308 | ||
f8d79e79 BD |
1309 | dm9000_reset(db); |
1310 | ||
1311 | /* try multiple times, DM9000 sometimes gets the read wrong */ | |
1312 | for (i = 0; i < 8; i++) { | |
1313 | id_val = ior(db, DM9000_VIDL); | |
1314 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
1315 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
1316 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
1317 | ||
1318 | if (id_val == DM9000_ID) | |
1319 | break; | |
1320 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); | |
1321 | } | |
1322 | ||
1323 | if (id_val != DM9000_ID) { | |
1324 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); | |
1325 | ret = -ENODEV; | |
1326 | goto out; | |
1327 | } | |
1328 | ||
1329 | /* Identify what type of DM9000 we are working on */ | |
1330 | ||
1331 | id_val = ior(db, DM9000_CHIPR); | |
1332 | dev_dbg(db->dev, "dm9000 revision 0x%02x\n", id_val); | |
1333 | ||
1334 | switch (id_val) { | |
1335 | case CHIPR_DM9000A: | |
1336 | db->type = TYPE_DM9000A; | |
1337 | break; | |
1338 | case CHIPR_DM9000B: | |
1339 | db->type = TYPE_DM9000B; | |
1340 | break; | |
1341 | default: | |
1342 | dev_dbg(db->dev, "ID %02x => defaulting to DM9000E\n", id_val); | |
1343 | db->type = TYPE_DM9000E; | |
1344 | } | |
1345 | ||
1346 | /* from this point we assume that we have found a DM9000 */ | |
1347 | ||
1348 | /* driver system function */ | |
1349 | ether_setup(ndev); | |
1350 | ||
1351 | ndev->open = &dm9000_open; | |
1352 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
1353 | ndev->tx_timeout = &dm9000_timeout; | |
1354 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
1355 | ndev->stop = &dm9000_stop; | |
1356 | ndev->set_multicast_list = &dm9000_hash_table; | |
1357 | ndev->ethtool_ops = &dm9000_ethtool_ops; | |
1358 | ndev->do_ioctl = &dm9000_ioctl; | |
1359 | ||
1360 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1361 | ndev->poll_controller = &dm9000_poll_controller; | |
1362 | #endif | |
1363 | ||
1364 | db->msg_enable = NETIF_MSG_LINK; | |
1365 | db->mii.phy_id_mask = 0x1f; | |
1366 | db->mii.reg_num_mask = 0x1f; | |
1367 | db->mii.force_media = 0; | |
1368 | db->mii.full_duplex = 0; | |
1369 | db->mii.dev = ndev; | |
1370 | db->mii.mdio_read = dm9000_phy_read; | |
1371 | db->mii.mdio_write = dm9000_phy_write; | |
1372 | ||
1373 | mac_src = "eeprom"; | |
1374 | ||
1375 | /* try reading the node address from the attached EEPROM */ | |
1376 | for (i = 0; i < 6; i += 2) | |
1377 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
1378 | ||
1379 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
1380 | /* try reading from mac */ | |
1381 | ||
1382 | mac_src = "chip"; | |
1383 | for (i = 0; i < 6; i++) | |
1384 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
1385 | } | |
1386 | ||
1387 | if (!is_valid_ether_addr(ndev->dev_addr)) | |
1388 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " | |
1389 | "set using ifconfig\n", ndev->name); | |
1390 | ||
1391 | platform_set_drvdata(pdev, ndev); | |
1392 | ret = register_netdev(ndev); | |
1393 | ||
1394 | if (ret == 0) { | |
1395 | DECLARE_MAC_BUF(mac); | |
1396 | printk(KERN_INFO "%s: dm9000%c at %p,%p IRQ %d MAC: %s (%s)\n", | |
1397 | ndev->name, dm9000_type_to_char(db->type), | |
1398 | db->io_addr, db->io_data, ndev->irq, | |
1399 | print_mac(mac, ndev->dev_addr), mac_src); | |
1400 | } | |
1401 | return 0; | |
1402 | ||
1403 | out: | |
1404 | dev_err(db->dev, "not found (%d).\n", ret); | |
1405 | ||
1406 | dm9000_release_board(pdev, db); | |
1407 | free_netdev(ndev); | |
1408 | ||
1409 | return ret; | |
1410 | } | |
1411 | ||
a1365275 | 1412 | static int |
3ae5eaec | 1413 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1414 | { |
3ae5eaec | 1415 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1416 | board_info_t *db; |
a1365275 | 1417 | |
9480e307 | 1418 | if (ndev) { |
321f69a4 BD |
1419 | db = (board_info_t *) ndev->priv; |
1420 | db->in_suspend = 1; | |
1421 | ||
a1365275 SH |
1422 | if (netif_running(ndev)) { |
1423 | netif_device_detach(ndev); | |
1424 | dm9000_shutdown(ndev); | |
1425 | } | |
1426 | } | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static int | |
3ae5eaec | 1431 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1432 | { |
3ae5eaec | 1433 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1434 | board_info_t *db = (board_info_t *) ndev->priv; |
1435 | ||
9480e307 | 1436 | if (ndev) { |
a1365275 SH |
1437 | |
1438 | if (netif_running(ndev)) { | |
1439 | dm9000_reset(db); | |
1440 | dm9000_init_dm9000(ndev); | |
1441 | ||
1442 | netif_device_attach(ndev); | |
1443 | } | |
321f69a4 BD |
1444 | |
1445 | db->in_suspend = 0; | |
a1365275 SH |
1446 | } |
1447 | return 0; | |
1448 | } | |
1449 | ||
e21fd4f0 | 1450 | static int __devexit |
3ae5eaec | 1451 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1452 | { |
3ae5eaec | 1453 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1454 | |
3ae5eaec | 1455 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1456 | |
1457 | unregister_netdev(ndev); | |
1458 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1459 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1460 | |
a76836f9 | 1461 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1462 | return 0; |
1463 | } | |
1464 | ||
3ae5eaec | 1465 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1466 | .driver = { |
1467 | .name = "dm9000", | |
1468 | .owner = THIS_MODULE, | |
1469 | }, | |
a1365275 | 1470 | .probe = dm9000_probe, |
e21fd4f0 | 1471 | .remove = __devexit_p(dm9000_drv_remove), |
a1365275 SH |
1472 | .suspend = dm9000_drv_suspend, |
1473 | .resume = dm9000_drv_resume, | |
1474 | }; | |
1475 | ||
1476 | static int __init | |
1477 | dm9000_init(void) | |
1478 | { | |
7da99859 | 1479 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1480 | |
59eae1fa | 1481 | return platform_driver_register(&dm9000_driver); |
a1365275 SH |
1482 | } |
1483 | ||
1484 | static void __exit | |
1485 | dm9000_cleanup(void) | |
1486 | { | |
3ae5eaec | 1487 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1488 | } |
1489 | ||
1490 | module_init(dm9000_init); | |
1491 | module_exit(dm9000_cleanup); | |
1492 | ||
1493 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1494 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1495 | MODULE_LICENSE("GPL"); | |
72abb461 | 1496 | MODULE_ALIAS("platform:dm9000"); |