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1da177e4 LT |
1 | /* |
2 | * File Name: | |
3 | * defxx.c | |
4 | * | |
5 | * Copyright Information: | |
6 | * Copyright Digital Equipment Corporation 1996. | |
7 | * | |
8 | * This software may be used and distributed according to the terms of | |
9 | * the GNU General Public License, incorporated herein by reference. | |
10 | * | |
11 | * Abstract: | |
12 | * A Linux device driver supporting the Digital Equipment Corporation | |
13 | * FDDI EISA and PCI controller families. Supported adapters include: | |
14 | * | |
15 | * DEC FDDIcontroller/EISA (DEFEA) | |
16 | * DEC FDDIcontroller/PCI (DEFPA) | |
17 | * | |
18 | * The original author: | |
19 | * LVS Lawrence V. Stefani <lstefani@yahoo.com> | |
20 | * | |
21 | * Maintainers: | |
22 | * macro Maciej W. Rozycki <macro@linux-mips.org> | |
23 | * | |
24 | * Credits: | |
25 | * I'd like to thank Patricia Cross for helping me get started with | |
26 | * Linux, David Davies for a lot of help upgrading and configuring | |
27 | * my development system and for answering many OS and driver | |
28 | * development questions, and Alan Cox for recommendations and | |
29 | * integration help on getting FDDI support into Linux. LVS | |
30 | * | |
31 | * Driver Architecture: | |
32 | * The driver architecture is largely based on previous driver work | |
33 | * for other operating systems. The upper edge interface and | |
34 | * functions were largely taken from existing Linux device drivers | |
35 | * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C | |
36 | * driver. | |
37 | * | |
38 | * Adapter Probe - | |
39 | * The driver scans for supported EISA adapters by reading the | |
40 | * SLOT ID register for each EISA slot and making a match | |
41 | * against the expected value. | |
42 | * | |
43 | * Bus-Specific Initialization - | |
44 | * This driver currently supports both EISA and PCI controller | |
45 | * families. While the custom DMA chip and FDDI logic is similar | |
46 | * or identical, the bus logic is very different. After | |
47 | * initialization, the only bus-specific differences is in how the | |
48 | * driver enables and disables interrupts. Other than that, the | |
49 | * run-time critical code behaves the same on both families. | |
50 | * It's important to note that both adapter families are configured | |
51 | * to I/O map, rather than memory map, the adapter registers. | |
52 | * | |
53 | * Driver Open/Close - | |
54 | * In the driver open routine, the driver ISR (interrupt service | |
55 | * routine) is registered and the adapter is brought to an | |
56 | * operational state. In the driver close routine, the opposite | |
57 | * occurs; the driver ISR is deregistered and the adapter is | |
58 | * brought to a safe, but closed state. Users may use consecutive | |
59 | * commands to bring the adapter up and down as in the following | |
60 | * example: | |
61 | * ifconfig fddi0 up | |
62 | * ifconfig fddi0 down | |
63 | * ifconfig fddi0 up | |
64 | * | |
65 | * Driver Shutdown - | |
66 | * Apparently, there is no shutdown or halt routine support under | |
67 | * Linux. This routine would be called during "reboot" or | |
68 | * "shutdown" to allow the driver to place the adapter in a safe | |
69 | * state before a warm reboot occurs. To be really safe, the user | |
70 | * should close the adapter before shutdown (eg. ifconfig fddi0 down) | |
71 | * to ensure that the adapter DMA engine is taken off-line. However, | |
72 | * the current driver code anticipates this problem and always issues | |
73 | * a soft reset of the adapter at the beginning of driver initialization. | |
74 | * A future driver enhancement in this area may occur in 2.1.X where | |
75 | * Alan indicated that a shutdown handler may be implemented. | |
76 | * | |
77 | * Interrupt Service Routine - | |
78 | * The driver supports shared interrupts, so the ISR is registered for | |
79 | * each board with the appropriate flag and the pointer to that board's | |
80 | * device structure. This provides the context during interrupt | |
81 | * processing to support shared interrupts and multiple boards. | |
82 | * | |
83 | * Interrupt enabling/disabling can occur at many levels. At the host | |
84 | * end, you can disable system interrupts, or disable interrupts at the | |
85 | * PIC (on Intel systems). Across the bus, both EISA and PCI adapters | |
86 | * have a bus-logic chip interrupt enable/disable as well as a DMA | |
87 | * controller interrupt enable/disable. | |
88 | * | |
89 | * The driver currently enables and disables adapter interrupts at the | |
90 | * bus-logic chip and assumes that Linux will take care of clearing or | |
91 | * acknowledging any host-based interrupt chips. | |
92 | * | |
93 | * Control Functions - | |
94 | * Control functions are those used to support functions such as adding | |
95 | * or deleting multicast addresses, enabling or disabling packet | |
96 | * reception filters, or other custom/proprietary commands. Presently, | |
97 | * the driver supports the "get statistics", "set multicast list", and | |
98 | * "set mac address" functions defined by Linux. A list of possible | |
99 | * enhancements include: | |
100 | * | |
101 | * - Custom ioctl interface for executing port interface commands | |
102 | * - Custom ioctl interface for adding unicast addresses to | |
103 | * adapter CAM (to support bridge functions). | |
104 | * - Custom ioctl interface for supporting firmware upgrades. | |
105 | * | |
106 | * Hardware (port interface) Support Routines - | |
107 | * The driver function names that start with "dfx_hw_" represent | |
108 | * low-level port interface routines that are called frequently. They | |
109 | * include issuing a DMA or port control command to the adapter, | |
110 | * resetting the adapter, or reading the adapter state. Since the | |
111 | * driver initialization and run-time code must make calls into the | |
112 | * port interface, these routines were written to be as generic and | |
113 | * usable as possible. | |
114 | * | |
115 | * Receive Path - | |
116 | * The adapter DMA engine supports a 256 entry receive descriptor block | |
117 | * of which up to 255 entries can be used at any given time. The | |
118 | * architecture is a standard producer, consumer, completion model in | |
119 | * which the driver "produces" receive buffers to the adapter, the | |
120 | * adapter "consumes" the receive buffers by DMAing incoming packet data, | |
121 | * and the driver "completes" the receive buffers by servicing the | |
122 | * incoming packet, then "produces" a new buffer and starts the cycle | |
123 | * again. Receive buffers can be fragmented in up to 16 fragments | |
124 | * (descriptor entries). For simplicity, this driver posts | |
125 | * single-fragment receive buffers of 4608 bytes, then allocates a | |
126 | * sk_buff, copies the data, then reposts the buffer. To reduce CPU | |
127 | * utilization, a better approach would be to pass up the receive | |
128 | * buffer (no extra copy) then allocate and post a replacement buffer. | |
129 | * This is a performance enhancement that should be looked into at | |
130 | * some point. | |
131 | * | |
132 | * Transmit Path - | |
133 | * Like the receive path, the adapter DMA engine supports a 256 entry | |
134 | * transmit descriptor block of which up to 255 entries can be used at | |
135 | * any given time. Transmit buffers can be fragmented in up to 255 | |
136 | * fragments (descriptor entries). This driver always posts one | |
137 | * fragment per transmit packet request. | |
138 | * | |
139 | * The fragment contains the entire packet from FC to end of data. | |
140 | * Before posting the buffer to the adapter, the driver sets a three-byte | |
141 | * packet request header (PRH) which is required by the Motorola MAC chip | |
142 | * used on the adapters. The PRH tells the MAC the type of token to | |
143 | * receive/send, whether or not to generate and append the CRC, whether | |
144 | * synchronous or asynchronous framing is used, etc. Since the PRH | |
145 | * definition is not necessarily consistent across all FDDI chipsets, | |
146 | * the driver, rather than the common FDDI packet handler routines, | |
147 | * sets these bytes. | |
148 | * | |
149 | * To reduce the amount of descriptor fetches needed per transmit request, | |
150 | * the driver takes advantage of the fact that there are at least three | |
151 | * bytes available before the skb->data field on the outgoing transmit | |
152 | * request. This is guaranteed by having fddi_setup() in net_init.c set | |
153 | * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest | |
154 | * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" | |
155 | * bytes which we'll use to store the PRH. | |
156 | * | |
157 | * There's a subtle advantage to adding these pad bytes to the | |
158 | * hard_header_len, it ensures that the data portion of the packet for | |
159 | * an 802.2 SNAP frame is longword aligned. Other FDDI driver | |
160 | * implementations may not need the extra padding and can start copying | |
161 | * or DMAing directly from the FC byte which starts at skb->data. Should | |
162 | * another driver implementation need ADDITIONAL padding, the net_init.c | |
163 | * module should be updated and dev->hard_header_len should be increased. | |
164 | * NOTE: To maintain the alignment on the data portion of the packet, | |
165 | * dev->hard_header_len should always be evenly divisible by 4 and at | |
166 | * least 24 bytes in size. | |
167 | * | |
168 | * Modification History: | |
169 | * Date Name Description | |
170 | * 16-Aug-96 LVS Created. | |
171 | * 20-Aug-96 LVS Updated dfx_probe so that version information | |
172 | * string is only displayed if 1 or more cards are | |
173 | * found. Changed dfx_rcv_queue_process to copy | |
174 | * 3 NULL bytes before FC to ensure that data is | |
175 | * longword aligned in receive buffer. | |
176 | * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable | |
177 | * LLC group promiscuous mode if multicast list | |
178 | * is too large. LLC individual/group promiscuous | |
179 | * mode is now disabled if IFF_PROMISC flag not set. | |
180 | * dfx_xmt_queue_pkt no longer checks for NULL skb | |
181 | * on Alan Cox recommendation. Added node address | |
182 | * override support. | |
183 | * 12-Sep-96 LVS Reset current address to factory address during | |
184 | * device open. Updated transmit path to post a | |
185 | * single fragment which includes PRH->end of data. | |
186 | * Mar 2000 AC Did various cleanups for 2.3.x | |
187 | * Jun 2000 jgarzik PCI and resource alloc cleanups | |
188 | * Jul 2000 tjeerd Much cleanup and some bug fixes | |
189 | * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup | |
190 | * Feb 2001 Skb allocation fixes | |
191 | * Feb 2001 davej PCI enable cleanups. | |
192 | * 04 Aug 2003 macro Converted to the DMA API. | |
193 | * 14 Aug 2004 macro Fix device names reported. | |
feea1db2 | 194 | * 14 Jun 2005 macro Use irqreturn_t. |
1da177e4 LT |
195 | */ |
196 | ||
197 | /* Include files */ | |
198 | ||
199 | #include <linux/module.h> | |
200 | #include <linux/kernel.h> | |
201 | #include <linux/string.h> | |
202 | #include <linux/errno.h> | |
203 | #include <linux/ioport.h> | |
204 | #include <linux/slab.h> | |
205 | #include <linux/interrupt.h> | |
206 | #include <linux/pci.h> | |
207 | #include <linux/delay.h> | |
208 | #include <linux/init.h> | |
209 | #include <linux/netdevice.h> | |
210 | #include <linux/fddidevice.h> | |
211 | #include <linux/skbuff.h> | |
212 | #include <linux/bitops.h> | |
213 | ||
214 | #include <asm/byteorder.h> | |
215 | #include <asm/io.h> | |
216 | ||
217 | #include "defxx.h" | |
218 | ||
219 | /* Version information string should be updated prior to each new release! */ | |
220 | #define DRV_NAME "defxx" | |
feea1db2 MR |
221 | #define DRV_VERSION "v1.08" |
222 | #define DRV_RELDATE "2005/06/14" | |
1da177e4 LT |
223 | |
224 | static char version[] __devinitdata = | |
225 | DRV_NAME ": " DRV_VERSION " " DRV_RELDATE | |
226 | " Lawrence V. Stefani and others\n"; | |
227 | ||
228 | #define DYNAMIC_BUFFERS 1 | |
229 | ||
230 | #define SKBUFF_RX_COPYBREAK 200 | |
231 | /* | |
232 | * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte | |
233 | * alignment for compatibility with old EISA boards. | |
234 | */ | |
235 | #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) | |
236 | ||
237 | /* Define module-wide (static) routines */ | |
238 | ||
239 | static void dfx_bus_init(struct net_device *dev); | |
240 | static void dfx_bus_config_check(DFX_board_t *bp); | |
241 | ||
242 | static int dfx_driver_init(struct net_device *dev, const char *print_name); | |
243 | static int dfx_adap_init(DFX_board_t *bp, int get_buffers); | |
244 | ||
245 | static int dfx_open(struct net_device *dev); | |
246 | static int dfx_close(struct net_device *dev); | |
247 | ||
248 | static void dfx_int_pr_halt_id(DFX_board_t *bp); | |
249 | static void dfx_int_type_0_process(DFX_board_t *bp); | |
250 | static void dfx_int_common(struct net_device *dev); | |
7d12e780 | 251 | static irqreturn_t dfx_interrupt(int irq, void *dev_id); |
1da177e4 LT |
252 | |
253 | static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); | |
254 | static void dfx_ctl_set_multicast_list(struct net_device *dev); | |
255 | static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); | |
256 | static int dfx_ctl_update_cam(DFX_board_t *bp); | |
257 | static int dfx_ctl_update_filters(DFX_board_t *bp); | |
258 | ||
259 | static int dfx_hw_dma_cmd_req(DFX_board_t *bp); | |
260 | static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); | |
261 | static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); | |
262 | static int dfx_hw_adap_state_rd(DFX_board_t *bp); | |
263 | static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); | |
264 | ||
265 | static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); | |
266 | static void dfx_rcv_queue_process(DFX_board_t *bp); | |
267 | static void dfx_rcv_flush(DFX_board_t *bp); | |
268 | ||
269 | static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev); | |
270 | static int dfx_xmt_done(DFX_board_t *bp); | |
271 | static void dfx_xmt_flush(DFX_board_t *bp); | |
272 | ||
273 | /* Define module-wide (static) variables */ | |
274 | ||
275 | static struct net_device *root_dfx_eisa_dev; | |
276 | ||
6aa20a22 | 277 | |
1da177e4 LT |
278 | /* |
279 | * ======================= | |
280 | * = dfx_port_write_byte = | |
281 | * = dfx_port_read_byte = | |
282 | * = dfx_port_write_long = | |
283 | * = dfx_port_read_long = | |
284 | * ======================= | |
6aa20a22 | 285 | * |
1da177e4 LT |
286 | * Overview: |
287 | * Routines for reading and writing values from/to adapter | |
6aa20a22 | 288 | * |
1da177e4 LT |
289 | * Returns: |
290 | * None | |
6aa20a22 | 291 | * |
1da177e4 LT |
292 | * Arguments: |
293 | * bp - pointer to board information | |
294 | * offset - register offset from base I/O address | |
295 | * data - for dfx_port_write_byte and dfx_port_write_long, this | |
296 | * is a value to write. | |
297 | * for dfx_port_read_byte and dfx_port_read_byte, this | |
298 | * is a pointer to store the read value. | |
299 | * | |
300 | * Functional Description: | |
301 | * These routines perform the correct operation to read or write | |
302 | * the adapter register. | |
6aa20a22 | 303 | * |
1da177e4 LT |
304 | * EISA port block base addresses are based on the slot number in which the |
305 | * controller is installed. For example, if the EISA controller is installed | |
306 | * in slot 4, the port block base address is 0x4000. If the controller is | |
307 | * installed in slot 2, the port block base address is 0x2000, and so on. | |
308 | * This port block can be used to access PDQ, ESIC, and DEFEA on-board | |
309 | * registers using the register offsets defined in DEFXX.H. | |
310 | * | |
311 | * PCI port block base addresses are assigned by the PCI BIOS or system | |
312 | * firmware. There is one 128 byte port block which can be accessed. It | |
313 | * allows for I/O mapping of both PDQ and PFI registers using the register | |
314 | * offsets defined in DEFXX.H. | |
315 | * | |
316 | * Return Codes: | |
317 | * None | |
318 | * | |
319 | * Assumptions: | |
320 | * bp->base_addr is a valid base I/O address for this adapter. | |
321 | * offset is a valid register offset for this adapter. | |
322 | * | |
323 | * Side Effects: | |
324 | * Rather than produce macros for these functions, these routines | |
325 | * are defined using "inline" to ensure that the compiler will | |
326 | * generate inline code and not waste a procedure call and return. | |
327 | * This provides all the benefits of macros, but with the | |
328 | * advantage of strict data type checking. | |
329 | */ | |
330 | ||
331 | static inline void dfx_port_write_byte( | |
332 | DFX_board_t *bp, | |
333 | int offset, | |
334 | u8 data | |
335 | ) | |
336 | ||
337 | { | |
338 | u16 port = bp->base_addr + offset; | |
339 | ||
340 | outb(data, port); | |
341 | } | |
342 | ||
343 | static inline void dfx_port_read_byte( | |
344 | DFX_board_t *bp, | |
345 | int offset, | |
346 | u8 *data | |
347 | ) | |
348 | ||
349 | { | |
350 | u16 port = bp->base_addr + offset; | |
351 | ||
352 | *data = inb(port); | |
353 | } | |
354 | ||
355 | static inline void dfx_port_write_long( | |
356 | DFX_board_t *bp, | |
357 | int offset, | |
358 | u32 data | |
359 | ) | |
360 | ||
361 | { | |
362 | u16 port = bp->base_addr + offset; | |
363 | ||
364 | outl(data, port); | |
365 | } | |
366 | ||
367 | static inline void dfx_port_read_long( | |
368 | DFX_board_t *bp, | |
369 | int offset, | |
370 | u32 *data | |
371 | ) | |
372 | ||
373 | { | |
374 | u16 port = bp->base_addr + offset; | |
375 | ||
376 | *data = inl(port); | |
377 | } | |
378 | ||
6aa20a22 | 379 | |
1da177e4 LT |
380 | /* |
381 | * ============= | |
382 | * = dfx_init_one_pci_or_eisa = | |
383 | * ============= | |
6aa20a22 | 384 | * |
1da177e4 LT |
385 | * Overview: |
386 | * Initializes a supported FDDI EISA or PCI controller | |
6aa20a22 | 387 | * |
1da177e4 LT |
388 | * Returns: |
389 | * Condition code | |
6aa20a22 | 390 | * |
1da177e4 LT |
391 | * Arguments: |
392 | * pdev - pointer to pci device information (NULL for EISA) | |
393 | * ioaddr - pointer to port (NULL for PCI) | |
394 | * | |
395 | * Functional Description: | |
396 | * | |
397 | * Return Codes: | |
398 | * 0 - This device (fddi0, fddi1, etc) configured successfully | |
399 | * -EBUSY - Failed to get resources, or dfx_driver_init failed. | |
400 | * | |
401 | * Assumptions: | |
402 | * It compiles so it should work :-( (PCI cards do :-) | |
403 | * | |
404 | * Side Effects: | |
405 | * Device structures for FDDI adapters (fddi0, fddi1, etc) are | |
406 | * initialized and the board resources are read and stored in | |
407 | * the device structure. | |
408 | */ | |
409 | static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr) | |
410 | { | |
411 | static int version_disp; | |
412 | char *print_name = DRV_NAME; | |
413 | struct net_device *dev; | |
414 | DFX_board_t *bp; /* board pointer */ | |
415 | int alloc_size; /* total buffer size used */ | |
416 | int err; | |
417 | ||
418 | if (!version_disp) { /* display version info if adapter is found */ | |
419 | version_disp = 1; /* set display flag to TRUE so that */ | |
420 | printk(version); /* we only display this string ONCE */ | |
421 | } | |
422 | ||
423 | if (pdev != NULL) | |
424 | print_name = pci_name(pdev); | |
425 | ||
426 | dev = alloc_fddidev(sizeof(*bp)); | |
427 | if (!dev) { | |
428 | printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n", | |
429 | print_name); | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
433 | /* Enable PCI device. */ | |
434 | if (pdev != NULL) { | |
435 | err = pci_enable_device (pdev); | |
436 | if (err) goto err_out; | |
437 | ioaddr = pci_resource_start (pdev, 1); | |
438 | } | |
439 | ||
440 | SET_MODULE_OWNER(dev); | |
feea1db2 MR |
441 | if (pdev != NULL) |
442 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1da177e4 LT |
443 | |
444 | bp = dev->priv; | |
445 | ||
446 | if (!request_region(ioaddr, | |
447 | pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, | |
448 | print_name)) { | |
449 | printk(KERN_ERR "%s: Cannot reserve I/O resource " | |
450 | "0x%x @ 0x%lx, aborting\n", print_name, | |
451 | pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, ioaddr); | |
452 | err = -EBUSY; | |
453 | goto err_out; | |
454 | } | |
455 | ||
456 | /* Initialize new device structure */ | |
457 | ||
458 | dev->base_addr = ioaddr; /* save port (I/O) base address */ | |
459 | ||
460 | dev->get_stats = dfx_ctl_get_stats; | |
461 | dev->open = dfx_open; | |
462 | dev->stop = dfx_close; | |
463 | dev->hard_start_xmit = dfx_xmt_queue_pkt; | |
464 | dev->set_multicast_list = dfx_ctl_set_multicast_list; | |
465 | dev->set_mac_address = dfx_ctl_set_mac_address; | |
466 | ||
467 | if (pdev == NULL) { | |
468 | /* EISA board */ | |
469 | bp->bus_type = DFX_BUS_TYPE_EISA; | |
470 | bp->next = root_dfx_eisa_dev; | |
471 | root_dfx_eisa_dev = dev; | |
472 | } else { | |
473 | /* PCI board */ | |
474 | bp->bus_type = DFX_BUS_TYPE_PCI; | |
475 | bp->pci_dev = pdev; | |
476 | pci_set_drvdata (pdev, dev); | |
477 | pci_set_master (pdev); | |
478 | } | |
479 | ||
480 | if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) { | |
481 | err = -ENODEV; | |
482 | goto err_out_region; | |
483 | } | |
484 | ||
485 | err = register_netdev(dev); | |
486 | if (err) | |
487 | goto err_out_kfree; | |
488 | ||
489 | printk("%s: registered as %s\n", print_name, dev->name); | |
490 | return 0; | |
491 | ||
492 | err_out_kfree: | |
493 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
494 | PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + | |
495 | #ifndef DYNAMIC_BUFFERS | |
496 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
497 | #endif | |
498 | sizeof(PI_CONSUMER_BLOCK) + | |
499 | (PI_ALIGN_K_DESC_BLK - 1); | |
500 | if (bp->kmalloced) | |
501 | pci_free_consistent(pdev, alloc_size, | |
502 | bp->kmalloced, bp->kmalloced_dma); | |
503 | err_out_region: | |
504 | release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN); | |
505 | err_out: | |
506 | free_netdev(dev); | |
507 | return err; | |
508 | } | |
509 | ||
510 | static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
511 | { | |
512 | return dfx_init_one_pci_or_eisa(pdev, 0); | |
513 | } | |
514 | ||
515 | static int __init dfx_eisa_init(void) | |
516 | { | |
517 | int rc = -ENODEV; | |
518 | int i; /* used in for loops */ | |
519 | u16 port; /* temporary I/O (port) address */ | |
520 | u32 slot_id; /* EISA hardware (slot) ID read from adapter */ | |
521 | ||
522 | DBG_printk("In dfx_eisa_init...\n"); | |
523 | ||
524 | /* Scan for FDDI EISA controllers */ | |
525 | ||
526 | for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */ | |
527 | { | |
528 | port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */ | |
529 | slot_id = inl(port); /* read EISA HW (slot) ID */ | |
530 | if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID) | |
531 | { | |
532 | port = (i << 12); /* recalc base addr */ | |
533 | ||
534 | if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0; | |
535 | } | |
536 | } | |
537 | return rc; | |
538 | } | |
6aa20a22 | 539 | |
1da177e4 LT |
540 | /* |
541 | * ================ | |
542 | * = dfx_bus_init = | |
543 | * ================ | |
6aa20a22 | 544 | * |
1da177e4 LT |
545 | * Overview: |
546 | * Initializes EISA and PCI controller bus-specific logic. | |
6aa20a22 | 547 | * |
1da177e4 LT |
548 | * Returns: |
549 | * None | |
6aa20a22 | 550 | * |
1da177e4 LT |
551 | * Arguments: |
552 | * dev - pointer to device information | |
553 | * | |
554 | * Functional Description: | |
555 | * Determine and save adapter IRQ in device table, | |
556 | * then perform bus-specific logic initialization. | |
557 | * | |
558 | * Return Codes: | |
559 | * None | |
560 | * | |
561 | * Assumptions: | |
562 | * dev->base_addr has already been set with the proper | |
563 | * base I/O address for this device. | |
564 | * | |
565 | * Side Effects: | |
566 | * Interrupts are enabled at the adapter bus-specific logic. | |
567 | * Note: Interrupts at the DMA engine (PDQ chip) are not | |
568 | * enabled yet. | |
569 | */ | |
570 | ||
571 | static void __devinit dfx_bus_init(struct net_device *dev) | |
572 | { | |
573 | DFX_board_t *bp = dev->priv; | |
574 | u8 val; /* used for I/O read/writes */ | |
575 | ||
576 | DBG_printk("In dfx_bus_init...\n"); | |
577 | ||
578 | /* | |
579 | * Initialize base I/O address field in bp structure | |
580 | * | |
581 | * Note: bp->base_addr is the same as dev->base_addr. | |
582 | * It's useful because often we'll need to read | |
583 | * or write registers where we already have the | |
584 | * bp pointer instead of the dev pointer. Having | |
585 | * the base address in the bp structure will | |
586 | * save a pointer dereference. | |
587 | * | |
588 | * IMPORTANT!! This field must be defined before | |
589 | * any of the dfx_port_* inline functions are | |
590 | * called. | |
591 | */ | |
592 | ||
593 | bp->base_addr = dev->base_addr; | |
594 | ||
595 | /* And a pointer back to the net_device struct */ | |
596 | bp->dev = dev; | |
597 | ||
598 | /* Initialize adapter based on bus type */ | |
599 | ||
600 | if (bp->bus_type == DFX_BUS_TYPE_EISA) | |
601 | { | |
602 | /* Get the interrupt level from the ESIC chip */ | |
603 | ||
604 | dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val); | |
605 | switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ) | |
606 | { | |
607 | case PI_CONFIG_STAT_0_IRQ_K_9: | |
608 | dev->irq = 9; | |
609 | break; | |
610 | ||
611 | case PI_CONFIG_STAT_0_IRQ_K_10: | |
612 | dev->irq = 10; | |
613 | break; | |
614 | ||
615 | case PI_CONFIG_STAT_0_IRQ_K_11: | |
616 | dev->irq = 11; | |
617 | break; | |
618 | ||
619 | case PI_CONFIG_STAT_0_IRQ_K_15: | |
620 | dev->irq = 15; | |
621 | break; | |
622 | } | |
623 | ||
624 | /* Enable access to I/O on the board by writing 0x03 to Function Control Register */ | |
625 | ||
626 | dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB); | |
627 | ||
628 | /* Set the I/O decode range of the board */ | |
629 | ||
630 | val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT); | |
631 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val); | |
632 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val); | |
633 | ||
634 | /* Enable access to rest of module (including PDQ and packet memory) */ | |
635 | ||
636 | dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB); | |
637 | ||
638 | /* | |
639 | * Map PDQ registers into I/O space. This is done by clearing a bit | |
640 | * in Burst Holdoff register. | |
641 | */ | |
642 | ||
643 | dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val); | |
644 | dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP)); | |
645 | ||
646 | /* Enable interrupts at EISA bus interface chip (ESIC) */ | |
647 | ||
648 | dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val); | |
649 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB)); | |
650 | } | |
651 | else | |
652 | { | |
653 | struct pci_dev *pdev = bp->pci_dev; | |
654 | ||
655 | /* Get the interrupt level from the PCI Configuration Table */ | |
656 | ||
657 | dev->irq = pdev->irq; | |
658 | ||
659 | /* Check Latency Timer and set if less than minimal */ | |
660 | ||
661 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); | |
662 | if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */ | |
663 | { | |
664 | val = PFI_K_LAT_TIMER_DEF; | |
665 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); | |
666 | } | |
667 | ||
668 | /* Enable interrupts at PCI bus interface chip (PFI) */ | |
669 | ||
670 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB)); | |
671 | } | |
672 | } | |
673 | ||
6aa20a22 | 674 | |
1da177e4 LT |
675 | /* |
676 | * ======================== | |
677 | * = dfx_bus_config_check = | |
678 | * ======================== | |
6aa20a22 | 679 | * |
1da177e4 LT |
680 | * Overview: |
681 | * Checks the configuration (burst size, full-duplex, etc.) If any parameters | |
682 | * are illegal, then this routine will set new defaults. | |
6aa20a22 | 683 | * |
1da177e4 LT |
684 | * Returns: |
685 | * None | |
6aa20a22 | 686 | * |
1da177e4 LT |
687 | * Arguments: |
688 | * bp - pointer to board information | |
689 | * | |
690 | * Functional Description: | |
691 | * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later | |
692 | * PDQ, and all FDDI PCI controllers, all values are legal. | |
693 | * | |
694 | * Return Codes: | |
695 | * None | |
696 | * | |
697 | * Assumptions: | |
698 | * dfx_adap_init has NOT been called yet so burst size and other items have | |
699 | * not been set. | |
700 | * | |
701 | * Side Effects: | |
702 | * None | |
703 | */ | |
704 | ||
705 | static void __devinit dfx_bus_config_check(DFX_board_t *bp) | |
706 | { | |
707 | int status; /* return code from adapter port control call */ | |
708 | u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */ | |
709 | u32 host_data; /* LW data returned from port control call */ | |
710 | ||
711 | DBG_printk("In dfx_bus_config_check...\n"); | |
712 | ||
713 | /* Configuration check only valid for EISA adapter */ | |
714 | ||
715 | if (bp->bus_type == DFX_BUS_TYPE_EISA) | |
716 | { | |
717 | dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id); | |
718 | ||
719 | /* | |
720 | * First check if revision 2 EISA controller. Rev. 1 cards used | |
721 | * PDQ revision B, so no workaround needed in this case. Rev. 3 | |
722 | * cards used PDQ revision E, so no workaround needed in this | |
723 | * case, either. Only Rev. 2 cards used either Rev. D or E | |
724 | * chips, so we must verify the chip revision on Rev. 2 cards. | |
725 | */ | |
726 | ||
727 | if (slot_id == DEFEA_PROD_ID_2) | |
728 | { | |
729 | /* | |
730 | * Revision 2 FDDI EISA controller found, so let's check PDQ | |
731 | * revision of adapter. | |
732 | */ | |
733 | ||
734 | status = dfx_hw_port_ctrl_req(bp, | |
735 | PI_PCTRL_M_SUB_CMD, | |
736 | PI_SUB_CMD_K_PDQ_REV_GET, | |
737 | 0, | |
738 | &host_data); | |
739 | if ((status != DFX_K_SUCCESS) || (host_data == 2)) | |
740 | { | |
741 | /* | |
742 | * Either we couldn't determine the PDQ revision, or | |
743 | * we determined that it is at revision D. In either case, | |
744 | * we need to implement the workaround. | |
745 | */ | |
746 | ||
747 | /* Ensure that the burst size is set to 8 longwords or less */ | |
748 | ||
749 | switch (bp->burst_size) | |
750 | { | |
751 | case PI_PDATA_B_DMA_BURST_SIZE_32: | |
752 | case PI_PDATA_B_DMA_BURST_SIZE_16: | |
753 | bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; | |
754 | break; | |
755 | ||
756 | default: | |
757 | break; | |
758 | } | |
759 | ||
760 | /* Ensure that full-duplex mode is not enabled */ | |
761 | ||
762 | bp->full_duplex_enb = PI_SNMP_K_FALSE; | |
763 | } | |
764 | } | |
765 | } | |
766 | } | |
767 | ||
6aa20a22 | 768 | |
1da177e4 LT |
769 | /* |
770 | * =================== | |
771 | * = dfx_driver_init = | |
772 | * =================== | |
6aa20a22 | 773 | * |
1da177e4 LT |
774 | * Overview: |
775 | * Initializes remaining adapter board structure information | |
776 | * and makes sure adapter is in a safe state prior to dfx_open(). | |
6aa20a22 | 777 | * |
1da177e4 LT |
778 | * Returns: |
779 | * Condition code | |
6aa20a22 | 780 | * |
1da177e4 LT |
781 | * Arguments: |
782 | * dev - pointer to device information | |
783 | * print_name - printable device name | |
784 | * | |
785 | * Functional Description: | |
786 | * This function allocates additional resources such as the host memory | |
787 | * blocks needed by the adapter (eg. descriptor and consumer blocks). | |
788 | * Remaining bus initialization steps are also completed. The adapter | |
789 | * is also reset so that it is in the DMA_UNAVAILABLE state. The OS | |
790 | * must call dfx_open() to open the adapter and bring it on-line. | |
791 | * | |
792 | * Return Codes: | |
793 | * DFX_K_SUCCESS - initialization succeeded | |
794 | * DFX_K_FAILURE - initialization failed - could not allocate memory | |
795 | * or read adapter MAC address | |
796 | * | |
797 | * Assumptions: | |
798 | * Memory allocated from pci_alloc_consistent() call is physically | |
799 | * contiguous, locked memory. | |
800 | * | |
801 | * Side Effects: | |
802 | * Adapter is reset and should be in DMA_UNAVAILABLE state before | |
803 | * returning from this routine. | |
804 | */ | |
805 | ||
806 | static int __devinit dfx_driver_init(struct net_device *dev, | |
807 | const char *print_name) | |
808 | { | |
809 | DFX_board_t *bp = dev->priv; | |
810 | int alloc_size; /* total buffer size needed */ | |
811 | char *top_v, *curr_v; /* virtual addrs into memory block */ | |
812 | dma_addr_t top_p, curr_p; /* physical addrs into memory block */ | |
813 | u32 data; /* host data register value */ | |
814 | ||
815 | DBG_printk("In dfx_driver_init...\n"); | |
816 | ||
817 | /* Initialize bus-specific hardware registers */ | |
818 | ||
819 | dfx_bus_init(dev); | |
820 | ||
821 | /* | |
822 | * Initialize default values for configurable parameters | |
823 | * | |
824 | * Note: All of these parameters are ones that a user may | |
825 | * want to customize. It'd be nice to break these | |
826 | * out into Space.c or someplace else that's more | |
827 | * accessible/understandable than this file. | |
828 | */ | |
829 | ||
830 | bp->full_duplex_enb = PI_SNMP_K_FALSE; | |
831 | bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ | |
832 | bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; | |
833 | bp->rcv_bufs_to_post = RCV_BUFS_DEF; | |
834 | ||
835 | /* | |
836 | * Ensure that HW configuration is OK | |
837 | * | |
838 | * Note: Depending on the hardware revision, we may need to modify | |
839 | * some of the configurable parameters to workaround hardware | |
840 | * limitations. We'll perform this configuration check AFTER | |
841 | * setting the parameters to their default values. | |
842 | */ | |
843 | ||
844 | dfx_bus_config_check(bp); | |
845 | ||
846 | /* Disable PDQ interrupts first */ | |
847 | ||
848 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
849 | ||
850 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
851 | ||
852 | (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); | |
853 | ||
854 | /* Read the factory MAC address from the adapter then save it */ | |
855 | ||
856 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, | |
857 | &data) != DFX_K_SUCCESS) { | |
858 | printk("%s: Could not read adapter factory MAC address!\n", | |
859 | print_name); | |
860 | return(DFX_K_FAILURE); | |
861 | } | |
862 | memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32)); | |
863 | ||
864 | if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, | |
865 | &data) != DFX_K_SUCCESS) { | |
866 | printk("%s: Could not read adapter factory MAC address!\n", | |
867 | print_name); | |
868 | return(DFX_K_FAILURE); | |
869 | } | |
870 | memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16)); | |
871 | ||
872 | /* | |
873 | * Set current address to factory address | |
874 | * | |
875 | * Note: Node address override support is handled through | |
876 | * dfx_ctl_set_mac_address. | |
877 | */ | |
878 | ||
879 | memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); | |
880 | if (bp->bus_type == DFX_BUS_TYPE_EISA) | |
881 | printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, " | |
882 | "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", | |
883 | print_name, dev->base_addr, dev->irq, | |
884 | dev->dev_addr[0], dev->dev_addr[1], | |
885 | dev->dev_addr[2], dev->dev_addr[3], | |
886 | dev->dev_addr[4], dev->dev_addr[5]); | |
887 | else | |
888 | printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, " | |
889 | "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n", | |
890 | print_name, dev->base_addr, dev->irq, | |
891 | dev->dev_addr[0], dev->dev_addr[1], | |
892 | dev->dev_addr[2], dev->dev_addr[3], | |
893 | dev->dev_addr[4], dev->dev_addr[5]); | |
894 | ||
895 | /* | |
896 | * Get memory for descriptor block, consumer block, and other buffers | |
897 | * that need to be DMA read or written to by the adapter. | |
898 | */ | |
899 | ||
900 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
901 | PI_CMD_REQ_K_SIZE_MAX + | |
902 | PI_CMD_RSP_K_SIZE_MAX + | |
903 | #ifndef DYNAMIC_BUFFERS | |
904 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
905 | #endif | |
906 | sizeof(PI_CONSUMER_BLOCK) + | |
907 | (PI_ALIGN_K_DESC_BLK - 1); | |
908 | bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size, | |
909 | &bp->kmalloced_dma); | |
910 | if (top_v == NULL) { | |
911 | printk("%s: Could not allocate memory for host buffers " | |
912 | "and structures!\n", print_name); | |
913 | return(DFX_K_FAILURE); | |
914 | } | |
915 | memset(top_v, 0, alloc_size); /* zero out memory before continuing */ | |
916 | top_p = bp->kmalloced_dma; /* get physical address of buffer */ | |
917 | ||
918 | /* | |
919 | * To guarantee the 8K alignment required for the descriptor block, 8K - 1 | |
920 | * plus the amount of memory needed was allocated. The physical address | |
921 | * is now 8K aligned. By carving up the memory in a specific order, | |
922 | * we'll guarantee the alignment requirements for all other structures. | |
923 | * | |
924 | * Note: If the assumptions change regarding the non-paged, non-cached, | |
925 | * physically contiguous nature of the memory block or the address | |
926 | * alignments, then we'll need to implement a different algorithm | |
927 | * for allocating the needed memory. | |
928 | */ | |
929 | ||
930 | curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); | |
931 | curr_v = top_v + (curr_p - top_p); | |
932 | ||
933 | /* Reserve space for descriptor block */ | |
934 | ||
935 | bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; | |
936 | bp->descr_block_phys = curr_p; | |
937 | curr_v += sizeof(PI_DESCR_BLOCK); | |
938 | curr_p += sizeof(PI_DESCR_BLOCK); | |
939 | ||
940 | /* Reserve space for command request buffer */ | |
941 | ||
942 | bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; | |
943 | bp->cmd_req_phys = curr_p; | |
944 | curr_v += PI_CMD_REQ_K_SIZE_MAX; | |
945 | curr_p += PI_CMD_REQ_K_SIZE_MAX; | |
946 | ||
947 | /* Reserve space for command response buffer */ | |
948 | ||
949 | bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; | |
950 | bp->cmd_rsp_phys = curr_p; | |
951 | curr_v += PI_CMD_RSP_K_SIZE_MAX; | |
952 | curr_p += PI_CMD_RSP_K_SIZE_MAX; | |
953 | ||
954 | /* Reserve space for the LLC host receive queue buffers */ | |
955 | ||
956 | bp->rcv_block_virt = curr_v; | |
957 | bp->rcv_block_phys = curr_p; | |
958 | ||
959 | #ifndef DYNAMIC_BUFFERS | |
960 | curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); | |
961 | curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); | |
962 | #endif | |
963 | ||
964 | /* Reserve space for the consumer block */ | |
965 | ||
966 | bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; | |
967 | bp->cons_block_phys = curr_p; | |
968 | ||
969 | /* Display virtual and physical addresses if debug driver */ | |
970 | ||
971 | DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", | |
972 | print_name, | |
973 | (long)bp->descr_block_virt, bp->descr_block_phys); | |
974 | DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", | |
975 | print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); | |
976 | DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", | |
977 | print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); | |
978 | DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", | |
979 | print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); | |
980 | DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", | |
981 | print_name, (long)bp->cons_block_virt, bp->cons_block_phys); | |
982 | ||
983 | return(DFX_K_SUCCESS); | |
984 | } | |
985 | ||
6aa20a22 | 986 | |
1da177e4 LT |
987 | /* |
988 | * ================= | |
989 | * = dfx_adap_init = | |
990 | * ================= | |
6aa20a22 | 991 | * |
1da177e4 LT |
992 | * Overview: |
993 | * Brings the adapter to the link avail/link unavailable state. | |
6aa20a22 | 994 | * |
1da177e4 LT |
995 | * Returns: |
996 | * Condition code | |
6aa20a22 | 997 | * |
1da177e4 LT |
998 | * Arguments: |
999 | * bp - pointer to board information | |
1000 | * get_buffers - non-zero if buffers to be allocated | |
1001 | * | |
1002 | * Functional Description: | |
1003 | * Issues the low-level firmware/hardware calls necessary to bring | |
1004 | * the adapter up, or to properly reset and restore adapter during | |
1005 | * run-time. | |
1006 | * | |
1007 | * Return Codes: | |
1008 | * DFX_K_SUCCESS - Adapter brought up successfully | |
1009 | * DFX_K_FAILURE - Adapter initialization failed | |
1010 | * | |
1011 | * Assumptions: | |
1012 | * bp->reset_type should be set to a valid reset type value before | |
1013 | * calling this routine. | |
1014 | * | |
1015 | * Side Effects: | |
1016 | * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state | |
1017 | * upon a successful return of this routine. | |
1018 | */ | |
1019 | ||
1020 | static int dfx_adap_init(DFX_board_t *bp, int get_buffers) | |
1021 | { | |
1022 | DBG_printk("In dfx_adap_init...\n"); | |
1023 | ||
1024 | /* Disable PDQ interrupts first */ | |
1025 | ||
1026 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1027 | ||
1028 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
1029 | ||
1030 | if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) | |
1031 | { | |
1032 | printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); | |
1033 | return(DFX_K_FAILURE); | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * When the PDQ is reset, some false Type 0 interrupts may be pending, | |
1038 | * so we'll acknowledge all Type 0 interrupts now before continuing. | |
1039 | */ | |
1040 | ||
1041 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); | |
1042 | ||
1043 | /* | |
1044 | * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state | |
1045 | * | |
1046 | * Note: We only need to clear host copies of these registers. The PDQ reset | |
1047 | * takes care of the on-board register values. | |
1048 | */ | |
1049 | ||
1050 | bp->cmd_req_reg.lword = 0; | |
1051 | bp->cmd_rsp_reg.lword = 0; | |
1052 | bp->rcv_xmt_reg.lword = 0; | |
1053 | ||
1054 | /* Clear consumer block before going to DMA_AVAILABLE state */ | |
1055 | ||
1056 | memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); | |
1057 | ||
1058 | /* Initialize the DMA Burst Size */ | |
1059 | ||
1060 | if (dfx_hw_port_ctrl_req(bp, | |
1061 | PI_PCTRL_M_SUB_CMD, | |
1062 | PI_SUB_CMD_K_BURST_SIZE_SET, | |
1063 | bp->burst_size, | |
1064 | NULL) != DFX_K_SUCCESS) | |
1065 | { | |
1066 | printk("%s: Could not set adapter burst size!\n", bp->dev->name); | |
1067 | return(DFX_K_FAILURE); | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Set base address of Consumer Block | |
1072 | * | |
1073 | * Assumption: 32-bit physical address of consumer block is 64 byte | |
1074 | * aligned. That is, bits 0-5 of the address must be zero. | |
1075 | */ | |
1076 | ||
1077 | if (dfx_hw_port_ctrl_req(bp, | |
1078 | PI_PCTRL_M_CONS_BLOCK, | |
1079 | bp->cons_block_phys, | |
1080 | 0, | |
1081 | NULL) != DFX_K_SUCCESS) | |
1082 | { | |
1083 | printk("%s: Could not set consumer block address!\n", bp->dev->name); | |
1084 | return(DFX_K_FAILURE); | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state | |
1089 | * | |
1090 | * Note: We also set the literal and data swapping requirements in this | |
1091 | * command. Since this driver presently runs on Intel platforms | |
1092 | * which are Little Endian, we'll tell the adapter to byte swap | |
1093 | * data only. This code will need to change when we support | |
1094 | * Big Endian systems (eg. PowerPC). | |
1095 | * | |
1096 | * Assumption: 32-bit physical address of descriptor block is 8Kbyte | |
1097 | * aligned. That is, bits 0-12 of the address must be zero. | |
1098 | */ | |
1099 | ||
1100 | if (dfx_hw_port_ctrl_req(bp, | |
1101 | PI_PCTRL_M_INIT, | |
1102 | (u32) (bp->descr_block_phys | PI_PDATA_A_INIT_M_BSWAP_DATA), | |
1103 | 0, | |
1104 | NULL) != DFX_K_SUCCESS) | |
1105 | { | |
1106 | printk("%s: Could not set descriptor block address!\n", bp->dev->name); | |
1107 | return(DFX_K_FAILURE); | |
1108 | } | |
1109 | ||
1110 | /* Set transmit flush timeout value */ | |
1111 | ||
1112 | bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; | |
1113 | bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; | |
1114 | bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ | |
1115 | bp->cmd_req_virt->char_set.item[0].item_index = 0; | |
1116 | bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; | |
1117 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1118 | { | |
1119 | printk("%s: DMA command request failed!\n", bp->dev->name); | |
1120 | return(DFX_K_FAILURE); | |
1121 | } | |
1122 | ||
1123 | /* Set the initial values for eFDXEnable and MACTReq MIB objects */ | |
1124 | ||
1125 | bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; | |
1126 | bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; | |
1127 | bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; | |
1128 | bp->cmd_req_virt->snmp_set.item[0].item_index = 0; | |
1129 | bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; | |
1130 | bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; | |
1131 | bp->cmd_req_virt->snmp_set.item[1].item_index = 0; | |
1132 | bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; | |
1133 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1134 | { | |
1135 | printk("%s: DMA command request failed!\n", bp->dev->name); | |
1136 | return(DFX_K_FAILURE); | |
1137 | } | |
1138 | ||
1139 | /* Initialize adapter CAM */ | |
1140 | ||
1141 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) | |
1142 | { | |
1143 | printk("%s: Adapter CAM update failed!\n", bp->dev->name); | |
1144 | return(DFX_K_FAILURE); | |
1145 | } | |
1146 | ||
1147 | /* Initialize adapter filters */ | |
1148 | ||
1149 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
1150 | { | |
1151 | printk("%s: Adapter filters update failed!\n", bp->dev->name); | |
1152 | return(DFX_K_FAILURE); | |
1153 | } | |
1154 | ||
1155 | /* | |
1156 | * Remove any existing dynamic buffers (i.e. if the adapter is being | |
1157 | * reinitialized) | |
1158 | */ | |
1159 | ||
1160 | if (get_buffers) | |
1161 | dfx_rcv_flush(bp); | |
1162 | ||
1163 | /* Initialize receive descriptor block and produce buffers */ | |
1164 | ||
1165 | if (dfx_rcv_init(bp, get_buffers)) | |
1166 | { | |
1167 | printk("%s: Receive buffer allocation failed\n", bp->dev->name); | |
1168 | if (get_buffers) | |
1169 | dfx_rcv_flush(bp); | |
1170 | return(DFX_K_FAILURE); | |
1171 | } | |
1172 | ||
1173 | /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ | |
1174 | ||
1175 | bp->cmd_req_virt->cmd_type = PI_CMD_K_START; | |
1176 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1177 | { | |
1178 | printk("%s: Start command failed\n", bp->dev->name); | |
1179 | if (get_buffers) | |
1180 | dfx_rcv_flush(bp); | |
1181 | return(DFX_K_FAILURE); | |
1182 | } | |
1183 | ||
1184 | /* Initialization succeeded, reenable PDQ interrupts */ | |
1185 | ||
1186 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); | |
1187 | return(DFX_K_SUCCESS); | |
1188 | } | |
1189 | ||
6aa20a22 | 1190 | |
1da177e4 LT |
1191 | /* |
1192 | * ============ | |
1193 | * = dfx_open = | |
1194 | * ============ | |
6aa20a22 | 1195 | * |
1da177e4 LT |
1196 | * Overview: |
1197 | * Opens the adapter | |
6aa20a22 | 1198 | * |
1da177e4 LT |
1199 | * Returns: |
1200 | * Condition code | |
6aa20a22 | 1201 | * |
1da177e4 LT |
1202 | * Arguments: |
1203 | * dev - pointer to device information | |
1204 | * | |
1205 | * Functional Description: | |
1206 | * This function brings the adapter to an operational state. | |
1207 | * | |
1208 | * Return Codes: | |
1209 | * 0 - Adapter was successfully opened | |
1210 | * -EAGAIN - Could not register IRQ or adapter initialization failed | |
1211 | * | |
1212 | * Assumptions: | |
1213 | * This routine should only be called for a device that was | |
1214 | * initialized successfully. | |
1215 | * | |
1216 | * Side Effects: | |
1217 | * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state | |
1218 | * if the open is successful. | |
1219 | */ | |
1220 | ||
1221 | static int dfx_open(struct net_device *dev) | |
1222 | { | |
1223 | int ret; | |
1224 | DFX_board_t *bp = dev->priv; | |
1225 | ||
1226 | DBG_printk("In dfx_open...\n"); | |
6aa20a22 | 1227 | |
1da177e4 LT |
1228 | /* Register IRQ - support shared interrupts by passing device ptr */ |
1229 | ||
1fb9df5d | 1230 | ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
1231 | if (ret) { |
1232 | printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); | |
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * Set current address to factory MAC address | |
1238 | * | |
1239 | * Note: We've already done this step in dfx_driver_init. | |
1240 | * However, it's possible that a user has set a node | |
1241 | * address override, then closed and reopened the | |
1242 | * adapter. Unless we reset the device address field | |
1243 | * now, we'll continue to use the existing modified | |
1244 | * address. | |
1245 | */ | |
1246 | ||
1247 | memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); | |
1248 | ||
1249 | /* Clear local unicast/multicast address tables and counts */ | |
1250 | ||
1251 | memset(bp->uc_table, 0, sizeof(bp->uc_table)); | |
1252 | memset(bp->mc_table, 0, sizeof(bp->mc_table)); | |
1253 | bp->uc_count = 0; | |
1254 | bp->mc_count = 0; | |
1255 | ||
1256 | /* Disable promiscuous filter settings */ | |
1257 | ||
1258 | bp->ind_group_prom = PI_FSTATE_K_BLOCK; | |
1259 | bp->group_prom = PI_FSTATE_K_BLOCK; | |
1260 | ||
1261 | spin_lock_init(&bp->lock); | |
1262 | ||
1263 | /* Reset and initialize adapter */ | |
1264 | ||
1265 | bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ | |
1266 | if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) | |
1267 | { | |
1268 | printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); | |
1269 | free_irq(dev->irq, dev); | |
1270 | return -EAGAIN; | |
1271 | } | |
1272 | ||
1273 | /* Set device structure info */ | |
1274 | netif_start_queue(dev); | |
1275 | return(0); | |
1276 | } | |
1277 | ||
6aa20a22 | 1278 | |
1da177e4 LT |
1279 | /* |
1280 | * ============= | |
1281 | * = dfx_close = | |
1282 | * ============= | |
6aa20a22 | 1283 | * |
1da177e4 LT |
1284 | * Overview: |
1285 | * Closes the device/module. | |
6aa20a22 | 1286 | * |
1da177e4 LT |
1287 | * Returns: |
1288 | * Condition code | |
6aa20a22 | 1289 | * |
1da177e4 LT |
1290 | * Arguments: |
1291 | * dev - pointer to device information | |
1292 | * | |
1293 | * Functional Description: | |
1294 | * This routine closes the adapter and brings it to a safe state. | |
1295 | * The interrupt service routine is deregistered with the OS. | |
1296 | * The adapter can be opened again with another call to dfx_open(). | |
1297 | * | |
1298 | * Return Codes: | |
1299 | * Always return 0. | |
1300 | * | |
1301 | * Assumptions: | |
1302 | * No further requests for this adapter are made after this routine is | |
1303 | * called. dfx_open() can be called to reset and reinitialize the | |
1304 | * adapter. | |
1305 | * | |
1306 | * Side Effects: | |
1307 | * Adapter should be in DMA_UNAVAILABLE state upon completion of this | |
1308 | * routine. | |
1309 | */ | |
1310 | ||
1311 | static int dfx_close(struct net_device *dev) | |
1312 | { | |
1313 | DFX_board_t *bp = dev->priv; | |
1314 | ||
1315 | DBG_printk("In dfx_close...\n"); | |
1316 | ||
1317 | /* Disable PDQ interrupts first */ | |
1318 | ||
1319 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1320 | ||
1321 | /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ | |
1322 | ||
1323 | (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); | |
1324 | ||
1325 | /* | |
1326 | * Flush any pending transmit buffers | |
1327 | * | |
1328 | * Note: It's important that we flush the transmit buffers | |
1329 | * BEFORE we clear our copy of the Type 2 register. | |
1330 | * Otherwise, we'll have no idea how many buffers | |
1331 | * we need to free. | |
1332 | */ | |
1333 | ||
1334 | dfx_xmt_flush(bp); | |
1335 | ||
1336 | /* | |
1337 | * Clear Type 1 and Type 2 registers after adapter reset | |
1338 | * | |
1339 | * Note: Even though we're closing the adapter, it's | |
1340 | * possible that an interrupt will occur after | |
1341 | * dfx_close is called. Without some assurance to | |
1342 | * the contrary we want to make sure that we don't | |
1343 | * process receive and transmit LLC frames and update | |
1344 | * the Type 2 register with bad information. | |
1345 | */ | |
1346 | ||
1347 | bp->cmd_req_reg.lword = 0; | |
1348 | bp->cmd_rsp_reg.lword = 0; | |
1349 | bp->rcv_xmt_reg.lword = 0; | |
1350 | ||
1351 | /* Clear consumer block for the same reason given above */ | |
1352 | ||
1353 | memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); | |
1354 | ||
1355 | /* Release all dynamically allocate skb in the receive ring. */ | |
1356 | ||
1357 | dfx_rcv_flush(bp); | |
1358 | ||
1359 | /* Clear device structure flags */ | |
1360 | ||
1361 | netif_stop_queue(dev); | |
6aa20a22 | 1362 | |
1da177e4 LT |
1363 | /* Deregister (free) IRQ */ |
1364 | ||
1365 | free_irq(dev->irq, dev); | |
6aa20a22 | 1366 | |
1da177e4 LT |
1367 | return(0); |
1368 | } | |
1369 | ||
6aa20a22 | 1370 | |
1da177e4 LT |
1371 | /* |
1372 | * ====================== | |
1373 | * = dfx_int_pr_halt_id = | |
1374 | * ====================== | |
6aa20a22 | 1375 | * |
1da177e4 LT |
1376 | * Overview: |
1377 | * Displays halt id's in string form. | |
6aa20a22 | 1378 | * |
1da177e4 LT |
1379 | * Returns: |
1380 | * None | |
6aa20a22 | 1381 | * |
1da177e4 LT |
1382 | * Arguments: |
1383 | * bp - pointer to board information | |
1384 | * | |
1385 | * Functional Description: | |
1386 | * Determine current halt id and display appropriate string. | |
1387 | * | |
1388 | * Return Codes: | |
1389 | * None | |
1390 | * | |
1391 | * Assumptions: | |
1392 | * None | |
1393 | * | |
1394 | * Side Effects: | |
1395 | * None | |
1396 | */ | |
1397 | ||
1398 | static void dfx_int_pr_halt_id(DFX_board_t *bp) | |
1399 | { | |
1400 | PI_UINT32 port_status; /* PDQ port status register value */ | |
1401 | PI_UINT32 halt_id; /* PDQ port status halt ID */ | |
1402 | ||
1403 | /* Read the latest port status */ | |
1404 | ||
1405 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
1406 | ||
1407 | /* Display halt state transition information */ | |
1408 | ||
1409 | halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; | |
1410 | switch (halt_id) | |
1411 | { | |
1412 | case PI_HALT_ID_K_SELFTEST_TIMEOUT: | |
1413 | printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); | |
1414 | break; | |
1415 | ||
1416 | case PI_HALT_ID_K_PARITY_ERROR: | |
1417 | printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); | |
1418 | break; | |
1419 | ||
1420 | case PI_HALT_ID_K_HOST_DIR_HALT: | |
1421 | printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); | |
1422 | break; | |
1423 | ||
1424 | case PI_HALT_ID_K_SW_FAULT: | |
1425 | printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); | |
1426 | break; | |
1427 | ||
1428 | case PI_HALT_ID_K_HW_FAULT: | |
1429 | printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); | |
1430 | break; | |
1431 | ||
1432 | case PI_HALT_ID_K_PC_TRACE: | |
1433 | printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); | |
1434 | break; | |
1435 | ||
1436 | case PI_HALT_ID_K_DMA_ERROR: | |
1437 | printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); | |
1438 | break; | |
1439 | ||
1440 | case PI_HALT_ID_K_IMAGE_CRC_ERROR: | |
1441 | printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); | |
1442 | break; | |
1443 | ||
1444 | case PI_HALT_ID_K_BUS_EXCEPTION: | |
1445 | printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); | |
1446 | break; | |
1447 | ||
1448 | default: | |
1449 | printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); | |
1450 | break; | |
1451 | } | |
1452 | } | |
1453 | ||
6aa20a22 | 1454 | |
1da177e4 LT |
1455 | /* |
1456 | * ========================== | |
1457 | * = dfx_int_type_0_process = | |
1458 | * ========================== | |
6aa20a22 | 1459 | * |
1da177e4 LT |
1460 | * Overview: |
1461 | * Processes Type 0 interrupts. | |
6aa20a22 | 1462 | * |
1da177e4 LT |
1463 | * Returns: |
1464 | * None | |
6aa20a22 | 1465 | * |
1da177e4 LT |
1466 | * Arguments: |
1467 | * bp - pointer to board information | |
1468 | * | |
1469 | * Functional Description: | |
1470 | * Processes all enabled Type 0 interrupts. If the reason for the interrupt | |
1471 | * is a serious fault on the adapter, then an error message is displayed | |
1472 | * and the adapter is reset. | |
1473 | * | |
1474 | * One tricky potential timing window is the rapid succession of "link avail" | |
1475 | * "link unavail" state change interrupts. The acknowledgement of the Type 0 | |
1476 | * interrupt must be done before reading the state from the Port Status | |
1477 | * register. This is true because a state change could occur after reading | |
1478 | * the data, but before acknowledging the interrupt. If this state change | |
1479 | * does happen, it would be lost because the driver is using the old state, | |
1480 | * and it will never know about the new state because it subsequently | |
1481 | * acknowledges the state change interrupt. | |
1482 | * | |
1483 | * INCORRECT CORRECT | |
1484 | * read type 0 int reasons read type 0 int reasons | |
1485 | * read adapter state ack type 0 interrupts | |
1486 | * ack type 0 interrupts read adapter state | |
1487 | * ... process interrupt ... ... process interrupt ... | |
1488 | * | |
1489 | * Return Codes: | |
1490 | * None | |
1491 | * | |
1492 | * Assumptions: | |
1493 | * None | |
1494 | * | |
1495 | * Side Effects: | |
1496 | * An adapter reset may occur if the adapter has any Type 0 error interrupts | |
1497 | * or if the port status indicates that the adapter is halted. The driver | |
1498 | * is responsible for reinitializing the adapter with the current CAM | |
1499 | * contents and adapter filter settings. | |
1500 | */ | |
1501 | ||
1502 | static void dfx_int_type_0_process(DFX_board_t *bp) | |
1503 | ||
1504 | { | |
1505 | PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ | |
1506 | PI_UINT32 state; /* current adap state (from port status) */ | |
1507 | ||
1508 | /* | |
1509 | * Read host interrupt Type 0 register to determine which Type 0 | |
1510 | * interrupts are pending. Immediately write it back out to clear | |
1511 | * those interrupts. | |
1512 | */ | |
1513 | ||
1514 | dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); | |
1515 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); | |
1516 | ||
1517 | /* Check for Type 0 error interrupts */ | |
1518 | ||
1519 | if (type_0_status & (PI_TYPE_0_STAT_M_NXM | | |
1520 | PI_TYPE_0_STAT_M_PM_PAR_ERR | | |
1521 | PI_TYPE_0_STAT_M_BUS_PAR_ERR)) | |
1522 | { | |
1523 | /* Check for Non-Existent Memory error */ | |
1524 | ||
1525 | if (type_0_status & PI_TYPE_0_STAT_M_NXM) | |
1526 | printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); | |
1527 | ||
1528 | /* Check for Packet Memory Parity error */ | |
1529 | ||
1530 | if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) | |
1531 | printk("%s: Packet Memory Parity Error\n", bp->dev->name); | |
1532 | ||
1533 | /* Check for Host Bus Parity error */ | |
1534 | ||
1535 | if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) | |
1536 | printk("%s: Host Bus Parity Error\n", bp->dev->name); | |
1537 | ||
1538 | /* Reset adapter and bring it back on-line */ | |
1539 | ||
1540 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1541 | bp->reset_type = 0; /* rerun on-board diagnostics */ | |
1542 | printk("%s: Resetting adapter...\n", bp->dev->name); | |
1543 | if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) | |
1544 | { | |
1545 | printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); | |
1546 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1547 | return; | |
1548 | } | |
1549 | printk("%s: Adapter reset successful!\n", bp->dev->name); | |
1550 | return; | |
1551 | } | |
1552 | ||
1553 | /* Check for transmit flush interrupt */ | |
1554 | ||
1555 | if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) | |
1556 | { | |
1557 | /* Flush any pending xmt's and acknowledge the flush interrupt */ | |
1558 | ||
1559 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1560 | dfx_xmt_flush(bp); /* flush any outstanding packets */ | |
1561 | (void) dfx_hw_port_ctrl_req(bp, | |
1562 | PI_PCTRL_M_XMT_DATA_FLUSH_DONE, | |
1563 | 0, | |
1564 | 0, | |
1565 | NULL); | |
1566 | } | |
1567 | ||
1568 | /* Check for adapter state change */ | |
1569 | ||
1570 | if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) | |
6aa20a22 | 1571 | { |
1da177e4 LT |
1572 | /* Get latest adapter state */ |
1573 | ||
1574 | state = dfx_hw_adap_state_rd(bp); /* get adapter state */ | |
1575 | if (state == PI_STATE_K_HALTED) | |
1576 | { | |
1577 | /* | |
1578 | * Adapter has transitioned to HALTED state, try to reset | |
1579 | * adapter to bring it back on-line. If reset fails, | |
1580 | * leave the adapter in the broken state. | |
1581 | */ | |
1582 | ||
1583 | printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); | |
1584 | dfx_int_pr_halt_id(bp); /* display halt id as string */ | |
1585 | ||
1586 | /* Reset adapter and bring it back on-line */ | |
1587 | ||
1588 | bp->link_available = PI_K_FALSE; /* link is no longer available */ | |
1589 | bp->reset_type = 0; /* rerun on-board diagnostics */ | |
1590 | printk("%s: Resetting adapter...\n", bp->dev->name); | |
1591 | if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) | |
1592 | { | |
1593 | printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); | |
1594 | dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); | |
1595 | return; | |
1596 | } | |
1597 | printk("%s: Adapter reset successful!\n", bp->dev->name); | |
1598 | } | |
1599 | else if (state == PI_STATE_K_LINK_AVAIL) | |
1600 | { | |
1601 | bp->link_available = PI_K_TRUE; /* set link available flag */ | |
1602 | } | |
1603 | } | |
1604 | } | |
1605 | ||
6aa20a22 | 1606 | |
1da177e4 LT |
1607 | /* |
1608 | * ================== | |
1609 | * = dfx_int_common = | |
1610 | * ================== | |
6aa20a22 | 1611 | * |
1da177e4 LT |
1612 | * Overview: |
1613 | * Interrupt service routine (ISR) | |
6aa20a22 | 1614 | * |
1da177e4 LT |
1615 | * Returns: |
1616 | * None | |
6aa20a22 | 1617 | * |
1da177e4 LT |
1618 | * Arguments: |
1619 | * bp - pointer to board information | |
1620 | * | |
1621 | * Functional Description: | |
1622 | * This is the ISR which processes incoming adapter interrupts. | |
1623 | * | |
1624 | * Return Codes: | |
1625 | * None | |
1626 | * | |
1627 | * Assumptions: | |
1628 | * This routine assumes PDQ interrupts have not been disabled. | |
1629 | * When interrupts are disabled at the PDQ, the Port Status register | |
1630 | * is automatically cleared. This routine uses the Port Status | |
1631 | * register value to determine whether a Type 0 interrupt occurred, | |
1632 | * so it's important that adapter interrupts are not normally | |
1633 | * enabled/disabled at the PDQ. | |
1634 | * | |
1635 | * It's vital that this routine is NOT reentered for the | |
1636 | * same board and that the OS is not in another section of | |
1637 | * code (eg. dfx_xmt_queue_pkt) for the same board on a | |
1638 | * different thread. | |
1639 | * | |
1640 | * Side Effects: | |
1641 | * Pending interrupts are serviced. Depending on the type of | |
1642 | * interrupt, acknowledging and clearing the interrupt at the | |
1643 | * PDQ involves writing a register to clear the interrupt bit | |
1644 | * or updating completion indices. | |
1645 | */ | |
1646 | ||
1647 | static void dfx_int_common(struct net_device *dev) | |
1648 | { | |
1649 | DFX_board_t *bp = dev->priv; | |
1650 | PI_UINT32 port_status; /* Port Status register */ | |
1651 | ||
1652 | /* Process xmt interrupts - frequent case, so always call this routine */ | |
1653 | ||
1654 | if(dfx_xmt_done(bp)) /* free consumed xmt packets */ | |
1655 | netif_wake_queue(dev); | |
1656 | ||
1657 | /* Process rcv interrupts - frequent case, so always call this routine */ | |
1658 | ||
1659 | dfx_rcv_queue_process(bp); /* service received LLC frames */ | |
1660 | ||
1661 | /* | |
1662 | * Transmit and receive producer and completion indices are updated on the | |
1663 | * adapter by writing to the Type 2 Producer register. Since the frequent | |
1664 | * case is that we'll be processing either LLC transmit or receive buffers, | |
1665 | * we'll optimize I/O writes by doing a single register write here. | |
1666 | */ | |
1667 | ||
1668 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
1669 | ||
1670 | /* Read PDQ Port Status register to find out which interrupts need processing */ | |
1671 | ||
1672 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
1673 | ||
1674 | /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ | |
1675 | ||
1676 | if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) | |
1677 | dfx_int_type_0_process(bp); /* process Type 0 interrupts */ | |
1678 | } | |
1679 | ||
6aa20a22 | 1680 | |
1da177e4 LT |
1681 | /* |
1682 | * ================= | |
1683 | * = dfx_interrupt = | |
1684 | * ================= | |
feea1db2 | 1685 | * |
1da177e4 LT |
1686 | * Overview: |
1687 | * Interrupt processing routine | |
feea1db2 | 1688 | * |
1da177e4 | 1689 | * Returns: |
feea1db2 MR |
1690 | * Whether a valid interrupt was seen. |
1691 | * | |
1da177e4 LT |
1692 | * Arguments: |
1693 | * irq - interrupt vector | |
1694 | * dev_id - pointer to device information | |
1da177e4 LT |
1695 | * |
1696 | * Functional Description: | |
1697 | * This routine calls the interrupt processing routine for this adapter. It | |
1698 | * disables and reenables adapter interrupts, as appropriate. We can support | |
1699 | * shared interrupts since the incoming dev_id pointer provides our device | |
1700 | * structure context. | |
1701 | * | |
1702 | * Return Codes: | |
feea1db2 MR |
1703 | * IRQ_HANDLED - an IRQ was handled. |
1704 | * IRQ_NONE - no IRQ was handled. | |
1da177e4 LT |
1705 | * |
1706 | * Assumptions: | |
1707 | * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC | |
1708 | * on Intel-based systems) is done by the operating system outside this | |
1709 | * routine. | |
1710 | * | |
1711 | * System interrupts are enabled through this call. | |
1712 | * | |
1713 | * Side Effects: | |
1714 | * Interrupts are disabled, then reenabled at the adapter. | |
1715 | */ | |
1716 | ||
7d12e780 | 1717 | static irqreturn_t dfx_interrupt(int irq, void *dev_id) |
feea1db2 | 1718 | { |
1da177e4 LT |
1719 | struct net_device *dev = dev_id; |
1720 | DFX_board_t *bp; /* private board structure pointer */ | |
1da177e4 LT |
1721 | |
1722 | /* Get board pointer only if device structure is valid */ | |
1723 | ||
1724 | bp = dev->priv; | |
1725 | ||
1da177e4 LT |
1726 | /* See if we're already servicing an interrupt */ |
1727 | ||
1728 | /* Service adapter interrupts */ | |
1729 | ||
feea1db2 MR |
1730 | if (bp->bus_type == DFX_BUS_TYPE_PCI) { |
1731 | u32 status; | |
1da177e4 | 1732 | |
feea1db2 MR |
1733 | dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); |
1734 | if (!(status & PFI_STATUS_M_PDQ_INT)) | |
1735 | return IRQ_NONE; | |
1da177e4 | 1736 | |
feea1db2 MR |
1737 | spin_lock(&bp->lock); |
1738 | ||
1739 | /* Disable PDQ-PFI interrupts at PFI */ | |
1740 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, | |
1741 | PFI_MODE_M_DMA_ENB); | |
1da177e4 | 1742 | |
feea1db2 | 1743 | /* Call interrupt service routine for this adapter */ |
1da177e4 LT |
1744 | dfx_int_common(dev); |
1745 | ||
1746 | /* Clear PDQ interrupt status bit and reenable interrupts */ | |
feea1db2 MR |
1747 | dfx_port_write_long(bp, PFI_K_REG_STATUS, |
1748 | PFI_STATUS_M_PDQ_INT); | |
1da177e4 | 1749 | dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, |
feea1db2 MR |
1750 | (PFI_MODE_M_PDQ_INT_ENB | |
1751 | PFI_MODE_M_DMA_ENB)); | |
1da177e4 | 1752 | |
feea1db2 MR |
1753 | spin_unlock(&bp->lock); |
1754 | } else { | |
1755 | u8 status; | |
1da177e4 | 1756 | |
feea1db2 MR |
1757 | dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status); |
1758 | if (!(status & PI_CONFIG_STAT_0_M_PEND)) | |
1759 | return IRQ_NONE; | |
1da177e4 | 1760 | |
feea1db2 MR |
1761 | spin_lock(&bp->lock); |
1762 | ||
1763 | /* Disable interrupts at the ESIC */ | |
1764 | status &= ~PI_CONFIG_STAT_0_M_INT_ENB; | |
1765 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status); | |
1766 | ||
1767 | /* Call interrupt service routine for this adapter */ | |
1da177e4 LT |
1768 | dfx_int_common(dev); |
1769 | ||
1770 | /* Reenable interrupts at the ESIC */ | |
feea1db2 MR |
1771 | dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status); |
1772 | status |= PI_CONFIG_STAT_0_M_INT_ENB; | |
1773 | dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status); | |
1da177e4 | 1774 | |
feea1db2 | 1775 | spin_unlock(&bp->lock); |
1da177e4 LT |
1776 | } |
1777 | ||
feea1db2 MR |
1778 | return IRQ_HANDLED; |
1779 | } | |
1780 | ||
6aa20a22 | 1781 | |
1da177e4 LT |
1782 | /* |
1783 | * ===================== | |
1784 | * = dfx_ctl_get_stats = | |
1785 | * ===================== | |
6aa20a22 | 1786 | * |
1da177e4 LT |
1787 | * Overview: |
1788 | * Get statistics for FDDI adapter | |
6aa20a22 | 1789 | * |
1da177e4 LT |
1790 | * Returns: |
1791 | * Pointer to FDDI statistics structure | |
6aa20a22 | 1792 | * |
1da177e4 LT |
1793 | * Arguments: |
1794 | * dev - pointer to device information | |
1795 | * | |
1796 | * Functional Description: | |
1797 | * Gets current MIB objects from adapter, then | |
1798 | * returns FDDI statistics structure as defined | |
1799 | * in if_fddi.h. | |
1800 | * | |
1801 | * Note: Since the FDDI statistics structure is | |
1802 | * still new and the device structure doesn't | |
1803 | * have an FDDI-specific get statistics handler, | |
1804 | * we'll return the FDDI statistics structure as | |
1805 | * a pointer to an Ethernet statistics structure. | |
1806 | * That way, at least the first part of the statistics | |
1807 | * structure can be decoded properly, and it allows | |
1808 | * "smart" applications to perform a second cast to | |
1809 | * decode the FDDI-specific statistics. | |
1810 | * | |
1811 | * We'll have to pay attention to this routine as the | |
1812 | * device structure becomes more mature and LAN media | |
1813 | * independent. | |
1814 | * | |
1815 | * Return Codes: | |
1816 | * None | |
1817 | * | |
1818 | * Assumptions: | |
1819 | * None | |
1820 | * | |
1821 | * Side Effects: | |
1822 | * None | |
1823 | */ | |
1824 | ||
1825 | static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) | |
1826 | { | |
1827 | DFX_board_t *bp = dev->priv; | |
1828 | ||
1829 | /* Fill the bp->stats structure with driver-maintained counters */ | |
1830 | ||
1831 | bp->stats.gen.rx_packets = bp->rcv_total_frames; | |
1832 | bp->stats.gen.tx_packets = bp->xmt_total_frames; | |
1833 | bp->stats.gen.rx_bytes = bp->rcv_total_bytes; | |
1834 | bp->stats.gen.tx_bytes = bp->xmt_total_bytes; | |
1835 | bp->stats.gen.rx_errors = bp->rcv_crc_errors + | |
1836 | bp->rcv_frame_status_errors + | |
1837 | bp->rcv_length_errors; | |
1838 | bp->stats.gen.tx_errors = bp->xmt_length_errors; | |
1839 | bp->stats.gen.rx_dropped = bp->rcv_discards; | |
1840 | bp->stats.gen.tx_dropped = bp->xmt_discards; | |
1841 | bp->stats.gen.multicast = bp->rcv_multicast_frames; | |
1842 | bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ | |
1843 | ||
1844 | /* Get FDDI SMT MIB objects */ | |
1845 | ||
1846 | bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; | |
1847 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1848 | return((struct net_device_stats *) &bp->stats); | |
1849 | ||
1850 | /* Fill the bp->stats structure with the SMT MIB object values */ | |
1851 | ||
1852 | memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); | |
1853 | bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; | |
1854 | bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; | |
1855 | bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; | |
1856 | memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); | |
1857 | bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; | |
1858 | bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; | |
1859 | bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; | |
1860 | bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; | |
1861 | bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; | |
1862 | bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; | |
1863 | bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; | |
1864 | bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; | |
1865 | bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; | |
1866 | bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; | |
1867 | bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; | |
1868 | bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; | |
1869 | bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; | |
1870 | bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; | |
1871 | bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; | |
1872 | bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; | |
1873 | bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; | |
1874 | bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; | |
1875 | bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; | |
1876 | bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; | |
1877 | bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; | |
1878 | bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; | |
1879 | bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; | |
1880 | bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; | |
1881 | memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); | |
1882 | memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); | |
1883 | memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); | |
1884 | memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); | |
1885 | bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; | |
1886 | bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; | |
1887 | bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; | |
1888 | memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); | |
1889 | bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; | |
1890 | bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; | |
1891 | bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; | |
1892 | bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; | |
1893 | bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; | |
1894 | bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; | |
1895 | bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; | |
1896 | bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; | |
1897 | bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; | |
1898 | bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; | |
1899 | bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; | |
1900 | bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; | |
1901 | bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; | |
1902 | bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; | |
1903 | bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; | |
1904 | bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; | |
1905 | memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); | |
1906 | bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; | |
1907 | bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; | |
1908 | bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; | |
1909 | bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; | |
1910 | bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; | |
1911 | bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; | |
1912 | bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; | |
1913 | bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; | |
1914 | bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; | |
1915 | bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; | |
1916 | memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); | |
1917 | memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); | |
1918 | bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; | |
1919 | bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; | |
1920 | bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; | |
1921 | bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; | |
1922 | bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; | |
1923 | bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; | |
1924 | bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; | |
1925 | bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; | |
1926 | bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; | |
1927 | bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; | |
1928 | bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; | |
1929 | bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; | |
1930 | bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; | |
1931 | bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; | |
1932 | bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; | |
1933 | bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; | |
1934 | bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; | |
1935 | bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; | |
1936 | bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; | |
1937 | bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; | |
1938 | bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; | |
1939 | bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; | |
1940 | bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; | |
1941 | bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; | |
1942 | bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; | |
1943 | bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; | |
1944 | ||
1945 | /* Get FDDI counters */ | |
1946 | ||
1947 | bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; | |
1948 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
1949 | return((struct net_device_stats *) &bp->stats); | |
1950 | ||
1951 | /* Fill the bp->stats structure with the FDDI counter values */ | |
1952 | ||
1953 | bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; | |
1954 | bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; | |
1955 | bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; | |
1956 | bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; | |
1957 | bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; | |
1958 | bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; | |
1959 | bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; | |
1960 | bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; | |
1961 | bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; | |
1962 | bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; | |
1963 | bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; | |
1964 | ||
1965 | return((struct net_device_stats *) &bp->stats); | |
1966 | } | |
1967 | ||
6aa20a22 | 1968 | |
1da177e4 LT |
1969 | /* |
1970 | * ============================== | |
1971 | * = dfx_ctl_set_multicast_list = | |
1972 | * ============================== | |
6aa20a22 | 1973 | * |
1da177e4 LT |
1974 | * Overview: |
1975 | * Enable/Disable LLC frame promiscuous mode reception | |
1976 | * on the adapter and/or update multicast address table. | |
6aa20a22 | 1977 | * |
1da177e4 LT |
1978 | * Returns: |
1979 | * None | |
6aa20a22 | 1980 | * |
1da177e4 LT |
1981 | * Arguments: |
1982 | * dev - pointer to device information | |
1983 | * | |
1984 | * Functional Description: | |
1985 | * This routine follows a fairly simple algorithm for setting the | |
1986 | * adapter filters and CAM: | |
1987 | * | |
1988 | * if IFF_PROMISC flag is set | |
1989 | * enable LLC individual/group promiscuous mode | |
1990 | * else | |
1991 | * disable LLC individual/group promiscuous mode | |
1992 | * if number of incoming multicast addresses > | |
1993 | * (CAM max size - number of unicast addresses in CAM) | |
1994 | * enable LLC group promiscuous mode | |
1995 | * set driver-maintained multicast address count to zero | |
1996 | * else | |
1997 | * disable LLC group promiscuous mode | |
1998 | * set driver-maintained multicast address count to incoming count | |
1999 | * update adapter CAM | |
2000 | * update adapter filters | |
2001 | * | |
2002 | * Return Codes: | |
2003 | * None | |
2004 | * | |
2005 | * Assumptions: | |
2006 | * Multicast addresses are presented in canonical (LSB) format. | |
2007 | * | |
2008 | * Side Effects: | |
2009 | * On-board adapter CAM and filters are updated. | |
2010 | */ | |
2011 | ||
2012 | static void dfx_ctl_set_multicast_list(struct net_device *dev) | |
2013 | { | |
2014 | DFX_board_t *bp = dev->priv; | |
2015 | int i; /* used as index in for loop */ | |
2016 | struct dev_mc_list *dmi; /* ptr to multicast addr entry */ | |
2017 | ||
2018 | /* Enable LLC frame promiscuous mode, if necessary */ | |
2019 | ||
2020 | if (dev->flags & IFF_PROMISC) | |
2021 | bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ | |
2022 | ||
2023 | /* Else, update multicast address table */ | |
2024 | ||
2025 | else | |
2026 | { | |
2027 | bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ | |
2028 | /* | |
2029 | * Check whether incoming multicast address count exceeds table size | |
2030 | * | |
2031 | * Note: The adapters utilize an on-board 64 entry CAM for | |
2032 | * supporting perfect filtering of multicast packets | |
2033 | * and bridge functions when adding unicast addresses. | |
2034 | * There is no hash function available. To support | |
2035 | * additional multicast addresses, the all multicast | |
2036 | * filter (LLC group promiscuous mode) must be enabled. | |
2037 | * | |
2038 | * The firmware reserves two CAM entries for SMT-related | |
2039 | * multicast addresses, which leaves 62 entries available. | |
2040 | * The following code ensures that we're not being asked | |
2041 | * to add more than 62 addresses to the CAM. If we are, | |
2042 | * the driver will enable the all multicast filter. | |
2043 | * Should the number of multicast addresses drop below | |
2044 | * the high water mark, the filter will be disabled and | |
2045 | * perfect filtering will be used. | |
2046 | */ | |
2047 | ||
2048 | if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) | |
2049 | { | |
2050 | bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ | |
2051 | bp->mc_count = 0; /* Don't add mc addrs to CAM */ | |
2052 | } | |
2053 | else | |
2054 | { | |
2055 | bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ | |
2056 | bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */ | |
2057 | } | |
2058 | ||
2059 | /* Copy addresses to multicast address table, then update adapter CAM */ | |
2060 | ||
2061 | dmi = dev->mc_list; /* point to first multicast addr */ | |
2062 | for (i=0; i < bp->mc_count; i++) | |
2063 | { | |
2064 | memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN); | |
2065 | dmi = dmi->next; /* point to next multicast addr */ | |
2066 | } | |
2067 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) | |
2068 | { | |
2069 | DBG_printk("%s: Could not update multicast address table!\n", dev->name); | |
2070 | } | |
2071 | else | |
2072 | { | |
2073 | DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); | |
2074 | } | |
2075 | } | |
2076 | ||
2077 | /* Update adapter filters */ | |
2078 | ||
2079 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
2080 | { | |
2081 | DBG_printk("%s: Could not update adapter filters!\n", dev->name); | |
2082 | } | |
2083 | else | |
2084 | { | |
2085 | DBG_printk("%s: Adapter filters updated!\n", dev->name); | |
2086 | } | |
2087 | } | |
2088 | ||
6aa20a22 | 2089 | |
1da177e4 LT |
2090 | /* |
2091 | * =========================== | |
2092 | * = dfx_ctl_set_mac_address = | |
2093 | * =========================== | |
6aa20a22 | 2094 | * |
1da177e4 LT |
2095 | * Overview: |
2096 | * Add node address override (unicast address) to adapter | |
2097 | * CAM and update dev_addr field in device table. | |
6aa20a22 | 2098 | * |
1da177e4 LT |
2099 | * Returns: |
2100 | * None | |
6aa20a22 | 2101 | * |
1da177e4 LT |
2102 | * Arguments: |
2103 | * dev - pointer to device information | |
2104 | * addr - pointer to sockaddr structure containing unicast address to add | |
2105 | * | |
2106 | * Functional Description: | |
2107 | * The adapter supports node address overrides by adding one or more | |
2108 | * unicast addresses to the adapter CAM. This is similar to adding | |
2109 | * multicast addresses. In this routine we'll update the driver and | |
2110 | * device structures with the new address, then update the adapter CAM | |
2111 | * to ensure that the adapter will copy and strip frames destined and | |
2112 | * sourced by that address. | |
2113 | * | |
2114 | * Return Codes: | |
2115 | * Always returns zero. | |
2116 | * | |
2117 | * Assumptions: | |
2118 | * The address pointed to by addr->sa_data is a valid unicast | |
2119 | * address and is presented in canonical (LSB) format. | |
2120 | * | |
2121 | * Side Effects: | |
2122 | * On-board adapter CAM is updated. On-board adapter filters | |
2123 | * may be updated. | |
2124 | */ | |
2125 | ||
2126 | static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) | |
2127 | { | |
2128 | DFX_board_t *bp = dev->priv; | |
2129 | struct sockaddr *p_sockaddr = (struct sockaddr *)addr; | |
2130 | ||
2131 | /* Copy unicast address to driver-maintained structs and update count */ | |
2132 | ||
2133 | memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ | |
2134 | memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ | |
2135 | bp->uc_count = 1; | |
2136 | ||
2137 | /* | |
2138 | * Verify we're not exceeding the CAM size by adding unicast address | |
2139 | * | |
2140 | * Note: It's possible that before entering this routine we've | |
2141 | * already filled the CAM with 62 multicast addresses. | |
2142 | * Since we need to place the node address override into | |
2143 | * the CAM, we have to check to see that we're not | |
2144 | * exceeding the CAM size. If we are, we have to enable | |
2145 | * the LLC group (multicast) promiscuous mode filter as | |
2146 | * in dfx_ctl_set_multicast_list. | |
2147 | */ | |
2148 | ||
2149 | if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) | |
2150 | { | |
2151 | bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ | |
2152 | bp->mc_count = 0; /* Don't add mc addrs to CAM */ | |
2153 | ||
2154 | /* Update adapter filters */ | |
2155 | ||
2156 | if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) | |
2157 | { | |
2158 | DBG_printk("%s: Could not update adapter filters!\n", dev->name); | |
2159 | } | |
2160 | else | |
2161 | { | |
2162 | DBG_printk("%s: Adapter filters updated!\n", dev->name); | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | /* Update adapter CAM with new unicast address */ | |
2167 | ||
2168 | if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) | |
2169 | { | |
2170 | DBG_printk("%s: Could not set new MAC address!\n", dev->name); | |
2171 | } | |
2172 | else | |
2173 | { | |
2174 | DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); | |
2175 | } | |
2176 | return(0); /* always return zero */ | |
2177 | } | |
2178 | ||
6aa20a22 | 2179 | |
1da177e4 LT |
2180 | /* |
2181 | * ====================== | |
2182 | * = dfx_ctl_update_cam = | |
2183 | * ====================== | |
2184 | * | |
2185 | * Overview: | |
2186 | * Procedure to update adapter CAM (Content Addressable Memory) | |
2187 | * with desired unicast and multicast address entries. | |
2188 | * | |
2189 | * Returns: | |
2190 | * Condition code | |
2191 | * | |
2192 | * Arguments: | |
2193 | * bp - pointer to board information | |
2194 | * | |
2195 | * Functional Description: | |
2196 | * Updates adapter CAM with current contents of board structure | |
2197 | * unicast and multicast address tables. Since there are only 62 | |
2198 | * free entries in CAM, this routine ensures that the command | |
2199 | * request buffer is not overrun. | |
2200 | * | |
2201 | * Return Codes: | |
2202 | * DFX_K_SUCCESS - Request succeeded | |
2203 | * DFX_K_FAILURE - Request failed | |
2204 | * | |
2205 | * Assumptions: | |
2206 | * All addresses being added (unicast and multicast) are in canonical | |
2207 | * order. | |
2208 | * | |
2209 | * Side Effects: | |
2210 | * On-board adapter CAM is updated. | |
2211 | */ | |
2212 | ||
2213 | static int dfx_ctl_update_cam(DFX_board_t *bp) | |
2214 | { | |
2215 | int i; /* used as index */ | |
2216 | PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ | |
2217 | ||
2218 | /* | |
2219 | * Fill in command request information | |
2220 | * | |
2221 | * Note: Even though both the unicast and multicast address | |
2222 | * table entries are stored as contiguous 6 byte entries, | |
2223 | * the firmware address filter set command expects each | |
2224 | * entry to be two longwords (8 bytes total). We must be | |
2225 | * careful to only copy the six bytes of each unicast and | |
2226 | * multicast table entry into each command entry. This | |
2227 | * is also why we must first clear the entire command | |
2228 | * request buffer. | |
2229 | */ | |
2230 | ||
2231 | memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ | |
2232 | bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; | |
2233 | p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; | |
2234 | ||
2235 | /* Now add unicast addresses to command request buffer, if any */ | |
2236 | ||
2237 | for (i=0; i < (int)bp->uc_count; i++) | |
2238 | { | |
2239 | if (i < PI_CMD_ADDR_FILTER_K_SIZE) | |
2240 | { | |
2241 | memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); | |
2242 | p_addr++; /* point to next command entry */ | |
2243 | } | |
2244 | } | |
2245 | ||
2246 | /* Now add multicast addresses to command request buffer, if any */ | |
2247 | ||
2248 | for (i=0; i < (int)bp->mc_count; i++) | |
2249 | { | |
2250 | if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) | |
2251 | { | |
2252 | memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); | |
2253 | p_addr++; /* point to next command entry */ | |
2254 | } | |
2255 | } | |
2256 | ||
2257 | /* Issue command to update adapter CAM, then return */ | |
2258 | ||
2259 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
2260 | return(DFX_K_FAILURE); | |
2261 | return(DFX_K_SUCCESS); | |
2262 | } | |
2263 | ||
6aa20a22 | 2264 | |
1da177e4 LT |
2265 | /* |
2266 | * ========================== | |
2267 | * = dfx_ctl_update_filters = | |
2268 | * ========================== | |
2269 | * | |
2270 | * Overview: | |
2271 | * Procedure to update adapter filters with desired | |
2272 | * filter settings. | |
6aa20a22 | 2273 | * |
1da177e4 LT |
2274 | * Returns: |
2275 | * Condition code | |
6aa20a22 | 2276 | * |
1da177e4 LT |
2277 | * Arguments: |
2278 | * bp - pointer to board information | |
2279 | * | |
2280 | * Functional Description: | |
2281 | * Enables or disables filter using current filter settings. | |
2282 | * | |
2283 | * Return Codes: | |
2284 | * DFX_K_SUCCESS - Request succeeded. | |
2285 | * DFX_K_FAILURE - Request failed. | |
2286 | * | |
2287 | * Assumptions: | |
2288 | * We must always pass up packets destined to the broadcast | |
2289 | * address (FF-FF-FF-FF-FF-FF), so we'll always keep the | |
2290 | * broadcast filter enabled. | |
2291 | * | |
2292 | * Side Effects: | |
2293 | * On-board adapter filters are updated. | |
2294 | */ | |
2295 | ||
2296 | static int dfx_ctl_update_filters(DFX_board_t *bp) | |
2297 | { | |
2298 | int i = 0; /* used as index */ | |
2299 | ||
2300 | /* Fill in command request information */ | |
2301 | ||
2302 | bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; | |
2303 | ||
2304 | /* Initialize Broadcast filter - * ALWAYS ENABLED * */ | |
2305 | ||
2306 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; | |
2307 | bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; | |
2308 | ||
2309 | /* Initialize LLC Individual/Group Promiscuous filter */ | |
2310 | ||
2311 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; | |
2312 | bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; | |
2313 | ||
2314 | /* Initialize LLC Group Promiscuous filter */ | |
2315 | ||
2316 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; | |
2317 | bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; | |
2318 | ||
2319 | /* Terminate the item code list */ | |
2320 | ||
2321 | bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; | |
2322 | ||
2323 | /* Issue command to update adapter filters, then return */ | |
2324 | ||
2325 | if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) | |
2326 | return(DFX_K_FAILURE); | |
2327 | return(DFX_K_SUCCESS); | |
2328 | } | |
2329 | ||
6aa20a22 | 2330 | |
1da177e4 LT |
2331 | /* |
2332 | * ====================== | |
2333 | * = dfx_hw_dma_cmd_req = | |
2334 | * ====================== | |
6aa20a22 | 2335 | * |
1da177e4 LT |
2336 | * Overview: |
2337 | * Sends PDQ DMA command to adapter firmware | |
6aa20a22 | 2338 | * |
1da177e4 LT |
2339 | * Returns: |
2340 | * Condition code | |
6aa20a22 | 2341 | * |
1da177e4 LT |
2342 | * Arguments: |
2343 | * bp - pointer to board information | |
2344 | * | |
2345 | * Functional Description: | |
2346 | * The command request and response buffers are posted to the adapter in the manner | |
2347 | * described in the PDQ Port Specification: | |
2348 | * | |
2349 | * 1. Command Response Buffer is posted to adapter. | |
2350 | * 2. Command Request Buffer is posted to adapter. | |
2351 | * 3. Command Request consumer index is polled until it indicates that request | |
2352 | * buffer has been DMA'd to adapter. | |
2353 | * 4. Command Response consumer index is polled until it indicates that response | |
2354 | * buffer has been DMA'd from adapter. | |
2355 | * | |
2356 | * This ordering ensures that a response buffer is already available for the firmware | |
2357 | * to use once it's done processing the request buffer. | |
2358 | * | |
2359 | * Return Codes: | |
2360 | * DFX_K_SUCCESS - DMA command succeeded | |
2361 | * DFX_K_OUTSTATE - Adapter is NOT in proper state | |
2362 | * DFX_K_HW_TIMEOUT - DMA command timed out | |
2363 | * | |
2364 | * Assumptions: | |
2365 | * Command request buffer has already been filled with desired DMA command. | |
2366 | * | |
2367 | * Side Effects: | |
2368 | * None | |
2369 | */ | |
2370 | ||
2371 | static int dfx_hw_dma_cmd_req(DFX_board_t *bp) | |
2372 | { | |
2373 | int status; /* adapter status */ | |
2374 | int timeout_cnt; /* used in for loops */ | |
6aa20a22 | 2375 | |
1da177e4 | 2376 | /* Make sure the adapter is in a state that we can issue the DMA command in */ |
6aa20a22 | 2377 | |
1da177e4 LT |
2378 | status = dfx_hw_adap_state_rd(bp); |
2379 | if ((status == PI_STATE_K_RESET) || | |
2380 | (status == PI_STATE_K_HALTED) || | |
2381 | (status == PI_STATE_K_DMA_UNAVAIL) || | |
2382 | (status == PI_STATE_K_UPGRADE)) | |
2383 | return(DFX_K_OUTSTATE); | |
2384 | ||
2385 | /* Put response buffer on the command response queue */ | |
2386 | ||
2387 | bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | | |
2388 | ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); | |
2389 | bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; | |
2390 | ||
2391 | /* Bump (and wrap) the producer index and write out to register */ | |
2392 | ||
2393 | bp->cmd_rsp_reg.index.prod += 1; | |
2394 | bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; | |
2395 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); | |
2396 | ||
2397 | /* Put request buffer on the command request queue */ | |
6aa20a22 | 2398 | |
1da177e4 LT |
2399 | bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | |
2400 | PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); | |
2401 | bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; | |
2402 | ||
2403 | /* Bump (and wrap) the producer index and write out to register */ | |
2404 | ||
2405 | bp->cmd_req_reg.index.prod += 1; | |
2406 | bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; | |
2407 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); | |
2408 | ||
2409 | /* | |
2410 | * Here we wait for the command request consumer index to be equal | |
2411 | * to the producer, indicating that the adapter has DMAed the request. | |
2412 | */ | |
2413 | ||
2414 | for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) | |
2415 | { | |
2416 | if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) | |
2417 | break; | |
2418 | udelay(100); /* wait for 100 microseconds */ | |
2419 | } | |
6aa20a22 | 2420 | if (timeout_cnt == 0) |
1da177e4 LT |
2421 | return(DFX_K_HW_TIMEOUT); |
2422 | ||
2423 | /* Bump (and wrap) the completion index and write out to register */ | |
2424 | ||
2425 | bp->cmd_req_reg.index.comp += 1; | |
2426 | bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; | |
2427 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); | |
2428 | ||
2429 | /* | |
2430 | * Here we wait for the command response consumer index to be equal | |
2431 | * to the producer, indicating that the adapter has DMAed the response. | |
2432 | */ | |
2433 | ||
2434 | for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) | |
2435 | { | |
2436 | if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) | |
2437 | break; | |
2438 | udelay(100); /* wait for 100 microseconds */ | |
2439 | } | |
6aa20a22 | 2440 | if (timeout_cnt == 0) |
1da177e4 LT |
2441 | return(DFX_K_HW_TIMEOUT); |
2442 | ||
2443 | /* Bump (and wrap) the completion index and write out to register */ | |
2444 | ||
2445 | bp->cmd_rsp_reg.index.comp += 1; | |
2446 | bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; | |
2447 | dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); | |
2448 | return(DFX_K_SUCCESS); | |
2449 | } | |
2450 | ||
6aa20a22 | 2451 | |
1da177e4 LT |
2452 | /* |
2453 | * ======================== | |
2454 | * = dfx_hw_port_ctrl_req = | |
2455 | * ======================== | |
6aa20a22 | 2456 | * |
1da177e4 LT |
2457 | * Overview: |
2458 | * Sends PDQ port control command to adapter firmware | |
6aa20a22 | 2459 | * |
1da177e4 LT |
2460 | * Returns: |
2461 | * Host data register value in host_data if ptr is not NULL | |
6aa20a22 | 2462 | * |
1da177e4 LT |
2463 | * Arguments: |
2464 | * bp - pointer to board information | |
2465 | * command - port control command | |
2466 | * data_a - port data A register value | |
2467 | * data_b - port data B register value | |
2468 | * host_data - ptr to host data register value | |
2469 | * | |
2470 | * Functional Description: | |
2471 | * Send generic port control command to adapter by writing | |
2472 | * to various PDQ port registers, then polling for completion. | |
2473 | * | |
2474 | * Return Codes: | |
2475 | * DFX_K_SUCCESS - port control command succeeded | |
2476 | * DFX_K_HW_TIMEOUT - port control command timed out | |
2477 | * | |
2478 | * Assumptions: | |
2479 | * None | |
2480 | * | |
2481 | * Side Effects: | |
2482 | * None | |
2483 | */ | |
2484 | ||
2485 | static int dfx_hw_port_ctrl_req( | |
2486 | DFX_board_t *bp, | |
2487 | PI_UINT32 command, | |
2488 | PI_UINT32 data_a, | |
2489 | PI_UINT32 data_b, | |
2490 | PI_UINT32 *host_data | |
2491 | ) | |
2492 | ||
2493 | { | |
2494 | PI_UINT32 port_cmd; /* Port Control command register value */ | |
2495 | int timeout_cnt; /* used in for loops */ | |
2496 | ||
2497 | /* Set Command Error bit in command longword */ | |
6aa20a22 | 2498 | |
1da177e4 LT |
2499 | port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); |
2500 | ||
2501 | /* Issue port command to the adapter */ | |
2502 | ||
2503 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); | |
2504 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); | |
2505 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); | |
2506 | ||
2507 | /* Now wait for command to complete */ | |
2508 | ||
2509 | if (command == PI_PCTRL_M_BLAST_FLASH) | |
2510 | timeout_cnt = 600000; /* set command timeout count to 60 seconds */ | |
2511 | else | |
2512 | timeout_cnt = 20000; /* set command timeout count to 2 seconds */ | |
2513 | ||
2514 | for (; timeout_cnt > 0; timeout_cnt--) | |
2515 | { | |
2516 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); | |
2517 | if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) | |
2518 | break; | |
2519 | udelay(100); /* wait for 100 microseconds */ | |
2520 | } | |
6aa20a22 | 2521 | if (timeout_cnt == 0) |
1da177e4 LT |
2522 | return(DFX_K_HW_TIMEOUT); |
2523 | ||
2524 | /* | |
6aa20a22 JG |
2525 | * If the address of host_data is non-zero, assume caller has supplied a |
2526 | * non NULL pointer, and return the contents of the HOST_DATA register in | |
1da177e4 LT |
2527 | * it. |
2528 | */ | |
2529 | ||
2530 | if (host_data != NULL) | |
2531 | dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); | |
2532 | return(DFX_K_SUCCESS); | |
2533 | } | |
2534 | ||
6aa20a22 | 2535 | |
1da177e4 LT |
2536 | /* |
2537 | * ===================== | |
2538 | * = dfx_hw_adap_reset = | |
2539 | * ===================== | |
6aa20a22 | 2540 | * |
1da177e4 LT |
2541 | * Overview: |
2542 | * Resets adapter | |
6aa20a22 | 2543 | * |
1da177e4 LT |
2544 | * Returns: |
2545 | * None | |
6aa20a22 | 2546 | * |
1da177e4 LT |
2547 | * Arguments: |
2548 | * bp - pointer to board information | |
2549 | * type - type of reset to perform | |
2550 | * | |
2551 | * Functional Description: | |
2552 | * Issue soft reset to adapter by writing to PDQ Port Reset | |
2553 | * register. Use incoming reset type to tell adapter what | |
2554 | * kind of reset operation to perform. | |
2555 | * | |
2556 | * Return Codes: | |
2557 | * None | |
2558 | * | |
2559 | * Assumptions: | |
2560 | * This routine merely issues a soft reset to the adapter. | |
2561 | * It is expected that after this routine returns, the caller | |
2562 | * will appropriately poll the Port Status register for the | |
2563 | * adapter to enter the proper state. | |
2564 | * | |
2565 | * Side Effects: | |
2566 | * Internal adapter registers are cleared. | |
2567 | */ | |
2568 | ||
2569 | static void dfx_hw_adap_reset( | |
2570 | DFX_board_t *bp, | |
2571 | PI_UINT32 type | |
2572 | ) | |
2573 | ||
2574 | { | |
2575 | /* Set Reset type and assert reset */ | |
2576 | ||
2577 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ | |
2578 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); | |
2579 | ||
2580 | /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ | |
2581 | ||
2582 | udelay(20); | |
2583 | ||
2584 | /* Deassert reset */ | |
2585 | ||
2586 | dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); | |
2587 | } | |
2588 | ||
6aa20a22 | 2589 | |
1da177e4 LT |
2590 | /* |
2591 | * ======================== | |
2592 | * = dfx_hw_adap_state_rd = | |
2593 | * ======================== | |
6aa20a22 | 2594 | * |
1da177e4 LT |
2595 | * Overview: |
2596 | * Returns current adapter state | |
6aa20a22 | 2597 | * |
1da177e4 LT |
2598 | * Returns: |
2599 | * Adapter state per PDQ Port Specification | |
6aa20a22 | 2600 | * |
1da177e4 LT |
2601 | * Arguments: |
2602 | * bp - pointer to board information | |
2603 | * | |
2604 | * Functional Description: | |
2605 | * Reads PDQ Port Status register and returns adapter state. | |
2606 | * | |
2607 | * Return Codes: | |
2608 | * None | |
2609 | * | |
2610 | * Assumptions: | |
2611 | * None | |
2612 | * | |
2613 | * Side Effects: | |
2614 | * None | |
2615 | */ | |
2616 | ||
2617 | static int dfx_hw_adap_state_rd(DFX_board_t *bp) | |
2618 | { | |
2619 | PI_UINT32 port_status; /* Port Status register value */ | |
2620 | ||
2621 | dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); | |
2622 | return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE); | |
2623 | } | |
2624 | ||
6aa20a22 | 2625 | |
1da177e4 LT |
2626 | /* |
2627 | * ===================== | |
2628 | * = dfx_hw_dma_uninit = | |
2629 | * ===================== | |
6aa20a22 | 2630 | * |
1da177e4 LT |
2631 | * Overview: |
2632 | * Brings adapter to DMA_UNAVAILABLE state | |
6aa20a22 | 2633 | * |
1da177e4 LT |
2634 | * Returns: |
2635 | * Condition code | |
6aa20a22 | 2636 | * |
1da177e4 LT |
2637 | * Arguments: |
2638 | * bp - pointer to board information | |
2639 | * type - type of reset to perform | |
2640 | * | |
2641 | * Functional Description: | |
2642 | * Bring adapter to DMA_UNAVAILABLE state by performing the following: | |
2643 | * 1. Set reset type bit in Port Data A Register then reset adapter. | |
2644 | * 2. Check that adapter is in DMA_UNAVAILABLE state. | |
2645 | * | |
2646 | * Return Codes: | |
2647 | * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state | |
2648 | * DFX_K_HW_TIMEOUT - adapter did not reset properly | |
2649 | * | |
2650 | * Assumptions: | |
2651 | * None | |
2652 | * | |
2653 | * Side Effects: | |
2654 | * Internal adapter registers are cleared. | |
2655 | */ | |
2656 | ||
2657 | static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) | |
2658 | { | |
2659 | int timeout_cnt; /* used in for loops */ | |
2660 | ||
2661 | /* Set reset type bit and reset adapter */ | |
2662 | ||
2663 | dfx_hw_adap_reset(bp, type); | |
2664 | ||
2665 | /* Now wait for adapter to enter DMA_UNAVAILABLE state */ | |
2666 | ||
2667 | for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) | |
2668 | { | |
2669 | if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) | |
2670 | break; | |
2671 | udelay(100); /* wait for 100 microseconds */ | |
2672 | } | |
6aa20a22 | 2673 | if (timeout_cnt == 0) |
1da177e4 LT |
2674 | return(DFX_K_HW_TIMEOUT); |
2675 | return(DFX_K_SUCCESS); | |
2676 | } | |
6aa20a22 | 2677 | |
1da177e4 LT |
2678 | /* |
2679 | * Align an sk_buff to a boundary power of 2 | |
2680 | * | |
2681 | */ | |
6aa20a22 | 2682 | |
1da177e4 LT |
2683 | static void my_skb_align(struct sk_buff *skb, int n) |
2684 | { | |
2685 | unsigned long x = (unsigned long)skb->data; | |
2686 | unsigned long v; | |
6aa20a22 | 2687 | |
1da177e4 | 2688 | v = ALIGN(x, n); /* Where we want to be */ |
6aa20a22 | 2689 | |
1da177e4 LT |
2690 | skb_reserve(skb, v - x); |
2691 | } | |
2692 | ||
6aa20a22 | 2693 | |
1da177e4 LT |
2694 | /* |
2695 | * ================ | |
2696 | * = dfx_rcv_init = | |
2697 | * ================ | |
6aa20a22 | 2698 | * |
1da177e4 LT |
2699 | * Overview: |
2700 | * Produces buffers to adapter LLC Host receive descriptor block | |
6aa20a22 | 2701 | * |
1da177e4 LT |
2702 | * Returns: |
2703 | * None | |
6aa20a22 | 2704 | * |
1da177e4 LT |
2705 | * Arguments: |
2706 | * bp - pointer to board information | |
2707 | * get_buffers - non-zero if buffers to be allocated | |
2708 | * | |
2709 | * Functional Description: | |
2710 | * This routine can be called during dfx_adap_init() or during an adapter | |
2711 | * reset. It initializes the descriptor block and produces all allocated | |
2712 | * LLC Host queue receive buffers. | |
2713 | * | |
2714 | * Return Codes: | |
2715 | * Return 0 on success or -ENOMEM if buffer allocation failed (when using | |
2716 | * dynamic buffer allocation). If the buffer allocation failed, the | |
2717 | * already allocated buffers will not be released and the caller should do | |
2718 | * this. | |
2719 | * | |
2720 | * Assumptions: | |
2721 | * The PDQ has been reset and the adapter and driver maintained Type 2 | |
2722 | * register indices are cleared. | |
2723 | * | |
2724 | * Side Effects: | |
2725 | * Receive buffers are posted to the adapter LLC queue and the adapter | |
2726 | * is notified. | |
2727 | */ | |
2728 | ||
2729 | static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) | |
2730 | { | |
2731 | int i, j; /* used in for loop */ | |
2732 | ||
2733 | /* | |
2734 | * Since each receive buffer is a single fragment of same length, initialize | |
2735 | * first longword in each receive descriptor for entire LLC Host descriptor | |
2736 | * block. Also initialize second longword in each receive descriptor with | |
2737 | * physical address of receive buffer. We'll always allocate receive | |
2738 | * buffers in powers of 2 so that we can easily fill the 256 entry descriptor | |
2739 | * block and produce new receive buffers by simply updating the receive | |
2740 | * producer index. | |
2741 | * | |
2742 | * Assumptions: | |
2743 | * To support all shipping versions of PDQ, the receive buffer size | |
2744 | * must be mod 128 in length and the physical address must be 128 byte | |
2745 | * aligned. In other words, bits 0-6 of the length and address must | |
2746 | * be zero for the following descriptor field entries to be correct on | |
2747 | * all PDQ-based boards. We guaranteed both requirements during | |
2748 | * driver initialization when we allocated memory for the receive buffers. | |
2749 | */ | |
2750 | ||
2751 | if (get_buffers) { | |
2752 | #ifdef DYNAMIC_BUFFERS | |
2753 | for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) | |
2754 | for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
2755 | { | |
2756 | struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO); | |
2757 | if (!newskb) | |
2758 | return -ENOMEM; | |
2759 | bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | | |
2760 | ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); | |
2761 | /* | |
2762 | * align to 128 bytes for compatibility with | |
2763 | * the old EISA boards. | |
2764 | */ | |
6aa20a22 | 2765 | |
1da177e4 LT |
2766 | my_skb_align(newskb, 128); |
2767 | bp->descr_block_virt->rcv_data[i + j].long_1 = | |
2768 | (u32)pci_map_single(bp->pci_dev, newskb->data, | |
2769 | NEW_SKB_SIZE, | |
2770 | PCI_DMA_FROMDEVICE); | |
2771 | /* | |
2772 | * p_rcv_buff_va is only used inside the | |
2773 | * kernel so we put the skb pointer here. | |
2774 | */ | |
2775 | bp->p_rcv_buff_va[i+j] = (char *) newskb; | |
2776 | } | |
2777 | #else | |
2778 | for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) | |
2779 | for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
2780 | { | |
2781 | bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | | |
2782 | ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); | |
2783 | bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); | |
2784 | bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); | |
2785 | } | |
2786 | #endif | |
2787 | } | |
2788 | ||
2789 | /* Update receive producer and Type 2 register */ | |
2790 | ||
2791 | bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; | |
2792 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
2793 | return 0; | |
2794 | } | |
2795 | ||
6aa20a22 | 2796 | |
1da177e4 LT |
2797 | /* |
2798 | * ========================= | |
2799 | * = dfx_rcv_queue_process = | |
2800 | * ========================= | |
6aa20a22 | 2801 | * |
1da177e4 LT |
2802 | * Overview: |
2803 | * Process received LLC frames. | |
6aa20a22 | 2804 | * |
1da177e4 LT |
2805 | * Returns: |
2806 | * None | |
6aa20a22 | 2807 | * |
1da177e4 LT |
2808 | * Arguments: |
2809 | * bp - pointer to board information | |
2810 | * | |
2811 | * Functional Description: | |
2812 | * Received LLC frames are processed until there are no more consumed frames. | |
2813 | * Once all frames are processed, the receive buffers are returned to the | |
2814 | * adapter. Note that this algorithm fixes the length of time that can be spent | |
2815 | * in this routine, because there are a fixed number of receive buffers to | |
2816 | * process and buffers are not produced until this routine exits and returns | |
2817 | * to the ISR. | |
2818 | * | |
2819 | * Return Codes: | |
2820 | * None | |
2821 | * | |
2822 | * Assumptions: | |
2823 | * None | |
2824 | * | |
2825 | * Side Effects: | |
2826 | * None | |
2827 | */ | |
2828 | ||
2829 | static void dfx_rcv_queue_process( | |
2830 | DFX_board_t *bp | |
2831 | ) | |
2832 | ||
2833 | { | |
2834 | PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ | |
2835 | char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ | |
2836 | u32 descr, pkt_len; /* FMC descriptor field and packet length */ | |
2837 | struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ | |
2838 | ||
2839 | /* Service all consumed LLC receive frames */ | |
2840 | ||
2841 | p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); | |
2842 | while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) | |
2843 | { | |
2844 | /* Process any errors */ | |
2845 | ||
2846 | int entry; | |
2847 | ||
2848 | entry = bp->rcv_xmt_reg.index.rcv_comp; | |
2849 | #ifdef DYNAMIC_BUFFERS | |
2850 | p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); | |
2851 | #else | |
2852 | p_buff = (char *) bp->p_rcv_buff_va[entry]; | |
2853 | #endif | |
2854 | memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); | |
2855 | ||
2856 | if (descr & PI_FMC_DESCR_M_RCC_FLUSH) | |
2857 | { | |
2858 | if (descr & PI_FMC_DESCR_M_RCC_CRC) | |
2859 | bp->rcv_crc_errors++; | |
2860 | else | |
2861 | bp->rcv_frame_status_errors++; | |
2862 | } | |
2863 | else | |
2864 | { | |
2865 | int rx_in_place = 0; | |
2866 | ||
2867 | /* The frame was received without errors - verify packet length */ | |
2868 | ||
2869 | pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); | |
2870 | pkt_len -= 4; /* subtract 4 byte CRC */ | |
2871 | if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) | |
2872 | bp->rcv_length_errors++; | |
2873 | else{ | |
2874 | #ifdef DYNAMIC_BUFFERS | |
2875 | if (pkt_len > SKBUFF_RX_COPYBREAK) { | |
2876 | struct sk_buff *newskb; | |
2877 | ||
2878 | newskb = dev_alloc_skb(NEW_SKB_SIZE); | |
2879 | if (newskb){ | |
2880 | rx_in_place = 1; | |
6aa20a22 | 2881 | |
1da177e4 LT |
2882 | my_skb_align(newskb, 128); |
2883 | skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; | |
2884 | pci_unmap_single(bp->pci_dev, | |
2885 | bp->descr_block_virt->rcv_data[entry].long_1, | |
2886 | NEW_SKB_SIZE, | |
2887 | PCI_DMA_FROMDEVICE); | |
2888 | skb_reserve(skb, RCV_BUFF_K_PADDING); | |
2889 | bp->p_rcv_buff_va[entry] = (char *)newskb; | |
2890 | bp->descr_block_virt->rcv_data[entry].long_1 = | |
2891 | (u32)pci_map_single(bp->pci_dev, | |
2892 | newskb->data, | |
2893 | NEW_SKB_SIZE, | |
2894 | PCI_DMA_FROMDEVICE); | |
2895 | } else | |
2896 | skb = NULL; | |
2897 | } else | |
2898 | #endif | |
2899 | skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ | |
2900 | if (skb == NULL) | |
2901 | { | |
2902 | printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); | |
2903 | bp->rcv_discards++; | |
2904 | break; | |
2905 | } | |
2906 | else { | |
2907 | #ifndef DYNAMIC_BUFFERS | |
2908 | if (! rx_in_place) | |
2909 | #endif | |
2910 | { | |
2911 | /* Receive buffer allocated, pass receive packet up */ | |
2912 | ||
2913 | memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3); | |
2914 | } | |
6aa20a22 | 2915 | |
1da177e4 LT |
2916 | skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ |
2917 | skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ | |
2918 | skb->dev = bp->dev; /* pass up device pointer */ | |
2919 | ||
2920 | skb->protocol = fddi_type_trans(skb, bp->dev); | |
2921 | bp->rcv_total_bytes += skb->len; | |
2922 | netif_rx(skb); | |
2923 | ||
2924 | /* Update the rcv counters */ | |
2925 | bp->dev->last_rx = jiffies; | |
2926 | bp->rcv_total_frames++; | |
2927 | if (*(p_buff + RCV_BUFF_K_DA) & 0x01) | |
2928 | bp->rcv_multicast_frames++; | |
2929 | } | |
2930 | } | |
2931 | } | |
2932 | ||
2933 | /* | |
2934 | * Advance the producer (for recycling) and advance the completion | |
2935 | * (for servicing received frames). Note that it is okay to | |
2936 | * advance the producer without checking that it passes the | |
2937 | * completion index because they are both advanced at the same | |
2938 | * rate. | |
2939 | */ | |
2940 | ||
2941 | bp->rcv_xmt_reg.index.rcv_prod += 1; | |
2942 | bp->rcv_xmt_reg.index.rcv_comp += 1; | |
2943 | } | |
2944 | } | |
2945 | ||
6aa20a22 | 2946 | |
1da177e4 LT |
2947 | /* |
2948 | * ===================== | |
2949 | * = dfx_xmt_queue_pkt = | |
2950 | * ===================== | |
6aa20a22 | 2951 | * |
1da177e4 LT |
2952 | * Overview: |
2953 | * Queues packets for transmission | |
6aa20a22 | 2954 | * |
1da177e4 LT |
2955 | * Returns: |
2956 | * Condition code | |
6aa20a22 | 2957 | * |
1da177e4 LT |
2958 | * Arguments: |
2959 | * skb - pointer to sk_buff to queue for transmission | |
2960 | * dev - pointer to device information | |
2961 | * | |
2962 | * Functional Description: | |
2963 | * Here we assume that an incoming skb transmit request | |
2964 | * is contained in a single physically contiguous buffer | |
2965 | * in which the virtual address of the start of packet | |
2966 | * (skb->data) can be converted to a physical address | |
2967 | * by using pci_map_single(). | |
2968 | * | |
2969 | * Since the adapter architecture requires a three byte | |
2970 | * packet request header to prepend the start of packet, | |
2971 | * we'll write the three byte field immediately prior to | |
2972 | * the FC byte. This assumption is valid because we've | |
2973 | * ensured that dev->hard_header_len includes three pad | |
2974 | * bytes. By posting a single fragment to the adapter, | |
2975 | * we'll reduce the number of descriptor fetches and | |
2976 | * bus traffic needed to send the request. | |
2977 | * | |
2978 | * Also, we can't free the skb until after it's been DMA'd | |
2979 | * out by the adapter, so we'll queue it in the driver and | |
2980 | * return it in dfx_xmt_done. | |
2981 | * | |
2982 | * Return Codes: | |
2983 | * 0 - driver queued packet, link is unavailable, or skbuff was bad | |
2984 | * 1 - caller should requeue the sk_buff for later transmission | |
2985 | * | |
2986 | * Assumptions: | |
2987 | * First and foremost, we assume the incoming skb pointer | |
2988 | * is NOT NULL and is pointing to a valid sk_buff structure. | |
2989 | * | |
2990 | * The outgoing packet is complete, starting with the | |
2991 | * frame control byte including the last byte of data, | |
2992 | * but NOT including the 4 byte CRC. We'll let the | |
2993 | * adapter hardware generate and append the CRC. | |
2994 | * | |
2995 | * The entire packet is stored in one physically | |
2996 | * contiguous buffer which is not cached and whose | |
2997 | * 32-bit physical address can be determined. | |
2998 | * | |
2999 | * It's vital that this routine is NOT reentered for the | |
3000 | * same board and that the OS is not in another section of | |
3001 | * code (eg. dfx_int_common) for the same board on a | |
3002 | * different thread. | |
3003 | * | |
3004 | * Side Effects: | |
3005 | * None | |
3006 | */ | |
3007 | ||
3008 | static int dfx_xmt_queue_pkt( | |
3009 | struct sk_buff *skb, | |
3010 | struct net_device *dev | |
3011 | ) | |
3012 | ||
3013 | { | |
3014 | DFX_board_t *bp = dev->priv; | |
3015 | u8 prod; /* local transmit producer index */ | |
3016 | PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ | |
3017 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
3018 | unsigned long flags; | |
3019 | ||
3020 | netif_stop_queue(dev); | |
6aa20a22 | 3021 | |
1da177e4 LT |
3022 | /* |
3023 | * Verify that incoming transmit request is OK | |
3024 | * | |
3025 | * Note: The packet size check is consistent with other | |
3026 | * Linux device drivers, although the correct packet | |
3027 | * size should be verified before calling the | |
3028 | * transmit routine. | |
3029 | */ | |
3030 | ||
3031 | if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) | |
3032 | { | |
6aa20a22 | 3033 | printk("%s: Invalid packet length - %u bytes\n", |
1da177e4 LT |
3034 | dev->name, skb->len); |
3035 | bp->xmt_length_errors++; /* bump error counter */ | |
3036 | netif_wake_queue(dev); | |
3037 | dev_kfree_skb(skb); | |
3038 | return(0); /* return "success" */ | |
3039 | } | |
3040 | /* | |
3041 | * See if adapter link is available, if not, free buffer | |
3042 | * | |
3043 | * Note: If the link isn't available, free buffer and return 0 | |
3044 | * rather than tell the upper layer to requeue the packet. | |
3045 | * The methodology here is that by the time the link | |
3046 | * becomes available, the packet to be sent will be | |
3047 | * fairly stale. By simply dropping the packet, the | |
3048 | * higher layer protocols will eventually time out | |
3049 | * waiting for response packets which it won't receive. | |
3050 | */ | |
3051 | ||
3052 | if (bp->link_available == PI_K_FALSE) | |
3053 | { | |
3054 | if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ | |
3055 | bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ | |
3056 | else | |
3057 | { | |
3058 | bp->xmt_discards++; /* bump error counter */ | |
3059 | dev_kfree_skb(skb); /* free sk_buff now */ | |
3060 | netif_wake_queue(dev); | |
3061 | return(0); /* return "success" */ | |
3062 | } | |
3063 | } | |
3064 | ||
3065 | spin_lock_irqsave(&bp->lock, flags); | |
6aa20a22 | 3066 | |
1da177e4 LT |
3067 | /* Get the current producer and the next free xmt data descriptor */ |
3068 | ||
3069 | prod = bp->rcv_xmt_reg.index.xmt_prod; | |
3070 | p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); | |
3071 | ||
3072 | /* | |
3073 | * Get pointer to auxiliary queue entry to contain information | |
3074 | * for this packet. | |
3075 | * | |
3076 | * Note: The current xmt producer index will become the | |
3077 | * current xmt completion index when we complete this | |
3078 | * packet later on. So, we'll get the pointer to the | |
3079 | * next auxiliary queue entry now before we bump the | |
3080 | * producer index. | |
3081 | */ | |
3082 | ||
3083 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ | |
3084 | ||
3085 | /* Write the three PRH bytes immediately before the FC byte */ | |
3086 | ||
3087 | skb_push(skb,3); | |
3088 | skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ | |
3089 | skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ | |
3090 | skb->data[2] = DFX_PRH2_BYTE; /* specification */ | |
3091 | ||
3092 | /* | |
3093 | * Write the descriptor with buffer info and bump producer | |
3094 | * | |
3095 | * Note: Since we need to start DMA from the packet request | |
3096 | * header, we'll add 3 bytes to the DMA buffer length, | |
3097 | * and we'll determine the physical address of the | |
3098 | * buffer from the PRH, not skb->data. | |
3099 | * | |
3100 | * Assumptions: | |
3101 | * 1. Packet starts with the frame control (FC) byte | |
3102 | * at skb->data. | |
3103 | * 2. The 4-byte CRC is not appended to the buffer or | |
3104 | * included in the length. | |
3105 | * 3. Packet length (skb->len) is from FC to end of | |
3106 | * data, inclusive. | |
3107 | * 4. The packet length does not exceed the maximum | |
3108 | * FDDI LLC frame length of 4491 bytes. | |
3109 | * 5. The entire packet is contained in a physically | |
3110 | * contiguous, non-cached, locked memory space | |
3111 | * comprised of a single buffer pointed to by | |
3112 | * skb->data. | |
3113 | * 6. The physical address of the start of packet | |
3114 | * can be determined from the virtual address | |
3115 | * by using pci_map_single() and is only 32-bits | |
3116 | * wide. | |
3117 | */ | |
3118 | ||
3119 | p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); | |
3120 | p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data, | |
3121 | skb->len, PCI_DMA_TODEVICE); | |
3122 | ||
3123 | /* | |
3124 | * Verify that descriptor is actually available | |
3125 | * | |
3126 | * Note: If descriptor isn't available, return 1 which tells | |
3127 | * the upper layer to requeue the packet for later | |
3128 | * transmission. | |
3129 | * | |
3130 | * We need to ensure that the producer never reaches the | |
3131 | * completion, except to indicate that the queue is empty. | |
3132 | */ | |
3133 | ||
3134 | if (prod == bp->rcv_xmt_reg.index.xmt_comp) | |
3135 | { | |
3136 | skb_pull(skb,3); | |
3137 | spin_unlock_irqrestore(&bp->lock, flags); | |
3138 | return(1); /* requeue packet for later */ | |
3139 | } | |
3140 | ||
3141 | /* | |
3142 | * Save info for this packet for xmt done indication routine | |
3143 | * | |
3144 | * Normally, we'd save the producer index in the p_xmt_drv_descr | |
3145 | * structure so that we'd have it handy when we complete this | |
3146 | * packet later (in dfx_xmt_done). However, since the current | |
3147 | * transmit architecture guarantees a single fragment for the | |
3148 | * entire packet, we can simply bump the completion index by | |
3149 | * one (1) for each completed packet. | |
3150 | * | |
3151 | * Note: If this assumption changes and we're presented with | |
3152 | * an inconsistent number of transmit fragments for packet | |
3153 | * data, we'll need to modify this code to save the current | |
3154 | * transmit producer index. | |
3155 | */ | |
3156 | ||
3157 | p_xmt_drv_descr->p_skb = skb; | |
3158 | ||
3159 | /* Update Type 2 register */ | |
3160 | ||
3161 | bp->rcv_xmt_reg.index.xmt_prod = prod; | |
3162 | dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); | |
3163 | spin_unlock_irqrestore(&bp->lock, flags); | |
3164 | netif_wake_queue(dev); | |
3165 | return(0); /* packet queued to adapter */ | |
3166 | } | |
3167 | ||
6aa20a22 | 3168 | |
1da177e4 LT |
3169 | /* |
3170 | * ================ | |
3171 | * = dfx_xmt_done = | |
3172 | * ================ | |
6aa20a22 | 3173 | * |
1da177e4 LT |
3174 | * Overview: |
3175 | * Processes all frames that have been transmitted. | |
6aa20a22 | 3176 | * |
1da177e4 LT |
3177 | * Returns: |
3178 | * None | |
6aa20a22 | 3179 | * |
1da177e4 LT |
3180 | * Arguments: |
3181 | * bp - pointer to board information | |
3182 | * | |
3183 | * Functional Description: | |
3184 | * For all consumed transmit descriptors that have not | |
3185 | * yet been completed, we'll free the skb we were holding | |
3186 | * onto using dev_kfree_skb and bump the appropriate | |
3187 | * counters. | |
3188 | * | |
3189 | * Return Codes: | |
3190 | * None | |
3191 | * | |
3192 | * Assumptions: | |
3193 | * The Type 2 register is not updated in this routine. It is | |
3194 | * assumed that it will be updated in the ISR when dfx_xmt_done | |
3195 | * returns. | |
3196 | * | |
3197 | * Side Effects: | |
3198 | * None | |
3199 | */ | |
3200 | ||
3201 | static int dfx_xmt_done(DFX_board_t *bp) | |
3202 | { | |
3203 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
3204 | PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ | |
3205 | u8 comp; /* local transmit completion index */ | |
3206 | int freed = 0; /* buffers freed */ | |
3207 | ||
3208 | /* Service all consumed transmit frames */ | |
3209 | ||
3210 | p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); | |
3211 | while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) | |
3212 | { | |
3213 | /* Get pointer to the transmit driver descriptor block information */ | |
3214 | ||
3215 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); | |
3216 | ||
3217 | /* Increment transmit counters */ | |
3218 | ||
3219 | bp->xmt_total_frames++; | |
3220 | bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; | |
3221 | ||
3222 | /* Return skb to operating system */ | |
3223 | comp = bp->rcv_xmt_reg.index.xmt_comp; | |
3224 | pci_unmap_single(bp->pci_dev, | |
3225 | bp->descr_block_virt->xmt_data[comp].long_1, | |
3226 | p_xmt_drv_descr->p_skb->len, | |
3227 | PCI_DMA_TODEVICE); | |
3228 | dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); | |
3229 | ||
3230 | /* | |
3231 | * Move to start of next packet by updating completion index | |
3232 | * | |
3233 | * Here we assume that a transmit packet request is always | |
3234 | * serviced by posting one fragment. We can therefore | |
3235 | * simplify the completion code by incrementing the | |
3236 | * completion index by one. This code will need to be | |
3237 | * modified if this assumption changes. See comments | |
3238 | * in dfx_xmt_queue_pkt for more details. | |
3239 | */ | |
3240 | ||
3241 | bp->rcv_xmt_reg.index.xmt_comp += 1; | |
3242 | freed++; | |
3243 | } | |
3244 | return freed; | |
3245 | } | |
3246 | ||
6aa20a22 | 3247 | |
1da177e4 LT |
3248 | /* |
3249 | * ================= | |
3250 | * = dfx_rcv_flush = | |
3251 | * ================= | |
6aa20a22 | 3252 | * |
1da177e4 LT |
3253 | * Overview: |
3254 | * Remove all skb's in the receive ring. | |
6aa20a22 | 3255 | * |
1da177e4 LT |
3256 | * Returns: |
3257 | * None | |
6aa20a22 | 3258 | * |
1da177e4 LT |
3259 | * Arguments: |
3260 | * bp - pointer to board information | |
3261 | * | |
3262 | * Functional Description: | |
3263 | * Free's all the dynamically allocated skb's that are | |
3264 | * currently attached to the device receive ring. This | |
3265 | * function is typically only used when the device is | |
3266 | * initialized or reinitialized. | |
3267 | * | |
3268 | * Return Codes: | |
3269 | * None | |
3270 | * | |
3271 | * Side Effects: | |
3272 | * None | |
3273 | */ | |
3274 | #ifdef DYNAMIC_BUFFERS | |
3275 | static void dfx_rcv_flush( DFX_board_t *bp ) | |
3276 | { | |
3277 | int i, j; | |
3278 | ||
3279 | for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) | |
3280 | for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) | |
3281 | { | |
3282 | struct sk_buff *skb; | |
3283 | skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; | |
3284 | if (skb) | |
3285 | dev_kfree_skb(skb); | |
3286 | bp->p_rcv_buff_va[i+j] = NULL; | |
3287 | } | |
3288 | ||
3289 | } | |
3290 | #else | |
3291 | static inline void dfx_rcv_flush( DFX_board_t *bp ) | |
3292 | { | |
3293 | } | |
3294 | #endif /* DYNAMIC_BUFFERS */ | |
3295 | ||
3296 | /* | |
3297 | * ================= | |
3298 | * = dfx_xmt_flush = | |
3299 | * ================= | |
6aa20a22 | 3300 | * |
1da177e4 LT |
3301 | * Overview: |
3302 | * Processes all frames whether they've been transmitted | |
3303 | * or not. | |
6aa20a22 | 3304 | * |
1da177e4 LT |
3305 | * Returns: |
3306 | * None | |
6aa20a22 | 3307 | * |
1da177e4 LT |
3308 | * Arguments: |
3309 | * bp - pointer to board information | |
3310 | * | |
3311 | * Functional Description: | |
3312 | * For all produced transmit descriptors that have not | |
3313 | * yet been completed, we'll free the skb we were holding | |
3314 | * onto using dev_kfree_skb and bump the appropriate | |
3315 | * counters. Of course, it's possible that some of | |
3316 | * these transmit requests actually did go out, but we | |
3317 | * won't make that distinction here. Finally, we'll | |
3318 | * update the consumer index to match the producer. | |
3319 | * | |
3320 | * Return Codes: | |
3321 | * None | |
3322 | * | |
3323 | * Assumptions: | |
3324 | * This routine does NOT update the Type 2 register. It | |
3325 | * is assumed that this routine is being called during a | |
3326 | * transmit flush interrupt, or a shutdown or close routine. | |
3327 | * | |
3328 | * Side Effects: | |
3329 | * None | |
3330 | */ | |
3331 | ||
3332 | static void dfx_xmt_flush( DFX_board_t *bp ) | |
3333 | { | |
3334 | u32 prod_cons; /* rcv/xmt consumer block longword */ | |
3335 | XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ | |
3336 | u8 comp; /* local transmit completion index */ | |
3337 | ||
3338 | /* Flush all outstanding transmit frames */ | |
3339 | ||
3340 | while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) | |
3341 | { | |
3342 | /* Get pointer to the transmit driver descriptor block information */ | |
3343 | ||
3344 | p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); | |
3345 | ||
3346 | /* Return skb to operating system */ | |
3347 | comp = bp->rcv_xmt_reg.index.xmt_comp; | |
3348 | pci_unmap_single(bp->pci_dev, | |
3349 | bp->descr_block_virt->xmt_data[comp].long_1, | |
3350 | p_xmt_drv_descr->p_skb->len, | |
3351 | PCI_DMA_TODEVICE); | |
3352 | dev_kfree_skb(p_xmt_drv_descr->p_skb); | |
3353 | ||
3354 | /* Increment transmit error counter */ | |
3355 | ||
3356 | bp->xmt_discards++; | |
3357 | ||
3358 | /* | |
3359 | * Move to start of next packet by updating completion index | |
3360 | * | |
3361 | * Here we assume that a transmit packet request is always | |
3362 | * serviced by posting one fragment. We can therefore | |
3363 | * simplify the completion code by incrementing the | |
3364 | * completion index by one. This code will need to be | |
3365 | * modified if this assumption changes. See comments | |
3366 | * in dfx_xmt_queue_pkt for more details. | |
3367 | */ | |
3368 | ||
3369 | bp->rcv_xmt_reg.index.xmt_comp += 1; | |
3370 | } | |
3371 | ||
3372 | /* Update the transmit consumer index in the consumer block */ | |
3373 | ||
3374 | prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); | |
3375 | prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); | |
3376 | bp->cons_block_virt->xmt_rcv_data = prod_cons; | |
3377 | } | |
3378 | ||
3379 | static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev) | |
3380 | { | |
3381 | DFX_board_t *bp = dev->priv; | |
3382 | int alloc_size; /* total buffer size used */ | |
3383 | ||
3384 | unregister_netdev(dev); | |
3385 | release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN ); | |
3386 | ||
3387 | alloc_size = sizeof(PI_DESCR_BLOCK) + | |
3388 | PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + | |
3389 | #ifndef DYNAMIC_BUFFERS | |
3390 | (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + | |
3391 | #endif | |
3392 | sizeof(PI_CONSUMER_BLOCK) + | |
3393 | (PI_ALIGN_K_DESC_BLK - 1); | |
3394 | if (bp->kmalloced) | |
3395 | pci_free_consistent(pdev, alloc_size, bp->kmalloced, | |
3396 | bp->kmalloced_dma); | |
3397 | free_netdev(dev); | |
3398 | } | |
3399 | ||
3400 | static void __devexit dfx_remove_one (struct pci_dev *pdev) | |
3401 | { | |
3402 | struct net_device *dev = pci_get_drvdata(pdev); | |
3403 | ||
3404 | dfx_remove_one_pci_or_eisa(pdev, dev); | |
3405 | pci_set_drvdata(pdev, NULL); | |
3406 | } | |
3407 | ||
3408 | static struct pci_device_id dfx_pci_tbl[] = { | |
3409 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, }, | |
3410 | { 0, } | |
3411 | }; | |
3412 | MODULE_DEVICE_TABLE(pci, dfx_pci_tbl); | |
3413 | ||
3414 | static struct pci_driver dfx_driver = { | |
3415 | .name = "defxx", | |
3416 | .probe = dfx_init_one, | |
3417 | .remove = __devexit_p(dfx_remove_one), | |
3418 | .id_table = dfx_pci_tbl, | |
3419 | }; | |
3420 | ||
3421 | static int dfx_have_pci; | |
3422 | static int dfx_have_eisa; | |
3423 | ||
3424 | ||
3425 | static void __exit dfx_eisa_cleanup(void) | |
3426 | { | |
3427 | struct net_device *dev = root_dfx_eisa_dev; | |
3428 | ||
3429 | while (dev) | |
3430 | { | |
3431 | struct net_device *tmp; | |
3432 | DFX_board_t *bp; | |
3433 | ||
3434 | bp = (DFX_board_t*)dev->priv; | |
3435 | tmp = bp->next; | |
3436 | dfx_remove_one_pci_or_eisa(NULL, dev); | |
3437 | dev = tmp; | |
3438 | } | |
3439 | } | |
3440 | ||
3441 | static int __init dfx_init(void) | |
3442 | { | |
3443 | int rc_pci, rc_eisa; | |
3444 | ||
29917620 | 3445 | rc_pci = pci_register_driver(&dfx_driver); |
1da177e4 | 3446 | if (rc_pci >= 0) dfx_have_pci = 1; |
6aa20a22 | 3447 | |
1da177e4 LT |
3448 | rc_eisa = dfx_eisa_init(); |
3449 | if (rc_eisa >= 0) dfx_have_eisa = 1; | |
3450 | ||
6aa20a22 | 3451 | return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci); |
1da177e4 LT |
3452 | } |
3453 | ||
3454 | static void __exit dfx_cleanup(void) | |
3455 | { | |
3456 | if (dfx_have_pci) | |
3457 | pci_unregister_driver(&dfx_driver); | |
3458 | if (dfx_have_eisa) | |
3459 | dfx_eisa_cleanup(); | |
6aa20a22 JG |
3460 | |
3461 | } | |
1da177e4 LT |
3462 | |
3463 | module_init(dfx_init); | |
3464 | module_exit(dfx_cleanup); | |
3465 | MODULE_AUTHOR("Lawrence V. Stefani"); | |
3466 | MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver " | |
3467 | DRV_VERSION " " DRV_RELDATE); | |
3468 | MODULE_LICENSE("GPL"); | |
3469 | ||
6aa20a22 | 3470 | |
1da177e4 LT |
3471 | /* |
3472 | * Local variables: | |
3473 | * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c" | |
3474 | * End: | |
3475 | */ |