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cxgb4: fix TSO descriptors
[linux-2.6-block.git] / drivers / net / cxgb4 / t4fw_api.h
CommitLineData
bbc02c7e
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef _T4FW_INTERFACE_H_
36#define _T4FW_INTERFACE_H_
37
38#define FW_T4VF_SGE_BASE_ADDR 0x0000
39#define FW_T4VF_MPS_BASE_ADDR 0x0100
40#define FW_T4VF_PL_BASE_ADDR 0x0200
41#define FW_T4VF_MBDATA_BASE_ADDR 0x0240
42#define FW_T4VF_CIM_BASE_ADDR 0x0300
43
44enum fw_wr_opcodes {
45 FW_FILTER_WR = 0x02,
46 FW_ULPTX_WR = 0x04,
47 FW_TP_WR = 0x05,
48 FW_ETH_TX_PKT_WR = 0x08,
49 FW_FLOWC_WR = 0x0a,
50 FW_OFLD_TX_DATA_WR = 0x0b,
51 FW_CMD_WR = 0x10,
52 FW_ETH_TX_PKT_VM_WR = 0x11,
53 FW_RI_RES_WR = 0x0c,
54 FW_RI_INIT_WR = 0x0d,
55 FW_RI_RDMA_WRITE_WR = 0x14,
56 FW_RI_SEND_WR = 0x15,
57 FW_RI_RDMA_READ_WR = 0x16,
58 FW_RI_RECV_WR = 0x17,
59 FW_RI_BIND_MW_WR = 0x18,
60 FW_RI_FR_NSMR_WR = 0x19,
61 FW_RI_INV_LSTAG_WR = 0x1a,
62 FW_LASTC2E_WR = 0x40
63};
64
65struct fw_wr_hdr {
66 __be32 hi;
67 __be32 lo;
68};
69
70#define FW_WR_OP(x) ((x) << 24)
71#define FW_WR_ATOMIC(x) ((x) << 23)
72#define FW_WR_FLUSH(x) ((x) << 22)
73#define FW_WR_COMPL(x) ((x) << 21)
81323b74 74#define FW_WR_IMMDLEN_MASK 0xff
bbc02c7e
DM		 75#define FW_WR_IMMDLEN(x) ((x) << 0)
76
77#define FW_WR_EQUIQ (1U << 31)
78#define FW_WR_EQUEQ (1U << 30)
79#define FW_WR_FLOWID(x) ((x) << 8)
80#define FW_WR_LEN16(x) ((x) << 0)
81
82struct fw_ulptx_wr {
83 __be32 op_to_compl;
84 __be32 flowid_len16;
85 u64 cookie;
86};
87
88struct fw_tp_wr {
89 __be32 op_to_immdlen;
90 __be32 flowid_len16;
91 u64 cookie;
92};
93
94struct fw_eth_tx_pkt_wr {
95 __be32 op_immdlen;
96 __be32 equiq_to_len16;
97 __be64 r3;
98};
99
100enum fw_flowc_mnem {
101 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
102 FW_FLOWC_MNEM_CH,
103 FW_FLOWC_MNEM_PORT,
104 FW_FLOWC_MNEM_IQID,
105 FW_FLOWC_MNEM_SNDNXT,
106 FW_FLOWC_MNEM_RCVNXT,
107 FW_FLOWC_MNEM_SNDBUF,
108 FW_FLOWC_MNEM_MSS,
109};
110
111struct fw_flowc_mnemval {
112 u8 mnemonic;
113 u8 r4[3];
114 __be32 val;
115};
116
117struct fw_flowc_wr {
118 __be32 op_to_nparams;
119#define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
120 __be32 flowid_len16;
121 struct fw_flowc_mnemval mnemval[0];
122};
123
124struct fw_ofld_tx_data_wr {
125 __be32 op_to_immdlen;
126 __be32 flowid_len16;
127 __be32 plen;
128 __be32 tunnel_to_proxy;
129#define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
130#define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
131#define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
132#define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
133#define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
134#define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
135#define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
136#define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
137};
138
139struct fw_cmd_wr {
140 __be32 op_dma;
141#define FW_CMD_WR_DMA (1U << 17)
142 __be32 len16_pkd;
143 __be64 cookie_daddr;
144};
145
146struct fw_eth_tx_pkt_vm_wr {
147 __be32 op_immdlen;
148 __be32 equiq_to_len16;
149 __be32 r3[2];
150 u8 ethmacdst[6];
151 u8 ethmacsrc[6];
152 __be16 ethtype;
153 __be16 vlantci;
154};
155
156#define FW_CMD_MAX_TIMEOUT 3000
157
158enum fw_cmd_opcodes {
159 FW_LDST_CMD = 0x01,
160 FW_RESET_CMD = 0x03,
161 FW_HELLO_CMD = 0x04,
162 FW_BYE_CMD = 0x05,
163 FW_INITIALIZE_CMD = 0x06,
164 FW_CAPS_CONFIG_CMD = 0x07,
165 FW_PARAMS_CMD = 0x08,
166 FW_PFVF_CMD = 0x09,
167 FW_IQ_CMD = 0x10,
168 FW_EQ_MNGT_CMD = 0x11,
169 FW_EQ_ETH_CMD = 0x12,
170 FW_EQ_CTRL_CMD = 0x13,
171 FW_EQ_OFLD_CMD = 0x21,
172 FW_VI_CMD = 0x14,
173 FW_VI_MAC_CMD = 0x15,
174 FW_VI_RXMODE_CMD = 0x16,
175 FW_VI_ENABLE_CMD = 0x17,
176 FW_ACL_MAC_CMD = 0x18,
177 FW_ACL_VLAN_CMD = 0x19,
178 FW_VI_STATS_CMD = 0x1a,
179 FW_PORT_CMD = 0x1b,
180 FW_PORT_STATS_CMD = 0x1c,
181 FW_PORT_LB_STATS_CMD = 0x1d,
182 FW_PORT_TRACE_CMD = 0x1e,
183 FW_PORT_TRACE_MMAP_CMD = 0x1f,
184 FW_RSS_IND_TBL_CMD = 0x20,
185 FW_RSS_GLB_CONFIG_CMD = 0x22,
186 FW_RSS_VI_CONFIG_CMD = 0x23,
187 FW_LASTC2E_CMD = 0x40,
188 FW_ERROR_CMD = 0x80,
189 FW_DEBUG_CMD = 0x81,
190};
191
192enum fw_cmd_cap {
193 FW_CMD_CAP_PF = 0x01,
194 FW_CMD_CAP_DMAQ = 0x02,
195 FW_CMD_CAP_PORT = 0x04,
196 FW_CMD_CAP_PORTPROMISC = 0x08,
197 FW_CMD_CAP_PORTSTATS = 0x10,
198 FW_CMD_CAP_VF = 0x80,
199};
200
201/*
202 * Generic command header flit0
203 */
204struct fw_cmd_hdr {
205 __be32 hi;
206 __be32 lo;
207};
208
209#define FW_CMD_OP(x) ((x) << 24)
210#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
211#define FW_CMD_REQUEST (1U << 23)
212#define FW_CMD_READ (1U << 22)
213#define FW_CMD_WRITE (1U << 21)
214#define FW_CMD_EXEC (1U << 20)
215#define FW_CMD_RAMASK(x) ((x) << 20)
216#define FW_CMD_RETVAL(x) ((x) << 8)
217#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
218#define FW_CMD_LEN16(x) ((x) << 0)
219
220enum fw_ldst_addrspc {
221 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
222 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
223 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
224 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
225 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
226 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
227 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
228 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
229 FW_LDST_ADDRSPC_MDIO = 0x0018,
230 FW_LDST_ADDRSPC_MPS = 0x0020,
231 FW_LDST_ADDRSPC_FUNC = 0x0028
232};
233
234enum fw_ldst_mps_fid {
235 FW_LDST_MPS_ATRB,
236 FW_LDST_MPS_RPLC
237};
238
239enum fw_ldst_func_access_ctl {
240 FW_LDST_FUNC_ACC_CTL_VIID,
241 FW_LDST_FUNC_ACC_CTL_FID
242};
243
244enum fw_ldst_func_mod_index {
245 FW_LDST_FUNC_MPS
246};
247
248struct fw_ldst_cmd {
249 __be32 op_to_addrspace;
250#define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
251 __be32 cycles_to_len16;
252 union fw_ldst {
253 struct fw_ldst_addrval {
254 __be32 addr;
255 __be32 val;
256 } addrval;
257 struct fw_ldst_idctxt {
258 __be32 physid;
259 __be32 msg_pkd;
260 __be32 ctxt_data7;
261 __be32 ctxt_data6;
262 __be32 ctxt_data5;
263 __be32 ctxt_data4;
264 __be32 ctxt_data3;
265 __be32 ctxt_data2;
266 __be32 ctxt_data1;
267 __be32 ctxt_data0;
268 } idctxt;
269 struct fw_ldst_mdio {
270 __be16 paddr_mmd;
271 __be16 raddr;
272 __be16 vctl;
273 __be16 rval;
274 } mdio;
275 struct fw_ldst_mps {
276 __be16 fid_ctl;
277 __be16 rplcpf_pkd;
278 __be32 rplc127_96;
279 __be32 rplc95_64;
280 __be32 rplc63_32;
281 __be32 rplc31_0;
282 __be32 atrb;
283 __be16 vlan[16];
284 } mps;
285 struct fw_ldst_func {
286 u8 access_ctl;
287 u8 mod_index;
288 __be16 ctl_id;
289 __be32 offset;
290 __be64 data0;
291 __be64 data1;
292 } func;
293 } u;
294};
295
296#define FW_LDST_CMD_MSG(x) ((x) << 31)
297#define FW_LDST_CMD_PADDR(x) ((x) << 8)
298#define FW_LDST_CMD_MMD(x) ((x) << 0)
299#define FW_LDST_CMD_FID(x) ((x) << 15)
300#define FW_LDST_CMD_CTL(x) ((x) << 0)
301#define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
302
303struct fw_reset_cmd {
304 __be32 op_to_write;
305 __be32 retval_len16;
306 __be32 val;
307 __be32 r3;
308};
309
310struct fw_hello_cmd {
311 __be32 op_to_write;
312 __be32 retval_len16;
313 __be32 err_to_mbasyncnot;
314#define FW_HELLO_CMD_ERR (1U << 31)
315#define FW_HELLO_CMD_INIT (1U << 30)
316#define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
317#define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
318#define FW_HELLO_CMD_MBMASTER(x) ((x) << 24)
319#define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
320 __be32 fwrev;
321};
322
323struct fw_bye_cmd {
324 __be32 op_to_write;
325 __be32 retval_len16;
326 __be64 r3;
327};
328
329struct fw_initialize_cmd {
330 __be32 op_to_write;
331 __be32 retval_len16;
332 __be64 r3;
333};
334
335enum fw_caps_config_hm {
336 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
337 FW_CAPS_CONFIG_HM_PL = 0x00000002,
338 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
339 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
340 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
341 FW_CAPS_CONFIG_HM_TP = 0x00000020,
342 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
343 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
344 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
345 FW_CAPS_CONFIG_HM_MC = 0x00000200,
346 FW_CAPS_CONFIG_HM_LE = 0x00000400,
347 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
348 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
349 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
350 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
351 FW_CAPS_CONFIG_HM_MI = 0x00008000,
352 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
353 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
354 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
355 FW_CAPS_CONFIG_HM_MA = 0x00080000,
356 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
357 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
358 FW_CAPS_CONFIG_HM_UART = 0x00400000,
359 FW_CAPS_CONFIG_HM_SF = 0x00800000,
360};
361
362enum fw_caps_config_nbm {
363 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
364 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
365};
366
367enum fw_caps_config_link {
368 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
369 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
370 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
371};
372
373enum fw_caps_config_switch {
374 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
375 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
376};
377
378enum fw_caps_config_nic {
379 FW_CAPS_CONFIG_NIC = 0x00000001,
380 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
381};
382
383enum fw_caps_config_ofld {
384 FW_CAPS_CONFIG_OFLD = 0x00000001,
385};
386
387enum fw_caps_config_rdma {
388 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
389 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
390};
391
392enum fw_caps_config_iscsi {
393 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
394 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
395 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
396 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
397};
398
399enum fw_caps_config_fcoe {
400 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
401 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
402};
403
404struct fw_caps_config_cmd {
405 __be32 op_to_write;
406 __be32 retval_len16;
407 __be32 r2;
408 __be32 hwmbitmap;
409 __be16 nbmcaps;
410 __be16 linkcaps;
411 __be16 switchcaps;
412 __be16 r3;
413 __be16 niccaps;
414 __be16 ofldcaps;
415 __be16 rdmacaps;
416 __be16 r4;
417 __be16 iscsicaps;
418 __be16 fcoecaps;
419 __be32 r5;
420 __be64 r6;
421};
422
423/*
424 * params command mnemonics
425 */
426enum fw_params_mnem {
427 FW_PARAMS_MNEM_DEV = 1, /* device params */
428 FW_PARAMS_MNEM_PFVF = 2, /* function params */
429 FW_PARAMS_MNEM_REG = 3, /* limited register access */
430 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
431 FW_PARAMS_MNEM_LAST
432};
433
434/*
435 * device parameters
436 */
437enum fw_params_param_dev {
438 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
439 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
440 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
441 * allocated by the device's
442 * Lookup Engine
443 */
444 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
445 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
446 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
447 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
448 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
449 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
450 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
81323b74
CL		 451 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
452 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
453 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
bbc02c7e
DM		 454};
455
456/*
457 * physical and virtual function parameters
458 */
459enum fw_params_param_pfvf {
460 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
461 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
462 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
463 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
464 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
465 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
466 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
467 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
468 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
469 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
470 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
471 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
472 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
473 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
474 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
475 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
476 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
477 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
478 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
479 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
480 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
a0881cab
DM		 481 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
482 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
483 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
484 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
bbc02c7e 485 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
a0881cab
DM		 486 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
487 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
bbc02c7e
DM		 488};
489
490/*
491 * dma queue parameters
492 */
493enum fw_params_param_dmaq {
494 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
495 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
496 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
497 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
498 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
499};
500
501#define FW_PARAMS_MNEM(x) ((x) << 24)
502#define FW_PARAMS_PARAM_X(x) ((x) << 16)
503#define FW_PARAMS_PARAM_Y(x) ((x) << 8)
504#define FW_PARAMS_PARAM_Z(x) ((x) << 0)
505#define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
506#define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
507
508struct fw_params_cmd {
509 __be32 op_to_vfn;
510 __be32 retval_len16;
511 struct fw_params_param {
512 __be32 mnem;
513 __be32 val;
514 } param[7];
515};
516
517#define FW_PARAMS_CMD_PFN(x) ((x) << 8)
518#define FW_PARAMS_CMD_VFN(x) ((x) << 0)
519
520struct fw_pfvf_cmd {
521 __be32 op_to_vfn;
522 __be32 retval_len16;
523 __be32 niqflint_niq;
81323b74 524 __be32 type_to_neq;
bbc02c7e
DM		 525 __be32 tc_to_nexactf;
526 __be32 r_caps_to_nethctrl;
527 __be16 nricq;
528 __be16 nriqp;
529 __be32 r4;
530};
531
532#define FW_PFVF_CMD_PFN(x) ((x) << 8)
533#define FW_PFVF_CMD_VFN(x) ((x) << 0)
534
535#define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
536#define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
537
538#define FW_PFVF_CMD_NIQ(x) ((x) << 0)
539#define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
540
81323b74
CL		 541#define FW_PFVF_CMD_TYPE (1 << 31)
542#define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
543
bbc02c7e 544#define FW_PFVF_CMD_CMASK(x) ((x) << 24)
81323b74
CL		 545#define FW_PFVF_CMD_CMASK_MASK 0xf
546#define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
bbc02c7e
DM		 547
548#define FW_PFVF_CMD_PMASK(x) ((x) << 20)
81323b74
CL		 549#define FW_PFVF_CMD_PMASK_MASK 0xf
550#define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
bbc02c7e
DM		 551
552#define FW_PFVF_CMD_NEQ(x) ((x) << 0)
553#define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
554
555#define FW_PFVF_CMD_TC(x) ((x) << 24)
556#define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
557
558#define FW_PFVF_CMD_NVI(x) ((x) << 16)
559#define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
560
561#define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
562#define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
563
564#define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
565#define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
566
567#define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
568#define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
569
570#define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
571#define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
572
573enum fw_iq_type {
574 FW_IQ_TYPE_FL_INT_CAP,
575 FW_IQ_TYPE_NO_FL_INT_CAP
576};
577
578struct fw_iq_cmd {
579 __be32 op_to_vfn;
580 __be32 alloc_to_len16;
581 __be16 physiqid;
582 __be16 iqid;
583 __be16 fl0id;
584 __be16 fl1id;
585 __be32 type_to_iqandstindex;
586 __be16 iqdroprss_to_iqesize;
587 __be16 iqsize;
588 __be64 iqaddr;
589 __be32 iqns_to_fl0congen;
590 __be16 fl0dcaen_to_fl0cidxfthresh;
591 __be16 fl0size;
592 __be64 fl0addr;
593 __be32 fl1cngchmap_to_fl1congen;
594 __be16 fl1dcaen_to_fl1cidxfthresh;
595 __be16 fl1size;
596 __be64 fl1addr;
597};
598
599#define FW_IQ_CMD_PFN(x) ((x) << 8)
600#define FW_IQ_CMD_VFN(x) ((x) << 0)
601
602#define FW_IQ_CMD_ALLOC (1U << 31)
603#define FW_IQ_CMD_FREE (1U << 30)
604#define FW_IQ_CMD_MODIFY (1U << 29)
605#define FW_IQ_CMD_IQSTART(x) ((x) << 28)
606#define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
607
608#define FW_IQ_CMD_TYPE(x) ((x) << 29)
609#define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
610#define FW_IQ_CMD_VIID(x) ((x) << 16)
611#define FW_IQ_CMD_IQANDST(x) ((x) << 15)
612#define FW_IQ_CMD_IQANUS(x) ((x) << 14)
613#define FW_IQ_CMD_IQANUD(x) ((x) << 12)
614#define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
615
616#define FW_IQ_CMD_IQDROPRSS (1U << 15)
617#define FW_IQ_CMD_IQGTSMODE (1U << 14)
618#define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
619#define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
620#define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
621#define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
622#define FW_IQ_CMD_IQO (1U << 3)
623#define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
624#define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
625
626#define FW_IQ_CMD_IQNS(x) ((x) << 31)
627#define FW_IQ_CMD_IQRO(x) ((x) << 30)
628#define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
629#define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
630#define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
631#define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
632#define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
633#define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
634#define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
635#define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
636#define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
637#define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
638#define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
639#define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
640#define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
641#define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
642#define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
643#define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
644#define FW_IQ_CMD_FL0PADEN (1U << 2)
645#define FW_IQ_CMD_FL0PACKEN (1U << 1)
646#define FW_IQ_CMD_FL0CONGEN (1U << 0)
647
648#define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
649#define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
650#define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
651#define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
652#define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
653#define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
654
655#define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
656#define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
657#define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
658#define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
659#define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
660#define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
661#define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
662#define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
663#define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
664#define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
665#define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
666#define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
667#define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
668#define FW_IQ_CMD_FL1PADEN (1U << 2)
669#define FW_IQ_CMD_FL1PACKEN (1U << 1)
670#define FW_IQ_CMD_FL1CONGEN (1U << 0)
671
672#define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
673#define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
674#define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
675#define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
676#define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
677#define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
678
679struct fw_eq_eth_cmd {
680 __be32 op_to_vfn;
681 __be32 alloc_to_len16;
682 __be32 eqid_pkd;
683 __be32 physeqid_pkd;
684 __be32 fetchszm_to_iqid;
685 __be32 dcaen_to_eqsize;
686 __be64 eqaddr;
687 __be32 viid_pkd;
688 __be32 r8_lo;
689 __be64 r9;
690};
691
692#define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
693#define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
694#define FW_EQ_ETH_CMD_ALLOC (1U << 31)
695#define FW_EQ_ETH_CMD_FREE (1U << 30)
696#define FW_EQ_ETH_CMD_MODIFY (1U << 29)
697#define FW_EQ_ETH_CMD_EQSTART (1U << 28)
698#define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
699
700#define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
701#define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
702#define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
81323b74 703#define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
bbc02c7e
DM		 704
705#define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
706#define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
707#define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
708#define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
709#define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
710#define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
711#define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
712#define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
713#define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
714#define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
715
716#define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
717#define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
718#define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
719#define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
720#define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
721#define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
722#define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
723
724#define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
725
726struct fw_eq_ctrl_cmd {
727 __be32 op_to_vfn;
728 __be32 alloc_to_len16;
729 __be32 cmpliqid_eqid;
730 __be32 physeqid_pkd;
731 __be32 fetchszm_to_iqid;
732 __be32 dcaen_to_eqsize;
733 __be64 eqaddr;
734};
735
736#define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
737#define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
738
739#define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
740#define FW_EQ_CTRL_CMD_FREE (1U << 30)
741#define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
742#define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
743#define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
744
745#define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
746#define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
747#define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
748#define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
749
750#define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
751#define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
752#define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
753#define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
754#define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
755#define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
756#define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
757#define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
758#define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
759#define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
760
761#define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
762#define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
763#define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
764#define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
765#define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
766#define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
767#define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
768
769struct fw_eq_ofld_cmd {
770 __be32 op_to_vfn;
771 __be32 alloc_to_len16;
772 __be32 eqid_pkd;
773 __be32 physeqid_pkd;
774 __be32 fetchszm_to_iqid;
775 __be32 dcaen_to_eqsize;
776 __be64 eqaddr;
777};
778
779#define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
780#define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
781
782#define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
783#define FW_EQ_OFLD_CMD_FREE (1U << 30)
784#define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
785#define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
786#define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
787
788#define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
789#define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
790#define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
791
792#define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
793#define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
794#define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
795#define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
796#define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
797#define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
798#define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
799#define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
800#define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
801#define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
802
803#define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
804#define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
805#define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
806#define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
807#define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
808#define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
809#define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
810
811/*
812 * Macros for VIID parsing:
813 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
814 */
815#define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
816#define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
817#define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
818
819struct fw_vi_cmd {
820 __be32 op_to_vfn;
821 __be32 alloc_to_len16;
a0881cab 822 __be16 type_viid;
bbc02c7e
DM		 823 u8 mac[6];
824 u8 portid_pkd;
825 u8 nmac;
826 u8 nmac0[6];
827 __be16 rsssize_pkd;
828 u8 nmac1[6];
a0881cab 829 __be16 idsiiq_pkd;
bbc02c7e 830 u8 nmac2[6];
a0881cab 831 __be16 idseiq_pkd;
bbc02c7e
DM		 832 u8 nmac3[6];
833 __be64 r9;
834 __be64 r10;
835};
836
837#define FW_VI_CMD_PFN(x) ((x) << 8)
838#define FW_VI_CMD_VFN(x) ((x) << 0)
839#define FW_VI_CMD_ALLOC (1U << 31)
840#define FW_VI_CMD_FREE (1U << 30)
841#define FW_VI_CMD_VIID(x) ((x) << 0)
a0881cab 842#define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
bbc02c7e 843#define FW_VI_CMD_PORTID(x) ((x) << 4)
81323b74 844#define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
bbc02c7e
DM		 845#define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
846
847/* Special VI_MAC command index ids */
848#define FW_VI_MAC_ADD_MAC 0x3FF
849#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
850#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
81323b74 851#define FW_CLS_TCAM_NUM_ENTRIES 336
bbc02c7e
DM		 852
853enum fw_vi_mac_smac {
854 FW_VI_MAC_MPS_TCAM_ENTRY,
855 FW_VI_MAC_MPS_TCAM_ONLY,
856 FW_VI_MAC_SMT_ONLY,
857 FW_VI_MAC_SMT_AND_MPSTCAM
858};
859
860enum fw_vi_mac_result {
861 FW_VI_MAC_R_SUCCESS,
862 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
863 FW_VI_MAC_R_SMAC_FAIL,
864 FW_VI_MAC_R_F_ACL_CHECK
865};
866
867struct fw_vi_mac_cmd {
868 __be32 op_to_viid;
869 __be32 freemacs_to_len16;
870 union fw_vi_mac {
871 struct fw_vi_mac_exact {
872 __be16 valid_to_idx;
873 u8 macaddr[6];
874 } exact[7];
875 struct fw_vi_mac_hash {
876 __be64 hashvec;
877 } hash;
878 } u;
879};
880
881#define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
882#define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
883#define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
884#define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
885#define FW_VI_MAC_CMD_VALID (1U << 15)
886#define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
887#define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
888#define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
889#define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
890#define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
891
892#define FW_RXMODE_MTU_NO_CHG 65535
893
894struct fw_vi_rxmode_cmd {
895 __be32 op_to_viid;
896 __be32 retval_len16;
f8f5aafa 897 __be32 mtu_to_vlanexen;
bbc02c7e
DM		 898 __be32 r4_lo;
899};
900
901#define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
81323b74 902#define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
bbc02c7e
DM		 903#define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
904#define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
905#define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
906#define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
907#define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
908#define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
909#define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
f8f5aafa
DM		 910#define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
911#define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
bbc02c7e
DM		 912
913struct fw_vi_enable_cmd {
914 __be32 op_to_viid;
915 __be32 ien_to_len16;
916 __be16 blinkdur;
917 __be16 r3;
918 __be32 r4;
919};
920
921#define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
922#define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
923#define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
924#define FW_VI_ENABLE_CMD_LED (1U << 29)
925
926/* VI VF stats offset definitions */
927#define VI_VF_NUM_STATS 16
928enum fw_vi_stats_vf_index {
929 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
930 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
931 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
932 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
933 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
934 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
935 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
936 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
937 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
938 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
939 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
940 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
941 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
942 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
943 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
944 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
945};
946
947/* VI PF stats offset definitions */
948#define VI_PF_NUM_STATS 17
949enum fw_vi_stats_pf_index {
950 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
951 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
952 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
953 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
954 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
955 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
956 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
957 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
958 FW_VI_PF_STAT_RX_BYTES_IX,
959 FW_VI_PF_STAT_RX_FRAMES_IX,
960 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
961 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
962 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
963 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
964 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
965 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
966 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
967};
968
969struct fw_vi_stats_cmd {
970 __be32 op_to_viid;
971 __be32 retval_len16;
972 union fw_vi_stats {
973 struct fw_vi_stats_ctl {
974 __be16 nstats_ix;
975 __be16 r6;
976 __be32 r7;
977 __be64 stat0;
978 __be64 stat1;
979 __be64 stat2;
980 __be64 stat3;
981 __be64 stat4;
982 __be64 stat5;
983 } ctl;
984 struct fw_vi_stats_pf {
985 __be64 tx_bcast_bytes;
986 __be64 tx_bcast_frames;
987 __be64 tx_mcast_bytes;
988 __be64 tx_mcast_frames;
989 __be64 tx_ucast_bytes;
990 __be64 tx_ucast_frames;
991 __be64 tx_offload_bytes;
992 __be64 tx_offload_frames;
993 __be64 rx_pf_bytes;
994 __be64 rx_pf_frames;
995 __be64 rx_bcast_bytes;
996 __be64 rx_bcast_frames;
997 __be64 rx_mcast_bytes;
998 __be64 rx_mcast_frames;
999 __be64 rx_ucast_bytes;
1000 __be64 rx_ucast_frames;
1001 __be64 rx_err_frames;
1002 } pf;
1003 struct fw_vi_stats_vf {
1004 __be64 tx_bcast_bytes;
1005 __be64 tx_bcast_frames;
1006 __be64 tx_mcast_bytes;
1007 __be64 tx_mcast_frames;
1008 __be64 tx_ucast_bytes;
1009 __be64 tx_ucast_frames;
1010 __be64 tx_drop_frames;
1011 __be64 tx_offload_bytes;
1012 __be64 tx_offload_frames;
1013 __be64 rx_bcast_bytes;
1014 __be64 rx_bcast_frames;
1015 __be64 rx_mcast_bytes;
1016 __be64 rx_mcast_frames;
1017 __be64 rx_ucast_bytes;
1018 __be64 rx_ucast_frames;
1019 __be64 rx_err_frames;
1020 } vf;
1021 } u;
1022};
1023
1024#define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1025#define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1026#define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1027
1028struct fw_acl_mac_cmd {
1029 __be32 op_to_vfn;
1030 __be32 en_to_len16;
1031 u8 nmac;
1032 u8 r3[7];
1033 __be16 r4;
1034 u8 macaddr0[6];
1035 __be16 r5;
1036 u8 macaddr1[6];
1037 __be16 r6;
1038 u8 macaddr2[6];
1039 __be16 r7;
1040 u8 macaddr3[6];
1041};
1042
1043#define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1044#define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1045#define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1046
1047struct fw_acl_vlan_cmd {
1048 __be32 op_to_vfn;
1049 __be32 en_to_len16;
1050 u8 nvlan;
1051 u8 dropnovlan_fm;
1052 u8 r3_lo[6];
1053 __be16 vlanid[16];
1054};
1055
1056#define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1057#define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1058#define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1059#define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1060#define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1061
1062enum fw_port_cap {
1063 FW_PORT_CAP_SPEED_100M = 0x0001,
1064 FW_PORT_CAP_SPEED_1G = 0x0002,
1065 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1066 FW_PORT_CAP_SPEED_10G = 0x0008,
1067 FW_PORT_CAP_SPEED_40G = 0x0010,
1068 FW_PORT_CAP_SPEED_100G = 0x0020,
1069 FW_PORT_CAP_FC_RX = 0x0040,
1070 FW_PORT_CAP_FC_TX = 0x0080,
1071 FW_PORT_CAP_ANEG = 0x0100,
1072 FW_PORT_CAP_MDI_0 = 0x0200,
1073 FW_PORT_CAP_MDI_1 = 0x0400,
1074 FW_PORT_CAP_BEAN = 0x0800,
1075 FW_PORT_CAP_PMA_LPBK = 0x1000,
1076 FW_PORT_CAP_PCS_LPBK = 0x2000,
1077 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1078 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1079};
1080
1081enum fw_port_mdi {
1082 FW_PORT_MDI_UNCHANGED,
1083 FW_PORT_MDI_AUTO,
1084 FW_PORT_MDI_F_STRAIGHT,
1085 FW_PORT_MDI_F_CROSSOVER
1086};
1087
1088#define FW_PORT_MDI(x) ((x) << 9)
1089
1090enum fw_port_action {
1091 FW_PORT_ACTION_L1_CFG = 0x0001,
1092 FW_PORT_ACTION_L2_CFG = 0x0002,
1093 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1094 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1095 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1096 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1097 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1098 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1099 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1100 FW_PORT_ACTION_L1_LPBK = 0x0021,
1101 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1102 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1103 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1104 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1105 FW_PORT_ACTION_PHY_RESET = 0x0040,
1106 FW_PORT_ACTION_PMA_RESET = 0x0041,
1107 FW_PORT_ACTION_PCS_RESET = 0x0042,
1108 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1109 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1110 FW_PORT_ACTION_AN_RESET = 0x0045
1111};
1112
1113enum fw_port_l2cfg_ctlbf {
1114 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1115 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1116 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1117 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1118 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1119 FW_PORT_L2_CTLBF_TXIPG = 0x20
1120};
1121
1122enum fw_port_dcb_cfg {
1123 FW_PORT_DCB_CFG_PG = 0x01,
1124 FW_PORT_DCB_CFG_PFC = 0x02,
1125 FW_PORT_DCB_CFG_APPL = 0x04
1126};
1127
1128enum fw_port_dcb_cfg_rc {
1129 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1130 FW_PORT_DCB_CFG_ERROR = 0x1
1131};
1132
1133struct fw_port_cmd {
1134 __be32 op_to_portid;
1135 __be32 action_to_len16;
1136 union fw_port {
1137 struct fw_port_l1cfg {
1138 __be32 rcap;
1139 __be32 r;
1140 } l1cfg;
1141 struct fw_port_l2cfg {
1142 __be16 ctlbf_to_ivlan0;
1143 __be16 ivlantype;
1144 __be32 txipg_pkd;
1145 __be16 ovlan0mask;
1146 __be16 ovlan0type;
1147 __be16 ovlan1mask;
1148 __be16 ovlan1type;
1149 __be16 ovlan2mask;
1150 __be16 ovlan2type;
1151 __be16 ovlan3mask;
1152 __be16 ovlan3type;
1153 } l2cfg;
1154 struct fw_port_info {
1155 __be32 lstatus_to_modtype;
1156 __be16 pcap;
1157 __be16 acap;
a0881cab
DM		 1158 __be16 mtu;
1159 __u8 cbllen;
1160 __u8 r9;
1161 __be32 r10;
1162 __be64 r11;
bbc02c7e
DM		 1163 } info;
1164 struct fw_port_ppp {
1165 __be32 pppen_to_ncsich;
1166 __be32 r11;
1167 } ppp;
1168 struct fw_port_dcb {
1169 __be16 cfg;
1170 u8 up_map;
1171 u8 sf_cfgrc;
1172 __be16 prot_ix;
1173 u8 pe7_to_pe0;
1174 u8 numTCPFCs;
1175 __be32 pgid0_to_pgid7;
1176 __be32 numTCs_oui;
1177 u8 pgpc[8];
1178 } dcb;
1179 } u;
1180};
1181
1182#define FW_PORT_CMD_READ (1U << 22)
1183
1184#define FW_PORT_CMD_PORTID(x) ((x) << 0)
1185#define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1186
1187#define FW_PORT_CMD_ACTION(x) ((x) << 16)
81323b74 1188#define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
bbc02c7e
DM		 1189
1190#define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1191#define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1192#define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1193#define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1194#define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1195#define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1196
1197#define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1198
1199#define FW_PORT_CMD_LSTATUS (1U << 31)
1200#define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1201#define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1202#define FW_PORT_CMD_TXPAUSE (1U << 23)
1203#define FW_PORT_CMD_RXPAUSE (1U << 22)
1204#define FW_PORT_CMD_MDIOCAP (1U << 21)
1205#define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1206#define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1207#define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1208#define FW_PORT_CMD_PTYPE_MASK 0x1f
1209#define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1210#define FW_PORT_CMD_MODTYPE_MASK 0x1f
1211#define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1212
1213#define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1214#define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1215#define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1216
1217#define FW_PORT_CMD_CH0(x) ((x) << 20)
1218#define FW_PORT_CMD_CH1(x) ((x) << 16)
1219#define FW_PORT_CMD_CH2(x) ((x) << 12)
1220#define FW_PORT_CMD_CH3(x) ((x) << 8)
1221#define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1222
1223enum fw_port_type {
a0881cab
DM		 1224 FW_PORT_TYPE_FIBER_XFI,
1225 FW_PORT_TYPE_FIBER_XAUI,
bbc02c7e 1226 FW_PORT_TYPE_BT_SGMII,
a0881cab 1227 FW_PORT_TYPE_BT_XFI,
bbc02c7e 1228 FW_PORT_TYPE_BT_XAUI,
a0881cab 1229 FW_PORT_TYPE_KX4,
bbc02c7e 1230 FW_PORT_TYPE_CX4,
a0881cab
DM		 1231 FW_PORT_TYPE_KX,
1232 FW_PORT_TYPE_KR,
1233 FW_PORT_TYPE_SFP,
1234 FW_PORT_TYPE_BP_AP,
bbc02c7e
DM		 1235
1236 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1237};
1238
1239enum fw_port_module_type {
1240 FW_PORT_MOD_TYPE_NA,
1241 FW_PORT_MOD_TYPE_LR,
1242 FW_PORT_MOD_TYPE_SR,
1243 FW_PORT_MOD_TYPE_ER,
a0881cab
DM		 1244 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1245 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1246 FW_PORT_MOD_TYPE_LRM,
bbc02c7e
DM		 1247
1248 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1249};
1250
1251/* port stats */
1252#define FW_NUM_PORT_STATS 50
1253#define FW_NUM_PORT_TX_STATS 23
1254#define FW_NUM_PORT_RX_STATS 27
1255
1256enum fw_port_stats_tx_index {
1257 FW_STAT_TX_PORT_BYTES_IX,
1258 FW_STAT_TX_PORT_FRAMES_IX,
1259 FW_STAT_TX_PORT_BCAST_IX,
1260 FW_STAT_TX_PORT_MCAST_IX,
1261 FW_STAT_TX_PORT_UCAST_IX,
1262 FW_STAT_TX_PORT_ERROR_IX,
1263 FW_STAT_TX_PORT_64B_IX,
1264 FW_STAT_TX_PORT_65B_127B_IX,
1265 FW_STAT_TX_PORT_128B_255B_IX,
1266 FW_STAT_TX_PORT_256B_511B_IX,
1267 FW_STAT_TX_PORT_512B_1023B_IX,
1268 FW_STAT_TX_PORT_1024B_1518B_IX,
1269 FW_STAT_TX_PORT_1519B_MAX_IX,
1270 FW_STAT_TX_PORT_DROP_IX,
1271 FW_STAT_TX_PORT_PAUSE_IX,
1272 FW_STAT_TX_PORT_PPP0_IX,
1273 FW_STAT_TX_PORT_PPP1_IX,
1274 FW_STAT_TX_PORT_PPP2_IX,
1275 FW_STAT_TX_PORT_PPP3_IX,
1276 FW_STAT_TX_PORT_PPP4_IX,
1277 FW_STAT_TX_PORT_PPP5_IX,
1278 FW_STAT_TX_PORT_PPP6_IX,
1279 FW_STAT_TX_PORT_PPP7_IX
1280};
1281
1282enum fw_port_stat_rx_index {
1283 FW_STAT_RX_PORT_BYTES_IX,
1284 FW_STAT_RX_PORT_FRAMES_IX,
1285 FW_STAT_RX_PORT_BCAST_IX,
1286 FW_STAT_RX_PORT_MCAST_IX,
1287 FW_STAT_RX_PORT_UCAST_IX,
1288 FW_STAT_RX_PORT_MTU_ERROR_IX,
1289 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1290 FW_STAT_RX_PORT_CRC_ERROR_IX,
1291 FW_STAT_RX_PORT_LEN_ERROR_IX,
1292 FW_STAT_RX_PORT_SYM_ERROR_IX,
1293 FW_STAT_RX_PORT_64B_IX,
1294 FW_STAT_RX_PORT_65B_127B_IX,
1295 FW_STAT_RX_PORT_128B_255B_IX,
1296 FW_STAT_RX_PORT_256B_511B_IX,
1297 FW_STAT_RX_PORT_512B_1023B_IX,
1298 FW_STAT_RX_PORT_1024B_1518B_IX,
1299 FW_STAT_RX_PORT_1519B_MAX_IX,
1300 FW_STAT_RX_PORT_PAUSE_IX,
1301 FW_STAT_RX_PORT_PPP0_IX,
1302 FW_STAT_RX_PORT_PPP1_IX,
1303 FW_STAT_RX_PORT_PPP2_IX,
1304 FW_STAT_RX_PORT_PPP3_IX,
1305 FW_STAT_RX_PORT_PPP4_IX,
1306 FW_STAT_RX_PORT_PPP5_IX,
1307 FW_STAT_RX_PORT_PPP6_IX,
1308 FW_STAT_RX_PORT_PPP7_IX,
1309 FW_STAT_RX_PORT_LESS_64B_IX
1310};
1311
1312struct fw_port_stats_cmd {
1313 __be32 op_to_portid;
1314 __be32 retval_len16;
1315 union fw_port_stats {
1316 struct fw_port_stats_ctl {
1317 u8 nstats_bg_bm;
1318 u8 tx_ix;
1319 __be16 r6;
1320 __be32 r7;
1321 __be64 stat0;
1322 __be64 stat1;
1323 __be64 stat2;
1324 __be64 stat3;
1325 __be64 stat4;
1326 __be64 stat5;
1327 } ctl;
1328 struct fw_port_stats_all {
1329 __be64 tx_bytes;
1330 __be64 tx_frames;
1331 __be64 tx_bcast;
1332 __be64 tx_mcast;
1333 __be64 tx_ucast;
1334 __be64 tx_error;
1335 __be64 tx_64b;
1336 __be64 tx_65b_127b;
1337 __be64 tx_128b_255b;
1338 __be64 tx_256b_511b;
1339 __be64 tx_512b_1023b;
1340 __be64 tx_1024b_1518b;
1341 __be64 tx_1519b_max;
1342 __be64 tx_drop;
1343 __be64 tx_pause;
1344 __be64 tx_ppp0;
1345 __be64 tx_ppp1;
1346 __be64 tx_ppp2;
1347 __be64 tx_ppp3;
1348 __be64 tx_ppp4;
1349 __be64 tx_ppp5;
1350 __be64 tx_ppp6;
1351 __be64 tx_ppp7;
1352 __be64 rx_bytes;
1353 __be64 rx_frames;
1354 __be64 rx_bcast;
1355 __be64 rx_mcast;
1356 __be64 rx_ucast;
1357 __be64 rx_mtu_error;
1358 __be64 rx_mtu_crc_error;
1359 __be64 rx_crc_error;
1360 __be64 rx_len_error;
1361 __be64 rx_sym_error;
1362 __be64 rx_64b;
1363 __be64 rx_65b_127b;
1364 __be64 rx_128b_255b;
1365 __be64 rx_256b_511b;
1366 __be64 rx_512b_1023b;
1367 __be64 rx_1024b_1518b;
1368 __be64 rx_1519b_max;
1369 __be64 rx_pause;
1370 __be64 rx_ppp0;
1371 __be64 rx_ppp1;
1372 __be64 rx_ppp2;
1373 __be64 rx_ppp3;
1374 __be64 rx_ppp4;
1375 __be64 rx_ppp5;
1376 __be64 rx_ppp6;
1377 __be64 rx_ppp7;
1378 __be64 rx_less_64b;
1379 __be64 rx_bg_drop;
1380 __be64 rx_bg_trunc;
1381 } all;
1382 } u;
1383};
1384
1385#define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1386#define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1387#define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1388#define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1389
1390/* port loopback stats */
1391#define FW_NUM_LB_STATS 16
1392enum fw_port_lb_stats_index {
1393 FW_STAT_LB_PORT_BYTES_IX,
1394 FW_STAT_LB_PORT_FRAMES_IX,
1395 FW_STAT_LB_PORT_BCAST_IX,
1396 FW_STAT_LB_PORT_MCAST_IX,
1397 FW_STAT_LB_PORT_UCAST_IX,
1398 FW_STAT_LB_PORT_ERROR_IX,
1399 FW_STAT_LB_PORT_64B_IX,
1400 FW_STAT_LB_PORT_65B_127B_IX,
1401 FW_STAT_LB_PORT_128B_255B_IX,
1402 FW_STAT_LB_PORT_256B_511B_IX,
1403 FW_STAT_LB_PORT_512B_1023B_IX,
1404 FW_STAT_LB_PORT_1024B_1518B_IX,
1405 FW_STAT_LB_PORT_1519B_MAX_IX,
1406 FW_STAT_LB_PORT_DROP_FRAMES_IX
1407};
1408
1409struct fw_port_lb_stats_cmd {
1410 __be32 op_to_lbport;
1411 __be32 retval_len16;
1412 union fw_port_lb_stats {
1413 struct fw_port_lb_stats_ctl {
1414 u8 nstats_bg_bm;
1415 u8 ix_pkd;
1416 __be16 r6;
1417 __be32 r7;
1418 __be64 stat0;
1419 __be64 stat1;
1420 __be64 stat2;
1421 __be64 stat3;
1422 __be64 stat4;
1423 __be64 stat5;
1424 } ctl;
1425 struct fw_port_lb_stats_all {
1426 __be64 tx_bytes;
1427 __be64 tx_frames;
1428 __be64 tx_bcast;
1429 __be64 tx_mcast;
1430 __be64 tx_ucast;
1431 __be64 tx_error;
1432 __be64 tx_64b;
1433 __be64 tx_65b_127b;
1434 __be64 tx_128b_255b;
1435 __be64 tx_256b_511b;
1436 __be64 tx_512b_1023b;
1437 __be64 tx_1024b_1518b;
1438 __be64 tx_1519b_max;
1439 __be64 rx_lb_drop;
1440 __be64 rx_lb_trunc;
1441 } all;
1442 } u;
1443};
1444
1445#define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1446#define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1447#define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1448#define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1449
1450struct fw_rss_ind_tbl_cmd {
1451 __be32 op_to_viid;
1452#define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1453 __be32 retval_len16;
1454 __be16 niqid;
1455 __be16 startidx;
1456 __be32 r3;
1457 __be32 iq0_to_iq2;
1458#define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1459#define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1460#define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1461 __be32 iq3_to_iq5;
1462 __be32 iq6_to_iq8;
1463 __be32 iq9_to_iq11;
1464 __be32 iq12_to_iq14;
1465 __be32 iq15_to_iq17;
1466 __be32 iq18_to_iq20;
1467 __be32 iq21_to_iq23;
1468 __be32 iq24_to_iq26;
1469 __be32 iq27_to_iq29;
1470 __be32 iq30_iq31;
1471 __be32 r15_lo;
1472};
1473
1474struct fw_rss_glb_config_cmd {
1475 __be32 op_to_write;
1476 __be32 retval_len16;
1477 union fw_rss_glb_config {
1478 struct fw_rss_glb_config_manual {
1479 __be32 mode_pkd;
1480 __be32 r3;
1481 __be64 r4;
1482 __be64 r5;
1483 } manual;
1484 struct fw_rss_glb_config_basicvirtual {
1485 __be32 mode_pkd;
1486 __be32 synmapen_to_hashtoeplitz;
1487#define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
1488#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
1489#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
1490#define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
1491#define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
1492#define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
1493#define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
1494#define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
1495#define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
1496 __be64 r8;
1497 __be64 r9;
1498 } basicvirtual;
1499 } u;
1500};
1501
1502#define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
81323b74 1503#define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
bbc02c7e
DM		 1504
1505#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
1506#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
1507
1508struct fw_rss_vi_config_cmd {
1509 __be32 op_to_viid;
1510#define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
1511 __be32 retval_len16;
1512 union fw_rss_vi_config {
1513 struct fw_rss_vi_config_manual {
1514 __be64 r3;
1515 __be64 r4;
1516 __be64 r5;
1517 } manual;
1518 struct fw_rss_vi_config_basicvirtual {
1519 __be32 r6;
81323b74 1520 __be32 defaultq_to_udpen;
bbc02c7e 1521#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
81323b74 1522#define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
bbc02c7e
DM		 1523#define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
1524#define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
1525#define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
1526#define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
81323b74 1527#define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
bbc02c7e
DM		 1528 __be64 r9;
1529 __be64 r10;
1530 } basicvirtual;
1531 } u;
1532};
1533
1534enum fw_error_type {
1535 FW_ERROR_TYPE_EXCEPTION = 0x0,
1536 FW_ERROR_TYPE_HWMODULE = 0x1,
1537 FW_ERROR_TYPE_WR = 0x2,
1538 FW_ERROR_TYPE_ACL = 0x3,
1539};
1540
1541struct fw_error_cmd {
1542 __be32 op_to_type;
1543 __be32 len16_pkd;
1544 union fw_error {
1545 struct fw_error_exception {
1546 __be32 info[6];
1547 } exception;
1548 struct fw_error_hwmodule {
1549 __be32 regaddr;
1550 __be32 regval;
1551 } hwmodule;
1552 struct fw_error_wr {
1553 __be16 cidx;
1554 __be16 pfn_vfn;
1555 __be32 eqid;
1556 u8 wrhdr[16];
1557 } wr;
1558 struct fw_error_acl {
1559 __be16 cidx;
1560 __be16 pfn_vfn;
1561 __be32 eqid;
1562 __be16 mv_pkd;
1563 u8 val[6];
1564 __be64 r4;
1565 } acl;
1566 } u;
1567};
1568
1569struct fw_debug_cmd {
1570 __be32 op_type;
1571#define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
1572 __be32 len16_pkd;
1573 union fw_debug {
1574 struct fw_debug_assert {
1575 __be32 fcid;
1576 __be32 line;
1577 __be32 x;
1578 __be32 y;
1579 u8 filename_0_7[8];
1580 u8 filename_8_15[8];
1581 __be64 r3;
1582 } assert;
1583 struct fw_debug_prt {
1584 __be16 dprtstridx;
1585 __be16 r3[3];
1586 __be32 dprtstrparam0;
1587 __be32 dprtstrparam1;
1588 __be32 dprtstrparam2;
1589 __be32 dprtstrparam3;
1590 } prt;
1591 } u;
1592};
1593
1594struct fw_hdr {
1595 u8 ver;
1596 u8 reserved1;
1597 __be16 len512; /* bin length in units of 512-bytes */
1598 __be32 fw_ver; /* firmware version */
1599 __be32 tp_microcode_ver;
1600 u8 intfver_nic;
1601 u8 intfver_vnic;
1602 u8 intfver_ofld;
1603 u8 intfver_ri;
1604 u8 intfver_iscsipdu;
1605 u8 intfver_iscsi;
1606 u8 intfver_fcoe;
1607 u8 reserved2;
1608 __be32 reserved3[27];
1609};
1610
1611#define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
1612#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
1613#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
1614#define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
1615#endif /* _T4FW_INTERFACE_H_ */
Linux 6.x block layer and io_uring tree(s)