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Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / drivers / net / cxgb4 / cxgb4.h
CommitLineData
625ba2c2
DM		 1/*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CXGB4_H__
36#define __CXGB4_H__
37
38#include <linux/bitops.h>
39#include <linux/cache.h>
40#include <linux/interrupt.h>
41#include <linux/list.h>
42#include <linux/netdevice.h>
43#include <linux/pci.h>
44#include <linux/spinlock.h>
45#include <linux/timer.h>
46#include <asm/io.h>
47#include "cxgb4_uld.h"
48#include "t4_hw.h"
49
50#define FW_VERSION_MAJOR 1
51#define FW_VERSION_MINOR 1
52#define FW_VERSION_MICRO 0
53
54enum {
55 MAX_NPORTS = 4, /* max # of ports */
47d54d65 56 SERNUM_LEN = 24, /* Serial # length */
625ba2c2
DM		 57 EC_LEN = 16, /* E/C length */
58 ID_LEN = 16, /* ID length */
59};
60
61enum {
62 MEM_EDC0,
63 MEM_EDC1,
64 MEM_MC
65};
66
67enum dev_master {
68 MASTER_CANT,
69 MASTER_MAY,
70 MASTER_MUST
71};
72
73enum dev_state {
74 DEV_STATE_UNINIT,
75 DEV_STATE_INIT,
76 DEV_STATE_ERR
77};
78
79enum {
80 PAUSE_RX = 1 << 0,
81 PAUSE_TX = 1 << 1,
82 PAUSE_AUTONEG = 1 << 2
83};
84
85struct port_stats {
86 u64 tx_octets; /* total # of octets in good frames */
87 u64 tx_frames; /* all good frames */
88 u64 tx_bcast_frames; /* all broadcast frames */
89 u64 tx_mcast_frames; /* all multicast frames */
90 u64 tx_ucast_frames; /* all unicast frames */
91 u64 tx_error_frames; /* all error frames */
92
93 u64 tx_frames_64; /* # of Tx frames in a particular range */
94 u64 tx_frames_65_127;
95 u64 tx_frames_128_255;
96 u64 tx_frames_256_511;
97 u64 tx_frames_512_1023;
98 u64 tx_frames_1024_1518;
99 u64 tx_frames_1519_max;
100
101 u64 tx_drop; /* # of dropped Tx frames */
102 u64 tx_pause; /* # of transmitted pause frames */
103 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
104 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
105 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
106 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
107 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
108 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
109 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
110 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
111
112 u64 rx_octets; /* total # of octets in good frames */
113 u64 rx_frames; /* all good frames */
114 u64 rx_bcast_frames; /* all broadcast frames */
115 u64 rx_mcast_frames; /* all multicast frames */
116 u64 rx_ucast_frames; /* all unicast frames */
117 u64 rx_too_long; /* # of frames exceeding MTU */
118 u64 rx_jabber; /* # of jabber frames */
119 u64 rx_fcs_err; /* # of received frames with bad FCS */
120 u64 rx_len_err; /* # of received frames with length error */
121 u64 rx_symbol_err; /* symbol errors */
122 u64 rx_runt; /* # of short frames */
123
124 u64 rx_frames_64; /* # of Rx frames in a particular range */
125 u64 rx_frames_65_127;
126 u64 rx_frames_128_255;
127 u64 rx_frames_256_511;
128 u64 rx_frames_512_1023;
129 u64 rx_frames_1024_1518;
130 u64 rx_frames_1519_max;
131
132 u64 rx_pause; /* # of received pause frames */
133 u64 rx_ppp0; /* # of received PPP prio 0 frames */
134 u64 rx_ppp1; /* # of received PPP prio 1 frames */
135 u64 rx_ppp2; /* # of received PPP prio 2 frames */
136 u64 rx_ppp3; /* # of received PPP prio 3 frames */
137 u64 rx_ppp4; /* # of received PPP prio 4 frames */
138 u64 rx_ppp5; /* # of received PPP prio 5 frames */
139 u64 rx_ppp6; /* # of received PPP prio 6 frames */
140 u64 rx_ppp7; /* # of received PPP prio 7 frames */
141
142 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
143 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
144 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
145 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
146 u64 rx_trunc0; /* buffer-group 0 truncated packets */
147 u64 rx_trunc1; /* buffer-group 1 truncated packets */
148 u64 rx_trunc2; /* buffer-group 2 truncated packets */
149 u64 rx_trunc3; /* buffer-group 3 truncated packets */
150};
151
152struct lb_port_stats {
153 u64 octets;
154 u64 frames;
155 u64 bcast_frames;
156 u64 mcast_frames;
157 u64 ucast_frames;
158 u64 error_frames;
159
160 u64 frames_64;
161 u64 frames_65_127;
162 u64 frames_128_255;
163 u64 frames_256_511;
164 u64 frames_512_1023;
165 u64 frames_1024_1518;
166 u64 frames_1519_max;
167
168 u64 drop;
169
170 u64 ovflow0;
171 u64 ovflow1;
172 u64 ovflow2;
173 u64 ovflow3;
174 u64 trunc0;
175 u64 trunc1;
176 u64 trunc2;
177 u64 trunc3;
178};
179
180struct tp_tcp_stats {
181 u32 tcpOutRsts;
182 u64 tcpInSegs;
183 u64 tcpOutSegs;
184 u64 tcpRetransSegs;
185};
186
187struct tp_err_stats {
188 u32 macInErrs[4];
189 u32 hdrInErrs[4];
190 u32 tcpInErrs[4];
191 u32 tnlCongDrops[4];
192 u32 ofldChanDrops[4];
193 u32 tnlTxDrops[4];
194 u32 ofldVlanDrops[4];
195 u32 tcp6InErrs[4];
196 u32 ofldNoNeigh;
197 u32 ofldCongDefer;
198};
199
200struct tp_params {
201 unsigned int ntxchan; /* # of Tx channels */
202 unsigned int tre; /* log2 of core clocks per TP tick */
203};
204
205struct vpd_params {
206 unsigned int cclk;
207 u8 ec[EC_LEN + 1];
208 u8 sn[SERNUM_LEN + 1];
209 u8 id[ID_LEN + 1];
210};
211
212struct pci_params {
213 unsigned char speed;
214 unsigned char width;
215};
216
217struct adapter_params {
218 struct tp_params tp;
219 struct vpd_params vpd;
220 struct pci_params pci;
221
900a6596
DM		 222 unsigned int sf_size; /* serial flash size in bytes */
223 unsigned int sf_nsec; /* # of flash sectors */
224 unsigned int sf_fw_start; /* start of FW image in flash */
225
625ba2c2
DM		 226 unsigned int fw_vers;
227 unsigned int tp_vers;
228 u8 api_vers[7];
229
230 unsigned short mtus[NMTUS];
231 unsigned short a_wnd[NCCTRL_WIN];
232 unsigned short b_wnd[NCCTRL_WIN];
233
234 unsigned char nports; /* # of ethernet ports */
235 unsigned char portvec;
236 unsigned char rev; /* chip revision */
237 unsigned char offload;
238
239 unsigned int ofldq_wr_cred;
240};
241
242struct trace_params {
243 u32 data[TRACE_LEN / 4];
244 u32 mask[TRACE_LEN / 4];
245 unsigned short snap_len;
246 unsigned short min_len;
247 unsigned char skip_ofst;
248 unsigned char skip_len;
249 unsigned char invert;
250 unsigned char port;
251};
252
253struct link_config {
254 unsigned short supported; /* link capabilities */
255 unsigned short advertising; /* advertised capabilities */
256 unsigned short requested_speed; /* speed user has requested */
257 unsigned short speed; /* actual link speed */
258 unsigned char requested_fc; /* flow control user has requested */
259 unsigned char fc; /* actual link flow control */
260 unsigned char autoneg; /* autonegotiating? */
261 unsigned char link_ok; /* link up? */
262};
263
264#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
265
266enum {
267 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
268 MAX_OFLD_QSETS = 16, /* # of offload Tx/Rx queue sets */
269 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
270 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
271};
272
273enum {
274 MAX_EGRQ = 128, /* max # of egress queues, including FLs */
275 MAX_INGQ = 64 /* max # of interrupt-capable ingress queues */
276};
277
278struct adapter;
279struct vlan_group;
280struct sge_rspq;
281
282struct port_info {
283 struct adapter *adapter;
625ba2c2
DM		 284 u16 viid;
285 s16 xact_addr_filt; /* index of exact MAC address filter */
286 u16 rss_size; /* size of VI's RSS table slice */
287 s8 mdio_addr;
288 u8 port_type;
289 u8 mod_type;
290 u8 port_id;
291 u8 tx_chan;
292 u8 lport; /* associated offload logical port */
293 u8 rx_offload; /* CSO, etc */
294 u8 nqsets; /* # of qsets */
295 u8 first_qset; /* index of first qset */
f796564a 296 u8 rss_mode;
625ba2c2 297 struct link_config link_cfg;
671b0060 298 u16 *rss;
625ba2c2
DM		 299};
300
301/* port_info.rx_offload flags */
302enum {
303 RX_CSO = 1 << 0,
304};
305
306struct dentry;
307struct work_struct;
308
309enum { /* adapter flags */
310 FULL_INIT_DONE = (1 << 0),
311 USING_MSI = (1 << 1),
312 USING_MSIX = (1 << 2),
625ba2c2
DM		 313 FW_OK = (1 << 4),
314};
315
316struct rx_sw_desc;
317
318struct sge_fl { /* SGE free-buffer queue state */
319 unsigned int avail; /* # of available Rx buffers */
320 unsigned int pend_cred; /* new buffers since last FL DB ring */
321 unsigned int cidx; /* consumer index */
322 unsigned int pidx; /* producer index */
323 unsigned long alloc_failed; /* # of times buffer allocation failed */
324 unsigned long large_alloc_failed;
325 unsigned long starving;
326 /* RO fields */
327 unsigned int cntxt_id; /* SGE context id for the free list */
328 unsigned int size; /* capacity of free list */
329 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
330 __be64 *desc; /* address of HW Rx descriptor ring */
331 dma_addr_t addr; /* bus address of HW ring start */
332};
333
334/* A packet gather list */
335struct pkt_gl {
336 skb_frag_t frags[MAX_SKB_FRAGS];
337 void *va; /* virtual address of first byte */
338 unsigned int nfrags; /* # of fragments */
339 unsigned int tot_len; /* total length of fragments */
340};
341
342typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
343 const struct pkt_gl *gl);
344
345struct sge_rspq { /* state for an SGE response queue */
346 struct napi_struct napi;
347 const __be64 *cur_desc; /* current descriptor in queue */
348 unsigned int cidx; /* consumer index */
349 u8 gen; /* current generation bit */
350 u8 intr_params; /* interrupt holdoff parameters */
351 u8 next_intr_params; /* holdoff params for next interrupt */
352 u8 pktcnt_idx; /* interrupt packet threshold */
353 u8 uld; /* ULD handling this queue */
354 u8 idx; /* queue index within its group */
355 int offset; /* offset into current Rx buffer */
356 u16 cntxt_id; /* SGE context id for the response q */
357 u16 abs_id; /* absolute SGE id for the response q */
358 __be64 *desc; /* address of HW response ring */
359 dma_addr_t phys_addr; /* physical address of the ring */
360 unsigned int iqe_len; /* entry size */
361 unsigned int size; /* capacity of response queue */
362 struct adapter *adap;
363 struct net_device *netdev; /* associated net device */
364 rspq_handler_t handler;
365};
366
367struct sge_eth_stats { /* Ethernet queue statistics */
368 unsigned long pkts; /* # of ethernet packets */
369 unsigned long lro_pkts; /* # of LRO super packets */
370 unsigned long lro_merged; /* # of wire packets merged by LRO */
371 unsigned long rx_cso; /* # of Rx checksum offloads */
372 unsigned long vlan_ex; /* # of Rx VLAN extractions */
373 unsigned long rx_drops; /* # of packets dropped due to no mem */
374};
375
376struct sge_eth_rxq { /* SW Ethernet Rx queue */
377 struct sge_rspq rspq;
378 struct sge_fl fl;
379 struct sge_eth_stats stats;
380} ____cacheline_aligned_in_smp;
381
382struct sge_ofld_stats { /* offload queue statistics */
383 unsigned long pkts; /* # of packets */
384 unsigned long imm; /* # of immediate-data packets */
385 unsigned long an; /* # of asynchronous notifications */
386 unsigned long nomem; /* # of responses deferred due to no mem */
387};
388
389struct sge_ofld_rxq { /* SW offload Rx queue */
390 struct sge_rspq rspq;
391 struct sge_fl fl;
392 struct sge_ofld_stats stats;
393} ____cacheline_aligned_in_smp;
394
395struct tx_desc {
396 __be64 flit[8];
397};
398
399struct tx_sw_desc;
400
401struct sge_txq {
402 unsigned int in_use; /* # of in-use Tx descriptors */
403 unsigned int size; /* # of descriptors */
404 unsigned int cidx; /* SW consumer index */
405 unsigned int pidx; /* producer index */
406 unsigned long stops; /* # of times q has been stopped */
407 unsigned long restarts; /* # of queue restarts */
408 unsigned int cntxt_id; /* SGE context id for the Tx q */
409 struct tx_desc *desc; /* address of HW Tx descriptor ring */
410 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
411 struct sge_qstat *stat; /* queue status entry */
412 dma_addr_t phys_addr; /* physical address of the ring */
413};
414
415struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
416 struct sge_txq q;
417 struct netdev_queue *txq; /* associated netdev TX queue */
418 unsigned long tso; /* # of TSO requests */
419 unsigned long tx_cso; /* # of Tx checksum offloads */
420 unsigned long vlan_ins; /* # of Tx VLAN insertions */
421 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
422} ____cacheline_aligned_in_smp;
423
424struct sge_ofld_txq { /* state for an SGE offload Tx queue */
425 struct sge_txq q;
426 struct adapter *adap;
427 struct sk_buff_head sendq; /* list of backpressured packets */
428 struct tasklet_struct qresume_tsk; /* restarts the queue */
429 u8 full; /* the Tx ring is full */
430 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
431} ____cacheline_aligned_in_smp;
432
433struct sge_ctrl_txq { /* state for an SGE control Tx queue */
434 struct sge_txq q;
435 struct adapter *adap;
436 struct sk_buff_head sendq; /* list of backpressured packets */
437 struct tasklet_struct qresume_tsk; /* restarts the queue */
438 u8 full; /* the Tx ring is full */
439} ____cacheline_aligned_in_smp;
440
441struct sge {
442 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
443 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
444 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
445
446 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
447 struct sge_ofld_rxq ofldrxq[MAX_OFLD_QSETS];
448 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
449 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
450
451 struct sge_rspq intrq ____cacheline_aligned_in_smp;
452 spinlock_t intrq_lock;
453
454 u16 max_ethqsets; /* # of available Ethernet queue sets */
455 u16 ethqsets; /* # of active Ethernet queue sets */
456 u16 ethtxq_rover; /* Tx queue to clean up next */
457 u16 ofldqsets; /* # of active offload queue sets */
458 u16 rdmaqs; /* # of available RDMA Rx queues */
459 u16 ofld_rxq[MAX_OFLD_QSETS];
460 u16 rdma_rxq[NCHAN];
461 u16 timer_val[SGE_NTIMERS];
462 u8 counter_val[SGE_NCOUNTERS];
463 unsigned int starve_thres;
464 u8 idma_state[2];
e46dab4d
DM		 465 unsigned int egr_start;
466 unsigned int ingr_start;
625ba2c2
DM		 467 void *egr_map[MAX_EGRQ]; /* qid->queue egress queue map */
468 struct sge_rspq *ingr_map[MAX_INGQ]; /* qid->queue ingress queue map */
469 DECLARE_BITMAP(starving_fl, MAX_EGRQ);
470 DECLARE_BITMAP(txq_maperr, MAX_EGRQ);
471 struct timer_list rx_timer; /* refills starving FLs */
472 struct timer_list tx_timer; /* checks Tx queues */
473};
474
475#define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
476#define for_each_ofldrxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
477#define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
478
479struct l2t_data;
480
481struct adapter {
482 void __iomem *regs;
483 struct pci_dev *pdev;
484 struct device *pdev_dev;
060e0c75
DM		 485 unsigned int fn;
486 unsigned int flags;
625ba2c2 487
625ba2c2
DM		 488 int msg_enable;
489
490 struct adapter_params params;
491 struct cxgb4_virt_res vres;
492 unsigned int swintr;
493
494 unsigned int wol;
495
496 struct {
497 unsigned short vec;
8cd18ac4 498 char desc[IFNAMSIZ + 10];
625ba2c2
DM		 499 } msix_info[MAX_INGQ + 1];
500
501 struct sge sge;
502
503 struct net_device *port[MAX_NPORTS];
504 u8 chan_map[NCHAN]; /* channel -> port map */
505
506 struct l2t_data *l2t;
507 void *uld_handle[CXGB4_ULD_MAX];
508 struct list_head list_node;
509
510 struct tid_info tids;
511 void **tid_release_head;
512 spinlock_t tid_release_lock;
513 struct work_struct tid_release_task;
514 bool tid_release_task_busy;
515
516 struct dentry *debugfs_root;
517
518 spinlock_t stats_lock;
519};
520
521static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
522{
523 return readl(adap->regs + reg_addr);
524}
525
526static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
527{
528 writel(val, adap->regs + reg_addr);
529}
530
531#ifndef readq
532static inline u64 readq(const volatile void __iomem *addr)
533{
534 return readl(addr) + ((u64)readl(addr + 4) << 32);
535}
536
537static inline void writeq(u64 val, volatile void __iomem *addr)
538{
539 writel(val, addr);
540 writel(val >> 32, addr + 4);
541}
542#endif
543
544static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
545{
546 return readq(adap->regs + reg_addr);
547}
548
549static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
550{
551 writeq(val, adap->regs + reg_addr);
552}
553
554/**
555 * netdev2pinfo - return the port_info structure associated with a net_device
556 * @dev: the netdev
557 *
558 * Return the struct port_info associated with a net_device
559 */
560static inline struct port_info *netdev2pinfo(const struct net_device *dev)
561{
562 return netdev_priv(dev);
563}
564
565/**
566 * adap2pinfo - return the port_info of a port
567 * @adap: the adapter
568 * @idx: the port index
569 *
570 * Return the port_info structure for the port of the given index.
571 */
572static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
573{
574 return netdev_priv(adap->port[idx]);
575}
576
577/**
578 * netdev2adap - return the adapter structure associated with a net_device
579 * @dev: the netdev
580 *
581 * Return the struct adapter associated with a net_device
582 */
583static inline struct adapter *netdev2adap(const struct net_device *dev)
584{
585 return netdev2pinfo(dev)->adapter;
586}
587
588void t4_os_portmod_changed(const struct adapter *adap, int port_id);
589void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
590
591void *t4_alloc_mem(size_t size);
625ba2c2
DM		 592
593void t4_free_sge_resources(struct adapter *adap);
594irq_handler_t t4_intr_handler(struct adapter *adap);
595netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
596int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
597 const struct pkt_gl *gl);
598int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
599int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
600int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
601 struct net_device *dev, int intr_idx,
602 struct sge_fl *fl, rspq_handler_t hnd);
603int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
604 struct net_device *dev, struct netdev_queue *netdevq,
605 unsigned int iqid);
606int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
607 struct net_device *dev, unsigned int iqid,
608 unsigned int cmplqid);
609int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
610 struct net_device *dev, unsigned int iqid);
611irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
612void t4_sge_init(struct adapter *adap);
613void t4_sge_start(struct adapter *adap);
614void t4_sge_stop(struct adapter *adap);
615
616#define for_each_port(adapter, iter) \
617 for (iter = 0; iter < (adapter)->params.nports; ++iter)
618
619static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
620{
621 return adap->params.vpd.cclk / 1000;
622}
623
624static inline unsigned int us_to_core_ticks(const struct adapter *adap,
625 unsigned int us)
626{
627 return (us * adap->params.vpd.cclk) / 1000;
628}
629
630void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
631 u32 val);
632
633int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
634 void *rpl, bool sleep_ok);
635
636static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
637 int size, void *rpl)
638{
639 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
640}
641
642static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
643 int size, void *rpl)
644{
645 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
646}
647
648void t4_intr_enable(struct adapter *adapter);
649void t4_intr_disable(struct adapter *adapter);
625ba2c2
DM		 650int t4_slow_intr_handler(struct adapter *adapter);
651
204dc3c0 652int t4_wait_dev_ready(struct adapter *adap);
625ba2c2
DM		 653int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
654 struct link_config *lc);
655int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
656int t4_seeprom_wp(struct adapter *adapter, bool enable);
625ba2c2
DM		 657int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
658int t4_check_fw_version(struct adapter *adapter);
659int t4_prep_adapter(struct adapter *adapter);
660int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
661void t4_fatal_err(struct adapter *adapter);
625ba2c2
DM		 662int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
663 int start, int n, const u16 *rspq, unsigned int nrspq);
664int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
665 unsigned int flags);
625ba2c2
DM		 666int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity);
667int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
668 u64 *parity);
669
670void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
625ba2c2 671void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
625ba2c2
DM		 672void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
673 struct tp_tcp_stats *v6);
674void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
675 const unsigned short *alpha, const unsigned short *beta);
676
677void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
678 const u8 *addr);
679int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
680 u64 mask0, u64 mask1, unsigned int crc, bool enable);
681
682int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
683 enum dev_master master, enum dev_state *state);
684int t4_fw_bye(struct adapter *adap, unsigned int mbox);
685int t4_early_init(struct adapter *adap, unsigned int mbox);
686int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
687int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
688 unsigned int vf, unsigned int nparams, const u32 *params,
689 u32 *val);
690int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
691 unsigned int vf, unsigned int nparams, const u32 *params,
692 const u32 *val);
693int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
694 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
695 unsigned int rxqi, unsigned int rxq, unsigned int tc,
696 unsigned int vi, unsigned int cmask, unsigned int pmask,
697 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
698int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
699 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
700 unsigned int *rss_size);
625ba2c2 701int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
f8f5aafa
DM		 702 int mtu, int promisc, int all_multi, int bcast, int vlanex,
703 bool sleep_ok);
625ba2c2
DM		 704int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
705 unsigned int viid, bool free, unsigned int naddr,
706 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
707int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
708 int idx, const u8 *addr, bool persist, bool add_smt);
709int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
710 bool ucast, u64 vec, bool sleep_ok);
711int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
712 bool rx_en, bool tx_en);
713int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
714 unsigned int nblinks);
715int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
716 unsigned int mmd, unsigned int reg, u16 *valp);
717int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
718 unsigned int mmd, unsigned int reg, u16 val);
625ba2c2
DM		 719int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
720 unsigned int vf, unsigned int iqtype, unsigned int iqid,
721 unsigned int fl0id, unsigned int fl1id);
722int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
723 unsigned int vf, unsigned int eqid);
724int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
725 unsigned int vf, unsigned int eqid);
726int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
727 unsigned int vf, unsigned int eqid);
728int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
729#endif /* __CXGB4_H__ */
Linux 6.x block layer and io_uring tree(s)