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chelsio: sparse warning fixes (old cxgb2)
[linux-2.6-block.git] / drivers / net / cxgb3 / xgmac.c
CommitLineData
4d22de3e 1/*
1d68e93d 2 * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include "common.h"
33#include "regs.h"
34
35/*
36 * # of exact address filters. The first one is used for the station address,
37 * the rest are available for multicast addresses.
38 */
39#define EXACT_ADDR_FILTERS 8
40
41static inline int macidx(const struct cmac *mac)
42{
43 return mac->offset / (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR);
44}
45
46static void xaui_serdes_reset(struct cmac *mac)
47{
48 static const unsigned int clear[] = {
49 F_PWRDN0 | F_PWRDN1, F_RESETPLL01, F_RESET0 | F_RESET1,
50 F_PWRDN2 | F_PWRDN3, F_RESETPLL23, F_RESET2 | F_RESET3
51 };
52
53 int i;
54 struct adapter *adap = mac->adapter;
55 u32 ctrl = A_XGM_SERDES_CTRL0 + mac->offset;
56
57 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
58 F_RESET3 | F_RESET2 | F_RESET1 | F_RESET0 |
59 F_PWRDN3 | F_PWRDN2 | F_PWRDN1 | F_PWRDN0 |
60 F_RESETPLL23 | F_RESETPLL01);
61 t3_read_reg(adap, ctrl);
62 udelay(15);
63
64 for (i = 0; i < ARRAY_SIZE(clear); i++) {
65 t3_set_reg_field(adap, ctrl, clear[i], 0);
66 udelay(15);
67 }
68}
69
70void t3b_pcs_reset(struct cmac *mac)
71{
72 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
73 F_PCS_RESET_, 0);
74 udelay(20);
75 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset, 0,
76 F_PCS_RESET_);
77}
78
79int t3_mac_reset(struct cmac *mac)
80{
81 static const struct addr_val_pair mac_reset_avp[] = {
82 {A_XGM_TX_CTRL, 0},
83 {A_XGM_RX_CTRL, 0},
84 {A_XGM_RX_CFG, F_DISPAUSEFRAMES | F_EN1536BFRAMES |
85 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST},
86 {A_XGM_RX_HASH_LOW, 0},
87 {A_XGM_RX_HASH_HIGH, 0},
88 {A_XGM_RX_EXACT_MATCH_LOW_1, 0},
89 {A_XGM_RX_EXACT_MATCH_LOW_2, 0},
90 {A_XGM_RX_EXACT_MATCH_LOW_3, 0},
91 {A_XGM_RX_EXACT_MATCH_LOW_4, 0},
92 {A_XGM_RX_EXACT_MATCH_LOW_5, 0},
93 {A_XGM_RX_EXACT_MATCH_LOW_6, 0},
94 {A_XGM_RX_EXACT_MATCH_LOW_7, 0},
95 {A_XGM_RX_EXACT_MATCH_LOW_8, 0},
96 {A_XGM_STAT_CTRL, F_CLRSTATS}
97 };
98 u32 val;
99 struct adapter *adap = mac->adapter;
100 unsigned int oft = mac->offset;
101
102 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
104
105 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
106 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
107 F_RXSTRFRWRD | F_DISERRFRAMES,
108 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
109
110 if (uses_xaui(adap)) {
111 if (adap->params.rev == 0) {
112 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
113 F_RXENABLE | F_TXENABLE);
114 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
115 F_CMULOCK, 1, 5, 2)) {
116 CH_ERR(adap,
117 "MAC %d XAUI SERDES CMU lock failed\n",
118 macidx(mac));
119 return -1;
120 }
121 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
122 F_SERDESRESET_);
123 } else
124 xaui_serdes_reset(mac);
125 }
126
4d22de3e
DLR		 127 val = F_MAC_RESET_;
128 if (is_10G(adap))
129 val |= F_PCS_RESET_;
130 else if (uses_xaui(adap))
131 val |= F_PCS_RESET_ | F_XG2G_RESET_;
132 else
133 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
134 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
135 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
136 if ((val & F_PCS_RESET_) && adap->params.rev) {
137 msleep(1);
138 t3b_pcs_reset(mac);
139 }
140
141 memset(&mac->stats, 0, sizeof(mac->stats));
142 return 0;
143}
144
fc90664e
DLR		 145int t3b2_mac_reset(struct cmac *mac)
146{
147 struct adapter *adap = mac->adapter;
148 unsigned int oft = mac->offset;
149 u32 val;
150
151 if (!macidx(mac))
152 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
153 else
154 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
155
156 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
157 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
158
159 msleep(10);
160
161 /* Check for xgm Rx fifo empty */
162 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
163 0x80000000, 1, 5, 2)) {
164 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
165 macidx(mac));
166 return -1;
167 }
168
169 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0);
170 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
171
172 val = F_MAC_RESET_;
173 if (is_10G(adap))
174 val |= F_PCS_RESET_;
175 else if (uses_xaui(adap))
176 val |= F_PCS_RESET_ | F_XG2G_RESET_;
177 else
178 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
179 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
180 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
181 if ((val & F_PCS_RESET_) && adap->params.rev) {
182 msleep(1);
183 t3b_pcs_reset(mac);
184 }
185 t3_write_reg(adap, A_XGM_RX_CFG + oft,
186 F_DISPAUSEFRAMES | F_EN1536BFRAMES |
187 F_RMFCS | F_ENJUMBO | F_ENHASHMCAST);
188
189 if (!macidx(mac))
190 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
191 else
192 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
193
194 return 0;
195}
196
4d22de3e
DLR		 197/*
198 * Set the exact match register 'idx' to recognize the given Ethernet address.
199 */
200static void set_addr_filter(struct cmac *mac, int idx, const u8 * addr)
201{
202 u32 addr_lo, addr_hi;
203 unsigned int oft = mac->offset + idx * 8;
204
205 addr_lo = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
206 addr_hi = (addr[5] << 8) | addr[4];
207
208 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
209 t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
210}
211
212/* Set one of the station's unicast MAC addresses. */
213int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6])
214{
215 if (idx >= mac->nucast)
216 return -EINVAL;
217 set_addr_filter(mac, idx, addr);
218 return 0;
219}
220
221/*
222 * Specify the number of exact address filters that should be reserved for
223 * unicast addresses. Caller should reload the unicast and multicast addresses
224 * after calling this.
225 */
226int t3_mac_set_num_ucast(struct cmac *mac, int n)
227{
228 if (n > EXACT_ADDR_FILTERS)
229 return -EINVAL;
230 mac->nucast = n;
231 return 0;
232}
233
7b581a0f
DLR		 234static void disable_exact_filters(struct cmac *mac)
235{
236 unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_LOW_1;
237
238 for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {
239 u32 v = t3_read_reg(mac->adapter, reg);
240 t3_write_reg(mac->adapter, reg, v);
241 }
242 t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
243}
244
245static void enable_exact_filters(struct cmac *mac)
246{
247 unsigned int i, reg = mac->offset + A_XGM_RX_EXACT_MATCH_HIGH_1;
248
249 for (i = 0; i < EXACT_ADDR_FILTERS; i++, reg += 8) {
250 u32 v = t3_read_reg(mac->adapter, reg);
251 t3_write_reg(mac->adapter, reg, v);
252 }
253 t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
254}
255
4d22de3e
DLR		 256/* Calculate the RX hash filter index of an Ethernet address */
257static int hash_hw_addr(const u8 * addr)
258{
259 int hash = 0, octet, bit, i = 0, c;
260
261 for (octet = 0; octet < 6; ++octet)
262 for (c = addr[octet], bit = 0; bit < 8; c >>= 1, ++bit) {
263 hash ^= (c & 1) << i;
264 if (++i == 6)
265 i = 0;
266 }
267 return hash;
268}
269
270int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm)
271{
272 u32 val, hash_lo, hash_hi;
273 struct adapter *adap = mac->adapter;
274 unsigned int oft = mac->offset;
275
276 val = t3_read_reg(adap, A_XGM_RX_CFG + oft) & ~F_COPYALLFRAMES;
277 if (rm->dev->flags & IFF_PROMISC)
278 val |= F_COPYALLFRAMES;
279 t3_write_reg(adap, A_XGM_RX_CFG + oft, val);
280
281 if (rm->dev->flags & IFF_ALLMULTI)
282 hash_lo = hash_hi = 0xffffffff;
283 else {
284 u8 *addr;
285 int exact_addr_idx = mac->nucast;
286
287 hash_lo = hash_hi = 0;
288 while ((addr = t3_get_next_mcaddr(rm)))
289 if (exact_addr_idx < EXACT_ADDR_FILTERS)
290 set_addr_filter(mac, exact_addr_idx++, addr);
291 else {
292 int hash = hash_hw_addr(addr);
293
294 if (hash < 32)
295 hash_lo |= (1 << hash);
296 else
297 hash_hi |= (1 << (hash - 32));
298 }
299 }
300
301 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
302 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
303 return 0;
304}
305
7b581a0f
DLR		 306static int rx_fifo_hwm(int mtu)
307{
308 int hwm;
309
310 hwm = max(MAC_RXFIFO_SIZE - 3 * mtu, (MAC_RXFIFO_SIZE * 38) / 100);
311 return min(hwm, MAC_RXFIFO_SIZE - 8192);
312}
313
4d22de3e
DLR		 314int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
315{
316 int hwm, lwm;
317 unsigned int thres, v;
318 struct adapter *adap = mac->adapter;
319
320 /*
321 * MAX_FRAME_SIZE inludes header + FCS, mtu doesn't. The HW max
322 * packet size register includes header, but not FCS.
323 */
324 mtu += 14;
325 if (mtu > MAX_FRAME_SIZE - 4)
326 return -EINVAL;
327 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
328
329 /*
330 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
331 * HWM only if flow-control is enabled.
332 */
fc90664e
DLR		 333 hwm = max_t(unsigned int, MAC_RXFIFO_SIZE - 3 * mtu,
334 MAC_RXFIFO_SIZE * 38 / 100);
335 hwm = min(hwm, MAC_RXFIFO_SIZE - 8192);
336 lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
337
7b581a0f
DLR		 338 if (adap->params.rev == T3_REV_B2 &&
339 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
340 disable_exact_filters(mac);
549f8009
DLR		 341 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
342 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
7b581a0f
DLR		 343 F_ENHASHMCAST | F_COPYALLFRAMES, F_DISBCAST);
344
345 /* drain rx FIFO */
346 if (t3_wait_op_done(adap,
347 A_XGM_RX_MAX_PKT_SIZE_ERR_CNT +
348 mac->offset,
349 1 << 31, 1, 20, 5)) {
549f8009 350 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
7b581a0f
DLR		 351 enable_exact_filters(mac);
352 return -EIO;
353 }
354 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
549f8009 355 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
7b581a0f
DLR		 356 enable_exact_filters(mac);
357 } else
358 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
359
360 /*
361 * Adjust the PAUSE frame watermarks. We always set the LWM, and the
362 * HWM only if flow-control is enabled.
363 */
364 hwm = rx_fifo_hwm(mtu);
365 lwm = min(3 * (int)mtu, MAC_RXFIFO_SIZE / 4);
549f8009 366 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
4d22de3e
DLR		 367 v &= ~V_RXFIFOPAUSELWM(M_RXFIFOPAUSELWM);
368 v |= V_RXFIFOPAUSELWM(lwm / 8);
369 if (G_RXFIFOPAUSEHWM(v))
370 v = (v & ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM)) |
371 V_RXFIFOPAUSEHWM(hwm / 8);
7b581a0f 372
4d22de3e
DLR		 373 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
374
375 /* Adjust the TX FIFO threshold based on the MTU */
376 thres = (adap->params.vpd.cclk * 1000) / 15625;
377 thres = (thres * mtu) / 1000;
378 if (is_10G(adap))
379 thres /= 10;
380 thres = mtu > thres ? (mtu - thres + 7) / 8 : 0;
381 thres = max(thres, 8U); /* need at least 8 */
382 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
fc90664e
DLR		 383 V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
384 V_TXFIFOTHRESH(thres) | V_TXIPG(1));
385
386 if (adap->params.rev > 0)
387 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
388 (hwm - lwm) * 4 / 8);
389 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
390 MAC_RXFIFO_SIZE * 4 * 8 / 512);
4d22de3e
DLR		 391 return 0;
392}
393
394int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
395{
396 u32 val;
397 struct adapter *adap = mac->adapter;
398 unsigned int oft = mac->offset;
399
400 if (duplex >= 0 && duplex != DUPLEX_FULL)
401 return -EINVAL;
402 if (speed >= 0) {
403 if (speed == SPEED_10)
404 val = V_PORTSPEED(0);
405 else if (speed == SPEED_100)
406 val = V_PORTSPEED(1);
407 else if (speed == SPEED_1000)
408 val = V_PORTSPEED(2);
409 else if (speed == SPEED_10000)
410 val = V_PORTSPEED(3);
411 else
412 return -EINVAL;
413
414 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
415 V_PORTSPEED(M_PORTSPEED), val);
416 }
417
7b581a0f
DLR		 418 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
419 val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
420 if (fc & PAUSE_TX)
421 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(
422 t3_read_reg(adap,
423 A_XGM_RX_MAX_PKT_SIZE
424 + oft)) / 8);
425 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
426
4d22de3e
DLR		 427 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
428 (fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
429 return 0;
430}
431
432int t3_mac_enable(struct cmac *mac, int which)
433{
434 int idx = macidx(mac);
435 struct adapter *adap = mac->adapter;
436 unsigned int oft = mac->offset;
59cf8107
DLR		 437 struct mac_stats *s = &mac->stats;
438
4d22de3e 439 if (which & MAC_DIRECTION_TX) {
4d22de3e 440 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
fc90664e 441 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
4d22de3e
DLR		 442 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
443 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
fc90664e 444
b1c9e0f7
DLR		 445 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
446
fc90664e 447 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
59cf8107
DLR		 448 mac->tx_mcnt = s->tx_frames;
449 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
450 A_TP_PIO_DATA)));
451 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
452 A_XGM_TX_SPI4_SOP_EOP_CNT +
453 oft)));
454 mac->rx_mcnt = s->rx_frames;
b4687ff7 455 mac->rx_pause = s->rx_pause;
59cf8107
DLR		 456 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
457 A_XGM_RX_SPI4_SOP_EOP_CNT +
458 oft)));
b1c9e0f7 459 mac->rx_ocnt = s->rx_fifo_ovfl;
fc90664e
DLR		 460 mac->txen = F_TXEN;
461 mac->toggle_cnt = 0;
4d22de3e
DLR		 462 }
463 if (which & MAC_DIRECTION_RX)
464 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
465 return 0;
466}
467
468int t3_mac_disable(struct cmac *mac, int which)
469{
4d22de3e
DLR		 470 struct adapter *adap = mac->adapter;
471
472 if (which & MAC_DIRECTION_TX) {
473 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
fc90664e 474 mac->txen = 0;
4d22de3e 475 }
59cf8107 476 if (which & MAC_DIRECTION_RX) {
b1c9e0f7
DLR		 477 int val = F_MAC_RESET_;
478
59cf8107
DLR		 479 t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
480 F_PCS_RESET_, 0);
481 msleep(100);
4d22de3e 482 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
59cf8107
DLR		 483 if (is_10G(adap))
484 val |= F_PCS_RESET_;
485 else if (uses_xaui(adap))
486 val |= F_PCS_RESET_ | F_XG2G_RESET_;
487 else
488 val |= F_RGMII_RESET_ | F_XG2G_RESET_;
489 t3_write_reg(mac->adapter, A_XGM_RESET_CTRL + mac->offset, val);
490 }
4d22de3e
DLR		 491 return 0;
492}
493
fc90664e
DLR		 494int t3b2_mac_watchdog_task(struct cmac *mac)
495{
496 struct adapter *adap = mac->adapter;
59cf8107
DLR		 497 struct mac_stats *s = &mac->stats;
498 unsigned int tx_tcnt, tx_xcnt;
499 unsigned int tx_mcnt = s->tx_frames;
500 unsigned int rx_mcnt = s->rx_frames;
501 unsigned int rx_xcnt;
fc90664e
DLR		 502 int status;
503
2090dee4
DLR		 504 status = 0;
505 tx_xcnt = 1; /* By default tx_xcnt is making progress */
506 tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt */
507 rx_xcnt = 1; /* By default rx_xcnt is making progress */
b4687ff7 508 if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) {
59cf8107
DLR		 509 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
510 A_XGM_TX_SPI4_SOP_EOP_CNT +
511 mac->offset)));
512 if (tx_xcnt == 0) {
513 t3_write_reg(adap, A_TP_PIO_ADDR,
514 A_TP_TX_DROP_CNT_CH0 + macidx(mac));
515 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
516 A_TP_PIO_DATA)));
517 } else {
2090dee4 518 goto rxcheck;
59cf8107
DLR		 519 }
520 } else {
521 mac->toggle_cnt = 0;
2090dee4 522 goto rxcheck;
59cf8107
DLR		 523 }
524
0da18e38 525 if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
2090dee4 526 if (mac->toggle_cnt > 4) {
fc90664e 527 status = 2;
2090dee4
DLR		 528 goto out;
529 } else {
fc90664e 530 status = 1;
2090dee4
DLR		 531 goto out;
532 }
fc90664e
DLR		 533 } else {
534 mac->toggle_cnt = 0;
2090dee4 535 goto rxcheck;
fc90664e 536 }
fc90664e 537
2090dee4 538rxcheck:
b1c9e0f7 539 if (rx_mcnt != mac->rx_mcnt) {
59cf8107
DLR		 540 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
541 A_XGM_RX_SPI4_SOP_EOP_CNT +
b1c9e0f7
DLR		 542 mac->offset))) +
543 (s->rx_fifo_ovfl -
544 mac->rx_ocnt);
545 mac->rx_ocnt = s->rx_fifo_ovfl;
546 } else
2090dee4 547 goto out;
59cf8107 548
2090dee4
DLR		 549 if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 &&
550 mac->rx_xcnt == 0) {
59cf8107 551 status = 2;
2090dee4
DLR		 552 goto out;
553 }
554
555out:
59cf8107
DLR		 556 mac->tx_tcnt = tx_tcnt;
557 mac->tx_xcnt = tx_xcnt;
558 mac->tx_mcnt = s->tx_frames;
559 mac->rx_xcnt = rx_xcnt;
560 mac->rx_mcnt = s->rx_frames;
b4687ff7 561 mac->rx_pause = s->rx_pause;
59cf8107
DLR		 562 if (status == 1) {
563 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
564 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
565 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
566 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
567 mac->toggle_cnt++;
568 } else if (status == 2) {
569 t3b2_mac_reset(mac);
570 mac->toggle_cnt = 0;
571 }
fc90664e
DLR		 572 return status;
573}
574
4d22de3e
DLR		 575/*
576 * This function is called periodically to accumulate the current values of the
577 * RMON counters into the port statistics. Since the packet counters are only
578 * 32 bits they can overflow in ~286 secs at 10G, so the function should be
579 * called more frequently than that. The byte counters are 45-bit wide, they
580 * would overflow in ~7.8 hours.
581 */
582const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
583{
584#define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
585#define RMON_UPDATE(mac, name, reg) \
586 (mac)->stats.name += (u64)RMON_READ(mac, A_XGM_STAT_##reg)
587#define RMON_UPDATE64(mac, name, reg_lo, reg_hi) \
588 (mac)->stats.name += RMON_READ(mac, A_XGM_STAT_##reg_lo) + \
589 ((u64)RMON_READ(mac, A_XGM_STAT_##reg_hi) << 32)
590
591 u32 v, lo;
592
593 RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
594 RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
595 RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);
596 RMON_UPDATE(mac, rx_bcast_frames, RX_BCAST_FRAMES);
597 RMON_UPDATE(mac, rx_fcs_errs, RX_CRC_ERR_FRAMES);
598 RMON_UPDATE(mac, rx_pause, RX_PAUSE_FRAMES);
599 RMON_UPDATE(mac, rx_jabber, RX_JABBER_FRAMES);
600 RMON_UPDATE(mac, rx_short, RX_SHORT_FRAMES);
601 RMON_UPDATE(mac, rx_symbol_errs, RX_SYM_CODE_ERR_FRAMES);
602
603 RMON_UPDATE(mac, rx_too_long, RX_OVERSIZE_FRAMES);
4d22de3e 604
fc90664e
DLR		 605 v = RMON_READ(mac, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT);
606 if (mac->adapter->params.rev == T3_REV_B2)
607 v &= 0x7fffffff;
608 mac->stats.rx_too_long += v;
609
4d22de3e
DLR		 610 RMON_UPDATE(mac, rx_frames_64, RX_64B_FRAMES);
611 RMON_UPDATE(mac, rx_frames_65_127, RX_65_127B_FRAMES);
612 RMON_UPDATE(mac, rx_frames_128_255, RX_128_255B_FRAMES);
613 RMON_UPDATE(mac, rx_frames_256_511, RX_256_511B_FRAMES);
614 RMON_UPDATE(mac, rx_frames_512_1023, RX_512_1023B_FRAMES);
615 RMON_UPDATE(mac, rx_frames_1024_1518, RX_1024_1518B_FRAMES);
616 RMON_UPDATE(mac, rx_frames_1519_max, RX_1519_MAXB_FRAMES);
617
618 RMON_UPDATE64(mac, tx_octets, TX_BYTE_LOW, TX_BYTE_HIGH);
619 RMON_UPDATE64(mac, tx_frames, TX_FRAME_LOW, TX_FRAME_HIGH);
620 RMON_UPDATE(mac, tx_mcast_frames, TX_MCAST);
621 RMON_UPDATE(mac, tx_bcast_frames, TX_BCAST);
622 RMON_UPDATE(mac, tx_pause, TX_PAUSE);
623 /* This counts error frames in general (bad FCS, underrun, etc). */
624 RMON_UPDATE(mac, tx_underrun, TX_ERR_FRAMES);
625
626 RMON_UPDATE(mac, tx_frames_64, TX_64B_FRAMES);
627 RMON_UPDATE(mac, tx_frames_65_127, TX_65_127B_FRAMES);
628 RMON_UPDATE(mac, tx_frames_128_255, TX_128_255B_FRAMES);
629 RMON_UPDATE(mac, tx_frames_256_511, TX_256_511B_FRAMES);
630 RMON_UPDATE(mac, tx_frames_512_1023, TX_512_1023B_FRAMES);
631 RMON_UPDATE(mac, tx_frames_1024_1518, TX_1024_1518B_FRAMES);
632 RMON_UPDATE(mac, tx_frames_1519_max, TX_1519_MAXB_FRAMES);
633
634 /* The next stat isn't clear-on-read. */
635 t3_write_reg(mac->adapter, A_TP_MIB_INDEX, mac->offset ? 51 : 50);
636 v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
637 lo = (u32) mac->stats.rx_cong_drops;
638 mac->stats.rx_cong_drops += (u64) (v - lo);
639
640 return &mac->stats;
641}
Linux 6.x block layer and io_uring tree(s)