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cxgb3: Avoid flush_workqueue() deadlock.
[linux-2.6-block.git] / drivers / net / cxgb3 / cxgb3_main.c
CommitLineData
4d22de3e 1/*
a02d44a0 2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
4d22de3e 3 *
1d68e93d
DLR		 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
4d22de3e 9 *
1d68e93d
DLR		 10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
4d22de3e 31 */
4d22de3e
DLR		 32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/dma-mapping.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/if_vlan.h>
0f07c4ee 40#include <linux/mdio.h>
4d22de3e
DLR		 41#include <linux/sockios.h>
42#include <linux/workqueue.h>
43#include <linux/proc_fs.h>
44#include <linux/rtnetlink.h>
2e283962 45#include <linux/firmware.h>
d9da466a 46#include <linux/log2.h>
34336ec0 47#include <linux/stringify.h>
e998f245 48#include <linux/sched.h>
5a0e3ad6 49#include <linux/slab.h>
4d22de3e
DLR		 50#include <asm/uaccess.h>
51
52#include "common.h"
53#include "cxgb3_ioctl.h"
54#include "regs.h"
55#include "cxgb3_offload.h"
56#include "version.h"
57
58#include "cxgb3_ctl_defs.h"
59#include "t3_cpl.h"
60#include "firmware_exports.h"
61
62enum {
63 MAX_TXQ_ENTRIES = 16384,
64 MAX_CTRL_TXQ_ENTRIES = 1024,
65 MAX_RSPQ_ENTRIES = 16384,
66 MAX_RX_BUFFERS = 16384,
67 MAX_RX_JUMBO_BUFFERS = 16384,
68 MIN_TXQ_ENTRIES = 4,
69 MIN_CTRL_TXQ_ENTRIES = 4,
70 MIN_RSPQ_ENTRIES = 32,
71 MIN_FL_ENTRIES = 32
72};
73
74#define PORT_MASK ((1 << MAX_NPORTS) - 1)
75
76#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
78 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
79
80#define EEPROM_MAGIC 0x38E2F10C
81
678771d6
DLR		 82#define CH_DEVICE(devid, idx) \
83 { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, PCI_ANY_ID, 0, 0, idx }
4d22de3e 84
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(cxgb3_pci_tbl) = {
678771d6
DLR		 86 CH_DEVICE(0x20, 0), /* PE9000 */
87 CH_DEVICE(0x21, 1), /* T302E */
88 CH_DEVICE(0x22, 2), /* T310E */
89 CH_DEVICE(0x23, 3), /* T320X */
90 CH_DEVICE(0x24, 1), /* T302X */
91 CH_DEVICE(0x25, 3), /* T320E */
92 CH_DEVICE(0x26, 2), /* T310X */
93 CH_DEVICE(0x30, 2), /* T3B10 */
94 CH_DEVICE(0x31, 3), /* T3B20 */
95 CH_DEVICE(0x32, 1), /* T3B02 */
ce03aadd 96 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
74451424
DLR		 97 CH_DEVICE(0x36, 3), /* S320E-CR */
98 CH_DEVICE(0x37, 7), /* N320E-G2 */
4d22de3e
DLR		 99 {0,}
100};
101
102MODULE_DESCRIPTION(DRV_DESC);
103MODULE_AUTHOR("Chelsio Communications");
1d68e93d 104MODULE_LICENSE("Dual BSD/GPL");
4d22de3e
DLR		 105MODULE_VERSION(DRV_VERSION);
106MODULE_DEVICE_TABLE(pci, cxgb3_pci_tbl);
107
108static int dflt_msg_enable = DFLT_MSG_ENABLE;
109
110module_param(dflt_msg_enable, int, 0644);
111MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T3 default message enable bitmap");
112
113/*
114 * The driver uses the best interrupt scheme available on a platform in the
115 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
116 * of these schemes the driver may consider as follows:
117 *
118 * msi = 2: choose from among all three options
119 * msi = 1: only consider MSI and pin interrupts
120 * msi = 0: force pin interrupts
121 */
122static int msi = 2;
123
124module_param(msi, int, 0644);
125MODULE_PARM_DESC(msi, "whether to use MSI or MSI-X");
126
127/*
128 * The driver enables offload as a default.
129 * To disable it, use ofld_disable = 1.
130 */
131
132static int ofld_disable = 0;
133
134module_param(ofld_disable, int, 0644);
135MODULE_PARM_DESC(ofld_disable, "whether to enable offload at init time or not");
136
137/*
138 * We have work elements that we need to cancel when an interface is taken
139 * down. Normally the work elements would be executed by keventd but that
140 * can deadlock because of linkwatch. If our close method takes the rtnl
141 * lock and linkwatch is ahead of our work elements in keventd, linkwatch
142 * will block keventd as it needs the rtnl lock, and we'll deadlock waiting
143 * for our work to complete. Get our own work queue to solve this.
144 */
e998f245 145struct workqueue_struct *cxgb3_wq;
4d22de3e
DLR		 146
147/**
148 * link_report - show link status and link speed/duplex
149 * @p: the port whose settings are to be reported
150 *
151 * Shows the link status, speed, and duplex of a port.
152 */
153static void link_report(struct net_device *dev)
154{
155 if (!netif_carrier_ok(dev))
156 printk(KERN_INFO "%s: link down\n", dev->name);
157 else {
158 const char *s = "10Mbps";
159 const struct port_info *p = netdev_priv(dev);
160
161 switch (p->link_config.speed) {
162 case SPEED_10000:
163 s = "10Gbps";
164 break;
165 case SPEED_1000:
166 s = "1000Mbps";
167 break;
168 case SPEED_100:
169 s = "100Mbps";
170 break;
171 }
172
173 printk(KERN_INFO "%s: link up, %s, %s-duplex\n", dev->name, s,
174 p->link_config.duplex == DUPLEX_FULL ? "full" : "half");
175 }
176}
177
34701fde
DLR		 178static void enable_tx_fifo_drain(struct adapter *adapter,
179 struct port_info *pi)
180{
181 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset, 0,
182 F_ENDROPPKT);
183 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, 0);
184 t3_write_reg(adapter, A_XGM_TX_CTRL + pi->mac.offset, F_TXEN);
185 t3_write_reg(adapter, A_XGM_RX_CTRL + pi->mac.offset, F_RXEN);
186}
187
188static void disable_tx_fifo_drain(struct adapter *adapter,
189 struct port_info *pi)
190{
191 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + pi->mac.offset,
192 F_ENDROPPKT, 0);
193}
194
bf792094
DLR		 195void t3_os_link_fault(struct adapter *adap, int port_id, int state)
196{
197 struct net_device *dev = adap->port[port_id];
198 struct port_info *pi = netdev_priv(dev);
199
200 if (state == netif_carrier_ok(dev))
201 return;
202
203 if (state) {
204 struct cmac *mac = &pi->mac;
205
206 netif_carrier_on(dev);
207
34701fde
DLR		 208 disable_tx_fifo_drain(adap, pi);
209
bf792094
DLR		 210 /* Clear local faults */
211 t3_xgm_intr_disable(adap, pi->port_id);
212 t3_read_reg(adap, A_XGM_INT_STATUS +
213 pi->mac.offset);
214 t3_write_reg(adap,
215 A_XGM_INT_CAUSE + pi->mac.offset,
216 F_XGM_INT);
217
218 t3_set_reg_field(adap,
219 A_XGM_INT_ENABLE +
220 pi->mac.offset,
221 F_XGM_INT, F_XGM_INT);
222 t3_xgm_intr_enable(adap, pi->port_id);
223
224 t3_mac_enable(mac, MAC_DIRECTION_TX);
34701fde 225 } else {
bf792094
DLR		 226 netif_carrier_off(dev);
227
34701fde
DLR		 228 /* Flush TX FIFO */
229 enable_tx_fifo_drain(adap, pi);
230 }
bf792094
DLR		 231 link_report(dev);
232}
233
4d22de3e
DLR		 234/**
235 * t3_os_link_changed - handle link status changes
236 * @adapter: the adapter associated with the link change
237 * @port_id: the port index whose limk status has changed
238 * @link_stat: the new status of the link
239 * @speed: the new speed setting
240 * @duplex: the new duplex setting
241 * @pause: the new flow-control setting
242 *
243 * This is the OS-dependent handler for link status changes. The OS
244 * neutral handler takes care of most of the processing for these events,
245 * then calls this handler for any OS-specific processing.
246 */
247void t3_os_link_changed(struct adapter *adapter, int port_id, int link_stat,
248 int speed, int duplex, int pause)
249{
250 struct net_device *dev = adapter->port[port_id];
6d6dabac
DLR		 251 struct port_info *pi = netdev_priv(dev);
252 struct cmac *mac = &pi->mac;
4d22de3e
DLR		 253
254 /* Skip changes from disabled ports. */
255 if (!netif_running(dev))
256 return;
257
258 if (link_stat != netif_carrier_ok(dev)) {
6d6dabac 259 if (link_stat) {
34701fde
DLR		 260 disable_tx_fifo_drain(adapter, pi);
261
59cf8107 262 t3_mac_enable(mac, MAC_DIRECTION_RX);
bf792094
DLR		 263
264 /* Clear local faults */
265 t3_xgm_intr_disable(adapter, pi->port_id);
266 t3_read_reg(adapter, A_XGM_INT_STATUS +
267 pi->mac.offset);
268 t3_write_reg(adapter,
269 A_XGM_INT_CAUSE + pi->mac.offset,
270 F_XGM_INT);
271
272 t3_set_reg_field(adapter,
273 A_XGM_INT_ENABLE + pi->mac.offset,
274 F_XGM_INT, F_XGM_INT);
275 t3_xgm_intr_enable(adapter, pi->port_id);
276
4d22de3e 277 netif_carrier_on(dev);
6d6dabac 278 } else {
4d22de3e 279 netif_carrier_off(dev);
bf792094
DLR		 280
281 t3_xgm_intr_disable(adapter, pi->port_id);
282 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
283 t3_set_reg_field(adapter,
284 A_XGM_INT_ENABLE + pi->mac.offset,
285 F_XGM_INT, 0);
286
287 if (is_10G(adapter))
288 pi->phy.ops->power_down(&pi->phy, 1);
289
290 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
59cf8107
DLR		 291 t3_mac_disable(mac, MAC_DIRECTION_RX);
292 t3_link_start(&pi->phy, mac, &pi->link_config);
34701fde
DLR		 293
294 /* Flush TX FIFO */
295 enable_tx_fifo_drain(adapter, pi);
6d6dabac
DLR		 296 }
297
4d22de3e
DLR		 298 link_report(dev);
299 }
300}
301
1e882025
DLR		 302/**
303 * t3_os_phymod_changed - handle PHY module changes
304 * @phy: the PHY reporting the module change
305 * @mod_type: new module type
306 *
307 * This is the OS-dependent handler for PHY module changes. It is
308 * invoked when a PHY module is removed or inserted for any OS-specific
309 * processing.
310 */
311void t3_os_phymod_changed(struct adapter *adap, int port_id)
312{
313 static const char *mod_str[] = {
314 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
315 };
316
317 const struct net_device *dev = adap->port[port_id];
318 const struct port_info *pi = netdev_priv(dev);
319
320 if (pi->phy.modtype == phy_modtype_none)
321 printk(KERN_INFO "%s: PHY module unplugged\n", dev->name);
322 else
323 printk(KERN_INFO "%s: %s PHY module inserted\n", dev->name,
324 mod_str[pi->phy.modtype]);
325}
326
4d22de3e
DLR		 327static void cxgb_set_rxmode(struct net_device *dev)
328{
4d22de3e
DLR		 329 struct port_info *pi = netdev_priv(dev);
330
0988d269 331 t3_mac_set_rx_mode(&pi->mac, dev);
4d22de3e
DLR		 332}
333
334/**
335 * link_start - enable a port
336 * @dev: the device to enable
337 *
338 * Performs the MAC and PHY actions needed to enable a port.
339 */
340static void link_start(struct net_device *dev)
341{
4d22de3e
DLR		 342 struct port_info *pi = netdev_priv(dev);
343 struct cmac *mac = &pi->mac;
344
4d22de3e 345 t3_mac_reset(mac);
f14d42f3 346 t3_mac_set_num_ucast(mac, MAX_MAC_IDX);
4d22de3e 347 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3
KX		 348 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
349 t3_mac_set_address(mac, SAN_MAC_IDX, pi->iscsic.mac_addr);
0988d269 350 t3_mac_set_rx_mode(mac, dev);
4d22de3e
DLR		 351 t3_link_start(&pi->phy, mac, &pi->link_config);
352 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
353}
354
355static inline void cxgb_disable_msi(struct adapter *adapter)
356{
357 if (adapter->flags & USING_MSIX) {
358 pci_disable_msix(adapter->pdev);
359 adapter->flags &= ~USING_MSIX;
360 } else if (adapter->flags & USING_MSI) {
361 pci_disable_msi(adapter->pdev);
362 adapter->flags &= ~USING_MSI;
363 }
364}
365
366/*
367 * Interrupt handler for asynchronous events used with MSI-X.
368 */
369static irqreturn_t t3_async_intr_handler(int irq, void *cookie)
370{
371 t3_slow_intr_handler(cookie);
372 return IRQ_HANDLED;
373}
374
375/*
376 * Name the MSI-X interrupts.
377 */
378static void name_msix_vecs(struct adapter *adap)
379{
380 int i, j, msi_idx = 1, n = sizeof(adap->msix_info[0].desc) - 1;
381
382 snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
383 adap->msix_info[0].desc[n] = 0;
384
385 for_each_port(adap, j) {
386 struct net_device *d = adap->port[j];
387 const struct port_info *pi = netdev_priv(d);
388
389 for (i = 0; i < pi->nqsets; i++, msi_idx++) {
390 snprintf(adap->msix_info[msi_idx].desc, n,
8c263761 391 "%s-%d", d->name, pi->first_qset + i);
4d22de3e
DLR		 392 adap->msix_info[msi_idx].desc[n] = 0;
393 }
8c263761 394 }
4d22de3e
DLR		 395}
396
397static int request_msix_data_irqs(struct adapter *adap)
398{
399 int i, j, err, qidx = 0;
400
401 for_each_port(adap, i) {
402 int nqsets = adap2pinfo(adap, i)->nqsets;
403
404 for (j = 0; j < nqsets; ++j) {
405 err = request_irq(adap->msix_info[qidx + 1].vec,
406 t3_intr_handler(adap,
407 adap->sge.qs[qidx].
408 rspq.polling), 0,
409 adap->msix_info[qidx + 1].desc,
410 &adap->sge.qs[qidx]);
411 if (err) {
412 while (--qidx >= 0)
413 free_irq(adap->msix_info[qidx + 1].vec,
414 &adap->sge.qs[qidx]);
415 return err;
416 }
417 qidx++;
418 }
419 }
420 return 0;
421}
422
8c263761
DLR		 423static void free_irq_resources(struct adapter *adapter)
424{
425 if (adapter->flags & USING_MSIX) {
426 int i, n = 0;
427
428 free_irq(adapter->msix_info[0].vec, adapter);
429 for_each_port(adapter, i)
5cda9364 430 n += adap2pinfo(adapter, i)->nqsets;
8c263761
DLR		 431
432 for (i = 0; i < n; ++i)
433 free_irq(adapter->msix_info[i + 1].vec,
434 &adapter->sge.qs[i]);
435 } else
436 free_irq(adapter->pdev->irq, adapter);
437}
438
b881955b
DLR		 439static int await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
440 unsigned long n)
441{
e95ef5d3 442 int attempts = 10;
b881955b
DLR		 443
444 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
445 if (!--attempts)
446 return -ETIMEDOUT;
447 msleep(10);
448 }
449 return 0;
450}
451
452static int init_tp_parity(struct adapter *adap)
453{
454 int i;
455 struct sk_buff *skb;
456 struct cpl_set_tcb_field *greq;
457 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
458
459 t3_tp_set_offload_mode(adap, 1);
460
461 for (i = 0; i < 16; i++) {
462 struct cpl_smt_write_req *req;
463
74b793e1
DLR		 464 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
465 if (!skb)
466 skb = adap->nofail_skb;
467 if (!skb)
468 goto alloc_skb_fail;
469
b881955b
DLR		 470 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
471 memset(req, 0, sizeof(*req));
472 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
473 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
dce7d1d0 474 req->mtu_idx = NMTUS - 1;
b881955b
DLR		 475 req->iff = i;
476 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 477 if (skb == adap->nofail_skb) {
478 await_mgmt_replies(adap, cnt, i + 1);
479 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
480 if (!adap->nofail_skb)
481 goto alloc_skb_fail;
482 }
b881955b
DLR		 483 }
484
485 for (i = 0; i < 2048; i++) {
486 struct cpl_l2t_write_req *req;
487
74b793e1
DLR		 488 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
489 if (!skb)
490 skb = adap->nofail_skb;
491 if (!skb)
492 goto alloc_skb_fail;
493
b881955b
DLR		 494 req = (struct cpl_l2t_write_req *)__skb_put(skb, sizeof(*req));
495 memset(req, 0, sizeof(*req));
496 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
497 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
498 req->params = htonl(V_L2T_W_IDX(i));
499 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 500 if (skb == adap->nofail_skb) {
501 await_mgmt_replies(adap, cnt, 16 + i + 1);
502 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
503 if (!adap->nofail_skb)
504 goto alloc_skb_fail;
505 }
b881955b
DLR		 506 }
507
508 for (i = 0; i < 2048; i++) {
509 struct cpl_rte_write_req *req;
510
74b793e1
DLR		 511 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
512 if (!skb)
513 skb = adap->nofail_skb;
514 if (!skb)
515 goto alloc_skb_fail;
516
b881955b
DLR		 517 req = (struct cpl_rte_write_req *)__skb_put(skb, sizeof(*req));
518 memset(req, 0, sizeof(*req));
519 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
520 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
521 req->l2t_idx = htonl(V_L2T_W_IDX(i));
522 t3_mgmt_tx(adap, skb);
74b793e1
DLR		 523 if (skb == adap->nofail_skb) {
524 await_mgmt_replies(adap, cnt, 16 + 2048 + i + 1);
525 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
526 if (!adap->nofail_skb)
527 goto alloc_skb_fail;
528 }
b881955b
DLR		 529 }
530
74b793e1
DLR		 531 skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
532 if (!skb)
533 skb = adap->nofail_skb;
534 if (!skb)
535 goto alloc_skb_fail;
536
b881955b
DLR		 537 greq = (struct cpl_set_tcb_field *)__skb_put(skb, sizeof(*greq));
538 memset(greq, 0, sizeof(*greq));
539 greq->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
540 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
541 greq->mask = cpu_to_be64(1);
542 t3_mgmt_tx(adap, skb);
543
544 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
74b793e1
DLR		 545 if (skb == adap->nofail_skb) {
546 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
547 adap->nofail_skb = alloc_skb(sizeof(*greq), GFP_KERNEL);
548 }
549
b881955b
DLR		 550 t3_tp_set_offload_mode(adap, 0);
551 return i;
74b793e1
DLR		 552
553alloc_skb_fail:
554 t3_tp_set_offload_mode(adap, 0);
555 return -ENOMEM;
b881955b
DLR		 556}
557
4d22de3e
DLR		 558/**
559 * setup_rss - configure RSS
560 * @adap: the adapter
561 *
562 * Sets up RSS to distribute packets to multiple receive queues. We
563 * configure the RSS CPU lookup table to distribute to the number of HW
564 * receive queues, and the response queue lookup table to narrow that
565 * down to the response queues actually configured for each port.
566 * We always configure the RSS mapping for two ports since the mapping
567 * table has plenty of entries.
568 */
569static void setup_rss(struct adapter *adap)
570{
571 int i;
572 unsigned int nq0 = adap2pinfo(adap, 0)->nqsets;
573 unsigned int nq1 = adap->port[1] ? adap2pinfo(adap, 1)->nqsets : 1;
574 u8 cpus[SGE_QSETS + 1];
575 u16 rspq_map[RSS_TABLE_SIZE];
576
577 for (i = 0; i < SGE_QSETS; ++i)
578 cpus[i] = i;
579 cpus[SGE_QSETS] = 0xff; /* terminator */
580
581 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
582 rspq_map[i] = i % nq0;
583 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
584 }
585
586 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
587 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
a2604be5 588 V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ, cpus, rspq_map);
4d22de3e
DLR		 589}
590
e998f245
SW		 591static void ring_dbs(struct adapter *adap)
592{
593 int i, j;
594
595 for (i = 0; i < SGE_QSETS; i++) {
596 struct sge_qset *qs = &adap->sge.qs[i];
597
598 if (qs->adap)
599 for (j = 0; j < SGE_TXQ_PER_SET; j++)
600 t3_write_reg(adap, A_SG_KDOORBELL, F_SELEGRCNTX | V_EGRCNTX(qs->txq[j].cntxt_id));
601 }
602}
603
bea3348e 604static void init_napi(struct adapter *adap)
4d22de3e 605{
bea3348e 606 int i;
4d22de3e 607
bea3348e
SH		 608 for (i = 0; i < SGE_QSETS; i++) {
609 struct sge_qset *qs = &adap->sge.qs[i];
4d22de3e 610
bea3348e
SH		 611 if (qs->adap)
612 netif_napi_add(qs->netdev, &qs->napi, qs->napi.poll,
613 64);
4d22de3e 614 }
48c4b6db
DLR		 615
616 /*
617 * netif_napi_add() can be called only once per napi_struct because it
618 * adds each new napi_struct to a list. Be careful not to call it a
619 * second time, e.g., during EEH recovery, by making a note of it.
620 */
621 adap->flags |= NAPI_INIT;
4d22de3e
DLR		 622}
623
624/*
625 * Wait until all NAPI handlers are descheduled. This includes the handlers of
626 * both netdevices representing interfaces and the dummy ones for the extra
627 * queues.
628 */
629static void quiesce_rx(struct adapter *adap)
630{
631 int i;
4d22de3e 632
bea3348e
SH		 633 for (i = 0; i < SGE_QSETS; i++)
634 if (adap->sge.qs[i].adap)
635 napi_disable(&adap->sge.qs[i].napi);
636}
4d22de3e 637
bea3348e
SH		 638static void enable_all_napi(struct adapter *adap)
639{
640 int i;
641 for (i = 0; i < SGE_QSETS; i++)
642 if (adap->sge.qs[i].adap)
643 napi_enable(&adap->sge.qs[i].napi);
4d22de3e
DLR		 644}
645
04ecb072
DLR		 646/**
647 * set_qset_lro - Turn a queue set's LRO capability on and off
648 * @dev: the device the qset is attached to
649 * @qset_idx: the queue set index
650 * @val: the LRO switch
651 *
652 * Sets LRO on or off for a particular queue set.
653 * the device's features flag is updated to reflect the LRO
654 * capability when all queues belonging to the device are
655 * in the same state.
656 */
657static void set_qset_lro(struct net_device *dev, int qset_idx, int val)
658{
659 struct port_info *pi = netdev_priv(dev);
660 struct adapter *adapter = pi->adapter;
04ecb072
DLR		 661
662 adapter->params.sge.qset[qset_idx].lro = !!val;
663 adapter->sge.qs[qset_idx].lro_enabled = !!val;
04ecb072
DLR		 664}
665
4d22de3e
DLR		 666/**
667 * setup_sge_qsets - configure SGE Tx/Rx/response queues
668 * @adap: the adapter
669 *
670 * Determines how many sets of SGE queues to use and initializes them.
671 * We support multiple queue sets per port if we have MSI-X, otherwise
672 * just one queue set per port.
673 */
674static int setup_sge_qsets(struct adapter *adap)
675{
bea3348e 676 int i, j, err, irq_idx = 0, qset_idx = 0;
8ac3ba68 677 unsigned int ntxq = SGE_TXQ_PER_SET;
4d22de3e
DLR		 678
679 if (adap->params.rev > 0 && !(adap->flags & USING_MSI))
680 irq_idx = -1;
681
682 for_each_port(adap, i) {
683 struct net_device *dev = adap->port[i];
bea3348e 684 struct port_info *pi = netdev_priv(dev);
4d22de3e 685
bea3348e 686 pi->qs = &adap->sge.qs[pi->first_qset];
e594e96e 687 for (j = 0; j < pi->nqsets; ++j, ++qset_idx) {
47fd23fe 688 set_qset_lro(dev, qset_idx, pi->rx_offload & T3_LRO);
4d22de3e
DLR		 689 err = t3_sge_alloc_qset(adap, qset_idx, 1,
690 (adap->flags & USING_MSIX) ? qset_idx + 1 :
691 irq_idx,
82ad3329
DLR		 692 &adap->params.sge.qset[qset_idx], ntxq, dev,
693 netdev_get_tx_queue(dev, j));
4d22de3e
DLR		 694 if (err) {
695 t3_free_sge_resources(adap);
696 return err;
697 }
698 }
699 }
700
701 return 0;
702}
703
3e5192ee 704static ssize_t attr_show(struct device *d, char *buf,
896392ef 705 ssize_t(*format) (struct net_device *, char *))
4d22de3e
DLR		 706{
707 ssize_t len;
4d22de3e
DLR		 708
709 /* Synchronize with ioctls that may shut down the device */
710 rtnl_lock();
896392ef 711 len = (*format) (to_net_dev(d), buf);
4d22de3e
DLR		 712 rtnl_unlock();
713 return len;
714}
715
3e5192ee 716static ssize_t attr_store(struct device *d,
0ee8d33c 717 const char *buf, size_t len,
896392ef 718 ssize_t(*set) (struct net_device *, unsigned int),
4d22de3e
DLR		 719 unsigned int min_val, unsigned int max_val)
720{
721 char *endp;
722 ssize_t ret;
723 unsigned int val;
4d22de3e
DLR		 724
725 if (!capable(CAP_NET_ADMIN))
726 return -EPERM;
727
728 val = simple_strtoul(buf, &endp, 0);
729 if (endp == buf || val < min_val || val > max_val)
730 return -EINVAL;
731
732 rtnl_lock();
896392ef 733 ret = (*set) (to_net_dev(d), val);
4d22de3e
DLR		 734 if (!ret)
735 ret = len;
736 rtnl_unlock();
737 return ret;
738}
739
740#define CXGB3_SHOW(name, val_expr) \
896392ef 741static ssize_t format_##name(struct net_device *dev, char *buf) \
4d22de3e 742{ \
5fbf816f
DLR		 743 struct port_info *pi = netdev_priv(dev); \
744 struct adapter *adap = pi->adapter; \
4d22de3e
DLR		 745 return sprintf(buf, "%u\n", val_expr); \
746} \
0ee8d33c
DLR		 747static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
748 char *buf) \
4d22de3e 749{ \
3e5192ee 750 return attr_show(d, buf, format_##name); \
4d22de3e
DLR		 751}
752
896392ef 753static ssize_t set_nfilters(struct net_device *dev, unsigned int val)
4d22de3e 754{
5fbf816f
DLR		 755 struct port_info *pi = netdev_priv(dev);
756 struct adapter *adap = pi->adapter;
9f238486 757 int min_tids = is_offload(adap) ? MC5_MIN_TIDS : 0;
896392ef 758
4d22de3e
DLR		 759 if (adap->flags & FULL_INIT_DONE)
760 return -EBUSY;
761 if (val && adap->params.rev == 0)
762 return -EINVAL;
9f238486
DLR		 763 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
764 min_tids)
4d22de3e
DLR		 765 return -EINVAL;
766 adap->params.mc5.nfilters = val;
767 return 0;
768}
769
0ee8d33c
DLR		 770static ssize_t store_nfilters(struct device *d, struct device_attribute *attr,
771 const char *buf, size_t len)
4d22de3e 772{
3e5192ee 773 return attr_store(d, buf, len, set_nfilters, 0, ~0);
4d22de3e
DLR		 774}
775
896392ef 776static ssize_t set_nservers(struct net_device *dev, unsigned int val)
4d22de3e 777{
5fbf816f
DLR		 778 struct port_info *pi = netdev_priv(dev);
779 struct adapter *adap = pi->adapter;
896392ef 780
4d22de3e
DLR		 781 if (adap->flags & FULL_INIT_DONE)
782 return -EBUSY;
9f238486
DLR		 783 if (val > t3_mc5_size(&adap->mc5) - adap->params.mc5.nfilters -
784 MC5_MIN_TIDS)
4d22de3e
DLR		 785 return -EINVAL;
786 adap->params.mc5.nservers = val;
787 return 0;
788}
789
0ee8d33c
DLR		 790static ssize_t store_nservers(struct device *d, struct device_attribute *attr,
791 const char *buf, size_t len)
4d22de3e 792{
3e5192ee 793 return attr_store(d, buf, len, set_nservers, 0, ~0);
4d22de3e
DLR		 794}
795
796#define CXGB3_ATTR_R(name, val_expr) \
797CXGB3_SHOW(name, val_expr) \
0ee8d33c 798static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
4d22de3e
DLR		 799
800#define CXGB3_ATTR_RW(name, val_expr, store_method) \
801CXGB3_SHOW(name, val_expr) \
0ee8d33c 802static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_method)
4d22de3e
DLR		 803
804CXGB3_ATTR_R(cam_size, t3_mc5_size(&adap->mc5));
805CXGB3_ATTR_RW(nfilters, adap->params.mc5.nfilters, store_nfilters);
806CXGB3_ATTR_RW(nservers, adap->params.mc5.nservers, store_nservers);
807
808static struct attribute *cxgb3_attrs[] = {
0ee8d33c
DLR		 809 &dev_attr_cam_size.attr,
810 &dev_attr_nfilters.attr,
811 &dev_attr_nservers.attr,
4d22de3e
DLR		 812 NULL
813};
814
815static struct attribute_group cxgb3_attr_group = {.attrs = cxgb3_attrs };
816
3e5192ee 817static ssize_t tm_attr_show(struct device *d,
0ee8d33c 818 char *buf, int sched)
4d22de3e 819{
5fbf816f
DLR		 820 struct port_info *pi = netdev_priv(to_net_dev(d));
821 struct adapter *adap = pi->adapter;
4d22de3e 822 unsigned int v, addr, bpt, cpt;
5fbf816f 823 ssize_t len;
4d22de3e
DLR		 824
825 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
826 rtnl_lock();
827 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
828 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
829 if (sched & 1)
830 v >>= 16;
831 bpt = (v >> 8) & 0xff;
832 cpt = v & 0xff;
833 if (!cpt)
834 len = sprintf(buf, "disabled\n");
835 else {
836 v = (adap->params.vpd.cclk * 1000) / cpt;
837 len = sprintf(buf, "%u Kbps\n", (v * bpt) / 125);
838 }
839 rtnl_unlock();
840 return len;
841}
842
3e5192ee 843static ssize_t tm_attr_store(struct device *d,
0ee8d33c 844 const char *buf, size_t len, int sched)
4d22de3e 845{
5fbf816f
DLR		 846 struct port_info *pi = netdev_priv(to_net_dev(d));
847 struct adapter *adap = pi->adapter;
848 unsigned int val;
4d22de3e
DLR		 849 char *endp;
850 ssize_t ret;
4d22de3e
DLR		 851
852 if (!capable(CAP_NET_ADMIN))
853 return -EPERM;
854
855 val = simple_strtoul(buf, &endp, 0);
856 if (endp == buf || val > 10000000)
857 return -EINVAL;
858
859 rtnl_lock();
860 ret = t3_config_sched(adap, val, sched);
861 if (!ret)
862 ret = len;
863 rtnl_unlock();
864 return ret;
865}
866
867#define TM_ATTR(name, sched) \
0ee8d33c
DLR		 868static ssize_t show_##name(struct device *d, struct device_attribute *attr, \
869 char *buf) \
4d22de3e 870{ \
3e5192ee 871 return tm_attr_show(d, buf, sched); \
4d22de3e 872} \
0ee8d33c
DLR		 873static ssize_t store_##name(struct device *d, struct device_attribute *attr, \
874 const char *buf, size_t len) \
4d22de3e 875{ \
3e5192ee 876 return tm_attr_store(d, buf, len, sched); \
4d22de3e 877} \
0ee8d33c 878static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, show_##name, store_##name)
4d22de3e
DLR		 879
880TM_ATTR(sched0, 0);
881TM_ATTR(sched1, 1);
882TM_ATTR(sched2, 2);
883TM_ATTR(sched3, 3);
884TM_ATTR(sched4, 4);
885TM_ATTR(sched5, 5);
886TM_ATTR(sched6, 6);
887TM_ATTR(sched7, 7);
888
889static struct attribute *offload_attrs[] = {
0ee8d33c
DLR		 890 &dev_attr_sched0.attr,
891 &dev_attr_sched1.attr,
892 &dev_attr_sched2.attr,
893 &dev_attr_sched3.attr,
894 &dev_attr_sched4.attr,
895 &dev_attr_sched5.attr,
896 &dev_attr_sched6.attr,
897 &dev_attr_sched7.attr,
4d22de3e
DLR		 898 NULL
899};
900
901static struct attribute_group offload_attr_group = {.attrs = offload_attrs };
902
903/*
904 * Sends an sk_buff to an offload queue driver
905 * after dealing with any active network taps.
906 */
907static inline int offload_tx(struct t3cdev *tdev, struct sk_buff *skb)
908{
909 int ret;
910
911 local_bh_disable();
912 ret = t3_offload_tx(tdev, skb);
913 local_bh_enable();
914 return ret;
915}
916
917static int write_smt_entry(struct adapter *adapter, int idx)
918{
919 struct cpl_smt_write_req *req;
f14d42f3 920 struct port_info *pi = netdev_priv(adapter->port[idx]);
4d22de3e
DLR		 921 struct sk_buff *skb = alloc_skb(sizeof(*req), GFP_KERNEL);
922
923 if (!skb)
924 return -ENOMEM;
925
926 req = (struct cpl_smt_write_req *)__skb_put(skb, sizeof(*req));
927 req->wr.wr_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
928 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
929 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
930 req->iff = idx;
4d22de3e 931 memcpy(req->src_mac0, adapter->port[idx]->dev_addr, ETH_ALEN);
f14d42f3 932 memcpy(req->src_mac1, pi->iscsic.mac_addr, ETH_ALEN);
4d22de3e
DLR		 933 skb->priority = 1;
934 offload_tx(&adapter->tdev, skb);
935 return 0;
936}
937
938static int init_smt(struct adapter *adapter)
939{
940 int i;
941
942 for_each_port(adapter, i)
943 write_smt_entry(adapter, i);
944 return 0;
945}
946
947static void init_port_mtus(struct adapter *adapter)
948{
949 unsigned int mtus = adapter->port[0]->mtu;
950
951 if (adapter->port[1])
952 mtus |= adapter->port[1]->mtu << 16;
953 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
954}
955
8c263761 956static int send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
14ab9892
DLR		 957 int hi, int port)
958{
959 struct sk_buff *skb;
960 struct mngt_pktsched_wr *req;
8c263761 961 int ret;
14ab9892 962
74b793e1
DLR		 963 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
964 if (!skb)
965 skb = adap->nofail_skb;
966 if (!skb)
967 return -ENOMEM;
968
14ab9892
DLR		 969 req = (struct mngt_pktsched_wr *)skb_put(skb, sizeof(*req));
970 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
971 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
972 req->sched = sched;
973 req->idx = qidx;
974 req->min = lo;
975 req->max = hi;
976 req->binding = port;
8c263761 977 ret = t3_mgmt_tx(adap, skb);
74b793e1
DLR		 978 if (skb == adap->nofail_skb) {
979 adap->nofail_skb = alloc_skb(sizeof(struct cpl_set_tcb_field),
980 GFP_KERNEL);
981 if (!adap->nofail_skb)
982 ret = -ENOMEM;
983 }
8c263761
DLR		 984
985 return ret;
14ab9892
DLR		 986}
987
8c263761 988static int bind_qsets(struct adapter *adap)
14ab9892 989{
8c263761 990 int i, j, err = 0;
14ab9892
DLR		 991
992 for_each_port(adap, i) {
993 const struct port_info *pi = adap2pinfo(adap, i);
994
8c263761
DLR		 995 for (j = 0; j < pi->nqsets; ++j) {
996 int ret = send_pktsched_cmd(adap, 1,
997 pi->first_qset + j, -1,
998 -1, i);
999 if (ret)
1000 err = ret;
1001 }
14ab9892 1002 }
8c263761
DLR		 1003
1004 return err;
14ab9892
DLR		 1005}
1006
34336ec0
BH		 1007#define FW_VERSION __stringify(FW_VERSION_MAJOR) "." \
1008 __stringify(FW_VERSION_MINOR) "." __stringify(FW_VERSION_MICRO)
1009#define FW_FNAME "cxgb3/t3fw-" FW_VERSION ".bin"
1010#define TPSRAM_VERSION __stringify(TP_VERSION_MAJOR) "." \
1011 __stringify(TP_VERSION_MINOR) "." __stringify(TP_VERSION_MICRO)
1012#define TPSRAM_NAME "cxgb3/t3%c_psram-" TPSRAM_VERSION ".bin"
2e8c07c3
DLR		 1013#define AEL2005_OPT_EDC_NAME "cxgb3/ael2005_opt_edc.bin"
1014#define AEL2005_TWX_EDC_NAME "cxgb3/ael2005_twx_edc.bin"
9450526a 1015#define AEL2020_TWX_EDC_NAME "cxgb3/ael2020_twx_edc.bin"
34336ec0
BH		 1016MODULE_FIRMWARE(FW_FNAME);
1017MODULE_FIRMWARE("cxgb3/t3b_psram-" TPSRAM_VERSION ".bin");
1018MODULE_FIRMWARE("cxgb3/t3c_psram-" TPSRAM_VERSION ".bin");
1019MODULE_FIRMWARE(AEL2005_OPT_EDC_NAME);
1020MODULE_FIRMWARE(AEL2005_TWX_EDC_NAME);
1021MODULE_FIRMWARE(AEL2020_TWX_EDC_NAME);
2e8c07c3
DLR		 1022
1023static inline const char *get_edc_fw_name(int edc_idx)
1024{
1025 const char *fw_name = NULL;
1026
1027 switch (edc_idx) {
1028 case EDC_OPT_AEL2005:
1029 fw_name = AEL2005_OPT_EDC_NAME;
1030 break;
1031 case EDC_TWX_AEL2005:
1032 fw_name = AEL2005_TWX_EDC_NAME;
1033 break;
1034 case EDC_TWX_AEL2020:
1035 fw_name = AEL2020_TWX_EDC_NAME;
1036 break;
1037 }
1038 return fw_name;
1039}
1040
1041int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size)
1042{
1043 struct adapter *adapter = phy->adapter;
1044 const struct firmware *fw;
1045 char buf[64];
1046 u32 csum;
1047 const __be32 *p;
1048 u16 *cache = phy->phy_cache;
1049 int i, ret;
1050
1051 snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx));
1052
1053 ret = request_firmware(&fw, buf, &adapter->pdev->dev);
1054 if (ret < 0) {
1055 dev_err(&adapter->pdev->dev,
1056 "could not upgrade firmware: unable to load %s\n",
1057 buf);
1058 return ret;
1059 }
1060
1061 /* check size, take checksum in account */
1062 if (fw->size > size + 4) {
1063 CH_ERR(adapter, "firmware image too large %u, expected %d\n",
1064 (unsigned int)fw->size, size + 4);
1065 ret = -EINVAL;
1066 }
1067
1068 /* compute checksum */
1069 p = (const __be32 *)fw->data;
1070 for (csum = 0, i = 0; i < fw->size / sizeof(csum); i++)
1071 csum += ntohl(p[i]);
1072
1073 if (csum != 0xffffffff) {
1074 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1075 csum);
1076 ret = -EINVAL;
1077 }
1078
1079 for (i = 0; i < size / 4 ; i++) {
1080 *cache++ = (be32_to_cpu(p[i]) & 0xffff0000) >> 16;
1081 *cache++ = be32_to_cpu(p[i]) & 0xffff;
1082 }
1083
1084 release_firmware(fw);
1085
1086 return ret;
1087}
2e283962
DLR		 1088
1089static int upgrade_fw(struct adapter *adap)
1090{
1091 int ret;
2e283962
DLR		 1092 const struct firmware *fw;
1093 struct device *dev = &adap->pdev->dev;
1094
34336ec0 1095 ret = request_firmware(&fw, FW_FNAME, dev);
2e283962
DLR		 1096 if (ret < 0) {
1097 dev_err(dev, "could not upgrade firmware: unable to load %s\n",
34336ec0 1098 FW_FNAME);
2e283962
DLR		 1099 return ret;
1100 }
1101 ret = t3_load_fw(adap, fw->data, fw->size);
1102 release_firmware(fw);
47330077
DLR		 1103
1104 if (ret == 0)
1105 dev_info(dev, "successful upgrade to firmware %d.%d.%d\n",
1106 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
1107 else
1108 dev_err(dev, "failed to upgrade to firmware %d.%d.%d\n",
1109 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
2eab17ab 1110
47330077
DLR		 1111 return ret;
1112}
1113
1114static inline char t3rev2char(struct adapter *adapter)
1115{
1116 char rev = 0;
1117
1118 switch(adapter->params.rev) {
1119 case T3_REV_B:
1120 case T3_REV_B2:
1121 rev = 'b';
1122 break;
1aafee26
DLR		 1123 case T3_REV_C:
1124 rev = 'c';
1125 break;
47330077
DLR		 1126 }
1127 return rev;
1128}
1129
9265fabf 1130static int update_tpsram(struct adapter *adap)
47330077
DLR		 1131{
1132 const struct firmware *tpsram;
1133 char buf[64];
1134 struct device *dev = &adap->pdev->dev;
1135 int ret;
1136 char rev;
2eab17ab 1137
47330077
DLR		 1138 rev = t3rev2char(adap);
1139 if (!rev)
1140 return 0;
1141
34336ec0 1142 snprintf(buf, sizeof(buf), TPSRAM_NAME, rev);
47330077
DLR		 1143
1144 ret = request_firmware(&tpsram, buf, dev);
1145 if (ret < 0) {
1146 dev_err(dev, "could not load TP SRAM: unable to load %s\n",
1147 buf);
1148 return ret;
1149 }
2eab17ab 1150
47330077
DLR		 1151 ret = t3_check_tpsram(adap, tpsram->data, tpsram->size);
1152 if (ret)
2eab17ab 1153 goto release_tpsram;
47330077
DLR		 1154
1155 ret = t3_set_proto_sram(adap, tpsram->data);
1156 if (ret == 0)
1157 dev_info(dev,
1158 "successful update of protocol engine "
1159 "to %d.%d.%d\n",
1160 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1161 else
1162 dev_err(dev, "failed to update of protocol engine %d.%d.%d\n",
1163 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1164 if (ret)
1165 dev_err(dev, "loading protocol SRAM failed\n");
1166
1167release_tpsram:
1168 release_firmware(tpsram);
2eab17ab 1169
2e283962
DLR		 1170 return ret;
1171}
1172
4d22de3e
DLR		 1173/**
1174 * cxgb_up - enable the adapter
1175 * @adapter: adapter being enabled
1176 *
1177 * Called when the first port is enabled, this function performs the
1178 * actions necessary to make an adapter operational, such as completing
1179 * the initialization of HW modules, and enabling interrupts.
1180 *
1181 * Must be called with the rtnl lock held.
1182 */
1183static int cxgb_up(struct adapter *adap)
1184{
c54f5c24 1185 int err;
4d22de3e
DLR		 1186
1187 if (!(adap->flags & FULL_INIT_DONE)) {
8207befa 1188 err = t3_check_fw_version(adap);
a5a3b460 1189 if (err == -EINVAL) {
2e283962 1190 err = upgrade_fw(adap);
8207befa
DLR		 1191 CH_WARN(adap, "FW upgrade to %d.%d.%d %s\n",
1192 FW_VERSION_MAJOR, FW_VERSION_MINOR,
1193 FW_VERSION_MICRO, err ? "failed" : "succeeded");
a5a3b460 1194 }
4d22de3e 1195
8207befa 1196 err = t3_check_tpsram_version(adap);
47330077
DLR		 1197 if (err == -EINVAL) {
1198 err = update_tpsram(adap);
8207befa
DLR		 1199 CH_WARN(adap, "TP upgrade to %d.%d.%d %s\n",
1200 TP_VERSION_MAJOR, TP_VERSION_MINOR,
1201 TP_VERSION_MICRO, err ? "failed" : "succeeded");
47330077
DLR		 1202 }
1203
20d3fc11
DLR		 1204 /*
1205 * Clear interrupts now to catch errors if t3_init_hw fails.
1206 * We clear them again later as initialization may trigger
1207 * conditions that can interrupt.
1208 */
1209 t3_intr_clear(adap);
1210
4d22de3e
DLR		 1211 err = t3_init_hw(adap, 0);
1212 if (err)
1213 goto out;
1214
b881955b 1215 t3_set_reg_field(adap, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
6cdbd77e 1216 t3_write_reg(adap, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
bea3348e 1217
4d22de3e
DLR		 1218 err = setup_sge_qsets(adap);
1219 if (err)
1220 goto out;
1221
1222 setup_rss(adap);
48c4b6db
DLR		 1223 if (!(adap->flags & NAPI_INIT))
1224 init_napi(adap);
31563789
DLR		 1225
1226 t3_start_sge_timers(adap);
4d22de3e
DLR		 1227 adap->flags |= FULL_INIT_DONE;
1228 }
1229
1230 t3_intr_clear(adap);
1231
1232 if (adap->flags & USING_MSIX) {
1233 name_msix_vecs(adap);
1234 err = request_irq(adap->msix_info[0].vec,
1235 t3_async_intr_handler, 0,
1236 adap->msix_info[0].desc, adap);
1237 if (err)
1238 goto irq_err;
1239
42256f57
DLR		 1240 err = request_msix_data_irqs(adap);
1241 if (err) {
4d22de3e
DLR		 1242 free_irq(adap->msix_info[0].vec, adap);
1243 goto irq_err;
1244 }
1245 } else if ((err = request_irq(adap->pdev->irq,
1246 t3_intr_handler(adap,
1247 adap->sge.qs[0].rspq.
1248 polling),
2db6346f
TG		 1249 (adap->flags & USING_MSI) ?
1250 0 : IRQF_SHARED,
4d22de3e
DLR		 1251 adap->name, adap)))
1252 goto irq_err;
1253
bea3348e 1254 enable_all_napi(adap);
4d22de3e
DLR		 1255 t3_sge_start(adap);
1256 t3_intr_enable(adap);
14ab9892 1257
b881955b
DLR		 1258 if (adap->params.rev >= T3_REV_C && !(adap->flags & TP_PARITY_INIT) &&
1259 is_offload(adap) && init_tp_parity(adap) == 0)
1260 adap->flags |= TP_PARITY_INIT;
1261
1262 if (adap->flags & TP_PARITY_INIT) {
1263 t3_write_reg(adap, A_TP_INT_CAUSE,
1264 F_CMCACHEPERR | F_ARPLUTPERR);
1265 t3_write_reg(adap, A_TP_INT_ENABLE, 0x7fbfffff);
1266 }
1267
8c263761
DLR		 1268 if (!(adap->flags & QUEUES_BOUND)) {
1269 err = bind_qsets(adap);
1270 if (err) {
1271 CH_ERR(adap, "failed to bind qsets, err %d\n", err);
1272 t3_intr_disable(adap);
1273 free_irq_resources(adap);
1274 goto out;
1275 }
1276 adap->flags |= QUEUES_BOUND;
1277 }
14ab9892 1278
4d22de3e
DLR		 1279out:
1280 return err;
1281irq_err:
1282 CH_ERR(adap, "request_irq failed, err %d\n", err);
1283 goto out;
1284}
1285
1286/*
1287 * Release resources when all the ports and offloading have been stopped.
1288 */
55bc3228 1289static void cxgb_down(struct adapter *adapter, int on_wq)
4d22de3e
DLR		 1290{
1291 t3_sge_stop(adapter);
1292 spin_lock_irq(&adapter->work_lock); /* sync with PHY intr task */
1293 t3_intr_disable(adapter);
1294 spin_unlock_irq(&adapter->work_lock);
1295
8c263761 1296 free_irq_resources(adapter);
4d22de3e 1297 quiesce_rx(adapter);
a6f018e3 1298 t3_sge_stop(adapter);
55bc3228
CL		 1299 if (!on_wq)
1300 flush_workqueue(cxgb3_wq);/* wait for external IRQ handler */
4d22de3e
DLR		 1301}
1302
1303static void schedule_chk_task(struct adapter *adap)
1304{
1305 unsigned int timeo;
1306
1307 timeo = adap->params.linkpoll_period ?
1308 (HZ * adap->params.linkpoll_period) / 10 :
1309 adap->params.stats_update_period * HZ;
1310 if (timeo)
1311 queue_delayed_work(cxgb3_wq, &adap->adap_check_task, timeo);
1312}
1313
1314static int offload_open(struct net_device *dev)
1315{
5fbf816f
DLR		 1316 struct port_info *pi = netdev_priv(dev);
1317 struct adapter *adapter = pi->adapter;
1318 struct t3cdev *tdev = dev2t3cdev(dev);
4d22de3e 1319 int adap_up = adapter->open_device_map & PORT_MASK;
c54f5c24 1320 int err;
4d22de3e
DLR		 1321
1322 if (test_and_set_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1323 return 0;
1324
1325 if (!adap_up && (err = cxgb_up(adapter)) < 0)
48c4b6db 1326 goto out;
4d22de3e
DLR		 1327
1328 t3_tp_set_offload_mode(adapter, 1);
1329 tdev->lldev = adapter->port[0];
1330 err = cxgb3_offload_activate(adapter);
1331 if (err)
1332 goto out;
1333
1334 init_port_mtus(adapter);
1335 t3_load_mtus(adapter, adapter->params.mtus, adapter->params.a_wnd,
1336 adapter->params.b_wnd,
1337 adapter->params.rev == 0 ?
1338 adapter->port[0]->mtu : 0xffff);
1339 init_smt(adapter);
1340
d96a51f6
DN		 1341 if (sysfs_create_group(&tdev->lldev->dev.kobj, &offload_attr_group))
1342 dev_dbg(&dev->dev, "cannot create sysfs group\n");
4d22de3e
DLR		 1343
1344 /* Call back all registered clients */
1345 cxgb3_add_clients(tdev);
1346
1347out:
1348 /* restore them in case the offload module has changed them */
1349 if (err) {
1350 t3_tp_set_offload_mode(adapter, 0);
1351 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1352 cxgb3_set_dummy_ops(tdev);
1353 }
1354 return err;
1355}
1356
1357static int offload_close(struct t3cdev *tdev)
1358{
1359 struct adapter *adapter = tdev2adap(tdev);
1360
1361 if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
1362 return 0;
1363
1364 /* Call back all registered clients */
1365 cxgb3_remove_clients(tdev);
1366
0ee8d33c 1367 sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
4d22de3e 1368
c80b0c28
DLR		 1369 /* Flush work scheduled while releasing TIDs */
1370 flush_scheduled_work();
1371
4d22de3e
DLR		 1372 tdev->lldev = NULL;
1373 cxgb3_set_dummy_ops(tdev);
1374 t3_tp_set_offload_mode(adapter, 0);
1375 clear_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
1376
1377 if (!adapter->open_device_map)
55bc3228 1378 cxgb_down(adapter, 0);
4d22de3e
DLR		 1379
1380 cxgb3_offload_deactivate(adapter);
1381 return 0;
1382}
1383
1384static int cxgb_open(struct net_device *dev)
1385{
4d22de3e 1386 struct port_info *pi = netdev_priv(dev);
5fbf816f 1387 struct adapter *adapter = pi->adapter;
4d22de3e 1388 int other_ports = adapter->open_device_map & PORT_MASK;
5fbf816f 1389 int err;
4d22de3e 1390
48c4b6db 1391 if (!adapter->open_device_map && (err = cxgb_up(adapter)) < 0)
4d22de3e
DLR		 1392 return err;
1393
1394 set_bit(pi->port_id, &adapter->open_device_map);
8ac3ba68 1395 if (is_offload(adapter) && !ofld_disable) {
4d22de3e
DLR		 1396 err = offload_open(dev);
1397 if (err)
1398 printk(KERN_WARNING
1399 "Could not initialize offload capabilities\n");
1400 }
1401
82ad3329 1402 dev->real_num_tx_queues = pi->nqsets;
4d22de3e
DLR		 1403 link_start(dev);
1404 t3_port_intr_enable(adapter, pi->port_id);
82ad3329 1405 netif_tx_start_all_queues(dev);
4d22de3e
DLR		 1406 if (!other_ports)
1407 schedule_chk_task(adapter);
1408
fa0d4c11 1409 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_UP, pi->port_id);
4d22de3e
DLR		 1410 return 0;
1411}
1412
55bc3228 1413static int __cxgb_close(struct net_device *dev, int on_wq)
4d22de3e 1414{
5fbf816f
DLR		 1415 struct port_info *pi = netdev_priv(dev);
1416 struct adapter *adapter = pi->adapter;
4d22de3e 1417
e8d19370
DLR		 1418
1419 if (!adapter->open_device_map)
1420 return 0;
1421
bf792094
DLR		 1422 /* Stop link fault interrupts */
1423 t3_xgm_intr_disable(adapter, pi->port_id);
1424 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1425
5fbf816f 1426 t3_port_intr_disable(adapter, pi->port_id);
82ad3329 1427 netif_tx_stop_all_queues(dev);
5fbf816f 1428 pi->phy.ops->power_down(&pi->phy, 1);
4d22de3e 1429 netif_carrier_off(dev);
5fbf816f 1430 t3_mac_disable(&pi->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
4d22de3e 1431
20d3fc11 1432 spin_lock_irq(&adapter->work_lock); /* sync with update task */
5fbf816f 1433 clear_bit(pi->port_id, &adapter->open_device_map);
20d3fc11 1434 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 1435
1436 if (!(adapter->open_device_map & PORT_MASK))
c80b0c28 1437 cancel_delayed_work_sync(&adapter->adap_check_task);
4d22de3e
DLR		 1438
1439 if (!adapter->open_device_map)
55bc3228 1440 cxgb_down(adapter, on_wq);
4d22de3e 1441
fa0d4c11 1442 cxgb3_event_notify(&adapter->tdev, OFFLOAD_PORT_DOWN, pi->port_id);
4d22de3e
DLR		 1443 return 0;
1444}
1445
55bc3228
CL		 1446static int cxgb_close(struct net_device *dev)
1447{
1448 return __cxgb_close(dev, 0);
1449}
1450
4d22de3e
DLR		 1451static struct net_device_stats *cxgb_get_stats(struct net_device *dev)
1452{
5fbf816f
DLR		 1453 struct port_info *pi = netdev_priv(dev);
1454 struct adapter *adapter = pi->adapter;
1455 struct net_device_stats *ns = &pi->netstats;
4d22de3e
DLR		 1456 const struct mac_stats *pstats;
1457
1458 spin_lock(&adapter->stats_lock);
5fbf816f 1459 pstats = t3_mac_update_stats(&pi->mac);
4d22de3e
DLR		 1460 spin_unlock(&adapter->stats_lock);
1461
1462 ns->tx_bytes = pstats->tx_octets;
1463 ns->tx_packets = pstats->tx_frames;
1464 ns->rx_bytes = pstats->rx_octets;
1465 ns->rx_packets = pstats->rx_frames;
1466 ns->multicast = pstats->rx_mcast_frames;
1467
1468 ns->tx_errors = pstats->tx_underrun;
1469 ns->rx_errors = pstats->rx_symbol_errs + pstats->rx_fcs_errs +
1470 pstats->rx_too_long + pstats->rx_jabber + pstats->rx_short +
1471 pstats->rx_fifo_ovfl;
1472
1473 /* detailed rx_errors */
1474 ns->rx_length_errors = pstats->rx_jabber + pstats->rx_too_long;
1475 ns->rx_over_errors = 0;
1476 ns->rx_crc_errors = pstats->rx_fcs_errs;
1477 ns->rx_frame_errors = pstats->rx_symbol_errs;
1478 ns->rx_fifo_errors = pstats->rx_fifo_ovfl;
1479 ns->rx_missed_errors = pstats->rx_cong_drops;
1480
1481 /* detailed tx_errors */
1482 ns->tx_aborted_errors = 0;
1483 ns->tx_carrier_errors = 0;
1484 ns->tx_fifo_errors = pstats->tx_underrun;
1485 ns->tx_heartbeat_errors = 0;
1486 ns->tx_window_errors = 0;
1487 return ns;
1488}
1489
1490static u32 get_msglevel(struct net_device *dev)
1491{
5fbf816f
DLR		 1492 struct port_info *pi = netdev_priv(dev);
1493 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1494
1495 return adapter->msg_enable;
1496}
1497
1498static void set_msglevel(struct net_device *dev, u32 val)
1499{
5fbf816f
DLR		 1500 struct port_info *pi = netdev_priv(dev);
1501 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1502
1503 adapter->msg_enable = val;
1504}
1505
1506static char stats_strings[][ETH_GSTRING_LEN] = {
1507 "TxOctetsOK ",
1508 "TxFramesOK ",
1509 "TxMulticastFramesOK",
1510 "TxBroadcastFramesOK",
1511 "TxPauseFrames ",
1512 "TxUnderrun ",
1513 "TxExtUnderrun ",
1514
1515 "TxFrames64 ",
1516 "TxFrames65To127 ",
1517 "TxFrames128To255 ",
1518 "TxFrames256To511 ",
1519 "TxFrames512To1023 ",
1520 "TxFrames1024To1518 ",
1521 "TxFrames1519ToMax ",
1522
1523 "RxOctetsOK ",
1524 "RxFramesOK ",
1525 "RxMulticastFramesOK",
1526 "RxBroadcastFramesOK",
1527 "RxPauseFrames ",
1528 "RxFCSErrors ",
1529 "RxSymbolErrors ",
1530 "RxShortErrors ",
1531 "RxJabberErrors ",
1532 "RxLengthErrors ",
1533 "RxFIFOoverflow ",
1534
1535 "RxFrames64 ",
1536 "RxFrames65To127 ",
1537 "RxFrames128To255 ",
1538 "RxFrames256To511 ",
1539 "RxFrames512To1023 ",
1540 "RxFrames1024To1518 ",
1541 "RxFrames1519ToMax ",
1542
1543 "PhyFIFOErrors ",
1544 "TSO ",
1545 "VLANextractions ",
1546 "VLANinsertions ",
1547 "TxCsumOffload ",
1548 "RxCsumGood ",
b47385bd
DLR		 1549 "LroAggregated ",
1550 "LroFlushed ",
1551 "LroNoDesc ",
fc90664e
DLR		 1552 "RxDrops ",
1553
1554 "CheckTXEnToggled ",
1555 "CheckResets ",
1556
bf792094 1557 "LinkFaults ",
4d22de3e
DLR		 1558};
1559
b9f2c044 1560static int get_sset_count(struct net_device *dev, int sset)
4d22de3e 1561{
b9f2c044
JG		 1562 switch (sset) {
1563 case ETH_SS_STATS:
1564 return ARRAY_SIZE(stats_strings);
1565 default:
1566 return -EOPNOTSUPP;
1567 }
4d22de3e
DLR		 1568}
1569
1570#define T3_REGMAP_SIZE (3 * 1024)
1571
1572static int get_regs_len(struct net_device *dev)
1573{
1574 return T3_REGMAP_SIZE;
1575}
1576
1577static int get_eeprom_len(struct net_device *dev)
1578{
1579 return EEPROMSIZE;
1580}
1581
1582static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1583{
5fbf816f
DLR		 1584 struct port_info *pi = netdev_priv(dev);
1585 struct adapter *adapter = pi->adapter;
4d22de3e 1586 u32 fw_vers = 0;
47330077 1587 u32 tp_vers = 0;
4d22de3e 1588
cf3760da 1589 spin_lock(&adapter->stats_lock);
4d22de3e 1590 t3_get_fw_version(adapter, &fw_vers);
47330077 1591 t3_get_tp_version(adapter, &tp_vers);
cf3760da 1592 spin_unlock(&adapter->stats_lock);
4d22de3e
DLR		 1593
1594 strcpy(info->driver, DRV_NAME);
1595 strcpy(info->version, DRV_VERSION);
1596 strcpy(info->bus_info, pci_name(adapter->pdev));
1597 if (!fw_vers)
1598 strcpy(info->fw_version, "N/A");
4aac3899 1599 else {
4d22de3e 1600 snprintf(info->fw_version, sizeof(info->fw_version),
47330077 1601 "%s %u.%u.%u TP %u.%u.%u",
4aac3899
DLR		 1602 G_FW_VERSION_TYPE(fw_vers) ? "T" : "N",
1603 G_FW_VERSION_MAJOR(fw_vers),
1604 G_FW_VERSION_MINOR(fw_vers),
47330077
DLR		 1605 G_FW_VERSION_MICRO(fw_vers),
1606 G_TP_VERSION_MAJOR(tp_vers),
1607 G_TP_VERSION_MINOR(tp_vers),
1608 G_TP_VERSION_MICRO(tp_vers));
4aac3899 1609 }
4d22de3e
DLR		 1610}
1611
1612static void get_strings(struct net_device *dev, u32 stringset, u8 * data)
1613{
1614 if (stringset == ETH_SS_STATS)
1615 memcpy(data, stats_strings, sizeof(stats_strings));
1616}
1617
1618static unsigned long collect_sge_port_stats(struct adapter *adapter,
1619 struct port_info *p, int idx)
1620{
1621 int i;
1622 unsigned long tot = 0;
1623
8c263761
DLR		 1624 for (i = p->first_qset; i < p->first_qset + p->nqsets; ++i)
1625 tot += adapter->sge.qs[i].port_stats[idx];
4d22de3e
DLR		 1626 return tot;
1627}
1628
1629static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1630 u64 *data)
1631{
4d22de3e 1632 struct port_info *pi = netdev_priv(dev);
5fbf816f 1633 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1634 const struct mac_stats *s;
1635
1636 spin_lock(&adapter->stats_lock);
1637 s = t3_mac_update_stats(&pi->mac);
1638 spin_unlock(&adapter->stats_lock);
1639
1640 *data++ = s->tx_octets;
1641 *data++ = s->tx_frames;
1642 *data++ = s->tx_mcast_frames;
1643 *data++ = s->tx_bcast_frames;
1644 *data++ = s->tx_pause;
1645 *data++ = s->tx_underrun;
1646 *data++ = s->tx_fifo_urun;
1647
1648 *data++ = s->tx_frames_64;
1649 *data++ = s->tx_frames_65_127;
1650 *data++ = s->tx_frames_128_255;
1651 *data++ = s->tx_frames_256_511;
1652 *data++ = s->tx_frames_512_1023;
1653 *data++ = s->tx_frames_1024_1518;
1654 *data++ = s->tx_frames_1519_max;
1655
1656 *data++ = s->rx_octets;
1657 *data++ = s->rx_frames;
1658 *data++ = s->rx_mcast_frames;
1659 *data++ = s->rx_bcast_frames;
1660 *data++ = s->rx_pause;
1661 *data++ = s->rx_fcs_errs;
1662 *data++ = s->rx_symbol_errs;
1663 *data++ = s->rx_short;
1664 *data++ = s->rx_jabber;
1665 *data++ = s->rx_too_long;
1666 *data++ = s->rx_fifo_ovfl;
1667
1668 *data++ = s->rx_frames_64;
1669 *data++ = s->rx_frames_65_127;
1670 *data++ = s->rx_frames_128_255;
1671 *data++ = s->rx_frames_256_511;
1672 *data++ = s->rx_frames_512_1023;
1673 *data++ = s->rx_frames_1024_1518;
1674 *data++ = s->rx_frames_1519_max;
1675
1676 *data++ = pi->phy.fifo_errors;
1677
1678 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TSO);
1679 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANEX);
1680 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_VLANINS);
1681 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_TX_CSUM);
1682 *data++ = collect_sge_port_stats(adapter, pi, SGE_PSTAT_RX_CSUM_GOOD);
7be2df45
HX		 1683 *data++ = 0;
1684 *data++ = 0;
1685 *data++ = 0;
4d22de3e 1686 *data++ = s->rx_cong_drops;
fc90664e
DLR		 1687
1688 *data++ = s->num_toggled;
1689 *data++ = s->num_resets;
bf792094
DLR		 1690
1691 *data++ = s->link_faults;
4d22de3e
DLR		 1692}
1693
1694static inline void reg_block_dump(struct adapter *ap, void *buf,
1695 unsigned int start, unsigned int end)
1696{
1697 u32 *p = buf + start;
1698
1699 for (; start <= end; start += sizeof(u32))
1700 *p++ = t3_read_reg(ap, start);
1701}
1702
1703static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1704 void *buf)
1705{
5fbf816f
DLR		 1706 struct port_info *pi = netdev_priv(dev);
1707 struct adapter *ap = pi->adapter;
4d22de3e
DLR		 1708
1709 /*
1710 * Version scheme:
1711 * bits 0..9: chip version
1712 * bits 10..15: chip revision
1713 * bit 31: set for PCIe cards
1714 */
1715 regs->version = 3 | (ap->params.rev << 10) | (is_pcie(ap) << 31);
1716
1717 /*
1718 * We skip the MAC statistics registers because they are clear-on-read.
1719 * Also reading multi-register stats would need to synchronize with the
1720 * periodic mac stats accumulation. Hard to justify the complexity.
1721 */
1722 memset(buf, 0, T3_REGMAP_SIZE);
1723 reg_block_dump(ap, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
1724 reg_block_dump(ap, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
1725 reg_block_dump(ap, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
1726 reg_block_dump(ap, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
1727 reg_block_dump(ap, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
1728 reg_block_dump(ap, buf, A_XGM_SERDES_STATUS0,
1729 XGM_REG(A_XGM_SERDES_STAT3, 1));
1730 reg_block_dump(ap, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
1731 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
1732}
1733
1734static int restart_autoneg(struct net_device *dev)
1735{
1736 struct port_info *p = netdev_priv(dev);
1737
1738 if (!netif_running(dev))
1739 return -EAGAIN;
1740 if (p->link_config.autoneg != AUTONEG_ENABLE)
1741 return -EINVAL;
1742 p->phy.ops->autoneg_restart(&p->phy);
1743 return 0;
1744}
1745
1746static int cxgb3_phys_id(struct net_device *dev, u32 data)
1747{
5fbf816f
DLR		 1748 struct port_info *pi = netdev_priv(dev);
1749 struct adapter *adapter = pi->adapter;
4d22de3e 1750 int i;
4d22de3e
DLR		 1751
1752 if (data == 0)
1753 data = 2;
1754
1755 for (i = 0; i < data * 2; i++) {
1756 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1757 (i & 1) ? F_GPIO0_OUT_VAL : 0);
1758 if (msleep_interruptible(500))
1759 break;
1760 }
1761 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
1762 F_GPIO0_OUT_VAL);
1763 return 0;
1764}
1765
1766static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1767{
1768 struct port_info *p = netdev_priv(dev);
1769
1770 cmd->supported = p->link_config.supported;
1771 cmd->advertising = p->link_config.advertising;
1772
1773 if (netif_carrier_ok(dev)) {
1774 cmd->speed = p->link_config.speed;
1775 cmd->duplex = p->link_config.duplex;
1776 } else {
1777 cmd->speed = -1;
1778 cmd->duplex = -1;
1779 }
1780
1781 cmd->port = (cmd->supported & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
0f07c4ee 1782 cmd->phy_address = p->phy.mdio.prtad;
4d22de3e
DLR		 1783 cmd->transceiver = XCVR_EXTERNAL;
1784 cmd->autoneg = p->link_config.autoneg;
1785 cmd->maxtxpkt = 0;
1786 cmd->maxrxpkt = 0;
1787 return 0;
1788}
1789
1790static int speed_duplex_to_caps(int speed, int duplex)
1791{
1792 int cap = 0;
1793
1794 switch (speed) {
1795 case SPEED_10:
1796 if (duplex == DUPLEX_FULL)
1797 cap = SUPPORTED_10baseT_Full;
1798 else
1799 cap = SUPPORTED_10baseT_Half;
1800 break;
1801 case SPEED_100:
1802 if (duplex == DUPLEX_FULL)
1803 cap = SUPPORTED_100baseT_Full;
1804 else
1805 cap = SUPPORTED_100baseT_Half;
1806 break;
1807 case SPEED_1000:
1808 if (duplex == DUPLEX_FULL)
1809 cap = SUPPORTED_1000baseT_Full;
1810 else
1811 cap = SUPPORTED_1000baseT_Half;
1812 break;
1813 case SPEED_10000:
1814 if (duplex == DUPLEX_FULL)
1815 cap = SUPPORTED_10000baseT_Full;
1816 }
1817 return cap;
1818}
1819
1820#define ADVERTISED_MASK (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1821 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1822 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | \
1823 ADVERTISED_10000baseT_Full)
1824
1825static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1826{
1827 struct port_info *p = netdev_priv(dev);
1828 struct link_config *lc = &p->link_config;
1829
9b1e3656
DLR		 1830 if (!(lc->supported & SUPPORTED_Autoneg)) {
1831 /*
1832 * PHY offers a single speed/duplex. See if that's what's
1833 * being requested.
1834 */
1835 if (cmd->autoneg == AUTONEG_DISABLE) {
97915b5b 1836 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
9b1e3656
DLR		 1837 if (lc->supported & cap)
1838 return 0;
1839 }
1840 return -EINVAL;
1841 }
4d22de3e
DLR		 1842
1843 if (cmd->autoneg == AUTONEG_DISABLE) {
1844 int cap = speed_duplex_to_caps(cmd->speed, cmd->duplex);
1845
1846 if (!(lc->supported & cap) || cmd->speed == SPEED_1000)
1847 return -EINVAL;
1848 lc->requested_speed = cmd->speed;
1849 lc->requested_duplex = cmd->duplex;
1850 lc->advertising = 0;
1851 } else {
1852 cmd->advertising &= ADVERTISED_MASK;
1853 cmd->advertising &= lc->supported;
1854 if (!cmd->advertising)
1855 return -EINVAL;
1856 lc->requested_speed = SPEED_INVALID;
1857 lc->requested_duplex = DUPLEX_INVALID;
1858 lc->advertising = cmd->advertising | ADVERTISED_Autoneg;
1859 }
1860 lc->autoneg = cmd->autoneg;
1861 if (netif_running(dev))
1862 t3_link_start(&p->phy, &p->mac, lc);
1863 return 0;
1864}
1865
1866static void get_pauseparam(struct net_device *dev,
1867 struct ethtool_pauseparam *epause)
1868{
1869 struct port_info *p = netdev_priv(dev);
1870
1871 epause->autoneg = (p->link_config.requested_fc & PAUSE_AUTONEG) != 0;
1872 epause->rx_pause = (p->link_config.fc & PAUSE_RX) != 0;
1873 epause->tx_pause = (p->link_config.fc & PAUSE_TX) != 0;
1874}
1875
1876static int set_pauseparam(struct net_device *dev,
1877 struct ethtool_pauseparam *epause)
1878{
1879 struct port_info *p = netdev_priv(dev);
1880 struct link_config *lc = &p->link_config;
1881
1882 if (epause->autoneg == AUTONEG_DISABLE)
1883 lc->requested_fc = 0;
1884 else if (lc->supported & SUPPORTED_Autoneg)
1885 lc->requested_fc = PAUSE_AUTONEG;
1886 else
1887 return -EINVAL;
1888
1889 if (epause->rx_pause)
1890 lc->requested_fc |= PAUSE_RX;
1891 if (epause->tx_pause)
1892 lc->requested_fc |= PAUSE_TX;
1893 if (lc->autoneg == AUTONEG_ENABLE) {
1894 if (netif_running(dev))
1895 t3_link_start(&p->phy, &p->mac, lc);
1896 } else {
1897 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
1898 if (netif_running(dev))
1899 t3_mac_set_speed_duplex_fc(&p->mac, -1, -1, lc->fc);
1900 }
1901 return 0;
1902}
1903
1904static u32 get_rx_csum(struct net_device *dev)
1905{
1906 struct port_info *p = netdev_priv(dev);
1907
47fd23fe 1908 return p->rx_offload & T3_RX_CSUM;
4d22de3e
DLR		 1909}
1910
1911static int set_rx_csum(struct net_device *dev, u32 data)
1912{
1913 struct port_info *p = netdev_priv(dev);
1914
47fd23fe
RD		 1915 if (data) {
1916 p->rx_offload |= T3_RX_CSUM;
1917 } else {
b47385bd
DLR		 1918 int i;
1919
47fd23fe 1920 p->rx_offload &= ~(T3_RX_CSUM | T3_LRO);
04ecb072
DLR		 1921 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++)
1922 set_qset_lro(dev, i, 0);
b47385bd 1923 }
4d22de3e
DLR		 1924 return 0;
1925}
1926
1927static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1928{
5fbf816f
DLR		 1929 struct port_info *pi = netdev_priv(dev);
1930 struct adapter *adapter = pi->adapter;
05b97b30 1931 const struct qset_params *q = &adapter->params.sge.qset[pi->first_qset];
4d22de3e
DLR		 1932
1933 e->rx_max_pending = MAX_RX_BUFFERS;
1934 e->rx_mini_max_pending = 0;
1935 e->rx_jumbo_max_pending = MAX_RX_JUMBO_BUFFERS;
1936 e->tx_max_pending = MAX_TXQ_ENTRIES;
1937
05b97b30
DLR		 1938 e->rx_pending = q->fl_size;
1939 e->rx_mini_pending = q->rspq_size;
1940 e->rx_jumbo_pending = q->jumbo_size;
1941 e->tx_pending = q->txq_size[0];
4d22de3e
DLR		 1942}
1943
1944static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
1945{
5fbf816f
DLR		 1946 struct port_info *pi = netdev_priv(dev);
1947 struct adapter *adapter = pi->adapter;
05b97b30 1948 struct qset_params *q;
5fbf816f 1949 int i;
4d22de3e
DLR		 1950
1951 if (e->rx_pending > MAX_RX_BUFFERS ||
1952 e->rx_jumbo_pending > MAX_RX_JUMBO_BUFFERS ||
1953 e->tx_pending > MAX_TXQ_ENTRIES ||
1954 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1955 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1956 e->rx_pending < MIN_FL_ENTRIES ||
1957 e->rx_jumbo_pending < MIN_FL_ENTRIES ||
1958 e->tx_pending < adapter->params.nports * MIN_TXQ_ENTRIES)
1959 return -EINVAL;
1960
1961 if (adapter->flags & FULL_INIT_DONE)
1962 return -EBUSY;
1963
05b97b30
DLR		 1964 q = &adapter->params.sge.qset[pi->first_qset];
1965 for (i = 0; i < pi->nqsets; ++i, ++q) {
4d22de3e
DLR		 1966 q->rspq_size = e->rx_mini_pending;
1967 q->fl_size = e->rx_pending;
1968 q->jumbo_size = e->rx_jumbo_pending;
1969 q->txq_size[0] = e->tx_pending;
1970 q->txq_size[1] = e->tx_pending;
1971 q->txq_size[2] = e->tx_pending;
1972 }
1973 return 0;
1974}
1975
1976static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1977{
5fbf816f
DLR		 1978 struct port_info *pi = netdev_priv(dev);
1979 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1980 struct qset_params *qsp = &adapter->params.sge.qset[0];
1981 struct sge_qset *qs = &adapter->sge.qs[0];
1982
1983 if (c->rx_coalesce_usecs * 10 > M_NEWTIMER)
1984 return -EINVAL;
1985
1986 qsp->coalesce_usecs = c->rx_coalesce_usecs;
1987 t3_update_qset_coalesce(qs, qsp);
1988 return 0;
1989}
1990
1991static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
1992{
5fbf816f
DLR		 1993 struct port_info *pi = netdev_priv(dev);
1994 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 1995 struct qset_params *q = adapter->params.sge.qset;
1996
1997 c->rx_coalesce_usecs = q->coalesce_usecs;
1998 return 0;
1999}
2000
2001static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2002 u8 * data)
2003{
5fbf816f
DLR		 2004 struct port_info *pi = netdev_priv(dev);
2005 struct adapter *adapter = pi->adapter;
4d22de3e 2006 int i, err = 0;
4d22de3e
DLR		 2007
2008 u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2009 if (!buf)
2010 return -ENOMEM;
2011
2012 e->magic = EEPROM_MAGIC;
2013 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
05e5c116 2014 err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
4d22de3e
DLR		 2015
2016 if (!err)
2017 memcpy(data, buf + e->offset, e->len);
2018 kfree(buf);
2019 return err;
2020}
2021
2022static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2023 u8 * data)
2024{
5fbf816f
DLR		 2025 struct port_info *pi = netdev_priv(dev);
2026 struct adapter *adapter = pi->adapter;
05e5c116
AV		 2027 u32 aligned_offset, aligned_len;
2028 __le32 *p;
4d22de3e 2029 u8 *buf;
c54f5c24 2030 int err;
4d22de3e
DLR		 2031
2032 if (eeprom->magic != EEPROM_MAGIC)
2033 return -EINVAL;
2034
2035 aligned_offset = eeprom->offset & ~3;
2036 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2037
2038 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2039 buf = kmalloc(aligned_len, GFP_KERNEL);
2040 if (!buf)
2041 return -ENOMEM;
05e5c116 2042 err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
4d22de3e
DLR		 2043 if (!err && aligned_len > 4)
2044 err = t3_seeprom_read(adapter,
2045 aligned_offset + aligned_len - 4,
05e5c116 2046 (__le32 *) & buf[aligned_len - 4]);
4d22de3e
DLR		 2047 if (err)
2048 goto out;
2049 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2050 } else
2051 buf = data;
2052
2053 err = t3_seeprom_wp(adapter, 0);
2054 if (err)
2055 goto out;
2056
05e5c116 2057 for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
4d22de3e
DLR		 2058 err = t3_seeprom_write(adapter, aligned_offset, *p);
2059 aligned_offset += 4;
2060 }
2061
2062 if (!err)
2063 err = t3_seeprom_wp(adapter, 1);
2064out:
2065 if (buf != data)
2066 kfree(buf);
2067 return err;
2068}
2069
2070static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2071{
2072 wol->supported = 0;
2073 wol->wolopts = 0;
2074 memset(&wol->sopass, 0, sizeof(wol->sopass));
2075}
2076
2077static const struct ethtool_ops cxgb_ethtool_ops = {
2078 .get_settings = get_settings,
2079 .set_settings = set_settings,
2080 .get_drvinfo = get_drvinfo,
2081 .get_msglevel = get_msglevel,
2082 .set_msglevel = set_msglevel,
2083 .get_ringparam = get_sge_param,
2084 .set_ringparam = set_sge_param,
2085 .get_coalesce = get_coalesce,
2086 .set_coalesce = set_coalesce,
2087 .get_eeprom_len = get_eeprom_len,
2088 .get_eeprom = get_eeprom,
2089 .set_eeprom = set_eeprom,
2090 .get_pauseparam = get_pauseparam,
2091 .set_pauseparam = set_pauseparam,
2092 .get_rx_csum = get_rx_csum,
2093 .set_rx_csum = set_rx_csum,
4d22de3e 2094 .set_tx_csum = ethtool_op_set_tx_csum,
4d22de3e
DLR		 2095 .set_sg = ethtool_op_set_sg,
2096 .get_link = ethtool_op_get_link,
2097 .get_strings = get_strings,
2098 .phys_id = cxgb3_phys_id,
2099 .nway_reset = restart_autoneg,
b9f2c044 2100 .get_sset_count = get_sset_count,
4d22de3e
DLR		 2101 .get_ethtool_stats = get_stats,
2102 .get_regs_len = get_regs_len,
2103 .get_regs = get_regs,
2104 .get_wol = get_wol,
4d22de3e 2105 .set_tso = ethtool_op_set_tso,
4d22de3e
DLR		 2106};
2107
2108static int in_range(int val, int lo, int hi)
2109{
2110 return val < 0 || (val <= hi && val >= lo);
2111}
2112
2113static int cxgb_extension_ioctl(struct net_device *dev, void __user *useraddr)
2114{
5fbf816f
DLR		 2115 struct port_info *pi = netdev_priv(dev);
2116 struct adapter *adapter = pi->adapter;
4d22de3e 2117 u32 cmd;
5fbf816f 2118 int ret;
4d22de3e
DLR		 2119
2120 if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
2121 return -EFAULT;
2122
2123 switch (cmd) {
4d22de3e
DLR		 2124 case CHELSIO_SET_QSET_PARAMS:{
2125 int i;
2126 struct qset_params *q;
2127 struct ch_qset_params t;
8c263761
DLR		 2128 int q1 = pi->first_qset;
2129 int nqsets = pi->nqsets;
4d22de3e
DLR		 2130
2131 if (!capable(CAP_NET_ADMIN))
2132 return -EPERM;
2133 if (copy_from_user(&t, useraddr, sizeof(t)))
2134 return -EFAULT;
2135 if (t.qset_idx >= SGE_QSETS)
2136 return -EINVAL;
2137 if (!in_range(t.intr_lat, 0, M_NEWTIMER) ||
8e95a202
JP		 2138 !in_range(t.cong_thres, 0, 255) ||
2139 !in_range(t.txq_size[0], MIN_TXQ_ENTRIES,
2140 MAX_TXQ_ENTRIES) ||
2141 !in_range(t.txq_size[1], MIN_TXQ_ENTRIES,
2142 MAX_TXQ_ENTRIES) ||
2143 !in_range(t.txq_size[2], MIN_CTRL_TXQ_ENTRIES,
2144 MAX_CTRL_TXQ_ENTRIES) ||
2145 !in_range(t.fl_size[0], MIN_FL_ENTRIES,
2146 MAX_RX_BUFFERS) ||
2147 !in_range(t.fl_size[1], MIN_FL_ENTRIES,
2148 MAX_RX_JUMBO_BUFFERS) ||
2149 !in_range(t.rspq_size, MIN_RSPQ_ENTRIES,
2150 MAX_RSPQ_ENTRIES))
4d22de3e 2151 return -EINVAL;
8c263761
DLR		 2152
2153 if ((adapter->flags & FULL_INIT_DONE) && t.lro > 0)
2154 for_each_port(adapter, i) {
2155 pi = adap2pinfo(adapter, i);
2156 if (t.qset_idx >= pi->first_qset &&
2157 t.qset_idx < pi->first_qset + pi->nqsets &&
47fd23fe 2158 !(pi->rx_offload & T3_RX_CSUM))
8c263761
DLR		 2159 return -EINVAL;
2160 }
2161
4d22de3e
DLR		 2162 if ((adapter->flags & FULL_INIT_DONE) &&
2163 (t.rspq_size >= 0 || t.fl_size[0] >= 0 ||
2164 t.fl_size[1] >= 0 || t.txq_size[0] >= 0 ||
2165 t.txq_size[1] >= 0 || t.txq_size[2] >= 0 ||
2166 t.polling >= 0 || t.cong_thres >= 0))
2167 return -EBUSY;
2168
8c263761
DLR		 2169 /* Allow setting of any available qset when offload enabled */
2170 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2171 q1 = 0;
2172 for_each_port(adapter, i) {
2173 pi = adap2pinfo(adapter, i);
2174 nqsets += pi->first_qset + pi->nqsets;
2175 }
2176 }
2177
2178 if (t.qset_idx < q1)
2179 return -EINVAL;
2180 if (t.qset_idx > q1 + nqsets - 1)
2181 return -EINVAL;
2182
4d22de3e
DLR		 2183 q = &adapter->params.sge.qset[t.qset_idx];
2184
2185 if (t.rspq_size >= 0)
2186 q->rspq_size = t.rspq_size;
2187 if (t.fl_size[0] >= 0)
2188 q->fl_size = t.fl_size[0];
2189 if (t.fl_size[1] >= 0)
2190 q->jumbo_size = t.fl_size[1];
2191 if (t.txq_size[0] >= 0)
2192 q->txq_size[0] = t.txq_size[0];
2193 if (t.txq_size[1] >= 0)
2194 q->txq_size[1] = t.txq_size[1];
2195 if (t.txq_size[2] >= 0)
2196 q->txq_size[2] = t.txq_size[2];
2197 if (t.cong_thres >= 0)
2198 q->cong_thres = t.cong_thres;
2199 if (t.intr_lat >= 0) {
2200 struct sge_qset *qs =
2201 &adapter->sge.qs[t.qset_idx];
2202
2203 q->coalesce_usecs = t.intr_lat;
2204 t3_update_qset_coalesce(qs, q);
2205 }
2206 if (t.polling >= 0) {
2207 if (adapter->flags & USING_MSIX)
2208 q->polling = t.polling;
2209 else {
2210 /* No polling with INTx for T3A */
2211 if (adapter->params.rev == 0 &&
2212 !(adapter->flags & USING_MSI))
2213 t.polling = 0;
2214
2215 for (i = 0; i < SGE_QSETS; i++) {
2216 q = &adapter->params.sge.
2217 qset[i];
2218 q->polling = t.polling;
2219 }
2220 }
2221 }
04ecb072
DLR		 2222 if (t.lro >= 0)
2223 set_qset_lro(dev, t.qset_idx, t.lro);
2224
4d22de3e
DLR		 2225 break;
2226 }
2227 case CHELSIO_GET_QSET_PARAMS:{
2228 struct qset_params *q;
2229 struct ch_qset_params t;
8c263761
DLR		 2230 int q1 = pi->first_qset;
2231 int nqsets = pi->nqsets;
2232 int i;
4d22de3e
DLR		 2233
2234 if (copy_from_user(&t, useraddr, sizeof(t)))
2235 return -EFAULT;
8c263761
DLR		 2236
2237 /* Display qsets for all ports when offload enabled */
2238 if (test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
2239 q1 = 0;
2240 for_each_port(adapter, i) {
2241 pi = adap2pinfo(adapter, i);
2242 nqsets = pi->first_qset + pi->nqsets;
2243 }
2244 }
2245
2246 if (t.qset_idx >= nqsets)
4d22de3e
DLR		 2247 return -EINVAL;
2248
8c263761 2249 q = &adapter->params.sge.qset[q1 + t.qset_idx];
4d22de3e
DLR		 2250 t.rspq_size = q->rspq_size;
2251 t.txq_size[0] = q->txq_size[0];
2252 t.txq_size[1] = q->txq_size[1];
2253 t.txq_size[2] = q->txq_size[2];
2254 t.fl_size[0] = q->fl_size;
2255 t.fl_size[1] = q->jumbo_size;
2256 t.polling = q->polling;
b47385bd 2257 t.lro = q->lro;
4d22de3e
DLR		 2258 t.intr_lat = q->coalesce_usecs;
2259 t.cong_thres = q->cong_thres;
8c263761
DLR		 2260 t.qnum = q1;
2261
2262 if (adapter->flags & USING_MSIX)
2263 t.vector = adapter->msix_info[q1 + t.qset_idx + 1].vec;
2264 else
2265 t.vector = adapter->pdev->irq;
4d22de3e
DLR		 2266
2267 if (copy_to_user(useraddr, &t, sizeof(t)))
2268 return -EFAULT;
2269 break;
2270 }
2271 case CHELSIO_SET_QSET_NUM:{
2272 struct ch_reg edata;
4d22de3e
DLR		 2273 unsigned int i, first_qset = 0, other_qsets = 0;
2274
2275 if (!capable(CAP_NET_ADMIN))
2276 return -EPERM;
2277 if (adapter->flags & FULL_INIT_DONE)
2278 return -EBUSY;
2279 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2280 return -EFAULT;
2281 if (edata.val < 1 ||
2282 (edata.val > 1 && !(adapter->flags & USING_MSIX)))
2283 return -EINVAL;
2284
2285 for_each_port(adapter, i)
2286 if (adapter->port[i] && adapter->port[i] != dev)
2287 other_qsets += adap2pinfo(adapter, i)->nqsets;
2288
2289 if (edata.val + other_qsets > SGE_QSETS)
2290 return -EINVAL;
2291
2292 pi->nqsets = edata.val;
2293
2294 for_each_port(adapter, i)
2295 if (adapter->port[i]) {
2296 pi = adap2pinfo(adapter, i);
2297 pi->first_qset = first_qset;
2298 first_qset += pi->nqsets;
2299 }
2300 break;
2301 }
2302 case CHELSIO_GET_QSET_NUM:{
2303 struct ch_reg edata;
4d22de3e
DLR		 2304
2305 edata.cmd = CHELSIO_GET_QSET_NUM;
2306 edata.val = pi->nqsets;
2307 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2308 return -EFAULT;
2309 break;
2310 }
2311 case CHELSIO_LOAD_FW:{
2312 u8 *fw_data;
2313 struct ch_mem_range t;
2314
1b3aa7af 2315 if (!capable(CAP_SYS_RAWIO))
4d22de3e
DLR		 2316 return -EPERM;
2317 if (copy_from_user(&t, useraddr, sizeof(t)))
2318 return -EFAULT;
1b3aa7af 2319 /* Check t.len sanity ? */
c5dc9a35
JL		 2320 fw_data = memdup_user(useraddr + sizeof(t), t.len);
2321 if (IS_ERR(fw_data))
2322 return PTR_ERR(fw_data);
4d22de3e
DLR		 2323
2324 ret = t3_load_fw(adapter, fw_data, t.len);
2325 kfree(fw_data);
2326 if (ret)
2327 return ret;
2328 break;
2329 }
2330 case CHELSIO_SETMTUTAB:{
2331 struct ch_mtus m;
2332 int i;
2333
2334 if (!is_offload(adapter))
2335 return -EOPNOTSUPP;
2336 if (!capable(CAP_NET_ADMIN))
2337 return -EPERM;
2338 if (offload_running(adapter))
2339 return -EBUSY;
2340 if (copy_from_user(&m, useraddr, sizeof(m)))
2341 return -EFAULT;
2342 if (m.nmtus != NMTUS)
2343 return -EINVAL;
2344 if (m.mtus[0] < 81) /* accommodate SACK */
2345 return -EINVAL;
2346
2347 /* MTUs must be in ascending order */
2348 for (i = 1; i < NMTUS; ++i)
2349 if (m.mtus[i] < m.mtus[i - 1])
2350 return -EINVAL;
2351
2352 memcpy(adapter->params.mtus, m.mtus,
2353 sizeof(adapter->params.mtus));
2354 break;
2355 }
2356 case CHELSIO_GET_PM:{
2357 struct tp_params *p = &adapter->params.tp;
2358 struct ch_pm m = {.cmd = CHELSIO_GET_PM };
2359
2360 if (!is_offload(adapter))
2361 return -EOPNOTSUPP;
2362 m.tx_pg_sz = p->tx_pg_size;
2363 m.tx_num_pg = p->tx_num_pgs;
2364 m.rx_pg_sz = p->rx_pg_size;
2365 m.rx_num_pg = p->rx_num_pgs;
2366 m.pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2367 if (copy_to_user(useraddr, &m, sizeof(m)))
2368 return -EFAULT;
2369 break;
2370 }
2371 case CHELSIO_SET_PM:{
2372 struct ch_pm m;
2373 struct tp_params *p = &adapter->params.tp;
2374
2375 if (!is_offload(adapter))
2376 return -EOPNOTSUPP;
2377 if (!capable(CAP_NET_ADMIN))
2378 return -EPERM;
2379 if (adapter->flags & FULL_INIT_DONE)
2380 return -EBUSY;
2381 if (copy_from_user(&m, useraddr, sizeof(m)))
2382 return -EFAULT;
d9da466a 2383 if (!is_power_of_2(m.rx_pg_sz) ||
2384 !is_power_of_2(m.tx_pg_sz))
4d22de3e
DLR		 2385 return -EINVAL; /* not power of 2 */
2386 if (!(m.rx_pg_sz & 0x14000))
2387 return -EINVAL; /* not 16KB or 64KB */
2388 if (!(m.tx_pg_sz & 0x1554000))
2389 return -EINVAL;
2390 if (m.tx_num_pg == -1)
2391 m.tx_num_pg = p->tx_num_pgs;
2392 if (m.rx_num_pg == -1)
2393 m.rx_num_pg = p->rx_num_pgs;
2394 if (m.tx_num_pg % 24 || m.rx_num_pg % 24)
2395 return -EINVAL;
2396 if (m.rx_num_pg * m.rx_pg_sz > p->chan_rx_size ||
2397 m.tx_num_pg * m.tx_pg_sz > p->chan_tx_size)
2398 return -EINVAL;
2399 p->rx_pg_size = m.rx_pg_sz;
2400 p->tx_pg_size = m.tx_pg_sz;
2401 p->rx_num_pgs = m.rx_num_pg;
2402 p->tx_num_pgs = m.tx_num_pg;
2403 break;
2404 }
2405 case CHELSIO_GET_MEM:{
2406 struct ch_mem_range t;
2407 struct mc7 *mem;
2408 u64 buf[32];
2409
2410 if (!is_offload(adapter))
2411 return -EOPNOTSUPP;
2412 if (!(adapter->flags & FULL_INIT_DONE))
2413 return -EIO; /* need the memory controllers */
2414 if (copy_from_user(&t, useraddr, sizeof(t)))
2415 return -EFAULT;
2416 if ((t.addr & 7) || (t.len & 7))
2417 return -EINVAL;
2418 if (t.mem_id == MEM_CM)
2419 mem = &adapter->cm;
2420 else if (t.mem_id == MEM_PMRX)
2421 mem = &adapter->pmrx;
2422 else if (t.mem_id == MEM_PMTX)
2423 mem = &adapter->pmtx;
2424 else
2425 return -EINVAL;
2426
2427 /*
1825494a
DLR		 2428 * Version scheme:
2429 * bits 0..9: chip version
2430 * bits 10..15: chip revision
2431 */
4d22de3e
DLR		 2432 t.version = 3 | (adapter->params.rev << 10);
2433 if (copy_to_user(useraddr, &t, sizeof(t)))
2434 return -EFAULT;
2435
2436 /*
2437 * Read 256 bytes at a time as len can be large and we don't
2438 * want to use huge intermediate buffers.
2439 */
2440 useraddr += sizeof(t); /* advance to start of buffer */
2441 while (t.len) {
2442 unsigned int chunk =
2443 min_t(unsigned int, t.len, sizeof(buf));
2444
2445 ret =
2446 t3_mc7_bd_read(mem, t.addr / 8, chunk / 8,
2447 buf);
2448 if (ret)
2449 return ret;
2450 if (copy_to_user(useraddr, buf, chunk))
2451 return -EFAULT;
2452 useraddr += chunk;
2453 t.addr += chunk;
2454 t.len -= chunk;
2455 }
2456 break;
2457 }
2458 case CHELSIO_SET_TRACE_FILTER:{
2459 struct ch_trace t;
2460 const struct trace_params *tp;
2461
2462 if (!capable(CAP_NET_ADMIN))
2463 return -EPERM;
2464 if (!offload_running(adapter))
2465 return -EAGAIN;
2466 if (copy_from_user(&t, useraddr, sizeof(t)))
2467 return -EFAULT;
2468
2469 tp = (const struct trace_params *)&t.sip;
2470 if (t.config_tx)
2471 t3_config_trace_filter(adapter, tp, 0,
2472 t.invert_match,
2473 t.trace_tx);
2474 if (t.config_rx)
2475 t3_config_trace_filter(adapter, tp, 1,
2476 t.invert_match,
2477 t.trace_rx);
2478 break;
2479 }
4d22de3e
DLR		 2480 default:
2481 return -EOPNOTSUPP;
2482 }
2483 return 0;
2484}
2485
2486static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2487{
4d22de3e 2488 struct mii_ioctl_data *data = if_mii(req);
5fbf816f
DLR		 2489 struct port_info *pi = netdev_priv(dev);
2490 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2491
2492 switch (cmd) {
0f07c4ee
BH		 2493 case SIOCGMIIREG:
2494 case SIOCSMIIREG:
2495 /* Convert phy_id from older PRTAD/DEVAD format */
2496 if (is_10G(adapter) &&
2497 !mdio_phy_id_is_c45(data->phy_id) &&
2498 (data->phy_id & 0x1f00) &&
2499 !(data->phy_id & 0xe0e0))
2500 data->phy_id = mdio_phy_id_c45(data->phy_id >> 8,
2501 data->phy_id & 0x1f);
4d22de3e 2502 /* FALLTHRU */
0f07c4ee
BH		 2503 case SIOCGMIIPHY:
2504 return mdio_mii_ioctl(&pi->phy.mdio, data, cmd);
4d22de3e
DLR		 2505 case SIOCCHIOCTL:
2506 return cxgb_extension_ioctl(dev, req->ifr_data);
2507 default:
2508 return -EOPNOTSUPP;
2509 }
4d22de3e
DLR		 2510}
2511
2512static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2513{
4d22de3e 2514 struct port_info *pi = netdev_priv(dev);
5fbf816f
DLR		 2515 struct adapter *adapter = pi->adapter;
2516 int ret;
4d22de3e
DLR		 2517
2518 if (new_mtu < 81) /* accommodate SACK */
2519 return -EINVAL;
2520 if ((ret = t3_mac_set_mtu(&pi->mac, new_mtu)))
2521 return ret;
2522 dev->mtu = new_mtu;
2523 init_port_mtus(adapter);
2524 if (adapter->params.rev == 0 && offload_running(adapter))
2525 t3_load_mtus(adapter, adapter->params.mtus,
2526 adapter->params.a_wnd, adapter->params.b_wnd,
2527 adapter->port[0]->mtu);
2528 return 0;
2529}
2530
2531static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2532{
4d22de3e 2533 struct port_info *pi = netdev_priv(dev);
5fbf816f 2534 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2535 struct sockaddr *addr = p;
2536
2537 if (!is_valid_ether_addr(addr->sa_data))
2538 return -EINVAL;
2539
2540 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
f14d42f3 2541 t3_mac_set_address(&pi->mac, LAN_MAC_IDX, dev->dev_addr);
4d22de3e
DLR		 2542 if (offload_running(adapter))
2543 write_smt_entry(adapter, pi->port_id);
2544 return 0;
2545}
2546
2547/**
2548 * t3_synchronize_rx - wait for current Rx processing on a port to complete
2549 * @adap: the adapter
2550 * @p: the port
2551 *
2552 * Ensures that current Rx processing on any of the queues associated with
2553 * the given port completes before returning. We do this by acquiring and
2554 * releasing the locks of the response queues associated with the port.
2555 */
2556static void t3_synchronize_rx(struct adapter *adap, const struct port_info *p)
2557{
2558 int i;
2559
8c263761
DLR		 2560 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
2561 struct sge_rspq *q = &adap->sge.qs[i].rspq;
4d22de3e
DLR		 2562
2563 spin_lock_irq(&q->lock);
2564 spin_unlock_irq(&q->lock);
2565 }
2566}
2567
2568static void vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2569{
4d22de3e 2570 struct port_info *pi = netdev_priv(dev);
5fbf816f 2571 struct adapter *adapter = pi->adapter;
4d22de3e
DLR		 2572
2573 pi->vlan_grp = grp;
2574 if (adapter->params.rev > 0)
2575 t3_set_vlan_accel(adapter, 1 << pi->port_id, grp != NULL);
2576 else {
2577 /* single control for all ports */
2578 unsigned int i, have_vlans = 0;
2579 for_each_port(adapter, i)
2580 have_vlans |= adap2pinfo(adapter, i)->vlan_grp != NULL;
2581
2582 t3_set_vlan_accel(adapter, 1, have_vlans);
2583 }
2584 t3_synchronize_rx(adapter, pi);
2585}
2586
4d22de3e
DLR		 2587#ifdef CONFIG_NET_POLL_CONTROLLER
2588static void cxgb_netpoll(struct net_device *dev)
2589{
890de332 2590 struct port_info *pi = netdev_priv(dev);
5fbf816f 2591 struct adapter *adapter = pi->adapter;
890de332 2592 int qidx;
4d22de3e 2593
890de332
DLR		 2594 for (qidx = pi->first_qset; qidx < pi->first_qset + pi->nqsets; qidx++) {
2595 struct sge_qset *qs = &adapter->sge.qs[qidx];
2596 void *source;
2eab17ab 2597
890de332
DLR		 2598 if (adapter->flags & USING_MSIX)
2599 source = qs;
2600 else
2601 source = adapter;
2602
2603 t3_intr_handler(adapter, qs->rspq.polling) (0, source);
2604 }
4d22de3e
DLR		 2605}
2606#endif
2607
2608/*
2609 * Periodic accumulation of MAC statistics.
2610 */
2611static void mac_stats_update(struct adapter *adapter)
2612{
2613 int i;
2614
2615 for_each_port(adapter, i) {
2616 struct net_device *dev = adapter->port[i];
2617 struct port_info *p = netdev_priv(dev);
2618
2619 if (netif_running(dev)) {
2620 spin_lock(&adapter->stats_lock);
2621 t3_mac_update_stats(&p->mac);
2622 spin_unlock(&adapter->stats_lock);
2623 }
2624 }
2625}
2626
2627static void check_link_status(struct adapter *adapter)
2628{
2629 int i;
2630
2631 for_each_port(adapter, i) {
2632 struct net_device *dev = adapter->port[i];
2633 struct port_info *p = netdev_priv(dev);
c22c8149 2634 int link_fault;
4d22de3e 2635
bf792094 2636 spin_lock_irq(&adapter->work_lock);
c22c8149
DLR		 2637 link_fault = p->link_fault;
2638 spin_unlock_irq(&adapter->work_lock);
2639
2640 if (link_fault) {
3851c66c 2641 t3_link_fault(adapter, i);
bf792094
DLR		 2642 continue;
2643 }
bf792094
DLR		 2644
2645 if (!(p->phy.caps & SUPPORTED_IRQ) && netif_running(dev)) {
2646 t3_xgm_intr_disable(adapter, i);
2647 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2648
4d22de3e 2649 t3_link_changed(adapter, i);
bf792094
DLR		 2650 t3_xgm_intr_enable(adapter, i);
2651 }
4d22de3e
DLR		 2652 }
2653}
2654
fc90664e
DLR		 2655static void check_t3b2_mac(struct adapter *adapter)
2656{
2657 int i;
2658
f2d961c9
DLR		 2659 if (!rtnl_trylock()) /* synchronize with ifdown */
2660 return;
2661
fc90664e
DLR		 2662 for_each_port(adapter, i) {
2663 struct net_device *dev = adapter->port[i];
2664 struct port_info *p = netdev_priv(dev);
2665 int status;
2666
2667 if (!netif_running(dev))
2668 continue;
2669
2670 status = 0;
6d6dabac 2671 if (netif_running(dev) && netif_carrier_ok(dev))
fc90664e
DLR		 2672 status = t3b2_mac_watchdog_task(&p->mac);
2673 if (status == 1)
2674 p->mac.stats.num_toggled++;
2675 else if (status == 2) {
2676 struct cmac *mac = &p->mac;
2677
2678 t3_mac_set_mtu(mac, dev->mtu);
f14d42f3 2679 t3_mac_set_address(mac, LAN_MAC_IDX, dev->dev_addr);
fc90664e
DLR		 2680 cxgb_set_rxmode(dev);
2681 t3_link_start(&p->phy, mac, &p->link_config);
2682 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2683 t3_port_intr_enable(adapter, p->port_id);
2684 p->mac.stats.num_resets++;
2685 }
2686 }
2687 rtnl_unlock();
2688}
2689
2690
4d22de3e
DLR		 2691static void t3_adap_check_task(struct work_struct *work)
2692{
2693 struct adapter *adapter = container_of(work, struct adapter,
2694 adap_check_task.work);
2695 const struct adapter_params *p = &adapter->params;
fc882196
DLR		 2696 int port;
2697 unsigned int v, status, reset;
4d22de3e
DLR		 2698
2699 adapter->check_task_cnt++;
2700
3851c66c 2701 check_link_status(adapter);
4d22de3e
DLR		 2702
2703 /* Accumulate MAC stats if needed */
2704 if (!p->linkpoll_period ||
2705 (adapter->check_task_cnt * p->linkpoll_period) / 10 >=
2706 p->stats_update_period) {
2707 mac_stats_update(adapter);
2708 adapter->check_task_cnt = 0;
2709 }
2710
fc90664e
DLR		 2711 if (p->rev == T3_REV_B2)
2712 check_t3b2_mac(adapter);
2713
fc882196
DLR		 2714 /*
2715 * Scan the XGMAC's to check for various conditions which we want to
2716 * monitor in a periodic polling manner rather than via an interrupt
2717 * condition. This is used for conditions which would otherwise flood
2718 * the system with interrupts and we only really need to know that the
2719 * conditions are "happening" ... For each condition we count the
2720 * detection of the condition and reset it for the next polling loop.
2721 */
2722 for_each_port(adapter, port) {
2723 struct cmac *mac = &adap2pinfo(adapter, port)->mac;
2724 u32 cause;
2725
2726 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2727 reset = 0;
2728 if (cause & F_RXFIFO_OVERFLOW) {
2729 mac->stats.rx_fifo_ovfl++;
2730 reset |= F_RXFIFO_OVERFLOW;
2731 }
2732
2733 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, reset);
2734 }
2735
2736 /*
2737 * We do the same as above for FL_EMPTY interrupts.
2738 */
2739 status = t3_read_reg(adapter, A_SG_INT_CAUSE);
2740 reset = 0;
2741
2742 if (status & F_FLEMPTY) {
2743 struct sge_qset *qs = &adapter->sge.qs[0];
2744 int i = 0;
2745
2746 reset |= F_FLEMPTY;
2747
2748 v = (t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS) >> S_FL0EMPTY) &
2749 0xffff;
2750
2751 while (v) {
2752 qs->fl[i].empty += (v & 1);
2753 if (i)
2754 qs++;
2755 i ^= 1;
2756 v >>= 1;
2757 }
2758 }
2759
2760 t3_write_reg(adapter, A_SG_INT_CAUSE, reset);
2761
4d22de3e 2762 /* Schedule the next check update if any port is active. */
20d3fc11 2763 spin_lock_irq(&adapter->work_lock);
4d22de3e
DLR		 2764 if (adapter->open_device_map & PORT_MASK)
2765 schedule_chk_task(adapter);
20d3fc11 2766 spin_unlock_irq(&adapter->work_lock);
4d22de3e
DLR		 2767}
2768
e998f245
SW		 2769static void db_full_task(struct work_struct *work)
2770{
2771 struct adapter *adapter = container_of(work, struct adapter,
2772 db_full_task);
2773
2774 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_FULL, 0);
2775}
2776
2777static void db_empty_task(struct work_struct *work)
2778{
2779 struct adapter *adapter = container_of(work, struct adapter,
2780 db_empty_task);
2781
2782 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_EMPTY, 0);
2783}
2784
2785static void db_drop_task(struct work_struct *work)
2786{
2787 struct adapter *adapter = container_of(work, struct adapter,
2788 db_drop_task);
2789 unsigned long delay = 1000;
2790 unsigned short r;
2791
2792 cxgb3_event_notify(&adapter->tdev, OFFLOAD_DB_DROP, 0);
2793
2794 /*
2795 * Sleep a while before ringing the driver qset dbs.
2796 * The delay is between 1000-2023 usecs.
2797 */
2798 get_random_bytes(&r, 2);
2799 delay += r & 1023;
2800 set_current_state(TASK_UNINTERRUPTIBLE);
2801 schedule_timeout(usecs_to_jiffies(delay));
2802 ring_dbs(adapter);
2803}
2804
4d22de3e
DLR		 2805/*
2806 * Processes external (PHY) interrupts in process context.
2807 */
2808static void ext_intr_task(struct work_struct *work)
2809{
2810 struct adapter *adapter = container_of(work, struct adapter,
2811 ext_intr_handler_task);
bf792094
DLR		 2812 int i;
2813
2814 /* Disable link fault interrupts */
2815 for_each_port(adapter, i) {
2816 struct net_device *dev = adapter->port[i];
2817 struct port_info *p = netdev_priv(dev);
2818
2819 t3_xgm_intr_disable(adapter, i);
2820 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2821 }
4d22de3e 2822
bf792094 2823 /* Re-enable link fault interrupts */
4d22de3e
DLR		 2824 t3_phy_intr_handler(adapter);
2825
bf792094
DLR		 2826 for_each_port(adapter, i)
2827 t3_xgm_intr_enable(adapter, i);
2828
4d22de3e
DLR		 2829 /* Now reenable external interrupts */
2830 spin_lock_irq(&adapter->work_lock);
2831 if (adapter->slow_intr_mask) {
2832 adapter->slow_intr_mask |= F_T3DBG;
2833 t3_write_reg(adapter, A_PL_INT_CAUSE0, F_T3DBG);
2834 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2835 adapter->slow_intr_mask);
2836 }
2837 spin_unlock_irq(&adapter->work_lock);
2838}
2839
2840/*
2841 * Interrupt-context handler for external (PHY) interrupts.
2842 */
2843void t3_os_ext_intr_handler(struct adapter *adapter)
2844{
2845 /*
2846 * Schedule a task to handle external interrupts as they may be slow
2847 * and we use a mutex to protect MDIO registers. We disable PHY
2848 * interrupts in the meantime and let the task reenable them when
2849 * it's done.
2850 */
2851 spin_lock(&adapter->work_lock);
2852 if (adapter->slow_intr_mask) {
2853 adapter->slow_intr_mask &= ~F_T3DBG;
2854 t3_write_reg(adapter, A_PL_INT_ENABLE0,
2855 adapter->slow_intr_mask);
2856 queue_work(cxgb3_wq, &adapter->ext_intr_handler_task);
2857 }
2858 spin_unlock(&adapter->work_lock);
2859}
2860
bf792094
DLR		 2861void t3_os_link_fault_handler(struct adapter *adapter, int port_id)
2862{
2863 struct net_device *netdev = adapter->port[port_id];
2864 struct port_info *pi = netdev_priv(netdev);
2865
2866 spin_lock(&adapter->work_lock);
2867 pi->link_fault = 1;
bf792094
DLR		 2868 spin_unlock(&adapter->work_lock);
2869}
2870
55bc3228 2871static int t3_adapter_error(struct adapter *adapter, int reset, int on_wq)
20d3fc11
DLR		 2872{
2873 int i, ret = 0;
2874
cb0bc205
DLR		 2875 if (is_offload(adapter) &&
2876 test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map)) {
fa0d4c11 2877 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_DOWN, 0);
cb0bc205
DLR		 2878 offload_close(&adapter->tdev);
2879 }
2880
20d3fc11
DLR		 2881 /* Stop all ports */
2882 for_each_port(adapter, i) {
2883 struct net_device *netdev = adapter->port[i];
2884
2885 if (netif_running(netdev))
55bc3228 2886 __cxgb_close(netdev, on_wq);
20d3fc11
DLR		 2887 }
2888
20d3fc11
DLR		 2889 /* Stop SGE timers */
2890 t3_stop_sge_timers(adapter);
2891
2892 adapter->flags &= ~FULL_INIT_DONE;
2893
2894 if (reset)
2895 ret = t3_reset_adapter(adapter);
2896
2897 pci_disable_device(adapter->pdev);
2898
2899 return ret;
2900}
2901
2902static int t3_reenable_adapter(struct adapter *adapter)
2903{
2904 if (pci_enable_device(adapter->pdev)) {
2905 dev_err(&adapter->pdev->dev,
2906 "Cannot re-enable PCI device after reset.\n");
2907 goto err;
2908 }
2909 pci_set_master(adapter->pdev);
2910 pci_restore_state(adapter->pdev);
ccdddf50 2911 pci_save_state(adapter->pdev);
20d3fc11
DLR		 2912
2913 /* Free sge resources */
2914 t3_free_sge_resources(adapter);
2915
2916 if (t3_replay_prep_adapter(adapter))
2917 goto err;
2918
2919 return 0;
2920err:
2921 return -1;
2922}
2923
2924static void t3_resume_ports(struct adapter *adapter)
2925{
2926 int i;
2927
2928 /* Restart the ports */
2929 for_each_port(adapter, i) {
2930 struct net_device *netdev = adapter->port[i];
2931
2932 if (netif_running(netdev)) {
2933 if (cxgb_open(netdev)) {
2934 dev_err(&adapter->pdev->dev,
2935 "can't bring device back up"
2936 " after reset\n");
2937 continue;
2938 }
2939 }
2940 }
cb0bc205
DLR		 2941
2942 if (is_offload(adapter) && !ofld_disable)
fa0d4c11 2943 cxgb3_event_notify(&adapter->tdev, OFFLOAD_STATUS_UP, 0);
20d3fc11
DLR		 2944}
2945
2946/*
2947 * processes a fatal error.
2948 * Bring the ports down, reset the chip, bring the ports back up.
2949 */
2950static void fatal_error_task(struct work_struct *work)
2951{
2952 struct adapter *adapter = container_of(work, struct adapter,
2953 fatal_error_handler_task);
2954 int err = 0;
2955
2956 rtnl_lock();
55bc3228 2957 err = t3_adapter_error(adapter, 1, 1);
20d3fc11
DLR		 2958 if (!err)
2959 err = t3_reenable_adapter(adapter);
2960 if (!err)
2961 t3_resume_ports(adapter);
2962
2963 CH_ALERT(adapter, "adapter reset %s\n", err ? "failed" : "succeeded");
2964 rtnl_unlock();
2965}
2966
4d22de3e
DLR		 2967void t3_fatal_err(struct adapter *adapter)
2968{
2969 unsigned int fw_status[4];
2970
2971 if (adapter->flags & FULL_INIT_DONE) {
2972 t3_sge_stop(adapter);
c64c2eae
DLR		 2973 t3_write_reg(adapter, A_XGM_TX_CTRL, 0);
2974 t3_write_reg(adapter, A_XGM_RX_CTRL, 0);
2975 t3_write_reg(adapter, XGM_REG(A_XGM_TX_CTRL, 1), 0);
2976 t3_write_reg(adapter, XGM_REG(A_XGM_RX_CTRL, 1), 0);
20d3fc11
DLR		 2977
2978 spin_lock(&adapter->work_lock);
4d22de3e 2979 t3_intr_disable(adapter);
20d3fc11
DLR		 2980 queue_work(cxgb3_wq, &adapter->fatal_error_handler_task);
2981 spin_unlock(&adapter->work_lock);
4d22de3e
DLR		 2982 }
2983 CH_ALERT(adapter, "encountered fatal error, operation suspended\n");
2984 if (!t3_cim_ctl_blk_read(adapter, 0xa0, 4, fw_status))
2985 CH_ALERT(adapter, "FW status: 0x%x, 0x%x, 0x%x, 0x%x\n",
2986 fw_status[0], fw_status[1],
2987 fw_status[2], fw_status[3]);
4d22de3e
DLR		 2988}
2989
91a6b50c
DLR		 2990/**
2991 * t3_io_error_detected - called when PCI error is detected
2992 * @pdev: Pointer to PCI device
2993 * @state: The current pci connection state
2994 *
2995 * This function is called after a PCI bus error affecting
2996 * this device has been detected.
2997 */
2998static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
2999 pci_channel_state_t state)
3000{
bc4b6b52 3001 struct adapter *adapter = pci_get_drvdata(pdev);
20d3fc11 3002 int ret;
91a6b50c 3003
e8d19370
DLR		 3004 if (state == pci_channel_io_perm_failure)
3005 return PCI_ERS_RESULT_DISCONNECT;
3006
55bc3228 3007 ret = t3_adapter_error(adapter, 0, 0);
91a6b50c 3008
48c4b6db 3009 /* Request a slot reset. */
91a6b50c
DLR		 3010 return PCI_ERS_RESULT_NEED_RESET;
3011}
3012
3013/**
3014 * t3_io_slot_reset - called after the pci bus has been reset.
3015 * @pdev: Pointer to PCI device
3016 *
3017 * Restart the card from scratch, as if from a cold-boot.
3018 */
3019static pci_ers_result_t t3_io_slot_reset(struct pci_dev *pdev)
3020{
bc4b6b52 3021 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3022
20d3fc11
DLR		 3023 if (!t3_reenable_adapter(adapter))
3024 return PCI_ERS_RESULT_RECOVERED;
91a6b50c 3025
48c4b6db 3026 return PCI_ERS_RESULT_DISCONNECT;
91a6b50c
DLR		 3027}
3028
3029/**
3030 * t3_io_resume - called when traffic can start flowing again.
3031 * @pdev: Pointer to PCI device
3032 *
3033 * This callback is called when the error recovery driver tells us that
3034 * its OK to resume normal operation.
3035 */
3036static void t3_io_resume(struct pci_dev *pdev)
3037{
bc4b6b52 3038 struct adapter *adapter = pci_get_drvdata(pdev);
91a6b50c 3039
68f40c10
DLR		 3040 CH_ALERT(adapter, "adapter recovering, PEX ERR 0x%x\n",
3041 t3_read_reg(adapter, A_PCIE_PEX_ERR));
3042
20d3fc11 3043 t3_resume_ports(adapter);
91a6b50c
DLR		 3044}
3045
3046static struct pci_error_handlers t3_err_handler = {
3047 .error_detected = t3_io_error_detected,
3048 .slot_reset = t3_io_slot_reset,
3049 .resume = t3_io_resume,
3050};
3051
8c263761
DLR		 3052/*
3053 * Set the number of qsets based on the number of CPUs and the number of ports,
3054 * not to exceed the number of available qsets, assuming there are enough qsets
3055 * per port in HW.
3056 */
3057static void set_nqsets(struct adapter *adap)
3058{
3059 int i, j = 0;
3060 int num_cpus = num_online_cpus();
3061 int hwports = adap->params.nports;
5cda9364 3062 int nqsets = adap->msix_nvectors - 1;
8c263761 3063
f9ee3882 3064 if (adap->params.rev > 0 && adap->flags & USING_MSIX) {
8c263761
DLR		 3065 if (hwports == 2 &&
3066 (hwports * nqsets > SGE_QSETS ||
3067 num_cpus >= nqsets / hwports))
3068 nqsets /= hwports;
3069 if (nqsets > num_cpus)
3070 nqsets = num_cpus;
3071 if (nqsets < 1 || hwports == 4)
3072 nqsets = 1;
3073 } else
3074 nqsets = 1;
3075
3076 for_each_port(adap, i) {
3077 struct port_info *pi = adap2pinfo(adap, i);
3078
3079 pi->first_qset = j;
3080 pi->nqsets = nqsets;
3081 j = pi->first_qset + nqsets;
3082
3083 dev_info(&adap->pdev->dev,
3084 "Port %d using %d queue sets.\n", i, nqsets);
3085 }
3086}
3087
4d22de3e
DLR		 3088static int __devinit cxgb_enable_msix(struct adapter *adap)
3089{
3090 struct msix_entry entries[SGE_QSETS + 1];
5cda9364 3091 int vectors;
4d22de3e
DLR		 3092 int i, err;
3093
5cda9364
DLR		 3094 vectors = ARRAY_SIZE(entries);
3095 for (i = 0; i < vectors; ++i)
4d22de3e
DLR		 3096 entries[i].entry = i;
3097
5cda9364
DLR		 3098 while ((err = pci_enable_msix(adap->pdev, entries, vectors)) > 0)
3099 vectors = err;
3100
2c2f409f
DLR		 3101 if (err < 0)
3102 pci_disable_msix(adap->pdev);
3103
3104 if (!err && vectors < (adap->params.nports + 1)) {
3105 pci_disable_msix(adap->pdev);
5cda9364 3106 err = -1;
2c2f409f 3107 }
5cda9364 3108
4d22de3e 3109 if (!err) {
5cda9364 3110 for (i = 0; i < vectors; ++i)
4d22de3e 3111 adap->msix_info[i].vec = entries[i].vector;
5cda9364
DLR		 3112 adap->msix_nvectors = vectors;
3113 }
3114
4d22de3e
DLR		 3115 return err;
3116}
3117
3118static void __devinit print_port_info(struct adapter *adap,
3119 const struct adapter_info *ai)
3120{
3121 static const char *pci_variant[] = {
3122 "PCI", "PCI-X", "PCI-X ECC", "PCI-X 266", "PCI Express"
3123 };
3124
3125 int i;
3126 char buf[80];
3127
3128 if (is_pcie(adap))
3129 snprintf(buf, sizeof(buf), "%s x%d",
3130 pci_variant[adap->params.pci.variant],
3131 adap->params.pci.width);
3132 else
3133 snprintf(buf, sizeof(buf), "%s %dMHz/%d-bit",
3134 pci_variant[adap->params.pci.variant],
3135 adap->params.pci.speed, adap->params.pci.width);
3136
3137 for_each_port(adap, i) {
3138 struct net_device *dev = adap->port[i];
3139 const struct port_info *pi = netdev_priv(dev);
3140
3141 if (!test_bit(i, &adap->registered_device_map))
3142 continue;
8ac3ba68 3143 printk(KERN_INFO "%s: %s %s %sNIC (rev %d) %s%s\n",
04497982 3144 dev->name, ai->desc, pi->phy.desc,
8ac3ba68 3145 is_offload(adap) ? "R" : "", adap->params.rev, buf,
4d22de3e
DLR		 3146 (adap->flags & USING_MSIX) ? " MSI-X" :
3147 (adap->flags & USING_MSI) ? " MSI" : "");
3148 if (adap->name == dev->name && adap->params.vpd.mclk)
167cdf5f
DLR		 3149 printk(KERN_INFO
3150 "%s: %uMB CM, %uMB PMTX, %uMB PMRX, S/N: %s\n",
4d22de3e
DLR		 3151 adap->name, t3_mc7_size(&adap->cm) >> 20,
3152 t3_mc7_size(&adap->pmtx) >> 20,
167cdf5f
DLR		 3153 t3_mc7_size(&adap->pmrx) >> 20,
3154 adap->params.vpd.sn);
4d22de3e
DLR		 3155 }
3156}
3157
dd752696
SH		 3158static const struct net_device_ops cxgb_netdev_ops = {
3159 .ndo_open = cxgb_open,
3160 .ndo_stop = cxgb_close,
43a944f3 3161 .ndo_start_xmit = t3_eth_xmit,
dd752696
SH		 3162 .ndo_get_stats = cxgb_get_stats,
3163 .ndo_validate_addr = eth_validate_addr,
3164 .ndo_set_multicast_list = cxgb_set_rxmode,
3165 .ndo_do_ioctl = cxgb_ioctl,
3166 .ndo_change_mtu = cxgb_change_mtu,
3167 .ndo_set_mac_address = cxgb_set_mac_addr,
3168 .ndo_vlan_rx_register = vlan_rx_register,
3169#ifdef CONFIG_NET_POLL_CONTROLLER
3170 .ndo_poll_controller = cxgb_netpoll,
3171#endif
3172};
3173
f14d42f3
KX		 3174static void __devinit cxgb3_init_iscsi_mac(struct net_device *dev)
3175{
3176 struct port_info *pi = netdev_priv(dev);
3177
3178 memcpy(pi->iscsic.mac_addr, dev->dev_addr, ETH_ALEN);
3179 pi->iscsic.mac_addr[3] |= 0x80;
3180}
3181
4d22de3e
DLR		 3182static int __devinit init_one(struct pci_dev *pdev,
3183 const struct pci_device_id *ent)
3184{
3185 static int version_printed;
3186
3187 int i, err, pci_using_dac = 0;
68f40c10 3188 resource_size_t mmio_start, mmio_len;
4d22de3e
DLR		 3189 const struct adapter_info *ai;
3190 struct adapter *adapter = NULL;
3191 struct port_info *pi;
3192
3193 if (!version_printed) {
3194 printk(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
3195 ++version_printed;
3196 }
3197
3198 if (!cxgb3_wq) {
3199 cxgb3_wq = create_singlethread_workqueue(DRV_NAME);
3200 if (!cxgb3_wq) {
3201 printk(KERN_ERR DRV_NAME
3202 ": cannot initialize work queue\n");
3203 return -ENOMEM;
3204 }
3205 }
3206
7aaaaa1e 3207 err = pci_enable_device(pdev);
4d22de3e 3208 if (err) {
7aaaaa1e
KV		 3209 dev_err(&pdev->dev, "cannot enable PCI device\n");
3210 goto out;
4d22de3e
DLR		 3211 }
3212
7aaaaa1e 3213 err = pci_request_regions(pdev, DRV_NAME);
4d22de3e 3214 if (err) {
7aaaaa1e
KV		 3215 /* Just info, some other driver may have claimed the device. */
3216 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
3217 goto out_disable_device;
4d22de3e
DLR		 3218 }
3219
6a35528a 3220 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4d22de3e 3221 pci_using_dac = 1;
6a35528a 3222 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4d22de3e
DLR		 3223 if (err) {
3224 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
3225 "coherent allocations\n");
7aaaaa1e 3226 goto out_release_regions;
4d22de3e 3227 }
284901a9 3228 } else if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
4d22de3e 3229 dev_err(&pdev->dev, "no usable DMA configuration\n");
7aaaaa1e 3230 goto out_release_regions;
4d22de3e
DLR		 3231 }
3232
3233 pci_set_master(pdev);
204e2f98 3234 pci_save_state(pdev);
4d22de3e
DLR		 3235
3236 mmio_start = pci_resource_start(pdev, 0);
3237 mmio_len = pci_resource_len(pdev, 0);
3238 ai = t3_get_adapter_info(ent->driver_data);
3239
3240 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
3241 if (!adapter) {
3242 err = -ENOMEM;
7aaaaa1e 3243 goto out_release_regions;
4d22de3e
DLR		 3244 }
3245
74b793e1
DLR		 3246 adapter->nofail_skb =
3247 alloc_skb(sizeof(struct cpl_set_tcb_field), GFP_KERNEL);
3248 if (!adapter->nofail_skb) {
3249 dev_err(&pdev->dev, "cannot allocate nofail buffer\n");
3250 err = -ENOMEM;
3251 goto out_free_adapter;
3252 }
3253
4d22de3e
DLR		 3254 adapter->regs = ioremap_nocache(mmio_start, mmio_len);
3255 if (!adapter->regs) {
3256 dev_err(&pdev->dev, "cannot map device registers\n");
3257 err = -ENOMEM;
3258 goto out_free_adapter;
3259 }
3260
3261 adapter->pdev = pdev;
3262 adapter->name = pci_name(pdev);
3263 adapter->msg_enable = dflt_msg_enable;
3264 adapter->mmio_len = mmio_len;
3265
3266 mutex_init(&adapter->mdio_lock);
3267 spin_lock_init(&adapter->work_lock);
3268 spin_lock_init(&adapter->stats_lock);
3269
3270 INIT_LIST_HEAD(&adapter->adapter_list);
3271 INIT_WORK(&adapter->ext_intr_handler_task, ext_intr_task);
20d3fc11 3272 INIT_WORK(&adapter->fatal_error_handler_task, fatal_error_task);
e998f245
SW		 3273
3274 INIT_WORK(&adapter->db_full_task, db_full_task);
3275 INIT_WORK(&adapter->db_empty_task, db_empty_task);
3276 INIT_WORK(&adapter->db_drop_task, db_drop_task);
3277
4d22de3e
DLR		 3278 INIT_DELAYED_WORK(&adapter->adap_check_task, t3_adap_check_task);
3279
952cdf33 3280 for (i = 0; i < ai->nports0 + ai->nports1; ++i) {
4d22de3e
DLR		 3281 struct net_device *netdev;
3282
82ad3329 3283 netdev = alloc_etherdev_mq(sizeof(struct port_info), SGE_QSETS);
4d22de3e
DLR		 3284 if (!netdev) {
3285 err = -ENOMEM;
3286 goto out_free_dev;
3287 }
3288
4d22de3e
DLR		 3289 SET_NETDEV_DEV(netdev, &pdev->dev);
3290
3291 adapter->port[i] = netdev;
3292 pi = netdev_priv(netdev);
5fbf816f 3293 pi->adapter = adapter;
47fd23fe 3294 pi->rx_offload = T3_RX_CSUM | T3_LRO;
4d22de3e
DLR		 3295 pi->port_id = i;
3296 netif_carrier_off(netdev);
82ad3329 3297 netif_tx_stop_all_queues(netdev);
4d22de3e
DLR		 3298 netdev->irq = pdev->irq;
3299 netdev->mem_start = mmio_start;
3300 netdev->mem_end = mmio_start + mmio_len - 1;
4d22de3e 3301 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
7be2df45 3302 netdev->features |= NETIF_F_GRO;
4d22de3e
DLR		 3303 if (pci_using_dac)
3304 netdev->features |= NETIF_F_HIGHDMA;
3305
3306 netdev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
dd752696 3307 netdev->netdev_ops = &cxgb_netdev_ops;
4d22de3e
DLR		 3308 SET_ETHTOOL_OPS(netdev, &cxgb_ethtool_ops);
3309 }
3310
5fbf816f 3311 pci_set_drvdata(pdev, adapter);
4d22de3e
DLR		 3312 if (t3_prep_adapter(adapter, ai, 1) < 0) {
3313 err = -ENODEV;
3314 goto out_free_dev;
3315 }
2eab17ab 3316
4d22de3e
DLR		 3317 /*
3318 * The card is now ready to go. If any errors occur during device
3319 * registration we do not fail the whole card but rather proceed only
3320 * with the ports we manage to register successfully. However we must
3321 * register at least one net device.
3322 */
3323 for_each_port(adapter, i) {
3324 err = register_netdev(adapter->port[i]);
3325 if (err)
3326 dev_warn(&pdev->dev,
3327 "cannot register net device %s, skipping\n",
3328 adapter->port[i]->name);
3329 else {
3330 /*
3331 * Change the name we use for messages to the name of
3332 * the first successfully registered interface.
3333 */
3334 if (!adapter->registered_device_map)
3335 adapter->name = adapter->port[i]->name;
3336
3337 __set_bit(i, &adapter->registered_device_map);
3338 }
3339 }
3340 if (!adapter->registered_device_map) {
3341 dev_err(&pdev->dev, "could not register any net devices\n");
3342 goto out_free_dev;
3343 }
3344
f14d42f3
KX		 3345 for_each_port(adapter, i)
3346 cxgb3_init_iscsi_mac(adapter->port[i]);
3347
4d22de3e
DLR		 3348 /* Driver's ready. Reflect it on LEDs */
3349 t3_led_ready(adapter);
3350
3351 if (is_offload(adapter)) {
3352 __set_bit(OFFLOAD_DEVMAP_BIT, &adapter->registered_device_map);
3353 cxgb3_adapter_ofld(adapter);
3354 }
3355
3356 /* See what interrupts we'll be using */
3357 if (msi > 1 && cxgb_enable_msix(adapter) == 0)
3358 adapter->flags |= USING_MSIX;
3359 else if (msi > 0 && pci_enable_msi(pdev) == 0)
3360 adapter->flags |= USING_MSI;
3361
8c263761
DLR		 3362 set_nqsets(adapter);
3363
0ee8d33c 3364 err = sysfs_create_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3365 &cxgb3_attr_group);
3366
3367 print_port_info(adapter, ai);
3368 return 0;
3369
3370out_free_dev:
3371 iounmap(adapter->regs);
952cdf33 3372 for (i = ai->nports0 + ai->nports1 - 1; i >= 0; --i)
4d22de3e
DLR		 3373 if (adapter->port[i])
3374 free_netdev(adapter->port[i]);
3375
3376out_free_adapter:
3377 kfree(adapter);
3378
4d22de3e
DLR		 3379out_release_regions:
3380 pci_release_regions(pdev);
7aaaaa1e
KV		 3381out_disable_device:
3382 pci_disable_device(pdev);
4d22de3e 3383 pci_set_drvdata(pdev, NULL);
7aaaaa1e 3384out:
4d22de3e
DLR		 3385 return err;
3386}
3387
3388static void __devexit remove_one(struct pci_dev *pdev)
3389{
5fbf816f 3390 struct adapter *adapter = pci_get_drvdata(pdev);
4d22de3e 3391
5fbf816f 3392 if (adapter) {
4d22de3e 3393 int i;
4d22de3e
DLR		 3394
3395 t3_sge_stop(adapter);
0ee8d33c 3396 sysfs_remove_group(&adapter->port[0]->dev.kobj,
4d22de3e
DLR		 3397 &cxgb3_attr_group);
3398
4d22de3e
DLR		 3399 if (is_offload(adapter)) {
3400 cxgb3_adapter_unofld(adapter);
3401 if (test_bit(OFFLOAD_DEVMAP_BIT,
3402 &adapter->open_device_map))
3403 offload_close(&adapter->tdev);
3404 }
3405
67d92ab7
DLR		 3406 for_each_port(adapter, i)
3407 if (test_bit(i, &adapter->registered_device_map))
3408 unregister_netdev(adapter->port[i]);
3409
0ca41c04 3410 t3_stop_sge_timers(adapter);
4d22de3e
DLR		 3411 t3_free_sge_resources(adapter);
3412 cxgb_disable_msi(adapter);
3413
4d22de3e
DLR		 3414 for_each_port(adapter, i)
3415 if (adapter->port[i])
3416 free_netdev(adapter->port[i]);
3417
3418 iounmap(adapter->regs);
74b793e1
DLR		 3419 if (adapter->nofail_skb)
3420 kfree_skb(adapter->nofail_skb);
4d22de3e
DLR		 3421 kfree(adapter);
3422 pci_release_regions(pdev);
3423 pci_disable_device(pdev);
3424 pci_set_drvdata(pdev, NULL);
3425 }
3426}
3427
3428static struct pci_driver driver = {
3429 .name = DRV_NAME,
3430 .id_table = cxgb3_pci_tbl,
3431 .probe = init_one,
3432 .remove = __devexit_p(remove_one),
91a6b50c 3433 .err_handler = &t3_err_handler,
4d22de3e
DLR		 3434};
3435
3436static int __init cxgb3_init_module(void)
3437{
3438 int ret;
3439
3440 cxgb3_offload_init();
3441
3442 ret = pci_register_driver(&driver);
3443 return ret;
3444}
3445
3446static void __exit cxgb3_cleanup_module(void)
3447{
3448 pci_unregister_driver(&driver);
3449 if (cxgb3_wq)
3450 destroy_workqueue(cxgb3_wq);
3451}
3452
3453module_init(cxgb3_init_module);
3454module_exit(cxgb3_cleanup_module);
Linux 6.x block layer and io_uring tree(s)