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1f26dac3 DM |
1 | /* cassini.c: Sun Microsystems Cassini(+) ethernet driver. |
2 | * | |
3 | * Copyright (C) 2004 Sun Microsystems Inc. | |
4 | * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of the | |
9 | * License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA | |
19 | * 02111-1307, USA. | |
20 | * | |
21 | * This driver uses the sungem driver (c) David Miller | |
22 | * (davem@redhat.com) as its basis. | |
23 | * | |
24 | * The cassini chip has a number of features that distinguish it from | |
25 | * the gem chip: | |
26 | * 4 transmit descriptor rings that are used for either QoS (VLAN) or | |
27 | * load balancing (non-VLAN mode) | |
28 | * batching of multiple packets | |
29 | * multiple CPU dispatching | |
30 | * page-based RX descriptor engine with separate completion rings | |
31 | * Gigabit support (GMII and PCS interface) | |
32 | * MIF link up/down detection works | |
33 | * | |
34 | * RX is handled by page sized buffers that are attached as fragments to | |
35 | * the skb. here's what's done: | |
36 | * -- driver allocates pages at a time and keeps reference counts | |
37 | * on them. | |
38 | * -- the upper protocol layers assume that the header is in the skb | |
39 | * itself. as a result, cassini will copy a small amount (64 bytes) | |
40 | * to make them happy. | |
41 | * -- driver appends the rest of the data pages as frags to skbuffs | |
42 | * and increments the reference count | |
43 | * -- on page reclamation, the driver swaps the page with a spare page. | |
44 | * if that page is still in use, it frees its reference to that page, | |
45 | * and allocates a new page for use. otherwise, it just recycles the | |
6aa20a22 | 46 | * the page. |
1f26dac3 DM |
47 | * |
48 | * NOTE: cassini can parse the header. however, it's not worth it | |
49 | * as long as the network stack requires a header copy. | |
50 | * | |
51 | * TX has 4 queues. currently these queues are used in a round-robin | |
52 | * fashion for load balancing. They can also be used for QoS. for that | |
53 | * to work, however, QoS information needs to be exposed down to the driver | |
54 | * level so that subqueues get targetted to particular transmit rings. | |
55 | * alternatively, the queues can be configured via use of the all-purpose | |
56 | * ioctl. | |
57 | * | |
58 | * RX DATA: the rx completion ring has all the info, but the rx desc | |
59 | * ring has all of the data. RX can conceivably come in under multiple | |
60 | * interrupts, but the INT# assignment needs to be set up properly by | |
61 | * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do | |
62 | * that. also, the two descriptor rings are designed to distinguish between | |
6aa20a22 | 63 | * encrypted and non-encrypted packets, but we use them for buffering |
1f26dac3 DM |
64 | * instead. |
65 | * | |
6aa20a22 | 66 | * by default, the selective clear mask is set up to process rx packets. |
1f26dac3 DM |
67 | */ |
68 | ||
436d27d1 | 69 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
1f26dac3 DM |
70 | |
71 | #include <linux/module.h> | |
72 | #include <linux/kernel.h> | |
73 | #include <linux/types.h> | |
74 | #include <linux/compiler.h> | |
75 | #include <linux/slab.h> | |
76 | #include <linux/delay.h> | |
77 | #include <linux/init.h> | |
fcaa4066 | 78 | #include <linux/vmalloc.h> |
1f26dac3 DM |
79 | #include <linux/ioport.h> |
80 | #include <linux/pci.h> | |
81 | #include <linux/mm.h> | |
82 | #include <linux/highmem.h> | |
83 | #include <linux/list.h> | |
84 | #include <linux/dma-mapping.h> | |
85 | ||
86 | #include <linux/netdevice.h> | |
87 | #include <linux/etherdevice.h> | |
88 | #include <linux/skbuff.h> | |
89 | #include <linux/ethtool.h> | |
90 | #include <linux/crc32.h> | |
91 | #include <linux/random.h> | |
92 | #include <linux/mii.h> | |
93 | #include <linux/ip.h> | |
94 | #include <linux/tcp.h> | |
758df69e | 95 | #include <linux/mutex.h> |
fcaa4066 | 96 | #include <linux/firmware.h> |
1f26dac3 DM |
97 | |
98 | #include <net/checksum.h> | |
99 | ||
100 | #include <asm/atomic.h> | |
101 | #include <asm/system.h> | |
102 | #include <asm/io.h> | |
103 | #include <asm/byteorder.h> | |
104 | #include <asm/uaccess.h> | |
105 | ||
106 | #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ) | |
107 | #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ) | |
108 | #define CAS_NCPUS num_online_cpus() | |
109 | ||
257ddbda | 110 | #ifdef CONFIG_CASSINI_NAPI |
1f26dac3 DM |
111 | #define USE_NAPI |
112 | #define cas_skb_release(x) netif_receive_skb(x) | |
113 | #else | |
114 | #define cas_skb_release(x) netif_rx(x) | |
115 | #endif | |
116 | ||
117 | /* select which firmware to use */ | |
6aa20a22 | 118 | #define USE_HP_WORKAROUND |
1f26dac3 DM |
119 | #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */ |
120 | #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */ | |
121 | ||
122 | #include "cassini.h" | |
123 | ||
124 | #define USE_TX_COMPWB /* use completion writeback registers */ | |
125 | #define USE_CSMA_CD_PROTO /* standard CSMA/CD */ | |
126 | #define USE_RX_BLANK /* hw interrupt mitigation */ | |
127 | #undef USE_ENTROPY_DEV /* don't test for entropy device */ | |
128 | ||
129 | /* NOTE: these aren't useable unless PCI interrupts can be assigned. | |
130 | * also, we need to make cp->lock finer-grained. | |
131 | */ | |
132 | #undef USE_PCI_INTB | |
133 | #undef USE_PCI_INTC | |
134 | #undef USE_PCI_INTD | |
135 | #undef USE_QOS | |
136 | ||
137 | #undef USE_VPD_DEBUG /* debug vpd information if defined */ | |
138 | ||
139 | /* rx processing options */ | |
140 | #define USE_PAGE_ORDER /* specify to allocate large rx pages */ | |
141 | #define RX_DONT_BATCH 0 /* if 1, don't batch flows */ | |
142 | #define RX_COPY_ALWAYS 0 /* if 0, use frags */ | |
143 | #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */ | |
144 | #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */ | |
145 | ||
146 | #define DRV_MODULE_NAME "cassini" | |
b1443e2f DM |
147 | #define DRV_MODULE_VERSION "1.6" |
148 | #define DRV_MODULE_RELDATE "21 May 2008" | |
1f26dac3 DM |
149 | |
150 | #define CAS_DEF_MSG_ENABLE \ | |
151 | (NETIF_MSG_DRV | \ | |
152 | NETIF_MSG_PROBE | \ | |
153 | NETIF_MSG_LINK | \ | |
154 | NETIF_MSG_TIMER | \ | |
155 | NETIF_MSG_IFDOWN | \ | |
156 | NETIF_MSG_IFUP | \ | |
157 | NETIF_MSG_RX_ERR | \ | |
158 | NETIF_MSG_TX_ERR) | |
159 | ||
160 | /* length of time before we decide the hardware is borked, | |
161 | * and dev->tx_timeout() should be called to fix the problem | |
162 | */ | |
163 | #define CAS_TX_TIMEOUT (HZ) | |
164 | #define CAS_LINK_TIMEOUT (22*HZ/10) | |
165 | #define CAS_LINK_FAST_TIMEOUT (1) | |
166 | ||
167 | /* timeout values for state changing. these specify the number | |
168 | * of 10us delays to be used before giving up. | |
169 | */ | |
170 | #define STOP_TRIES_PHY 1000 | |
171 | #define STOP_TRIES 5000 | |
172 | ||
6aa20a22 | 173 | /* specify a minimum frame size to deal with some fifo issues |
1f26dac3 DM |
174 | * max mtu == 2 * page size - ethernet header - 64 - swivel = |
175 | * 2 * page_size - 0x50 | |
176 | */ | |
177 | #define CAS_MIN_FRAME 97 | |
178 | #define CAS_1000MB_MIN_FRAME 255 | |
179 | #define CAS_MIN_MTU 60 | |
180 | #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000) | |
181 | ||
182 | #if 1 | |
183 | /* | |
184 | * Eliminate these and use separate atomic counters for each, to | |
185 | * avoid a race condition. | |
186 | */ | |
187 | #else | |
188 | #define CAS_RESET_MTU 1 | |
189 | #define CAS_RESET_ALL 2 | |
190 | #define CAS_RESET_SPARE 3 | |
191 | #endif | |
192 | ||
193 | static char version[] __devinitdata = | |
194 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | |
195 | ||
8d3b33f6 RR |
196 | static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */ |
197 | static int link_mode; | |
198 | ||
1f26dac3 DM |
199 | MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)"); |
200 | MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver"); | |
201 | MODULE_LICENSE("GPL"); | |
fcaa4066 | 202 | MODULE_FIRMWARE("sun/cassini.bin"); |
8d3b33f6 | 203 | module_param(cassini_debug, int, 0); |
1f26dac3 | 204 | MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value"); |
8d3b33f6 | 205 | module_param(link_mode, int, 0); |
1f26dac3 DM |
206 | MODULE_PARM_DESC(link_mode, "default link mode"); |
207 | ||
208 | /* | |
209 | * Work around for a PCS bug in which the link goes down due to the chip | |
210 | * being confused and never showing a link status of "up." | |
211 | */ | |
212 | #define DEFAULT_LINKDOWN_TIMEOUT 5 | |
6aa20a22 | 213 | /* |
1f26dac3 DM |
214 | * Value in seconds, for user input. |
215 | */ | |
216 | static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT; | |
8d3b33f6 | 217 | module_param(linkdown_timeout, int, 0); |
1f26dac3 DM |
218 | MODULE_PARM_DESC(linkdown_timeout, |
219 | "min reset interval in sec. for PCS linkdown issue; disabled if not positive"); | |
220 | ||
221 | /* | |
222 | * value in 'ticks' (units used by jiffies). Set when we init the | |
223 | * module because 'HZ' in actually a function call on some flavors of | |
224 | * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ. | |
225 | */ | |
226 | static int link_transition_timeout; | |
227 | ||
228 | ||
1f26dac3 DM |
229 | |
230 | static u16 link_modes[] __devinitdata = { | |
231 | BMCR_ANENABLE, /* 0 : autoneg */ | |
232 | 0, /* 1 : 10bt half duplex */ | |
233 | BMCR_SPEED100, /* 2 : 100bt half duplex */ | |
234 | BMCR_FULLDPLX, /* 3 : 10bt full duplex */ | |
235 | BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */ | |
236 | CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */ | |
237 | }; | |
238 | ||
a3aa1884 | 239 | static DEFINE_PCI_DEVICE_TABLE(cas_pci_tbl) = { |
1f26dac3 DM |
240 | { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI, |
241 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
242 | { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN, | |
243 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | |
244 | { 0, } | |
245 | }; | |
246 | ||
247 | MODULE_DEVICE_TABLE(pci, cas_pci_tbl); | |
248 | ||
249 | static void cas_set_link_modes(struct cas *cp); | |
250 | ||
251 | static inline void cas_lock_tx(struct cas *cp) | |
252 | { | |
253 | int i; | |
254 | ||
6aa20a22 | 255 | for (i = 0; i < N_TX_RINGS; i++) |
1f26dac3 DM |
256 | spin_lock(&cp->tx_lock[i]); |
257 | } | |
258 | ||
259 | static inline void cas_lock_all(struct cas *cp) | |
260 | { | |
261 | spin_lock_irq(&cp->lock); | |
262 | cas_lock_tx(cp); | |
263 | } | |
264 | ||
265 | /* WTZ: QA was finding deadlock problems with the previous | |
266 | * versions after long test runs with multiple cards per machine. | |
267 | * See if replacing cas_lock_all with safer versions helps. The | |
268 | * symptoms QA is reporting match those we'd expect if interrupts | |
269 | * aren't being properly restored, and we fixed a previous deadlock | |
270 | * with similar symptoms by using save/restore versions in other | |
271 | * places. | |
272 | */ | |
273 | #define cas_lock_all_save(cp, flags) \ | |
274 | do { \ | |
275 | struct cas *xxxcp = (cp); \ | |
276 | spin_lock_irqsave(&xxxcp->lock, flags); \ | |
277 | cas_lock_tx(xxxcp); \ | |
278 | } while (0) | |
279 | ||
280 | static inline void cas_unlock_tx(struct cas *cp) | |
281 | { | |
282 | int i; | |
283 | ||
6aa20a22 JG |
284 | for (i = N_TX_RINGS; i > 0; i--) |
285 | spin_unlock(&cp->tx_lock[i - 1]); | |
1f26dac3 DM |
286 | } |
287 | ||
288 | static inline void cas_unlock_all(struct cas *cp) | |
289 | { | |
290 | cas_unlock_tx(cp); | |
291 | spin_unlock_irq(&cp->lock); | |
292 | } | |
293 | ||
294 | #define cas_unlock_all_restore(cp, flags) \ | |
295 | do { \ | |
296 | struct cas *xxxcp = (cp); \ | |
297 | cas_unlock_tx(xxxcp); \ | |
298 | spin_unlock_irqrestore(&xxxcp->lock, flags); \ | |
299 | } while (0) | |
300 | ||
301 | static void cas_disable_irq(struct cas *cp, const int ring) | |
302 | { | |
303 | /* Make sure we won't get any more interrupts */ | |
304 | if (ring == 0) { | |
305 | writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); | |
306 | return; | |
307 | } | |
308 | ||
309 | /* disable completion interrupts and selectively mask */ | |
310 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
311 | switch (ring) { | |
312 | #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) | |
313 | #ifdef USE_PCI_INTB | |
314 | case 1: | |
315 | #endif | |
316 | #ifdef USE_PCI_INTC | |
317 | case 2: | |
318 | #endif | |
319 | #ifdef USE_PCI_INTD | |
320 | case 3: | |
321 | #endif | |
6aa20a22 | 322 | writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, |
1f26dac3 DM |
323 | cp->regs + REG_PLUS_INTRN_MASK(ring)); |
324 | break; | |
325 | #endif | |
326 | default: | |
327 | writel(INTRN_MASK_CLEAR_ALL, cp->regs + | |
328 | REG_PLUS_INTRN_MASK(ring)); | |
329 | break; | |
330 | } | |
331 | } | |
332 | } | |
333 | ||
334 | static inline void cas_mask_intr(struct cas *cp) | |
335 | { | |
336 | int i; | |
337 | ||
338 | for (i = 0; i < N_RX_COMP_RINGS; i++) | |
339 | cas_disable_irq(cp, i); | |
340 | } | |
341 | ||
342 | static void cas_enable_irq(struct cas *cp, const int ring) | |
343 | { | |
344 | if (ring == 0) { /* all but TX_DONE */ | |
345 | writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); | |
346 | return; | |
347 | } | |
348 | ||
349 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
350 | switch (ring) { | |
351 | #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) | |
352 | #ifdef USE_PCI_INTB | |
353 | case 1: | |
354 | #endif | |
355 | #ifdef USE_PCI_INTC | |
356 | case 2: | |
357 | #endif | |
358 | #ifdef USE_PCI_INTD | |
359 | case 3: | |
360 | #endif | |
361 | writel(INTRN_MASK_RX_EN, cp->regs + | |
362 | REG_PLUS_INTRN_MASK(ring)); | |
363 | break; | |
364 | #endif | |
365 | default: | |
366 | break; | |
367 | } | |
368 | } | |
369 | } | |
370 | ||
371 | static inline void cas_unmask_intr(struct cas *cp) | |
372 | { | |
373 | int i; | |
374 | ||
375 | for (i = 0; i < N_RX_COMP_RINGS; i++) | |
376 | cas_enable_irq(cp, i); | |
377 | } | |
378 | ||
379 | static inline void cas_entropy_gather(struct cas *cp) | |
380 | { | |
381 | #ifdef USE_ENTROPY_DEV | |
382 | if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) | |
383 | return; | |
384 | ||
385 | batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), | |
386 | readl(cp->regs + REG_ENTROPY_IV), | |
387 | sizeof(uint64_t)*8); | |
388 | #endif | |
389 | } | |
390 | ||
391 | static inline void cas_entropy_reset(struct cas *cp) | |
392 | { | |
393 | #ifdef USE_ENTROPY_DEV | |
394 | if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) | |
395 | return; | |
396 | ||
6aa20a22 | 397 | writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, |
1f26dac3 DM |
398 | cp->regs + REG_BIM_LOCAL_DEV_EN); |
399 | writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET); | |
400 | writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG); | |
401 | ||
402 | /* if we read back 0x0, we don't have an entropy device */ | |
403 | if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0) | |
404 | cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV; | |
405 | #endif | |
406 | } | |
407 | ||
6aa20a22 | 408 | /* access to the phy. the following assumes that we've initialized the MIF to |
1f26dac3 DM |
409 | * be in frame rather than bit-bang mode |
410 | */ | |
411 | static u16 cas_phy_read(struct cas *cp, int reg) | |
412 | { | |
413 | u32 cmd; | |
414 | int limit = STOP_TRIES_PHY; | |
415 | ||
416 | cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ; | |
417 | cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); | |
418 | cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); | |
419 | cmd |= MIF_FRAME_TURN_AROUND_MSB; | |
420 | writel(cmd, cp->regs + REG_MIF_FRAME); | |
6aa20a22 | 421 | |
1f26dac3 DM |
422 | /* poll for completion */ |
423 | while (limit-- > 0) { | |
424 | udelay(10); | |
425 | cmd = readl(cp->regs + REG_MIF_FRAME); | |
426 | if (cmd & MIF_FRAME_TURN_AROUND_LSB) | |
427 | return (cmd & MIF_FRAME_DATA_MASK); | |
428 | } | |
429 | return 0xFFFF; /* -1 */ | |
430 | } | |
431 | ||
432 | static int cas_phy_write(struct cas *cp, int reg, u16 val) | |
433 | { | |
434 | int limit = STOP_TRIES_PHY; | |
435 | u32 cmd; | |
436 | ||
437 | cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE; | |
438 | cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); | |
439 | cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); | |
440 | cmd |= MIF_FRAME_TURN_AROUND_MSB; | |
441 | cmd |= val & MIF_FRAME_DATA_MASK; | |
442 | writel(cmd, cp->regs + REG_MIF_FRAME); | |
6aa20a22 | 443 | |
1f26dac3 DM |
444 | /* poll for completion */ |
445 | while (limit-- > 0) { | |
446 | udelay(10); | |
447 | cmd = readl(cp->regs + REG_MIF_FRAME); | |
448 | if (cmd & MIF_FRAME_TURN_AROUND_LSB) | |
449 | return 0; | |
450 | } | |
451 | return -1; | |
452 | } | |
453 | ||
454 | static void cas_phy_powerup(struct cas *cp) | |
455 | { | |
6aa20a22 | 456 | u16 ctl = cas_phy_read(cp, MII_BMCR); |
1f26dac3 DM |
457 | |
458 | if ((ctl & BMCR_PDOWN) == 0) | |
459 | return; | |
460 | ctl &= ~BMCR_PDOWN; | |
461 | cas_phy_write(cp, MII_BMCR, ctl); | |
462 | } | |
463 | ||
464 | static void cas_phy_powerdown(struct cas *cp) | |
465 | { | |
6aa20a22 | 466 | u16 ctl = cas_phy_read(cp, MII_BMCR); |
1f26dac3 DM |
467 | |
468 | if (ctl & BMCR_PDOWN) | |
469 | return; | |
470 | ctl |= BMCR_PDOWN; | |
471 | cas_phy_write(cp, MII_BMCR, ctl); | |
472 | } | |
473 | ||
474 | /* cp->lock held. note: the last put_page will free the buffer */ | |
475 | static int cas_page_free(struct cas *cp, cas_page_t *page) | |
476 | { | |
6aa20a22 | 477 | pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size, |
1f26dac3 DM |
478 | PCI_DMA_FROMDEVICE); |
479 | __free_pages(page->buffer, cp->page_order); | |
480 | kfree(page); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | #ifdef RX_COUNT_BUFFERS | |
485 | #define RX_USED_ADD(x, y) ((x)->used += (y)) | |
486 | #define RX_USED_SET(x, y) ((x)->used = (y)) | |
487 | #else | |
6aa20a22 | 488 | #define RX_USED_ADD(x, y) |
1f26dac3 DM |
489 | #define RX_USED_SET(x, y) |
490 | #endif | |
491 | ||
492 | /* local page allocation routines for the receive buffers. jumbo pages | |
493 | * require at least 8K contiguous and 8K aligned buffers. | |
494 | */ | |
9e24974d | 495 | static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags) |
1f26dac3 DM |
496 | { |
497 | cas_page_t *page; | |
498 | ||
499 | page = kmalloc(sizeof(cas_page_t), flags); | |
500 | if (!page) | |
501 | return NULL; | |
502 | ||
503 | INIT_LIST_HEAD(&page->list); | |
504 | RX_USED_SET(page, 0); | |
505 | page->buffer = alloc_pages(flags, cp->page_order); | |
506 | if (!page->buffer) | |
507 | goto page_err; | |
508 | page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0, | |
509 | cp->page_size, PCI_DMA_FROMDEVICE); | |
510 | return page; | |
511 | ||
512 | page_err: | |
513 | kfree(page); | |
514 | return NULL; | |
515 | } | |
516 | ||
517 | /* initialize spare pool of rx buffers, but allocate during the open */ | |
518 | static void cas_spare_init(struct cas *cp) | |
519 | { | |
520 | spin_lock(&cp->rx_inuse_lock); | |
521 | INIT_LIST_HEAD(&cp->rx_inuse_list); | |
522 | spin_unlock(&cp->rx_inuse_lock); | |
523 | ||
524 | spin_lock(&cp->rx_spare_lock); | |
525 | INIT_LIST_HEAD(&cp->rx_spare_list); | |
526 | cp->rx_spares_needed = RX_SPARE_COUNT; | |
527 | spin_unlock(&cp->rx_spare_lock); | |
528 | } | |
529 | ||
530 | /* used on close. free all the spare buffers. */ | |
531 | static void cas_spare_free(struct cas *cp) | |
532 | { | |
533 | struct list_head list, *elem, *tmp; | |
534 | ||
535 | /* free spare buffers */ | |
536 | INIT_LIST_HEAD(&list); | |
537 | spin_lock(&cp->rx_spare_lock); | |
9bd512f6 | 538 | list_splice_init(&cp->rx_spare_list, &list); |
1f26dac3 DM |
539 | spin_unlock(&cp->rx_spare_lock); |
540 | list_for_each_safe(elem, tmp, &list) { | |
541 | cas_page_free(cp, list_entry(elem, cas_page_t, list)); | |
542 | } | |
543 | ||
544 | INIT_LIST_HEAD(&list); | |
545 | #if 1 | |
546 | /* | |
547 | * Looks like Adrian had protected this with a different | |
548 | * lock than used everywhere else to manipulate this list. | |
549 | */ | |
550 | spin_lock(&cp->rx_inuse_lock); | |
9bd512f6 | 551 | list_splice_init(&cp->rx_inuse_list, &list); |
1f26dac3 DM |
552 | spin_unlock(&cp->rx_inuse_lock); |
553 | #else | |
554 | spin_lock(&cp->rx_spare_lock); | |
9bd512f6 | 555 | list_splice_init(&cp->rx_inuse_list, &list); |
1f26dac3 DM |
556 | spin_unlock(&cp->rx_spare_lock); |
557 | #endif | |
558 | list_for_each_safe(elem, tmp, &list) { | |
559 | cas_page_free(cp, list_entry(elem, cas_page_t, list)); | |
560 | } | |
561 | } | |
562 | ||
563 | /* replenish spares if needed */ | |
9e24974d | 564 | static void cas_spare_recover(struct cas *cp, const gfp_t flags) |
1f26dac3 DM |
565 | { |
566 | struct list_head list, *elem, *tmp; | |
567 | int needed, i; | |
568 | ||
569 | /* check inuse list. if we don't need any more free buffers, | |
570 | * just free it | |
571 | */ | |
572 | ||
573 | /* make a local copy of the list */ | |
574 | INIT_LIST_HEAD(&list); | |
575 | spin_lock(&cp->rx_inuse_lock); | |
9bd512f6 | 576 | list_splice_init(&cp->rx_inuse_list, &list); |
1f26dac3 | 577 | spin_unlock(&cp->rx_inuse_lock); |
6aa20a22 | 578 | |
1f26dac3 DM |
579 | list_for_each_safe(elem, tmp, &list) { |
580 | cas_page_t *page = list_entry(elem, cas_page_t, list); | |
581 | ||
e286781d NP |
582 | /* |
583 | * With the lockless pagecache, cassini buffering scheme gets | |
584 | * slightly less accurate: we might find that a page has an | |
585 | * elevated reference count here, due to a speculative ref, | |
586 | * and skip it as in-use. Ideally we would be able to reclaim | |
587 | * it. However this would be such a rare case, it doesn't | |
588 | * matter too much as we should pick it up the next time round. | |
589 | * | |
590 | * Importantly, if we find that the page has a refcount of 1 | |
591 | * here (our refcount), then we know it is definitely not inuse | |
592 | * so we can reuse it. | |
593 | */ | |
9de4dfb4 | 594 | if (page_count(page->buffer) > 1) |
1f26dac3 DM |
595 | continue; |
596 | ||
597 | list_del(elem); | |
598 | spin_lock(&cp->rx_spare_lock); | |
599 | if (cp->rx_spares_needed > 0) { | |
600 | list_add(elem, &cp->rx_spare_list); | |
601 | cp->rx_spares_needed--; | |
602 | spin_unlock(&cp->rx_spare_lock); | |
603 | } else { | |
604 | spin_unlock(&cp->rx_spare_lock); | |
605 | cas_page_free(cp, page); | |
606 | } | |
607 | } | |
608 | ||
609 | /* put any inuse buffers back on the list */ | |
610 | if (!list_empty(&list)) { | |
611 | spin_lock(&cp->rx_inuse_lock); | |
612 | list_splice(&list, &cp->rx_inuse_list); | |
613 | spin_unlock(&cp->rx_inuse_lock); | |
614 | } | |
6aa20a22 | 615 | |
1f26dac3 DM |
616 | spin_lock(&cp->rx_spare_lock); |
617 | needed = cp->rx_spares_needed; | |
618 | spin_unlock(&cp->rx_spare_lock); | |
619 | if (!needed) | |
620 | return; | |
621 | ||
622 | /* we still need spares, so try to allocate some */ | |
623 | INIT_LIST_HEAD(&list); | |
624 | i = 0; | |
625 | while (i < needed) { | |
626 | cas_page_t *spare = cas_page_alloc(cp, flags); | |
6aa20a22 | 627 | if (!spare) |
1f26dac3 DM |
628 | break; |
629 | list_add(&spare->list, &list); | |
630 | i++; | |
631 | } | |
632 | ||
633 | spin_lock(&cp->rx_spare_lock); | |
634 | list_splice(&list, &cp->rx_spare_list); | |
635 | cp->rx_spares_needed -= i; | |
636 | spin_unlock(&cp->rx_spare_lock); | |
637 | } | |
638 | ||
639 | /* pull a page from the list. */ | |
640 | static cas_page_t *cas_page_dequeue(struct cas *cp) | |
641 | { | |
642 | struct list_head *entry; | |
643 | int recover; | |
644 | ||
645 | spin_lock(&cp->rx_spare_lock); | |
646 | if (list_empty(&cp->rx_spare_list)) { | |
647 | /* try to do a quick recovery */ | |
648 | spin_unlock(&cp->rx_spare_lock); | |
649 | cas_spare_recover(cp, GFP_ATOMIC); | |
650 | spin_lock(&cp->rx_spare_lock); | |
651 | if (list_empty(&cp->rx_spare_list)) { | |
436d27d1 JP |
652 | netif_err(cp, rx_err, cp->dev, |
653 | "no spare buffers available\n"); | |
1f26dac3 DM |
654 | spin_unlock(&cp->rx_spare_lock); |
655 | return NULL; | |
656 | } | |
657 | } | |
658 | ||
659 | entry = cp->rx_spare_list.next; | |
660 | list_del(entry); | |
661 | recover = ++cp->rx_spares_needed; | |
662 | spin_unlock(&cp->rx_spare_lock); | |
663 | ||
664 | /* trigger the timer to do the recovery */ | |
665 | if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) { | |
666 | #if 1 | |
667 | atomic_inc(&cp->reset_task_pending); | |
668 | atomic_inc(&cp->reset_task_pending_spare); | |
669 | schedule_work(&cp->reset_task); | |
670 | #else | |
671 | atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE); | |
672 | schedule_work(&cp->reset_task); | |
673 | #endif | |
674 | } | |
675 | return list_entry(entry, cas_page_t, list); | |
676 | } | |
677 | ||
678 | ||
679 | static void cas_mif_poll(struct cas *cp, const int enable) | |
680 | { | |
681 | u32 cfg; | |
6aa20a22 JG |
682 | |
683 | cfg = readl(cp->regs + REG_MIF_CFG); | |
1f26dac3 DM |
684 | cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1); |
685 | ||
686 | if (cp->phy_type & CAS_PHY_MII_MDIO1) | |
6aa20a22 | 687 | cfg |= MIF_CFG_PHY_SELECT; |
1f26dac3 DM |
688 | |
689 | /* poll and interrupt on link status change. */ | |
690 | if (enable) { | |
691 | cfg |= MIF_CFG_POLL_EN; | |
692 | cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR); | |
693 | cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr); | |
694 | } | |
6aa20a22 JG |
695 | writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, |
696 | cp->regs + REG_MIF_MASK); | |
1f26dac3 DM |
697 | writel(cfg, cp->regs + REG_MIF_CFG); |
698 | } | |
699 | ||
700 | /* Must be invoked under cp->lock */ | |
701 | static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep) | |
702 | { | |
703 | u16 ctl; | |
704 | #if 1 | |
705 | int lcntl; | |
706 | int changed = 0; | |
707 | int oldstate = cp->lstate; | |
708 | int link_was_not_down = !(oldstate == link_down); | |
709 | #endif | |
710 | /* Setup link parameters */ | |
711 | if (!ep) | |
712 | goto start_aneg; | |
713 | lcntl = cp->link_cntl; | |
714 | if (ep->autoneg == AUTONEG_ENABLE) | |
715 | cp->link_cntl = BMCR_ANENABLE; | |
716 | else { | |
717 | cp->link_cntl = 0; | |
718 | if (ep->speed == SPEED_100) | |
719 | cp->link_cntl |= BMCR_SPEED100; | |
720 | else if (ep->speed == SPEED_1000) | |
721 | cp->link_cntl |= CAS_BMCR_SPEED1000; | |
722 | if (ep->duplex == DUPLEX_FULL) | |
723 | cp->link_cntl |= BMCR_FULLDPLX; | |
724 | } | |
725 | #if 1 | |
726 | changed = (lcntl != cp->link_cntl); | |
727 | #endif | |
728 | start_aneg: | |
729 | if (cp->lstate == link_up) { | |
436d27d1 | 730 | netdev_info(cp->dev, "PCS link down\n"); |
1f26dac3 DM |
731 | } else { |
732 | if (changed) { | |
436d27d1 | 733 | netdev_info(cp->dev, "link configuration changed\n"); |
1f26dac3 DM |
734 | } |
735 | } | |
736 | cp->lstate = link_down; | |
737 | cp->link_transition = LINK_TRANSITION_LINK_DOWN; | |
738 | if (!cp->hw_running) | |
739 | return; | |
740 | #if 1 | |
741 | /* | |
742 | * WTZ: If the old state was link_up, we turn off the carrier | |
743 | * to replicate everything we do elsewhere on a link-down | |
6aa20a22 | 744 | * event when we were already in a link-up state.. |
1f26dac3 DM |
745 | */ |
746 | if (oldstate == link_up) | |
747 | netif_carrier_off(cp->dev); | |
748 | if (changed && link_was_not_down) { | |
749 | /* | |
750 | * WTZ: This branch will simply schedule a full reset after | |
751 | * we explicitly changed link modes in an ioctl. See if this | |
6aa20a22 | 752 | * fixes the link-problems we were having for forced mode. |
1f26dac3 DM |
753 | */ |
754 | atomic_inc(&cp->reset_task_pending); | |
755 | atomic_inc(&cp->reset_task_pending_all); | |
756 | schedule_work(&cp->reset_task); | |
757 | cp->timer_ticks = 0; | |
758 | mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); | |
759 | return; | |
760 | } | |
761 | #endif | |
762 | if (cp->phy_type & CAS_PHY_SERDES) { | |
763 | u32 val = readl(cp->regs + REG_PCS_MII_CTRL); | |
764 | ||
765 | if (cp->link_cntl & BMCR_ANENABLE) { | |
766 | val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN); | |
767 | cp->lstate = link_aneg; | |
768 | } else { | |
769 | if (cp->link_cntl & BMCR_FULLDPLX) | |
770 | val |= PCS_MII_CTRL_DUPLEX; | |
771 | val &= ~PCS_MII_AUTONEG_EN; | |
772 | cp->lstate = link_force_ok; | |
773 | } | |
774 | cp->link_transition = LINK_TRANSITION_LINK_CONFIG; | |
775 | writel(val, cp->regs + REG_PCS_MII_CTRL); | |
776 | ||
777 | } else { | |
778 | cas_mif_poll(cp, 0); | |
779 | ctl = cas_phy_read(cp, MII_BMCR); | |
6aa20a22 | 780 | ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | |
1f26dac3 DM |
781 | CAS_BMCR_SPEED1000 | BMCR_ANENABLE); |
782 | ctl |= cp->link_cntl; | |
783 | if (ctl & BMCR_ANENABLE) { | |
784 | ctl |= BMCR_ANRESTART; | |
785 | cp->lstate = link_aneg; | |
786 | } else { | |
787 | cp->lstate = link_force_ok; | |
788 | } | |
789 | cp->link_transition = LINK_TRANSITION_LINK_CONFIG; | |
790 | cas_phy_write(cp, MII_BMCR, ctl); | |
791 | cas_mif_poll(cp, 1); | |
792 | } | |
793 | ||
794 | cp->timer_ticks = 0; | |
795 | mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); | |
796 | } | |
797 | ||
798 | /* Must be invoked under cp->lock. */ | |
799 | static int cas_reset_mii_phy(struct cas *cp) | |
800 | { | |
801 | int limit = STOP_TRIES_PHY; | |
802 | u16 val; | |
6aa20a22 | 803 | |
1f26dac3 DM |
804 | cas_phy_write(cp, MII_BMCR, BMCR_RESET); |
805 | udelay(100); | |
ff01b916 | 806 | while (--limit) { |
1f26dac3 DM |
807 | val = cas_phy_read(cp, MII_BMCR); |
808 | if ((val & BMCR_RESET) == 0) | |
809 | break; | |
810 | udelay(10); | |
811 | } | |
812 | return (limit <= 0); | |
813 | } | |
814 | ||
fcaa4066 JS |
815 | static int cas_saturn_firmware_init(struct cas *cp) |
816 | { | |
817 | const struct firmware *fw; | |
818 | const char fw_name[] = "sun/cassini.bin"; | |
819 | int err; | |
820 | ||
821 | if (PHY_NS_DP83065 != cp->phy_id) | |
822 | return 0; | |
823 | ||
824 | err = request_firmware(&fw, fw_name, &cp->pdev->dev); | |
825 | if (err) { | |
436d27d1 | 826 | pr_err("Failed to load firmware \"%s\"\n", |
fcaa4066 JS |
827 | fw_name); |
828 | return err; | |
829 | } | |
830 | if (fw->size < 2) { | |
436d27d1 | 831 | pr_err("bogus length %zu in \"%s\"\n", |
fcaa4066 JS |
832 | fw->size, fw_name); |
833 | err = -EINVAL; | |
834 | goto out; | |
835 | } | |
836 | cp->fw_load_addr= fw->data[1] << 8 | fw->data[0]; | |
837 | cp->fw_size = fw->size - 2; | |
838 | cp->fw_data = vmalloc(cp->fw_size); | |
839 | if (!cp->fw_data) { | |
840 | err = -ENOMEM; | |
436d27d1 | 841 | pr_err("\"%s\" Failed %d\n", fw_name, err); |
fcaa4066 JS |
842 | goto out; |
843 | } | |
844 | memcpy(cp->fw_data, &fw->data[2], cp->fw_size); | |
845 | out: | |
846 | release_firmware(fw); | |
847 | return err; | |
848 | } | |
849 | ||
1f26dac3 DM |
850 | static void cas_saturn_firmware_load(struct cas *cp) |
851 | { | |
fcaa4066 | 852 | int i; |
1f26dac3 DM |
853 | |
854 | cas_phy_powerdown(cp); | |
855 | ||
856 | /* expanded memory access mode */ | |
857 | cas_phy_write(cp, DP83065_MII_MEM, 0x0); | |
858 | ||
859 | /* pointer configuration for new firmware */ | |
860 | cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9); | |
861 | cas_phy_write(cp, DP83065_MII_REGD, 0xbd); | |
862 | cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa); | |
863 | cas_phy_write(cp, DP83065_MII_REGD, 0x82); | |
864 | cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb); | |
865 | cas_phy_write(cp, DP83065_MII_REGD, 0x0); | |
866 | cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc); | |
867 | cas_phy_write(cp, DP83065_MII_REGD, 0x39); | |
868 | ||
869 | /* download new firmware */ | |
870 | cas_phy_write(cp, DP83065_MII_MEM, 0x1); | |
fcaa4066 JS |
871 | cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr); |
872 | for (i = 0; i < cp->fw_size; i++) | |
873 | cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]); | |
1f26dac3 DM |
874 | |
875 | /* enable firmware */ | |
876 | cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8); | |
877 | cas_phy_write(cp, DP83065_MII_REGD, 0x1); | |
878 | } | |
879 | ||
880 | ||
881 | /* phy initialization */ | |
882 | static void cas_phy_init(struct cas *cp) | |
883 | { | |
884 | u16 val; | |
885 | ||
886 | /* if we're in MII/GMII mode, set up phy */ | |
887 | if (CAS_PHY_MII(cp->phy_type)) { | |
888 | writel(PCS_DATAPATH_MODE_MII, | |
889 | cp->regs + REG_PCS_DATAPATH_MODE); | |
890 | ||
891 | cas_mif_poll(cp, 0); | |
892 | cas_reset_mii_phy(cp); /* take out of isolate mode */ | |
893 | ||
894 | if (PHY_LUCENT_B0 == cp->phy_id) { | |
895 | /* workaround link up/down issue with lucent */ | |
896 | cas_phy_write(cp, LUCENT_MII_REG, 0x8000); | |
897 | cas_phy_write(cp, MII_BMCR, 0x00f1); | |
898 | cas_phy_write(cp, LUCENT_MII_REG, 0x0); | |
899 | ||
900 | } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) { | |
901 | /* workarounds for broadcom phy */ | |
902 | cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20); | |
903 | cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012); | |
904 | cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804); | |
905 | cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013); | |
906 | cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204); | |
907 | cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); | |
908 | cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132); | |
909 | cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); | |
910 | cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232); | |
911 | cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F); | |
912 | cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20); | |
913 | ||
914 | } else if (PHY_BROADCOM_5411 == cp->phy_id) { | |
915 | val = cas_phy_read(cp, BROADCOM_MII_REG4); | |
916 | val = cas_phy_read(cp, BROADCOM_MII_REG4); | |
917 | if (val & 0x0080) { | |
918 | /* link workaround */ | |
6aa20a22 | 919 | cas_phy_write(cp, BROADCOM_MII_REG4, |
1f26dac3 DM |
920 | val & ~0x0080); |
921 | } | |
6aa20a22 | 922 | |
1f26dac3 | 923 | } else if (cp->cas_flags & CAS_FLAG_SATURN) { |
6aa20a22 JG |
924 | writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? |
925 | SATURN_PCFG_FSI : 0x0, | |
1f26dac3 DM |
926 | cp->regs + REG_SATURN_PCFG); |
927 | ||
928 | /* load firmware to address 10Mbps auto-negotiation | |
6aa20a22 | 929 | * issue. NOTE: this will need to be changed if the |
1f26dac3 DM |
930 | * default firmware gets fixed. |
931 | */ | |
932 | if (PHY_NS_DP83065 == cp->phy_id) { | |
933 | cas_saturn_firmware_load(cp); | |
934 | } | |
935 | cas_phy_powerup(cp); | |
936 | } | |
937 | ||
938 | /* advertise capabilities */ | |
939 | val = cas_phy_read(cp, MII_BMCR); | |
940 | val &= ~BMCR_ANENABLE; | |
941 | cas_phy_write(cp, MII_BMCR, val); | |
942 | udelay(10); | |
943 | ||
944 | cas_phy_write(cp, MII_ADVERTISE, | |
945 | cas_phy_read(cp, MII_ADVERTISE) | | |
946 | (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
947 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
6aa20a22 | 948 | CAS_ADVERTISE_PAUSE | |
1f26dac3 | 949 | CAS_ADVERTISE_ASYM_PAUSE)); |
6aa20a22 | 950 | |
1f26dac3 DM |
951 | if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { |
952 | /* make sure that we don't advertise half | |
953 | * duplex to avoid a chip issue | |
954 | */ | |
955 | val = cas_phy_read(cp, CAS_MII_1000_CTRL); | |
956 | val &= ~CAS_ADVERTISE_1000HALF; | |
957 | val |= CAS_ADVERTISE_1000FULL; | |
958 | cas_phy_write(cp, CAS_MII_1000_CTRL, val); | |
959 | } | |
960 | ||
961 | } else { | |
962 | /* reset pcs for serdes */ | |
963 | u32 val; | |
964 | int limit; | |
965 | ||
966 | writel(PCS_DATAPATH_MODE_SERDES, | |
967 | cp->regs + REG_PCS_DATAPATH_MODE); | |
968 | ||
969 | /* enable serdes pins on saturn */ | |
970 | if (cp->cas_flags & CAS_FLAG_SATURN) | |
971 | writel(0, cp->regs + REG_SATURN_PCFG); | |
972 | ||
973 | /* Reset PCS unit. */ | |
974 | val = readl(cp->regs + REG_PCS_MII_CTRL); | |
975 | val |= PCS_MII_RESET; | |
976 | writel(val, cp->regs + REG_PCS_MII_CTRL); | |
977 | ||
978 | limit = STOP_TRIES; | |
ff01b916 | 979 | while (--limit > 0) { |
1f26dac3 | 980 | udelay(10); |
6aa20a22 | 981 | if ((readl(cp->regs + REG_PCS_MII_CTRL) & |
1f26dac3 DM |
982 | PCS_MII_RESET) == 0) |
983 | break; | |
984 | } | |
985 | if (limit <= 0) | |
436d27d1 JP |
986 | netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n", |
987 | readl(cp->regs + REG_PCS_STATE_MACHINE)); | |
1f26dac3 DM |
988 | |
989 | /* Make sure PCS is disabled while changing advertisement | |
990 | * configuration. | |
991 | */ | |
992 | writel(0x0, cp->regs + REG_PCS_CFG); | |
993 | ||
994 | /* Advertise all capabilities except half-duplex. */ | |
995 | val = readl(cp->regs + REG_PCS_MII_ADVERT); | |
996 | val &= ~PCS_MII_ADVERT_HD; | |
6aa20a22 | 997 | val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | |
1f26dac3 DM |
998 | PCS_MII_ADVERT_ASYM_PAUSE); |
999 | writel(val, cp->regs + REG_PCS_MII_ADVERT); | |
1000 | ||
1001 | /* enable PCS */ | |
1002 | writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); | |
1003 | ||
1004 | /* pcs workaround: enable sync detect */ | |
1005 | writel(PCS_SERDES_CTRL_SYNCD_EN, | |
1006 | cp->regs + REG_PCS_SERDES_CTRL); | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | ||
1011 | static int cas_pcs_link_check(struct cas *cp) | |
1012 | { | |
1013 | u32 stat, state_machine; | |
1014 | int retval = 0; | |
1015 | ||
1016 | /* The link status bit latches on zero, so you must | |
1017 | * read it twice in such a case to see a transition | |
1018 | * to the link being up. | |
1019 | */ | |
1020 | stat = readl(cp->regs + REG_PCS_MII_STATUS); | |
1021 | if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0) | |
1022 | stat = readl(cp->regs + REG_PCS_MII_STATUS); | |
1023 | ||
1024 | /* The remote-fault indication is only valid | |
1025 | * when autoneg has completed. | |
1026 | */ | |
1027 | if ((stat & (PCS_MII_STATUS_AUTONEG_COMP | | |
1028 | PCS_MII_STATUS_REMOTE_FAULT)) == | |
436d27d1 JP |
1029 | (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) |
1030 | netif_info(cp, link, cp->dev, "PCS RemoteFault\n"); | |
1f26dac3 DM |
1031 | |
1032 | /* work around link detection issue by querying the PCS state | |
1033 | * machine directly. | |
1034 | */ | |
1035 | state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); | |
1036 | if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) { | |
1037 | stat &= ~PCS_MII_STATUS_LINK_STATUS; | |
1038 | } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) { | |
1039 | stat |= PCS_MII_STATUS_LINK_STATUS; | |
1040 | } | |
1041 | ||
1042 | if (stat & PCS_MII_STATUS_LINK_STATUS) { | |
1043 | if (cp->lstate != link_up) { | |
1044 | if (cp->opened) { | |
1045 | cp->lstate = link_up; | |
1046 | cp->link_transition = LINK_TRANSITION_LINK_UP; | |
6aa20a22 | 1047 | |
1f26dac3 DM |
1048 | cas_set_link_modes(cp); |
1049 | netif_carrier_on(cp->dev); | |
1050 | } | |
1051 | } | |
1052 | } else if (cp->lstate == link_up) { | |
1053 | cp->lstate = link_down; | |
1054 | if (link_transition_timeout != 0 && | |
1055 | cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && | |
1056 | !cp->link_transition_jiffies_valid) { | |
1057 | /* | |
6aa20a22 JG |
1058 | * force a reset, as a workaround for the |
1059 | * link-failure problem. May want to move this to a | |
1f26dac3 DM |
1060 | * point a bit earlier in the sequence. If we had |
1061 | * generated a reset a short time ago, we'll wait for | |
1062 | * the link timer to check the status until a | |
1063 | * timer expires (link_transistion_jiffies_valid is | |
1064 | * true when the timer is running.) Instead of using | |
1065 | * a system timer, we just do a check whenever the | |
1066 | * link timer is running - this clears the flag after | |
1067 | * a suitable delay. | |
1068 | */ | |
1069 | retval = 1; | |
1070 | cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; | |
1071 | cp->link_transition_jiffies = jiffies; | |
1072 | cp->link_transition_jiffies_valid = 1; | |
1073 | } else { | |
1074 | cp->link_transition = LINK_TRANSITION_ON_FAILURE; | |
1075 | } | |
1076 | netif_carrier_off(cp->dev); | |
436d27d1 JP |
1077 | if (cp->opened) |
1078 | netif_info(cp, link, cp->dev, "PCS link down\n"); | |
1f26dac3 DM |
1079 | |
1080 | /* Cassini only: if you force a mode, there can be | |
1081 | * sync problems on link down. to fix that, the following | |
1082 | * things need to be checked: | |
1083 | * 1) read serialink state register | |
1084 | * 2) read pcs status register to verify link down. | |
1085 | * 3) if link down and serial link == 0x03, then you need | |
1086 | * to global reset the chip. | |
1087 | */ | |
1088 | if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) { | |
1089 | /* should check to see if we're in a forced mode */ | |
1090 | stat = readl(cp->regs + REG_PCS_SERDES_STATE); | |
1091 | if (stat == 0x03) | |
1092 | return 1; | |
1093 | } | |
1094 | } else if (cp->lstate == link_down) { | |
1095 | if (link_transition_timeout != 0 && | |
1096 | cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && | |
1097 | !cp->link_transition_jiffies_valid) { | |
1098 | /* force a reset, as a workaround for the | |
1099 | * link-failure problem. May want to move | |
1100 | * this to a point a bit earlier in the | |
1101 | * sequence. | |
1102 | */ | |
1103 | retval = 1; | |
1104 | cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; | |
1105 | cp->link_transition_jiffies = jiffies; | |
1106 | cp->link_transition_jiffies_valid = 1; | |
1107 | } else { | |
1108 | cp->link_transition = LINK_TRANSITION_STILL_FAILED; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | return retval; | |
1113 | } | |
1114 | ||
6aa20a22 | 1115 | static int cas_pcs_interrupt(struct net_device *dev, |
1f26dac3 DM |
1116 | struct cas *cp, u32 status) |
1117 | { | |
1118 | u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); | |
1119 | ||
6aa20a22 | 1120 | if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) |
1f26dac3 DM |
1121 | return 0; |
1122 | return cas_pcs_link_check(cp); | |
1123 | } | |
1124 | ||
6aa20a22 | 1125 | static int cas_txmac_interrupt(struct net_device *dev, |
1f26dac3 DM |
1126 | struct cas *cp, u32 status) |
1127 | { | |
1128 | u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); | |
1129 | ||
1130 | if (!txmac_stat) | |
1131 | return 0; | |
1132 | ||
436d27d1 JP |
1133 | netif_printk(cp, intr, KERN_DEBUG, cp->dev, |
1134 | "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat); | |
1f26dac3 DM |
1135 | |
1136 | /* Defer timer expiration is quite normal, | |
1137 | * don't even log the event. | |
1138 | */ | |
1139 | if ((txmac_stat & MAC_TX_DEFER_TIMER) && | |
1140 | !(txmac_stat & ~MAC_TX_DEFER_TIMER)) | |
1141 | return 0; | |
1142 | ||
1143 | spin_lock(&cp->stat_lock[0]); | |
1144 | if (txmac_stat & MAC_TX_UNDERRUN) { | |
436d27d1 | 1145 | netdev_err(dev, "TX MAC xmit underrun\n"); |
1f26dac3 DM |
1146 | cp->net_stats[0].tx_fifo_errors++; |
1147 | } | |
1148 | ||
1149 | if (txmac_stat & MAC_TX_MAX_PACKET_ERR) { | |
436d27d1 | 1150 | netdev_err(dev, "TX MAC max packet size error\n"); |
1f26dac3 DM |
1151 | cp->net_stats[0].tx_errors++; |
1152 | } | |
1153 | ||
1154 | /* The rest are all cases of one of the 16-bit TX | |
1155 | * counters expiring. | |
1156 | */ | |
1157 | if (txmac_stat & MAC_TX_COLL_NORMAL) | |
1158 | cp->net_stats[0].collisions += 0x10000; | |
1159 | ||
1160 | if (txmac_stat & MAC_TX_COLL_EXCESS) { | |
1161 | cp->net_stats[0].tx_aborted_errors += 0x10000; | |
1162 | cp->net_stats[0].collisions += 0x10000; | |
1163 | } | |
1164 | ||
1165 | if (txmac_stat & MAC_TX_COLL_LATE) { | |
1166 | cp->net_stats[0].tx_aborted_errors += 0x10000; | |
1167 | cp->net_stats[0].collisions += 0x10000; | |
1168 | } | |
1169 | spin_unlock(&cp->stat_lock[0]); | |
1170 | ||
1171 | /* We do not keep track of MAC_TX_COLL_FIRST and | |
1172 | * MAC_TX_PEAK_ATTEMPTS events. | |
1173 | */ | |
1174 | return 0; | |
1175 | } | |
1176 | ||
6aa20a22 | 1177 | static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) |
1f26dac3 DM |
1178 | { |
1179 | cas_hp_inst_t *inst; | |
1180 | u32 val; | |
1181 | int i; | |
1182 | ||
1183 | i = 0; | |
1184 | while ((inst = firmware) && inst->note) { | |
1185 | writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); | |
1186 | ||
1187 | val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); | |
1188 | val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); | |
1189 | writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); | |
1190 | ||
1191 | val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); | |
1192 | val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); | |
1193 | val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); | |
1194 | val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); | |
1195 | val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); | |
1196 | val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); | |
1197 | val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); | |
1198 | writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); | |
1199 | ||
1200 | val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); | |
1201 | val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); | |
1202 | val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); | |
1203 | val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); | |
1204 | writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); | |
1205 | ++firmware; | |
1206 | ++i; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | static void cas_init_rx_dma(struct cas *cp) | |
1211 | { | |
6aa20a22 | 1212 | u64 desc_dma = cp->block_dvma; |
1f26dac3 DM |
1213 | u32 val; |
1214 | int i, size; | |
1215 | ||
1216 | /* rx free descriptors */ | |
6aa20a22 | 1217 | val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); |
1f26dac3 DM |
1218 | val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0)); |
1219 | val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0)); | |
1220 | if ((N_RX_DESC_RINGS > 1) && | |
1221 | (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */ | |
1222 | val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1)); | |
1223 | writel(val, cp->regs + REG_RX_CFG); | |
1224 | ||
6aa20a22 | 1225 | val = (unsigned long) cp->init_rxds[0] - |
1f26dac3 DM |
1226 | (unsigned long) cp->init_block; |
1227 | writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); | |
1228 | writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); | |
1229 | writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); | |
1230 | ||
1231 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
6aa20a22 | 1232 | /* rx desc 2 is for IPSEC packets. however, |
1f26dac3 DM |
1233 | * we don't it that for that purpose. |
1234 | */ | |
6aa20a22 | 1235 | val = (unsigned long) cp->init_rxds[1] - |
1f26dac3 DM |
1236 | (unsigned long) cp->init_block; |
1237 | writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); | |
6aa20a22 | 1238 | writel((desc_dma + val) & 0xffffffff, cp->regs + |
1f26dac3 | 1239 | REG_PLUS_RX_DB1_LOW); |
6aa20a22 | 1240 | writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + |
1f26dac3 DM |
1241 | REG_PLUS_RX_KICK1); |
1242 | } | |
6aa20a22 | 1243 | |
1f26dac3 | 1244 | /* rx completion registers */ |
6aa20a22 | 1245 | val = (unsigned long) cp->init_rxcs[0] - |
1f26dac3 DM |
1246 | (unsigned long) cp->init_block; |
1247 | writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); | |
1248 | writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); | |
1249 | ||
1250 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
1251 | /* rx comp 2-4 */ | |
1252 | for (i = 1; i < MAX_RX_COMP_RINGS; i++) { | |
6aa20a22 | 1253 | val = (unsigned long) cp->init_rxcs[i] - |
1f26dac3 | 1254 | (unsigned long) cp->init_block; |
6aa20a22 | 1255 | writel((desc_dma + val) >> 32, cp->regs + |
1f26dac3 | 1256 | REG_PLUS_RX_CBN_HI(i)); |
6aa20a22 | 1257 | writel((desc_dma + val) & 0xffffffff, cp->regs + |
1f26dac3 DM |
1258 | REG_PLUS_RX_CBN_LOW(i)); |
1259 | } | |
1260 | } | |
1261 | ||
1262 | /* read selective clear regs to prevent spurious interrupts | |
1263 | * on reset because complete == kick. | |
1264 | * selective clear set up to prevent interrupts on resets | |
1265 | */ | |
1266 | readl(cp->regs + REG_INTR_STATUS_ALIAS); | |
1267 | writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); | |
1268 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
1269 | for (i = 1; i < N_RX_COMP_RINGS; i++) | |
1270 | readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i)); | |
1271 | ||
1272 | /* 2 is different from 3 and 4 */ | |
1273 | if (N_RX_COMP_RINGS > 1) | |
6aa20a22 | 1274 | writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, |
1f26dac3 DM |
1275 | cp->regs + REG_PLUS_ALIASN_CLEAR(1)); |
1276 | ||
6aa20a22 JG |
1277 | for (i = 2; i < N_RX_COMP_RINGS; i++) |
1278 | writel(INTR_RX_DONE_ALT, | |
1f26dac3 DM |
1279 | cp->regs + REG_PLUS_ALIASN_CLEAR(i)); |
1280 | } | |
1281 | ||
1282 | /* set up pause thresholds */ | |
1283 | val = CAS_BASE(RX_PAUSE_THRESH_OFF, | |
1284 | cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM); | |
6aa20a22 | 1285 | val |= CAS_BASE(RX_PAUSE_THRESH_ON, |
1f26dac3 DM |
1286 | cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM); |
1287 | writel(val, cp->regs + REG_RX_PAUSE_THRESH); | |
6aa20a22 | 1288 | |
1f26dac3 DM |
1289 | /* zero out dma reassembly buffers */ |
1290 | for (i = 0; i < 64; i++) { | |
1291 | writel(i, cp->regs + REG_RX_TABLE_ADDR); | |
1292 | writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); | |
1293 | writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); | |
1294 | writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); | |
1295 | } | |
1296 | ||
1297 | /* make sure address register is 0 for normal operation */ | |
1298 | writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); | |
1299 | writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); | |
1300 | ||
1301 | /* interrupt mitigation */ | |
1302 | #ifdef USE_RX_BLANK | |
1303 | val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL); | |
1304 | val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL); | |
1305 | writel(val, cp->regs + REG_RX_BLANK); | |
1306 | #else | |
1307 | writel(0x0, cp->regs + REG_RX_BLANK); | |
1308 | #endif | |
1309 | ||
1310 | /* interrupt generation as a function of low water marks for | |
1311 | * free desc and completion entries. these are used to trigger | |
1312 | * housekeeping for rx descs. we don't use the free interrupt | |
1313 | * as it's not very useful | |
1314 | */ | |
1315 | /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */ | |
1316 | val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL); | |
1317 | writel(val, cp->regs + REG_RX_AE_THRESH); | |
1318 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
1319 | val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1)); | |
1320 | writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); | |
1321 | } | |
1322 | ||
1323 | /* Random early detect registers. useful for congestion avoidance. | |
1324 | * this should be tunable. | |
1325 | */ | |
1326 | writel(0x0, cp->regs + REG_RX_RED); | |
6aa20a22 | 1327 | |
1f26dac3 DM |
1328 | /* receive page sizes. default == 2K (0x800) */ |
1329 | val = 0; | |
1330 | if (cp->page_size == 0x1000) | |
1331 | val = 0x1; | |
1332 | else if (cp->page_size == 0x2000) | |
1333 | val = 0x2; | |
1334 | else if (cp->page_size == 0x4000) | |
1335 | val = 0x3; | |
6aa20a22 | 1336 | |
1f26dac3 DM |
1337 | /* round mtu + offset. constrain to page size. */ |
1338 | size = cp->dev->mtu + 64; | |
1339 | if (size > cp->page_size) | |
1340 | size = cp->page_size; | |
1341 | ||
1342 | if (size <= 0x400) | |
1343 | i = 0x0; | |
1344 | else if (size <= 0x800) | |
1345 | i = 0x1; | |
1346 | else if (size <= 0x1000) | |
1347 | i = 0x2; | |
1348 | else | |
1349 | i = 0x3; | |
1350 | ||
1351 | cp->mtu_stride = 1 << (i + 10); | |
1352 | val = CAS_BASE(RX_PAGE_SIZE, val); | |
6aa20a22 | 1353 | val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); |
1f26dac3 DM |
1354 | val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); |
1355 | val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1); | |
1356 | writel(val, cp->regs + REG_RX_PAGE_SIZE); | |
6aa20a22 | 1357 | |
1f26dac3 DM |
1358 | /* enable the header parser if desired */ |
1359 | if (CAS_HP_FIRMWARE == cas_prog_null) | |
1360 | return; | |
1361 | ||
1362 | val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); | |
1363 | val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK; | |
1364 | val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL); | |
1365 | writel(val, cp->regs + REG_HP_CFG); | |
1366 | } | |
1367 | ||
1368 | static inline void cas_rxc_init(struct cas_rx_comp *rxc) | |
1369 | { | |
1370 | memset(rxc, 0, sizeof(*rxc)); | |
6aa20a22 | 1371 | rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); |
1f26dac3 DM |
1372 | } |
1373 | ||
1374 | /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1] | |
1375 | * flipping is protected by the fact that the chip will not | |
1376 | * hand back the same page index while it's being processed. | |
1377 | */ | |
1378 | static inline cas_page_t *cas_page_spare(struct cas *cp, const int index) | |
1379 | { | |
1380 | cas_page_t *page = cp->rx_pages[1][index]; | |
1381 | cas_page_t *new; | |
1382 | ||
9de4dfb4 | 1383 | if (page_count(page->buffer) == 1) |
1f26dac3 DM |
1384 | return page; |
1385 | ||
1386 | new = cas_page_dequeue(cp); | |
1387 | if (new) { | |
1388 | spin_lock(&cp->rx_inuse_lock); | |
1389 | list_add(&page->list, &cp->rx_inuse_list); | |
1390 | spin_unlock(&cp->rx_inuse_lock); | |
1391 | } | |
1392 | return new; | |
1393 | } | |
6aa20a22 | 1394 | |
1f26dac3 | 1395 | /* this needs to be changed if we actually use the ENC RX DESC ring */ |
6aa20a22 | 1396 | static cas_page_t *cas_page_swap(struct cas *cp, const int ring, |
1f26dac3 DM |
1397 | const int index) |
1398 | { | |
1399 | cas_page_t **page0 = cp->rx_pages[0]; | |
1400 | cas_page_t **page1 = cp->rx_pages[1]; | |
1401 | ||
1402 | /* swap if buffer is in use */ | |
9de4dfb4 | 1403 | if (page_count(page0[index]->buffer) > 1) { |
1f26dac3 DM |
1404 | cas_page_t *new = cas_page_spare(cp, index); |
1405 | if (new) { | |
1406 | page1[index] = page0[index]; | |
1407 | page0[index] = new; | |
1408 | } | |
6aa20a22 | 1409 | } |
1f26dac3 DM |
1410 | RX_USED_SET(page0[index], 0); |
1411 | return page0[index]; | |
1412 | } | |
1413 | ||
1414 | static void cas_clean_rxds(struct cas *cp) | |
1415 | { | |
1416 | /* only clean ring 0 as ring 1 is used for spare buffers */ | |
1417 | struct cas_rx_desc *rxd = cp->init_rxds[0]; | |
1418 | int i, size; | |
1419 | ||
1420 | /* release all rx flows */ | |
1421 | for (i = 0; i < N_RX_FLOWS; i++) { | |
1422 | struct sk_buff *skb; | |
1423 | while ((skb = __skb_dequeue(&cp->rx_flows[i]))) { | |
1424 | cas_skb_release(skb); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | /* initialize descriptors */ | |
1429 | size = RX_DESC_RINGN_SIZE(0); | |
1430 | for (i = 0; i < size; i++) { | |
1431 | cas_page_t *page = cas_page_swap(cp, 0, i); | |
1432 | rxd[i].buffer = cpu_to_le64(page->dma_addr); | |
6aa20a22 | 1433 | rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | |
1f26dac3 DM |
1434 | CAS_BASE(RX_INDEX_RING, 0)); |
1435 | } | |
1436 | ||
6aa20a22 | 1437 | cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4; |
1f26dac3 DM |
1438 | cp->rx_last[0] = 0; |
1439 | cp->cas_flags &= ~CAS_FLAG_RXD_POST(0); | |
1440 | } | |
1441 | ||
1442 | static void cas_clean_rxcs(struct cas *cp) | |
1443 | { | |
1444 | int i, j; | |
1445 | ||
1446 | /* take ownership of rx comp descriptors */ | |
1447 | memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS); | |
1448 | memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS); | |
1449 | for (i = 0; i < N_RX_COMP_RINGS; i++) { | |
1450 | struct cas_rx_comp *rxc = cp->init_rxcs[i]; | |
1451 | for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) { | |
1452 | cas_rxc_init(rxc + j); | |
1453 | } | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | #if 0 | |
1458 | /* When we get a RX fifo overflow, the RX unit is probably hung | |
1459 | * so we do the following. | |
1460 | * | |
1461 | * If any part of the reset goes wrong, we return 1 and that causes the | |
1462 | * whole chip to be reset. | |
1463 | */ | |
1464 | static int cas_rxmac_reset(struct cas *cp) | |
1465 | { | |
1466 | struct net_device *dev = cp->dev; | |
1467 | int limit; | |
1468 | u32 val; | |
1469 | ||
1470 | /* First, reset MAC RX. */ | |
1471 | writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); | |
1472 | for (limit = 0; limit < STOP_TRIES; limit++) { | |
1473 | if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN)) | |
1474 | break; | |
1475 | udelay(10); | |
1476 | } | |
1477 | if (limit == STOP_TRIES) { | |
436d27d1 | 1478 | netdev_err(dev, "RX MAC will not disable, resetting whole chip\n"); |
1f26dac3 DM |
1479 | return 1; |
1480 | } | |
1481 | ||
1482 | /* Second, disable RX DMA. */ | |
1483 | writel(0, cp->regs + REG_RX_CFG); | |
1484 | for (limit = 0; limit < STOP_TRIES; limit++) { | |
1485 | if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN)) | |
1486 | break; | |
1487 | udelay(10); | |
1488 | } | |
1489 | if (limit == STOP_TRIES) { | |
436d27d1 | 1490 | netdev_err(dev, "RX DMA will not disable, resetting whole chip\n"); |
1f26dac3 DM |
1491 | return 1; |
1492 | } | |
1493 | ||
1494 | mdelay(5); | |
1495 | ||
1496 | /* Execute RX reset command. */ | |
1497 | writel(SW_RESET_RX, cp->regs + REG_SW_RESET); | |
1498 | for (limit = 0; limit < STOP_TRIES; limit++) { | |
1499 | if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX)) | |
1500 | break; | |
1501 | udelay(10); | |
1502 | } | |
1503 | if (limit == STOP_TRIES) { | |
436d27d1 | 1504 | netdev_err(dev, "RX reset command will not execute, resetting whole chip\n"); |
1f26dac3 DM |
1505 | return 1; |
1506 | } | |
1507 | ||
1508 | /* reset driver rx state */ | |
1509 | cas_clean_rxds(cp); | |
1510 | cas_clean_rxcs(cp); | |
1511 | ||
1512 | /* Now, reprogram the rest of RX unit. */ | |
1513 | cas_init_rx_dma(cp); | |
1514 | ||
1515 | /* re-enable */ | |
1516 | val = readl(cp->regs + REG_RX_CFG); | |
1517 | writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG); | |
1518 | writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); | |
1519 | val = readl(cp->regs + REG_MAC_RX_CFG); | |
1520 | writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); | |
1521 | return 0; | |
1522 | } | |
1523 | #endif | |
1524 | ||
1525 | static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp, | |
1526 | u32 status) | |
1527 | { | |
1528 | u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); | |
1529 | ||
1530 | if (!stat) | |
1531 | return 0; | |
1532 | ||
436d27d1 | 1533 | netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat); |
1f26dac3 DM |
1534 | |
1535 | /* these are all rollovers */ | |
1536 | spin_lock(&cp->stat_lock[0]); | |
6aa20a22 | 1537 | if (stat & MAC_RX_ALIGN_ERR) |
1f26dac3 DM |
1538 | cp->net_stats[0].rx_frame_errors += 0x10000; |
1539 | ||
1540 | if (stat & MAC_RX_CRC_ERR) | |
1541 | cp->net_stats[0].rx_crc_errors += 0x10000; | |
1542 | ||
1543 | if (stat & MAC_RX_LEN_ERR) | |
1544 | cp->net_stats[0].rx_length_errors += 0x10000; | |
1545 | ||
1546 | if (stat & MAC_RX_OVERFLOW) { | |
1547 | cp->net_stats[0].rx_over_errors++; | |
1548 | cp->net_stats[0].rx_fifo_errors++; | |
1549 | } | |
1550 | ||
1551 | /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR | |
1552 | * events. | |
1553 | */ | |
1554 | spin_unlock(&cp->stat_lock[0]); | |
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int cas_mac_interrupt(struct net_device *dev, struct cas *cp, | |
1559 | u32 status) | |
1560 | { | |
1561 | u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); | |
1562 | ||
1563 | if (!stat) | |
1564 | return 0; | |
1565 | ||
436d27d1 JP |
1566 | netif_printk(cp, intr, KERN_DEBUG, cp->dev, |
1567 | "mac interrupt, stat: 0x%x\n", stat); | |
1f26dac3 DM |
1568 | |
1569 | /* This interrupt is just for pause frame and pause | |
1570 | * tracking. It is useful for diagnostics and debug | |
1571 | * but probably by default we will mask these events. | |
1572 | */ | |
1573 | if (stat & MAC_CTRL_PAUSE_STATE) | |
1574 | cp->pause_entered++; | |
1575 | ||
1576 | if (stat & MAC_CTRL_PAUSE_RECEIVED) | |
1577 | cp->pause_last_time_recvd = (stat >> 16); | |
1578 | ||
1579 | return 0; | |
1580 | } | |
1581 | ||
6aa20a22 | 1582 | |
1f26dac3 DM |
1583 | /* Must be invoked under cp->lock. */ |
1584 | static inline int cas_mdio_link_not_up(struct cas *cp) | |
1585 | { | |
1586 | u16 val; | |
6aa20a22 | 1587 | |
1f26dac3 DM |
1588 | switch (cp->lstate) { |
1589 | case link_force_ret: | |
436d27d1 | 1590 | netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n"); |
1f26dac3 DM |
1591 | cas_phy_write(cp, MII_BMCR, cp->link_fcntl); |
1592 | cp->timer_ticks = 5; | |
1593 | cp->lstate = link_force_ok; | |
1594 | cp->link_transition = LINK_TRANSITION_LINK_CONFIG; | |
1595 | break; | |
6aa20a22 | 1596 | |
1f26dac3 DM |
1597 | case link_aneg: |
1598 | val = cas_phy_read(cp, MII_BMCR); | |
1599 | ||
1600 | /* Try forced modes. we try things in the following order: | |
1601 | * 1000 full -> 100 full/half -> 10 half | |
1602 | */ | |
1603 | val &= ~(BMCR_ANRESTART | BMCR_ANENABLE); | |
1604 | val |= BMCR_FULLDPLX; | |
6aa20a22 | 1605 | val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? |
1f26dac3 DM |
1606 | CAS_BMCR_SPEED1000 : BMCR_SPEED100; |
1607 | cas_phy_write(cp, MII_BMCR, val); | |
1608 | cp->timer_ticks = 5; | |
1609 | cp->lstate = link_force_try; | |
1610 | cp->link_transition = LINK_TRANSITION_LINK_CONFIG; | |
1611 | break; | |
1612 | ||
1613 | case link_force_try: | |
1614 | /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */ | |
1615 | val = cas_phy_read(cp, MII_BMCR); | |
1616 | cp->timer_ticks = 5; | |
1617 | if (val & CAS_BMCR_SPEED1000) { /* gigabit */ | |
1618 | val &= ~CAS_BMCR_SPEED1000; | |
1619 | val |= (BMCR_SPEED100 | BMCR_FULLDPLX); | |
1620 | cas_phy_write(cp, MII_BMCR, val); | |
1621 | break; | |
1622 | } | |
1623 | ||
1624 | if (val & BMCR_SPEED100) { | |
1625 | if (val & BMCR_FULLDPLX) /* fd failed */ | |
1626 | val &= ~BMCR_FULLDPLX; | |
1627 | else { /* 100Mbps failed */ | |
1628 | val &= ~BMCR_SPEED100; | |
1629 | } | |
1630 | cas_phy_write(cp, MII_BMCR, val); | |
1631 | break; | |
1632 | } | |
1633 | default: | |
1634 | break; | |
1635 | } | |
1636 | return 0; | |
1637 | } | |
1638 | ||
1639 | ||
1640 | /* must be invoked with cp->lock held */ | |
1641 | static int cas_mii_link_check(struct cas *cp, const u16 bmsr) | |
1642 | { | |
1643 | int restart; | |
1644 | ||
1645 | if (bmsr & BMSR_LSTATUS) { | |
1646 | /* Ok, here we got a link. If we had it due to a forced | |
6aa20a22 | 1647 | * fallback, and we were configured for autoneg, we |
1f26dac3 DM |
1648 | * retry a short autoneg pass. If you know your hub is |
1649 | * broken, use ethtool ;) | |
1650 | */ | |
6aa20a22 | 1651 | if ((cp->lstate == link_force_try) && |
1f26dac3 DM |
1652 | (cp->link_cntl & BMCR_ANENABLE)) { |
1653 | cp->lstate = link_force_ret; | |
1654 | cp->link_transition = LINK_TRANSITION_LINK_CONFIG; | |
1655 | cas_mif_poll(cp, 0); | |
1656 | cp->link_fcntl = cas_phy_read(cp, MII_BMCR); | |
1657 | cp->timer_ticks = 5; | |
436d27d1 JP |
1658 | if (cp->opened) |
1659 | netif_info(cp, link, cp->dev, | |
1660 | "Got link after fallback, retrying autoneg once...\n"); | |
1f26dac3 DM |
1661 | cas_phy_write(cp, MII_BMCR, |
1662 | cp->link_fcntl | BMCR_ANENABLE | | |
1663 | BMCR_ANRESTART); | |
1664 | cas_mif_poll(cp, 1); | |
1665 | ||
1666 | } else if (cp->lstate != link_up) { | |
1667 | cp->lstate = link_up; | |
1668 | cp->link_transition = LINK_TRANSITION_LINK_UP; | |
1669 | ||
1670 | if (cp->opened) { | |
1671 | cas_set_link_modes(cp); | |
1672 | netif_carrier_on(cp->dev); | |
1673 | } | |
1674 | } | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | /* link not up. if the link was previously up, we restart the | |
1679 | * whole process | |
1680 | */ | |
1681 | restart = 0; | |
1682 | if (cp->lstate == link_up) { | |
1683 | cp->lstate = link_down; | |
1684 | cp->link_transition = LINK_TRANSITION_LINK_DOWN; | |
1685 | ||
1686 | netif_carrier_off(cp->dev); | |
436d27d1 JP |
1687 | if (cp->opened) |
1688 | netif_info(cp, link, cp->dev, "Link down\n"); | |
1f26dac3 | 1689 | restart = 1; |
6aa20a22 | 1690 | |
1f26dac3 DM |
1691 | } else if (++cp->timer_ticks > 10) |
1692 | cas_mdio_link_not_up(cp); | |
6aa20a22 | 1693 | |
1f26dac3 DM |
1694 | return restart; |
1695 | } | |
1696 | ||
1697 | static int cas_mif_interrupt(struct net_device *dev, struct cas *cp, | |
1698 | u32 status) | |
1699 | { | |
1700 | u32 stat = readl(cp->regs + REG_MIF_STATUS); | |
1701 | u16 bmsr; | |
1702 | ||
1703 | /* check for a link change */ | |
1704 | if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0) | |
1705 | return 0; | |
1706 | ||
1707 | bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat); | |
1708 | return cas_mii_link_check(cp, bmsr); | |
1709 | } | |
1710 | ||
1711 | static int cas_pci_interrupt(struct net_device *dev, struct cas *cp, | |
1712 | u32 status) | |
1713 | { | |
1714 | u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); | |
1715 | ||
1716 | if (!stat) | |
1717 | return 0; | |
1718 | ||
436d27d1 JP |
1719 | netdev_err(dev, "PCI error [%04x:%04x]", |
1720 | stat, readl(cp->regs + REG_BIM_DIAG)); | |
1f26dac3 DM |
1721 | |
1722 | /* cassini+ has this reserved */ | |
1723 | if ((stat & PCI_ERR_BADACK) && | |
1724 | ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0)) | |
436d27d1 | 1725 | pr_cont(" <No ACK64# during ABS64 cycle>"); |
1f26dac3 DM |
1726 | |
1727 | if (stat & PCI_ERR_DTRTO) | |
436d27d1 | 1728 | pr_cont(" <Delayed transaction timeout>"); |
1f26dac3 | 1729 | if (stat & PCI_ERR_OTHER) |
436d27d1 | 1730 | pr_cont(" <other>"); |
1f26dac3 | 1731 | if (stat & PCI_ERR_BIM_DMA_WRITE) |
436d27d1 | 1732 | pr_cont(" <BIM DMA 0 write req>"); |
1f26dac3 | 1733 | if (stat & PCI_ERR_BIM_DMA_READ) |
436d27d1 JP |
1734 | pr_cont(" <BIM DMA 0 read req>"); |
1735 | pr_cont("\n"); | |
1f26dac3 DM |
1736 | |
1737 | if (stat & PCI_ERR_OTHER) { | |
1738 | u16 cfg; | |
1739 | ||
1740 | /* Interrogate PCI config space for the | |
1741 | * true cause. | |
1742 | */ | |
1743 | pci_read_config_word(cp->pdev, PCI_STATUS, &cfg); | |
436d27d1 | 1744 | netdev_err(dev, "Read PCI cfg space status [%04x]\n", cfg); |
1f26dac3 | 1745 | if (cfg & PCI_STATUS_PARITY) |
436d27d1 | 1746 | netdev_err(dev, "PCI parity error detected\n"); |
1f26dac3 | 1747 | if (cfg & PCI_STATUS_SIG_TARGET_ABORT) |
436d27d1 | 1748 | netdev_err(dev, "PCI target abort\n"); |
1f26dac3 | 1749 | if (cfg & PCI_STATUS_REC_TARGET_ABORT) |
436d27d1 | 1750 | netdev_err(dev, "PCI master acks target abort\n"); |
1f26dac3 | 1751 | if (cfg & PCI_STATUS_REC_MASTER_ABORT) |
436d27d1 | 1752 | netdev_err(dev, "PCI master abort\n"); |
1f26dac3 | 1753 | if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR) |
436d27d1 | 1754 | netdev_err(dev, "PCI system error SERR#\n"); |
1f26dac3 | 1755 | if (cfg & PCI_STATUS_DETECTED_PARITY) |
436d27d1 | 1756 | netdev_err(dev, "PCI parity error\n"); |
1f26dac3 DM |
1757 | |
1758 | /* Write the error bits back to clear them. */ | |
1759 | cfg &= (PCI_STATUS_PARITY | | |
1760 | PCI_STATUS_SIG_TARGET_ABORT | | |
1761 | PCI_STATUS_REC_TARGET_ABORT | | |
1762 | PCI_STATUS_REC_MASTER_ABORT | | |
1763 | PCI_STATUS_SIG_SYSTEM_ERROR | | |
1764 | PCI_STATUS_DETECTED_PARITY); | |
1765 | pci_write_config_word(cp->pdev, PCI_STATUS, cfg); | |
1766 | } | |
1767 | ||
1768 | /* For all PCI errors, we should reset the chip. */ | |
1769 | return 1; | |
1770 | } | |
1771 | ||
1772 | /* All non-normal interrupt conditions get serviced here. | |
1773 | * Returns non-zero if we should just exit the interrupt | |
1774 | * handler right now (ie. if we reset the card which invalidates | |
1775 | * all of the other original irq status bits). | |
1776 | */ | |
1777 | static int cas_abnormal_irq(struct net_device *dev, struct cas *cp, | |
1778 | u32 status) | |
1779 | { | |
1780 | if (status & INTR_RX_TAG_ERROR) { | |
1781 | /* corrupt RX tag framing */ | |
436d27d1 JP |
1782 | netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, |
1783 | "corrupt rx tag framing\n"); | |
1f26dac3 DM |
1784 | spin_lock(&cp->stat_lock[0]); |
1785 | cp->net_stats[0].rx_errors++; | |
1786 | spin_unlock(&cp->stat_lock[0]); | |
1787 | goto do_reset; | |
1788 | } | |
1789 | ||
1790 | if (status & INTR_RX_LEN_MISMATCH) { | |
1791 | /* length mismatch. */ | |
436d27d1 JP |
1792 | netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, |
1793 | "length mismatch for rx frame\n"); | |
1f26dac3 DM |
1794 | spin_lock(&cp->stat_lock[0]); |
1795 | cp->net_stats[0].rx_errors++; | |
1796 | spin_unlock(&cp->stat_lock[0]); | |
1797 | goto do_reset; | |
1798 | } | |
1799 | ||
1800 | if (status & INTR_PCS_STATUS) { | |
1801 | if (cas_pcs_interrupt(dev, cp, status)) | |
1802 | goto do_reset; | |
1803 | } | |
1804 | ||
1805 | if (status & INTR_TX_MAC_STATUS) { | |
1806 | if (cas_txmac_interrupt(dev, cp, status)) | |
1807 | goto do_reset; | |
1808 | } | |
1809 | ||
1810 | if (status & INTR_RX_MAC_STATUS) { | |
1811 | if (cas_rxmac_interrupt(dev, cp, status)) | |
1812 | goto do_reset; | |
1813 | } | |
1814 | ||
1815 | if (status & INTR_MAC_CTRL_STATUS) { | |
1816 | if (cas_mac_interrupt(dev, cp, status)) | |
1817 | goto do_reset; | |
1818 | } | |
1819 | ||
1820 | if (status & INTR_MIF_STATUS) { | |
1821 | if (cas_mif_interrupt(dev, cp, status)) | |
1822 | goto do_reset; | |
1823 | } | |
1824 | ||
1825 | if (status & INTR_PCI_ERROR_STATUS) { | |
1826 | if (cas_pci_interrupt(dev, cp, status)) | |
1827 | goto do_reset; | |
1828 | } | |
1829 | return 0; | |
1830 | ||
1831 | do_reset: | |
1832 | #if 1 | |
1833 | atomic_inc(&cp->reset_task_pending); | |
1834 | atomic_inc(&cp->reset_task_pending_all); | |
436d27d1 | 1835 | netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status); |
1f26dac3 DM |
1836 | schedule_work(&cp->reset_task); |
1837 | #else | |
1838 | atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); | |
436d27d1 | 1839 | netdev_err(dev, "reset called in cas_abnormal_irq\n"); |
1f26dac3 DM |
1840 | schedule_work(&cp->reset_task); |
1841 | #endif | |
1842 | return 1; | |
1843 | } | |
1844 | ||
1845 | /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when | |
1846 | * determining whether to do a netif_stop/wakeup | |
1847 | */ | |
1848 | #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1) | |
1849 | #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK) | |
1850 | static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr, | |
1851 | const int len) | |
1852 | { | |
1853 | unsigned long off = addr + len; | |
1854 | ||
1855 | if (CAS_TABORT(cp) == 1) | |
1856 | return 0; | |
1857 | if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN) | |
1858 | return 0; | |
1859 | return TX_TARGET_ABORT_LEN; | |
1860 | } | |
1861 | ||
1862 | static inline void cas_tx_ringN(struct cas *cp, int ring, int limit) | |
1863 | { | |
1864 | struct cas_tx_desc *txds; | |
1865 | struct sk_buff **skbs; | |
1866 | struct net_device *dev = cp->dev; | |
1867 | int entry, count; | |
1868 | ||
1869 | spin_lock(&cp->tx_lock[ring]); | |
1870 | txds = cp->init_txds[ring]; | |
1871 | skbs = cp->tx_skbs[ring]; | |
1872 | entry = cp->tx_old[ring]; | |
1873 | ||
1874 | count = TX_BUFF_COUNT(ring, entry, limit); | |
1875 | while (entry != limit) { | |
1876 | struct sk_buff *skb = skbs[entry]; | |
1877 | dma_addr_t daddr; | |
1878 | u32 dlen; | |
1879 | int frag; | |
1880 | ||
1881 | if (!skb) { | |
1882 | /* this should never occur */ | |
1883 | entry = TX_DESC_NEXT(ring, entry); | |
1884 | continue; | |
1885 | } | |
1886 | ||
1887 | /* however, we might get only a partial skb release. */ | |
1888 | count -= skb_shinfo(skb)->nr_frags + | |
1889 | + cp->tx_tiny_use[ring][entry].nbufs + 1; | |
1890 | if (count < 0) | |
1891 | break; | |
1892 | ||
436d27d1 JP |
1893 | netif_printk(cp, tx_done, KERN_DEBUG, cp->dev, |
1894 | "tx[%d] done, slot %d\n", ring, entry); | |
1f26dac3 DM |
1895 | |
1896 | skbs[entry] = NULL; | |
1897 | cp->tx_tiny_use[ring][entry].nbufs = 0; | |
6aa20a22 | 1898 | |
1f26dac3 DM |
1899 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { |
1900 | struct cas_tx_desc *txd = txds + entry; | |
1901 | ||
1902 | daddr = le64_to_cpu(txd->buffer); | |
1903 | dlen = CAS_VAL(TX_DESC_BUFLEN, | |
1904 | le64_to_cpu(txd->control)); | |
1905 | pci_unmap_page(cp->pdev, daddr, dlen, | |
1906 | PCI_DMA_TODEVICE); | |
1907 | entry = TX_DESC_NEXT(ring, entry); | |
1908 | ||
1909 | /* tiny buffer may follow */ | |
1910 | if (cp->tx_tiny_use[ring][entry].used) { | |
1911 | cp->tx_tiny_use[ring][entry].used = 0; | |
1912 | entry = TX_DESC_NEXT(ring, entry); | |
6aa20a22 | 1913 | } |
1f26dac3 DM |
1914 | } |
1915 | ||
1916 | spin_lock(&cp->stat_lock[ring]); | |
1917 | cp->net_stats[ring].tx_packets++; | |
1918 | cp->net_stats[ring].tx_bytes += skb->len; | |
1919 | spin_unlock(&cp->stat_lock[ring]); | |
1920 | dev_kfree_skb_irq(skb); | |
1921 | } | |
1922 | cp->tx_old[ring] = entry; | |
1923 | ||
1924 | /* this is wrong for multiple tx rings. the net device needs | |
1925 | * multiple queues for this to do the right thing. we wait | |
1926 | * for 2*packets to be available when using tiny buffers | |
1927 | */ | |
1928 | if (netif_queue_stopped(dev) && | |
1929 | (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))) | |
1930 | netif_wake_queue(dev); | |
1931 | spin_unlock(&cp->tx_lock[ring]); | |
1932 | } | |
1933 | ||
1934 | static void cas_tx(struct net_device *dev, struct cas *cp, | |
1935 | u32 status) | |
1936 | { | |
1937 | int limit, ring; | |
1938 | #ifdef USE_TX_COMPWB | |
1939 | u64 compwb = le64_to_cpu(cp->init_block->tx_compwb); | |
1940 | #endif | |
436d27d1 JP |
1941 | netif_printk(cp, intr, KERN_DEBUG, cp->dev, |
1942 | "tx interrupt, status: 0x%x, %llx\n", | |
1943 | status, (unsigned long long)compwb); | |
1f26dac3 DM |
1944 | /* process all the rings */ |
1945 | for (ring = 0; ring < N_TX_RINGS; ring++) { | |
1946 | #ifdef USE_TX_COMPWB | |
1947 | /* use the completion writeback registers */ | |
1948 | limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) | | |
1949 | CAS_VAL(TX_COMPWB_LSB, compwb); | |
1950 | compwb = TX_COMPWB_NEXT(compwb); | |
1951 | #else | |
1952 | limit = readl(cp->regs + REG_TX_COMPN(ring)); | |
1953 | #endif | |
6aa20a22 | 1954 | if (cp->tx_old[ring] != limit) |
1f26dac3 DM |
1955 | cas_tx_ringN(cp, ring, limit); |
1956 | } | |
1957 | } | |
1958 | ||
1959 | ||
6aa20a22 JG |
1960 | static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, |
1961 | int entry, const u64 *words, | |
1f26dac3 DM |
1962 | struct sk_buff **skbref) |
1963 | { | |
1964 | int dlen, hlen, len, i, alloclen; | |
1965 | int off, swivel = RX_SWIVEL_OFF_VAL; | |
1966 | struct cas_page *page; | |
1967 | struct sk_buff *skb; | |
1968 | void *addr, *crcaddr; | |
e5e02540 | 1969 | __sum16 csum; |
6aa20a22 | 1970 | char *p; |
1f26dac3 DM |
1971 | |
1972 | hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]); | |
1973 | dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]); | |
1974 | len = hlen + dlen; | |
1975 | ||
6aa20a22 | 1976 | if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) |
1f26dac3 | 1977 | alloclen = len; |
6aa20a22 | 1978 | else |
1f26dac3 DM |
1979 | alloclen = max(hlen, RX_COPY_MIN); |
1980 | ||
1981 | skb = dev_alloc_skb(alloclen + swivel + cp->crc_size); | |
6aa20a22 | 1982 | if (skb == NULL) |
1f26dac3 DM |
1983 | return -1; |
1984 | ||
1985 | *skbref = skb; | |
1f26dac3 DM |
1986 | skb_reserve(skb, swivel); |
1987 | ||
1988 | p = skb->data; | |
1989 | addr = crcaddr = NULL; | |
1990 | if (hlen) { /* always copy header pages */ | |
1991 | i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); | |
1992 | page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; | |
6aa20a22 | 1993 | off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + |
1f26dac3 DM |
1994 | swivel; |
1995 | ||
1996 | i = hlen; | |
1997 | if (!dlen) /* attach FCS */ | |
1998 | i += cp->crc_size; | |
1999 | pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, | |
2000 | PCI_DMA_FROMDEVICE); | |
2001 | addr = cas_page_map(page->buffer); | |
2002 | memcpy(p, addr + off, i); | |
2003 | pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, | |
2004 | PCI_DMA_FROMDEVICE); | |
2005 | cas_page_unmap(addr); | |
2006 | RX_USED_ADD(page, 0x100); | |
2007 | p += hlen; | |
2008 | swivel = 0; | |
6aa20a22 | 2009 | } |
1f26dac3 DM |
2010 | |
2011 | ||
2012 | if (alloclen < (hlen + dlen)) { | |
2013 | skb_frag_t *frag = skb_shinfo(skb)->frags; | |
2014 | ||
2015 | /* normal or jumbo packets. we use frags */ | |
2016 | i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); | |
2017 | page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; | |
2018 | off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; | |
2019 | ||
2020 | hlen = min(cp->page_size - off, dlen); | |
2021 | if (hlen < 0) { | |
436d27d1 JP |
2022 | netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, |
2023 | "rx page overflow: %d\n", hlen); | |
1f26dac3 DM |
2024 | dev_kfree_skb_irq(skb); |
2025 | return -1; | |
2026 | } | |
2027 | i = hlen; | |
2028 | if (i == dlen) /* attach FCS */ | |
2029 | i += cp->crc_size; | |
2030 | pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, | |
2031 | PCI_DMA_FROMDEVICE); | |
2032 | ||
2033 | /* make sure we always copy a header */ | |
2034 | swivel = 0; | |
2035 | if (p == (char *) skb->data) { /* not split */ | |
2036 | addr = cas_page_map(page->buffer); | |
2037 | memcpy(p, addr + off, RX_COPY_MIN); | |
2038 | pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, | |
2039 | PCI_DMA_FROMDEVICE); | |
2040 | cas_page_unmap(addr); | |
2041 | off += RX_COPY_MIN; | |
2042 | swivel = RX_COPY_MIN; | |
2043 | RX_USED_ADD(page, cp->mtu_stride); | |
2044 | } else { | |
2045 | RX_USED_ADD(page, hlen); | |
2046 | } | |
2047 | skb_put(skb, alloclen); | |
2048 | ||
2049 | skb_shinfo(skb)->nr_frags++; | |
2050 | skb->data_len += hlen - swivel; | |
d011a231 | 2051 | skb->truesize += hlen - swivel; |
1f26dac3 DM |
2052 | skb->len += hlen - swivel; |
2053 | ||
2054 | get_page(page->buffer); | |
2055 | frag->page = page->buffer; | |
2056 | frag->page_offset = off; | |
2057 | frag->size = hlen - swivel; | |
6aa20a22 | 2058 | |
1f26dac3 DM |
2059 | /* any more data? */ |
2060 | if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { | |
2061 | hlen = dlen; | |
2062 | off = 0; | |
2063 | ||
2064 | i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); | |
2065 | page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; | |
6aa20a22 JG |
2066 | pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, |
2067 | hlen + cp->crc_size, | |
1f26dac3 DM |
2068 | PCI_DMA_FROMDEVICE); |
2069 | pci_dma_sync_single_for_device(cp->pdev, page->dma_addr, | |
2070 | hlen + cp->crc_size, | |
2071 | PCI_DMA_FROMDEVICE); | |
2072 | ||
2073 | skb_shinfo(skb)->nr_frags++; | |
2074 | skb->data_len += hlen; | |
6aa20a22 | 2075 | skb->len += hlen; |
1f26dac3 DM |
2076 | frag++; |
2077 | ||
2078 | get_page(page->buffer); | |
2079 | frag->page = page->buffer; | |
2080 | frag->page_offset = 0; | |
2081 | frag->size = hlen; | |
2082 | RX_USED_ADD(page, hlen + cp->crc_size); | |
2083 | } | |
2084 | ||
2085 | if (cp->crc_size) { | |
2086 | addr = cas_page_map(page->buffer); | |
2087 | crcaddr = addr + off + hlen; | |
2088 | } | |
2089 | ||
2090 | } else { | |
2091 | /* copying packet */ | |
2092 | if (!dlen) | |
2093 | goto end_copy_pkt; | |
2094 | ||
2095 | i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); | |
2096 | page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; | |
2097 | off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; | |
2098 | hlen = min(cp->page_size - off, dlen); | |
2099 | if (hlen < 0) { | |
436d27d1 JP |
2100 | netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, |
2101 | "rx page overflow: %d\n", hlen); | |
1f26dac3 DM |
2102 | dev_kfree_skb_irq(skb); |
2103 | return -1; | |
2104 | } | |
2105 | i = hlen; | |
2106 | if (i == dlen) /* attach FCS */ | |
2107 | i += cp->crc_size; | |
2108 | pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, | |
2109 | PCI_DMA_FROMDEVICE); | |
2110 | addr = cas_page_map(page->buffer); | |
2111 | memcpy(p, addr + off, i); | |
2112 | pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, | |
2113 | PCI_DMA_FROMDEVICE); | |
2114 | cas_page_unmap(addr); | |
2115 | if (p == (char *) skb->data) /* not split */ | |
2116 | RX_USED_ADD(page, cp->mtu_stride); | |
2117 | else | |
2118 | RX_USED_ADD(page, i); | |
6aa20a22 | 2119 | |
1f26dac3 DM |
2120 | /* any more data? */ |
2121 | if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { | |
2122 | p += hlen; | |
2123 | i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); | |
2124 | page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; | |
6aa20a22 JG |
2125 | pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, |
2126 | dlen + cp->crc_size, | |
1f26dac3 DM |
2127 | PCI_DMA_FROMDEVICE); |
2128 | addr = cas_page_map(page->buffer); | |
2129 | memcpy(p, addr, dlen + cp->crc_size); | |
2130 | pci_dma_sync_single_for_device(cp->pdev, page->dma_addr, | |
2131 | dlen + cp->crc_size, | |
2132 | PCI_DMA_FROMDEVICE); | |
2133 | cas_page_unmap(addr); | |
6aa20a22 | 2134 | RX_USED_ADD(page, dlen + cp->crc_size); |
1f26dac3 DM |
2135 | } |
2136 | end_copy_pkt: | |
2137 | if (cp->crc_size) { | |
2138 | addr = NULL; | |
2139 | crcaddr = skb->data + alloclen; | |
2140 | } | |
2141 | skb_put(skb, alloclen); | |
2142 | } | |
2143 | ||
e5e02540 | 2144 | csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3])); |
1f26dac3 DM |
2145 | if (cp->crc_size) { |
2146 | /* checksum includes FCS. strip it out. */ | |
e5e02540 AV |
2147 | csum = csum_fold(csum_partial(crcaddr, cp->crc_size, |
2148 | csum_unfold(csum))); | |
1f26dac3 DM |
2149 | if (addr) |
2150 | cas_page_unmap(addr); | |
2151 | } | |
1f26dac3 | 2152 | skb->protocol = eth_type_trans(skb, cp->dev); |
b1443e2f DM |
2153 | if (skb->protocol == htons(ETH_P_IP)) { |
2154 | skb->csum = csum_unfold(~csum); | |
2155 | skb->ip_summed = CHECKSUM_COMPLETE; | |
2156 | } else | |
2157 | skb->ip_summed = CHECKSUM_NONE; | |
1f26dac3 DM |
2158 | return len; |
2159 | } | |
2160 | ||
2161 | ||
2162 | /* we can handle up to 64 rx flows at a time. we do the same thing | |
6aa20a22 | 2163 | * as nonreassm except that we batch up the buffers. |
1f26dac3 DM |
2164 | * NOTE: we currently just treat each flow as a bunch of packets that |
2165 | * we pass up. a better way would be to coalesce the packets | |
2166 | * into a jumbo packet. to do that, we need to do the following: | |
2167 | * 1) the first packet will have a clean split between header and | |
2168 | * data. save both. | |
2169 | * 2) each time the next flow packet comes in, extend the | |
2170 | * data length and merge the checksums. | |
2171 | * 3) on flow release, fix up the header. | |
2172 | * 4) make sure the higher layer doesn't care. | |
6aa20a22 | 2173 | * because packets get coalesced, we shouldn't run into fragment count |
1f26dac3 DM |
2174 | * issues. |
2175 | */ | |
2176 | static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words, | |
2177 | struct sk_buff *skb) | |
2178 | { | |
2179 | int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1); | |
2180 | struct sk_buff_head *flow = &cp->rx_flows[flowid]; | |
6aa20a22 JG |
2181 | |
2182 | /* this is protected at a higher layer, so no need to | |
1f26dac3 DM |
2183 | * do any additional locking here. stick the buffer |
2184 | * at the end. | |
2185 | */ | |
43f59c89 | 2186 | __skb_queue_tail(flow, skb); |
1f26dac3 DM |
2187 | if (words[0] & RX_COMP1_RELEASE_FLOW) { |
2188 | while ((skb = __skb_dequeue(flow))) { | |
2189 | cas_skb_release(skb); | |
2190 | } | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | /* put rx descriptor back on ring. if a buffer is in use by a higher | |
2195 | * layer, this will need to put in a replacement. | |
2196 | */ | |
2197 | static void cas_post_page(struct cas *cp, const int ring, const int index) | |
2198 | { | |
2199 | cas_page_t *new; | |
2200 | int entry; | |
2201 | ||
2202 | entry = cp->rx_old[ring]; | |
2203 | ||
2204 | new = cas_page_swap(cp, ring, index); | |
2205 | cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr); | |
2206 | cp->init_rxds[ring][entry].index = | |
6aa20a22 | 2207 | cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | |
1f26dac3 DM |
2208 | CAS_BASE(RX_INDEX_RING, ring)); |
2209 | ||
2210 | entry = RX_DESC_ENTRY(ring, entry + 1); | |
2211 | cp->rx_old[ring] = entry; | |
6aa20a22 | 2212 | |
1f26dac3 DM |
2213 | if (entry % 4) |
2214 | return; | |
2215 | ||
2216 | if (ring == 0) | |
2217 | writel(entry, cp->regs + REG_RX_KICK); | |
2218 | else if ((N_RX_DESC_RINGS > 1) && | |
6aa20a22 | 2219 | (cp->cas_flags & CAS_FLAG_REG_PLUS)) |
1f26dac3 DM |
2220 | writel(entry, cp->regs + REG_PLUS_RX_KICK1); |
2221 | } | |
2222 | ||
2223 | ||
2224 | /* only when things are bad */ | |
2225 | static int cas_post_rxds_ringN(struct cas *cp, int ring, int num) | |
2226 | { | |
2227 | unsigned int entry, last, count, released; | |
2228 | int cluster; | |
2229 | cas_page_t **page = cp->rx_pages[ring]; | |
2230 | ||
2231 | entry = cp->rx_old[ring]; | |
2232 | ||
436d27d1 JP |
2233 | netif_printk(cp, intr, KERN_DEBUG, cp->dev, |
2234 | "rxd[%d] interrupt, done: %d\n", ring, entry); | |
1f26dac3 DM |
2235 | |
2236 | cluster = -1; | |
6aa20a22 | 2237 | count = entry & 0x3; |
1f26dac3 DM |
2238 | last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4); |
2239 | released = 0; | |
2240 | while (entry != last) { | |
2241 | /* make a new buffer if it's still in use */ | |
9de4dfb4 | 2242 | if (page_count(page[entry]->buffer) > 1) { |
1f26dac3 DM |
2243 | cas_page_t *new = cas_page_dequeue(cp); |
2244 | if (!new) { | |
6aa20a22 | 2245 | /* let the timer know that we need to |
1f26dac3 DM |
2246 | * do this again |
2247 | */ | |
2248 | cp->cas_flags |= CAS_FLAG_RXD_POST(ring); | |
2249 | if (!timer_pending(&cp->link_timer)) | |
6aa20a22 | 2250 | mod_timer(&cp->link_timer, jiffies + |
1f26dac3 DM |
2251 | CAS_LINK_FAST_TIMEOUT); |
2252 | cp->rx_old[ring] = entry; | |
2253 | cp->rx_last[ring] = num ? num - released : 0; | |
2254 | return -ENOMEM; | |
2255 | } | |
2256 | spin_lock(&cp->rx_inuse_lock); | |
2257 | list_add(&page[entry]->list, &cp->rx_inuse_list); | |
2258 | spin_unlock(&cp->rx_inuse_lock); | |
6aa20a22 | 2259 | cp->init_rxds[ring][entry].buffer = |
1f26dac3 DM |
2260 | cpu_to_le64(new->dma_addr); |
2261 | page[entry] = new; | |
6aa20a22 | 2262 | |
1f26dac3 DM |
2263 | } |
2264 | ||
2265 | if (++count == 4) { | |
2266 | cluster = entry; | |
2267 | count = 0; | |
2268 | } | |
2269 | released++; | |
2270 | entry = RX_DESC_ENTRY(ring, entry + 1); | |
2271 | } | |
2272 | cp->rx_old[ring] = entry; | |
2273 | ||
6aa20a22 | 2274 | if (cluster < 0) |
1f26dac3 DM |
2275 | return 0; |
2276 | ||
2277 | if (ring == 0) | |
2278 | writel(cluster, cp->regs + REG_RX_KICK); | |
2279 | else if ((N_RX_DESC_RINGS > 1) && | |
6aa20a22 | 2280 | (cp->cas_flags & CAS_FLAG_REG_PLUS)) |
1f26dac3 DM |
2281 | writel(cluster, cp->regs + REG_PLUS_RX_KICK1); |
2282 | return 0; | |
2283 | } | |
2284 | ||
2285 | ||
2286 | /* process a completion ring. packets are set up in three basic ways: | |
2287 | * small packets: should be copied header + data in single buffer. | |
2288 | * large packets: header and data in a single buffer. | |
6aa20a22 | 2289 | * split packets: header in a separate buffer from data. |
1f26dac3 | 2290 | * data may be in multiple pages. data may be > 256 |
6aa20a22 | 2291 | * bytes but in a single page. |
1f26dac3 DM |
2292 | * |
2293 | * NOTE: RX page posting is done in this routine as well. while there's | |
2294 | * the capability of using multiple RX completion rings, it isn't | |
2295 | * really worthwhile due to the fact that the page posting will | |
6aa20a22 | 2296 | * force serialization on the single descriptor ring. |
1f26dac3 DM |
2297 | */ |
2298 | static int cas_rx_ringN(struct cas *cp, int ring, int budget) | |
2299 | { | |
2300 | struct cas_rx_comp *rxcs = cp->init_rxcs[ring]; | |
2301 | int entry, drops; | |
2302 | int npackets = 0; | |
2303 | ||
436d27d1 JP |
2304 | netif_printk(cp, intr, KERN_DEBUG, cp->dev, |
2305 | "rx[%d] interrupt, done: %d/%d\n", | |
2306 | ring, | |
2307 | readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]); | |
1f26dac3 DM |
2308 | |
2309 | entry = cp->rx_new[ring]; | |
2310 | drops = 0; | |
2311 | while (1) { | |
2312 | struct cas_rx_comp *rxc = rxcs + entry; | |
b71e839f | 2313 | struct sk_buff *uninitialized_var(skb); |
1f26dac3 DM |
2314 | int type, len; |
2315 | u64 words[4]; | |
2316 | int i, dring; | |
2317 | ||
2318 | words[0] = le64_to_cpu(rxc->word1); | |
2319 | words[1] = le64_to_cpu(rxc->word2); | |
2320 | words[2] = le64_to_cpu(rxc->word3); | |
2321 | words[3] = le64_to_cpu(rxc->word4); | |
2322 | ||
2323 | /* don't touch if still owned by hw */ | |
2324 | type = CAS_VAL(RX_COMP1_TYPE, words[0]); | |
2325 | if (type == 0) | |
2326 | break; | |
2327 | ||
2328 | /* hw hasn't cleared the zero bit yet */ | |
2329 | if (words[3] & RX_COMP4_ZERO) { | |
2330 | break; | |
2331 | } | |
2332 | ||
2333 | /* get info on the packet */ | |
2334 | if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) { | |
2335 | spin_lock(&cp->stat_lock[ring]); | |
2336 | cp->net_stats[ring].rx_errors++; | |
2337 | if (words[3] & RX_COMP4_LEN_MISMATCH) | |
2338 | cp->net_stats[ring].rx_length_errors++; | |
2339 | if (words[3] & RX_COMP4_BAD) | |
2340 | cp->net_stats[ring].rx_crc_errors++; | |
2341 | spin_unlock(&cp->stat_lock[ring]); | |
2342 | ||
2343 | /* We'll just return it to Cassini. */ | |
2344 | drop_it: | |
2345 | spin_lock(&cp->stat_lock[ring]); | |
2346 | ++cp->net_stats[ring].rx_dropped; | |
2347 | spin_unlock(&cp->stat_lock[ring]); | |
2348 | goto next; | |
2349 | } | |
2350 | ||
2351 | len = cas_rx_process_pkt(cp, rxc, entry, words, &skb); | |
2352 | if (len < 0) { | |
2353 | ++drops; | |
2354 | goto drop_it; | |
2355 | } | |
2356 | ||
2357 | /* see if it's a flow re-assembly or not. the driver | |
2358 | * itself handles release back up. | |
2359 | */ | |
2360 | if (RX_DONT_BATCH || (type == 0x2)) { | |
2361 | /* non-reassm: these always get released */ | |
6aa20a22 | 2362 | cas_skb_release(skb); |
1f26dac3 DM |
2363 | } else { |
2364 | cas_rx_flow_pkt(cp, words, skb); | |
2365 | } | |
2366 | ||
2367 | spin_lock(&cp->stat_lock[ring]); | |
2368 | cp->net_stats[ring].rx_packets++; | |
2369 | cp->net_stats[ring].rx_bytes += len; | |
2370 | spin_unlock(&cp->stat_lock[ring]); | |
1f26dac3 DM |
2371 | |
2372 | next: | |
2373 | npackets++; | |
2374 | ||
2375 | /* should it be released? */ | |
2376 | if (words[0] & RX_COMP1_RELEASE_HDR) { | |
2377 | i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); | |
2378 | dring = CAS_VAL(RX_INDEX_RING, i); | |
2379 | i = CAS_VAL(RX_INDEX_NUM, i); | |
2380 | cas_post_page(cp, dring, i); | |
2381 | } | |
6aa20a22 | 2382 | |
1f26dac3 DM |
2383 | if (words[0] & RX_COMP1_RELEASE_DATA) { |
2384 | i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); | |
2385 | dring = CAS_VAL(RX_INDEX_RING, i); | |
2386 | i = CAS_VAL(RX_INDEX_NUM, i); | |
2387 | cas_post_page(cp, dring, i); | |
2388 | } | |
2389 | ||
2390 | if (words[0] & RX_COMP1_RELEASE_NEXT) { | |
2391 | i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); | |
2392 | dring = CAS_VAL(RX_INDEX_RING, i); | |
2393 | i = CAS_VAL(RX_INDEX_NUM, i); | |
2394 | cas_post_page(cp, dring, i); | |
2395 | } | |
2396 | ||
2397 | /* skip to the next entry */ | |
6aa20a22 | 2398 | entry = RX_COMP_ENTRY(ring, entry + 1 + |
1f26dac3 DM |
2399 | CAS_VAL(RX_COMP1_SKIP, words[0])); |
2400 | #ifdef USE_NAPI | |
2401 | if (budget && (npackets >= budget)) | |
2402 | break; | |
2403 | #endif | |
2404 | } | |
2405 | cp->rx_new[ring] = entry; | |
2406 | ||
2407 | if (drops) | |
436d27d1 | 2408 | netdev_info(cp->dev, "Memory squeeze, deferring packet\n"); |
1f26dac3 DM |
2409 | return npackets; |
2410 | } | |
2411 | ||
2412 | ||
2413 | /* put completion entries back on the ring */ | |
2414 | static void cas_post_rxcs_ringN(struct net_device *dev, | |
2415 | struct cas *cp, int ring) | |
2416 | { | |
2417 | struct cas_rx_comp *rxc = cp->init_rxcs[ring]; | |
2418 | int last, entry; | |
2419 | ||
2420 | last = cp->rx_cur[ring]; | |
6aa20a22 | 2421 | entry = cp->rx_new[ring]; |
436d27d1 JP |
2422 | netif_printk(cp, intr, KERN_DEBUG, dev, |
2423 | "rxc[%d] interrupt, done: %d/%d\n", | |
2424 | ring, readl(cp->regs + REG_RX_COMP_HEAD), entry); | |
6aa20a22 | 2425 | |
1f26dac3 DM |
2426 | /* zero and re-mark descriptors */ |
2427 | while (last != entry) { | |
2428 | cas_rxc_init(rxc + last); | |
2429 | last = RX_COMP_ENTRY(ring, last + 1); | |
2430 | } | |
2431 | cp->rx_cur[ring] = last; | |
2432 | ||
2433 | if (ring == 0) | |
2434 | writel(last, cp->regs + REG_RX_COMP_TAIL); | |
6aa20a22 | 2435 | else if (cp->cas_flags & CAS_FLAG_REG_PLUS) |
1f26dac3 DM |
2436 | writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); |
2437 | } | |
2438 | ||
2439 | ||
2440 | ||
6aa20a22 | 2441 | /* cassini can use all four PCI interrupts for the completion ring. |
1f26dac3 DM |
2442 | * rings 3 and 4 are identical |
2443 | */ | |
2444 | #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD) | |
6aa20a22 | 2445 | static inline void cas_handle_irqN(struct net_device *dev, |
1f26dac3 DM |
2446 | struct cas *cp, const u32 status, |
2447 | const int ring) | |
2448 | { | |
6aa20a22 | 2449 | if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) |
1f26dac3 DM |
2450 | cas_post_rxcs_ringN(dev, cp, ring); |
2451 | } | |
2452 | ||
7d12e780 | 2453 | static irqreturn_t cas_interruptN(int irq, void *dev_id) |
1f26dac3 DM |
2454 | { |
2455 | struct net_device *dev = dev_id; | |
2456 | struct cas *cp = netdev_priv(dev); | |
2457 | unsigned long flags; | |
2458 | int ring; | |
2459 | u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); | |
2460 | ||
2461 | /* check for shared irq */ | |
2462 | if (status == 0) | |
2463 | return IRQ_NONE; | |
2464 | ||
2465 | ring = (irq == cp->pci_irq_INTC) ? 2 : 3; | |
2466 | spin_lock_irqsave(&cp->lock, flags); | |
2467 | if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ | |
2468 | #ifdef USE_NAPI | |
2469 | cas_mask_intr(cp); | |
288379f0 | 2470 | napi_schedule(&cp->napi); |
1f26dac3 DM |
2471 | #else |
2472 | cas_rx_ringN(cp, ring, 0); | |
2473 | #endif | |
2474 | status &= ~INTR_RX_DONE_ALT; | |
2475 | } | |
2476 | ||
2477 | if (status) | |
2478 | cas_handle_irqN(dev, cp, status, ring); | |
2479 | spin_unlock_irqrestore(&cp->lock, flags); | |
2480 | return IRQ_HANDLED; | |
2481 | } | |
2482 | #endif | |
2483 | ||
2484 | #ifdef USE_PCI_INTB | |
2485 | /* everything but rx packets */ | |
2486 | static inline void cas_handle_irq1(struct cas *cp, const u32 status) | |
2487 | { | |
2488 | if (status & INTR_RX_BUF_UNAVAIL_1) { | |
6aa20a22 | 2489 | /* Frame arrived, no free RX buffers available. |
1f26dac3 DM |
2490 | * NOTE: we can get this on a link transition. */ |
2491 | cas_post_rxds_ringN(cp, 1, 0); | |
2492 | spin_lock(&cp->stat_lock[1]); | |
2493 | cp->net_stats[1].rx_dropped++; | |
2494 | spin_unlock(&cp->stat_lock[1]); | |
2495 | } | |
2496 | ||
6aa20a22 JG |
2497 | if (status & INTR_RX_BUF_AE_1) |
2498 | cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - | |
1f26dac3 DM |
2499 | RX_AE_FREEN_VAL(1)); |
2500 | ||
2501 | if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) | |
2502 | cas_post_rxcs_ringN(cp, 1); | |
2503 | } | |
2504 | ||
2505 | /* ring 2 handles a few more events than 3 and 4 */ | |
7d12e780 | 2506 | static irqreturn_t cas_interrupt1(int irq, void *dev_id) |
1f26dac3 DM |
2507 | { |
2508 | struct net_device *dev = dev_id; | |
2509 | struct cas *cp = netdev_priv(dev); | |
2510 | unsigned long flags; | |
2511 | u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); | |
2512 | ||
2513 | /* check for shared interrupt */ | |
2514 | if (status == 0) | |
2515 | return IRQ_NONE; | |
2516 | ||
2517 | spin_lock_irqsave(&cp->lock, flags); | |
2518 | if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ | |
2519 | #ifdef USE_NAPI | |
2520 | cas_mask_intr(cp); | |
288379f0 | 2521 | napi_schedule(&cp->napi); |
1f26dac3 DM |
2522 | #else |
2523 | cas_rx_ringN(cp, 1, 0); | |
2524 | #endif | |
2525 | status &= ~INTR_RX_DONE_ALT; | |
2526 | } | |
2527 | if (status) | |
2528 | cas_handle_irq1(cp, status); | |
2529 | spin_unlock_irqrestore(&cp->lock, flags); | |
2530 | return IRQ_HANDLED; | |
2531 | } | |
2532 | #endif | |
2533 | ||
2534 | static inline void cas_handle_irq(struct net_device *dev, | |
2535 | struct cas *cp, const u32 status) | |
2536 | { | |
2537 | /* housekeeping interrupts */ | |
2538 | if (status & INTR_ERROR_MASK) | |
2539 | cas_abnormal_irq(dev, cp, status); | |
2540 | ||
2541 | if (status & INTR_RX_BUF_UNAVAIL) { | |
6aa20a22 | 2542 | /* Frame arrived, no free RX buffers available. |
1f26dac3 DM |
2543 | * NOTE: we can get this on a link transition. |
2544 | */ | |
2545 | cas_post_rxds_ringN(cp, 0, 0); | |
2546 | spin_lock(&cp->stat_lock[0]); | |
2547 | cp->net_stats[0].rx_dropped++; | |
2548 | spin_unlock(&cp->stat_lock[0]); | |
2549 | } else if (status & INTR_RX_BUF_AE) { | |
2550 | cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) - | |
2551 | RX_AE_FREEN_VAL(0)); | |
2552 | } | |
2553 | ||
2554 | if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) | |
2555 | cas_post_rxcs_ringN(dev, cp, 0); | |
2556 | } | |
2557 | ||
7d12e780 | 2558 | static irqreturn_t cas_interrupt(int irq, void *dev_id) |
1f26dac3 DM |
2559 | { |
2560 | struct net_device *dev = dev_id; | |
2561 | struct cas *cp = netdev_priv(dev); | |
2562 | unsigned long flags; | |
2563 | u32 status = readl(cp->regs + REG_INTR_STATUS); | |
2564 | ||
2565 | if (status == 0) | |
2566 | return IRQ_NONE; | |
2567 | ||
2568 | spin_lock_irqsave(&cp->lock, flags); | |
2569 | if (status & (INTR_TX_ALL | INTR_TX_INTME)) { | |
2570 | cas_tx(dev, cp, status); | |
2571 | status &= ~(INTR_TX_ALL | INTR_TX_INTME); | |
2572 | } | |
2573 | ||
2574 | if (status & INTR_RX_DONE) { | |
2575 | #ifdef USE_NAPI | |
2576 | cas_mask_intr(cp); | |
288379f0 | 2577 | napi_schedule(&cp->napi); |
1f26dac3 DM |
2578 | #else |
2579 | cas_rx_ringN(cp, 0, 0); | |
2580 | #endif | |
2581 | status &= ~INTR_RX_DONE; | |
2582 | } | |
2583 | ||
2584 | if (status) | |
2585 | cas_handle_irq(dev, cp, status); | |
2586 | spin_unlock_irqrestore(&cp->lock, flags); | |
2587 | return IRQ_HANDLED; | |
2588 | } | |
2589 | ||
2590 | ||
2591 | #ifdef USE_NAPI | |
bea3348e | 2592 | static int cas_poll(struct napi_struct *napi, int budget) |
1f26dac3 | 2593 | { |
bea3348e SH |
2594 | struct cas *cp = container_of(napi, struct cas, napi); |
2595 | struct net_device *dev = cp->dev; | |
86216268 | 2596 | int i, enable_intr, credits; |
1f26dac3 DM |
2597 | u32 status = readl(cp->regs + REG_INTR_STATUS); |
2598 | unsigned long flags; | |
2599 | ||
2600 | spin_lock_irqsave(&cp->lock, flags); | |
2601 | cas_tx(dev, cp, status); | |
2602 | spin_unlock_irqrestore(&cp->lock, flags); | |
2603 | ||
2604 | /* NAPI rx packets. we spread the credits across all of the | |
2605 | * rxc rings | |
bea3348e SH |
2606 | * |
2607 | * to make sure we're fair with the work we loop through each | |
6aa20a22 | 2608 | * ring N_RX_COMP_RING times with a request of |
bea3348e | 2609 | * budget / N_RX_COMP_RINGS |
1f26dac3 DM |
2610 | */ |
2611 | enable_intr = 1; | |
2612 | credits = 0; | |
2613 | for (i = 0; i < N_RX_COMP_RINGS; i++) { | |
2614 | int j; | |
2615 | for (j = 0; j < N_RX_COMP_RINGS; j++) { | |
bea3348e SH |
2616 | credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS); |
2617 | if (credits >= budget) { | |
1f26dac3 DM |
2618 | enable_intr = 0; |
2619 | goto rx_comp; | |
2620 | } | |
2621 | } | |
2622 | } | |
2623 | ||
2624 | rx_comp: | |
1f26dac3 DM |
2625 | /* final rx completion */ |
2626 | spin_lock_irqsave(&cp->lock, flags); | |
2627 | if (status) | |
2628 | cas_handle_irq(dev, cp, status); | |
2629 | ||
2630 | #ifdef USE_PCI_INTB | |
2631 | if (N_RX_COMP_RINGS > 1) { | |
2632 | status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); | |
2633 | if (status) | |
2634 | cas_handle_irq1(dev, cp, status); | |
2635 | } | |
2636 | #endif | |
2637 | ||
2638 | #ifdef USE_PCI_INTC | |
2639 | if (N_RX_COMP_RINGS > 2) { | |
2640 | status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); | |
2641 | if (status) | |
2642 | cas_handle_irqN(dev, cp, status, 2); | |
2643 | } | |
2644 | #endif | |
2645 | ||
2646 | #ifdef USE_PCI_INTD | |
2647 | if (N_RX_COMP_RINGS > 3) { | |
2648 | status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); | |
2649 | if (status) | |
2650 | cas_handle_irqN(dev, cp, status, 3); | |
2651 | } | |
2652 | #endif | |
2653 | spin_unlock_irqrestore(&cp->lock, flags); | |
2654 | if (enable_intr) { | |
288379f0 | 2655 | napi_complete(napi); |
1f26dac3 | 2656 | cas_unmask_intr(cp); |
1f26dac3 | 2657 | } |
bea3348e | 2658 | return credits; |
1f26dac3 DM |
2659 | } |
2660 | #endif | |
2661 | ||
2662 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2663 | static void cas_netpoll(struct net_device *dev) | |
2664 | { | |
2665 | struct cas *cp = netdev_priv(dev); | |
2666 | ||
2667 | cas_disable_irq(cp, 0); | |
7d12e780 | 2668 | cas_interrupt(cp->pdev->irq, dev); |
1f26dac3 DM |
2669 | cas_enable_irq(cp, 0); |
2670 | ||
2671 | #ifdef USE_PCI_INTB | |
2672 | if (N_RX_COMP_RINGS > 1) { | |
2673 | /* cas_interrupt1(); */ | |
2674 | } | |
2675 | #endif | |
2676 | #ifdef USE_PCI_INTC | |
2677 | if (N_RX_COMP_RINGS > 2) { | |
2678 | /* cas_interruptN(); */ | |
2679 | } | |
2680 | #endif | |
2681 | #ifdef USE_PCI_INTD | |
2682 | if (N_RX_COMP_RINGS > 3) { | |
2683 | /* cas_interruptN(); */ | |
2684 | } | |
2685 | #endif | |
2686 | } | |
2687 | #endif | |
2688 | ||
2689 | static void cas_tx_timeout(struct net_device *dev) | |
2690 | { | |
2691 | struct cas *cp = netdev_priv(dev); | |
2692 | ||
436d27d1 | 2693 | netdev_err(dev, "transmit timed out, resetting\n"); |
1f26dac3 | 2694 | if (!cp->hw_running) { |
436d27d1 | 2695 | netdev_err(dev, "hrm.. hw not running!\n"); |
1f26dac3 DM |
2696 | return; |
2697 | } | |
2698 | ||
436d27d1 JP |
2699 | netdev_err(dev, "MIF_STATE[%08x]\n", |
2700 | readl(cp->regs + REG_MIF_STATE_MACHINE)); | |
2701 | ||
2702 | netdev_err(dev, "MAC_STATE[%08x]\n", | |
2703 | readl(cp->regs + REG_MAC_STATE_MACHINE)); | |
2704 | ||
2705 | netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n", | |
2706 | readl(cp->regs + REG_TX_CFG), | |
2707 | readl(cp->regs + REG_MAC_TX_STATUS), | |
2708 | readl(cp->regs + REG_MAC_TX_CFG), | |
2709 | readl(cp->regs + REG_TX_FIFO_PKT_CNT), | |
2710 | readl(cp->regs + REG_TX_FIFO_WRITE_PTR), | |
2711 | readl(cp->regs + REG_TX_FIFO_READ_PTR), | |
2712 | readl(cp->regs + REG_TX_SM_1), | |
2713 | readl(cp->regs + REG_TX_SM_2)); | |
2714 | ||
2715 | netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n", | |
2716 | readl(cp->regs + REG_RX_CFG), | |
2717 | readl(cp->regs + REG_MAC_RX_STATUS), | |
2718 | readl(cp->regs + REG_MAC_RX_CFG)); | |
2719 | ||
2720 | netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n", | |
2721 | readl(cp->regs + REG_HP_STATE_MACHINE), | |
2722 | readl(cp->regs + REG_HP_STATUS0), | |
2723 | readl(cp->regs + REG_HP_STATUS1), | |
2724 | readl(cp->regs + REG_HP_STATUS2)); | |
1f26dac3 DM |
2725 | |
2726 | #if 1 | |
2727 | atomic_inc(&cp->reset_task_pending); | |
2728 | atomic_inc(&cp->reset_task_pending_all); | |
2729 | schedule_work(&cp->reset_task); | |
2730 | #else | |
2731 | atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); | |
2732 | schedule_work(&cp->reset_task); | |
2733 | #endif | |
2734 | } | |
2735 | ||
2736 | static inline int cas_intme(int ring, int entry) | |
2737 | { | |
2738 | /* Algorithm: IRQ every 1/2 of descriptors. */ | |
2739 | if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1))) | |
2740 | return 1; | |
2741 | return 0; | |
2742 | } | |
2743 | ||
2744 | ||
2745 | static void cas_write_txd(struct cas *cp, int ring, int entry, | |
2746 | dma_addr_t mapping, int len, u64 ctrl, int last) | |
2747 | { | |
2748 | struct cas_tx_desc *txd = cp->init_txds[ring] + entry; | |
2749 | ||
2750 | ctrl |= CAS_BASE(TX_DESC_BUFLEN, len); | |
2751 | if (cas_intme(ring, entry)) | |
2752 | ctrl |= TX_DESC_INTME; | |
2753 | if (last) | |
2754 | ctrl |= TX_DESC_EOF; | |
2755 | txd->control = cpu_to_le64(ctrl); | |
2756 | txd->buffer = cpu_to_le64(mapping); | |
2757 | } | |
2758 | ||
6aa20a22 | 2759 | static inline void *tx_tiny_buf(struct cas *cp, const int ring, |
1f26dac3 DM |
2760 | const int entry) |
2761 | { | |
2762 | return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry; | |
2763 | } | |
2764 | ||
6aa20a22 | 2765 | static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, |
1f26dac3 DM |
2766 | const int entry, const int tentry) |
2767 | { | |
2768 | cp->tx_tiny_use[ring][tentry].nbufs++; | |
2769 | cp->tx_tiny_use[ring][entry].used = 1; | |
2770 | return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry; | |
2771 | } | |
2772 | ||
6aa20a22 | 2773 | static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, |
1f26dac3 DM |
2774 | struct sk_buff *skb) |
2775 | { | |
2776 | struct net_device *dev = cp->dev; | |
2777 | int entry, nr_frags, frag, tabort, tentry; | |
2778 | dma_addr_t mapping; | |
2779 | unsigned long flags; | |
2780 | u64 ctrl; | |
2781 | u32 len; | |
2782 | ||
2783 | spin_lock_irqsave(&cp->tx_lock[ring], flags); | |
2784 | ||
2785 | /* This is a hard error, log it. */ | |
6aa20a22 | 2786 | if (TX_BUFFS_AVAIL(cp, ring) <= |
1f26dac3 DM |
2787 | CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) { |
2788 | netif_stop_queue(dev); | |
2789 | spin_unlock_irqrestore(&cp->tx_lock[ring], flags); | |
436d27d1 | 2790 | netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); |
1f26dac3 DM |
2791 | return 1; |
2792 | } | |
2793 | ||
2794 | ctrl = 0; | |
84fa7933 | 2795 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
ea2ae17d ACM |
2796 | const u64 csum_start_off = skb_transport_offset(skb); |
2797 | const u64 csum_stuff_off = csum_start_off + skb->csum_offset; | |
1f26dac3 | 2798 | |
6aa20a22 | 2799 | ctrl = TX_DESC_CSUM_EN | |
1f26dac3 DM |
2800 | CAS_BASE(TX_DESC_CSUM_START, csum_start_off) | |
2801 | CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off); | |
2802 | } | |
2803 | ||
2804 | entry = cp->tx_new[ring]; | |
2805 | cp->tx_skbs[ring][entry] = skb; | |
2806 | ||
2807 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2808 | len = skb_headlen(skb); | |
2809 | mapping = pci_map_page(cp->pdev, virt_to_page(skb->data), | |
2810 | offset_in_page(skb->data), len, | |
2811 | PCI_DMA_TODEVICE); | |
2812 | ||
2813 | tentry = entry; | |
2814 | tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len); | |
2815 | if (unlikely(tabort)) { | |
2816 | /* NOTE: len is always > tabort */ | |
6aa20a22 | 2817 | cas_write_txd(cp, ring, entry, mapping, len - tabort, |
1f26dac3 DM |
2818 | ctrl | TX_DESC_SOF, 0); |
2819 | entry = TX_DESC_NEXT(ring, entry); | |
2820 | ||
d626f62b ACM |
2821 | skb_copy_from_linear_data_offset(skb, len - tabort, |
2822 | tx_tiny_buf(cp, ring, entry), tabort); | |
1f26dac3 DM |
2823 | mapping = tx_tiny_map(cp, ring, entry, tentry); |
2824 | cas_write_txd(cp, ring, entry, mapping, tabort, ctrl, | |
2825 | (nr_frags == 0)); | |
2826 | } else { | |
6aa20a22 | 2827 | cas_write_txd(cp, ring, entry, mapping, len, ctrl | |
1f26dac3 DM |
2828 | TX_DESC_SOF, (nr_frags == 0)); |
2829 | } | |
2830 | entry = TX_DESC_NEXT(ring, entry); | |
2831 | ||
2832 | for (frag = 0; frag < nr_frags; frag++) { | |
2833 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; | |
2834 | ||
2835 | len = fragp->size; | |
2836 | mapping = pci_map_page(cp->pdev, fragp->page, | |
2837 | fragp->page_offset, len, | |
2838 | PCI_DMA_TODEVICE); | |
2839 | ||
2840 | tabort = cas_calc_tabort(cp, fragp->page_offset, len); | |
2841 | if (unlikely(tabort)) { | |
2842 | void *addr; | |
2843 | ||
2844 | /* NOTE: len is always > tabort */ | |
2845 | cas_write_txd(cp, ring, entry, mapping, len - tabort, | |
2846 | ctrl, 0); | |
2847 | entry = TX_DESC_NEXT(ring, entry); | |
6aa20a22 | 2848 | |
1f26dac3 DM |
2849 | addr = cas_page_map(fragp->page); |
2850 | memcpy(tx_tiny_buf(cp, ring, entry), | |
6aa20a22 | 2851 | addr + fragp->page_offset + len - tabort, |
1f26dac3 DM |
2852 | tabort); |
2853 | cas_page_unmap(addr); | |
2854 | mapping = tx_tiny_map(cp, ring, entry, tentry); | |
2855 | len = tabort; | |
2856 | } | |
2857 | ||
2858 | cas_write_txd(cp, ring, entry, mapping, len, ctrl, | |
2859 | (frag + 1 == nr_frags)); | |
2860 | entry = TX_DESC_NEXT(ring, entry); | |
2861 | } | |
2862 | ||
2863 | cp->tx_new[ring] = entry; | |
2864 | if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)) | |
2865 | netif_stop_queue(dev); | |
2866 | ||
436d27d1 JP |
2867 | netif_printk(cp, tx_queued, KERN_DEBUG, dev, |
2868 | "tx[%d] queued, slot %d, skblen %d, avail %d\n", | |
2869 | ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring)); | |
1f26dac3 DM |
2870 | writel(entry, cp->regs + REG_TX_KICKN(ring)); |
2871 | spin_unlock_irqrestore(&cp->tx_lock[ring], flags); | |
2872 | return 0; | |
6aa20a22 | 2873 | } |
1f26dac3 | 2874 | |
61357325 | 2875 | static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1f26dac3 DM |
2876 | { |
2877 | struct cas *cp = netdev_priv(dev); | |
2878 | ||
2879 | /* this is only used as a load-balancing hint, so it doesn't | |
2880 | * need to be SMP safe | |
2881 | */ | |
6aa20a22 | 2882 | static int ring; |
1f26dac3 | 2883 | |
5b057c6b | 2884 | if (skb_padto(skb, cp->min_frame_size)) |
6ed10654 | 2885 | return NETDEV_TX_OK; |
1f26dac3 DM |
2886 | |
2887 | /* XXX: we need some higher-level QoS hooks to steer packets to | |
2888 | * individual queues. | |
2889 | */ | |
2890 | if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb)) | |
5b548140 | 2891 | return NETDEV_TX_BUSY; |
1f26dac3 | 2892 | dev->trans_start = jiffies; |
6ed10654 | 2893 | return NETDEV_TX_OK; |
1f26dac3 DM |
2894 | } |
2895 | ||
2896 | static void cas_init_tx_dma(struct cas *cp) | |
2897 | { | |
2898 | u64 desc_dma = cp->block_dvma; | |
2899 | unsigned long off; | |
2900 | u32 val; | |
2901 | int i; | |
2902 | ||
2903 | /* set up tx completion writeback registers. must be 8-byte aligned */ | |
2904 | #ifdef USE_TX_COMPWB | |
2905 | off = offsetof(struct cas_init_block, tx_compwb); | |
2906 | writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); | |
2907 | writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); | |
2908 | #endif | |
2909 | ||
2910 | /* enable completion writebacks, enable paced mode, | |
2911 | * disable read pipe, and disable pre-interrupt compwbs | |
2912 | */ | |
6aa20a22 | 2913 | val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | |
1f26dac3 | 2914 | TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 | |
6aa20a22 | 2915 | TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | |
1f26dac3 DM |
2916 | TX_CFG_INTR_COMPWB_DIS; |
2917 | ||
2918 | /* write out tx ring info and tx desc bases */ | |
2919 | for (i = 0; i < MAX_TX_RINGS; i++) { | |
6aa20a22 | 2920 | off = (unsigned long) cp->init_txds[i] - |
1f26dac3 DM |
2921 | (unsigned long) cp->init_block; |
2922 | ||
2923 | val |= CAS_TX_RINGN_BASE(i); | |
2924 | writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); | |
2925 | writel((desc_dma + off) & 0xffffffff, cp->regs + | |
2926 | REG_TX_DBN_LOW(i)); | |
2927 | /* don't zero out the kick register here as the system | |
2928 | * will wedge | |
2929 | */ | |
2930 | } | |
2931 | writel(val, cp->regs + REG_TX_CFG); | |
2932 | ||
2933 | /* program max burst sizes. these numbers should be different | |
2934 | * if doing QoS. | |
2935 | */ | |
2936 | #ifdef USE_QOS | |
2937 | writel(0x800, cp->regs + REG_TX_MAXBURST_0); | |
2938 | writel(0x1600, cp->regs + REG_TX_MAXBURST_1); | |
2939 | writel(0x2400, cp->regs + REG_TX_MAXBURST_2); | |
2940 | writel(0x4800, cp->regs + REG_TX_MAXBURST_3); | |
2941 | #else | |
2942 | writel(0x800, cp->regs + REG_TX_MAXBURST_0); | |
2943 | writel(0x800, cp->regs + REG_TX_MAXBURST_1); | |
2944 | writel(0x800, cp->regs + REG_TX_MAXBURST_2); | |
2945 | writel(0x800, cp->regs + REG_TX_MAXBURST_3); | |
2946 | #endif | |
2947 | } | |
2948 | ||
2949 | /* Must be invoked under cp->lock. */ | |
2950 | static inline void cas_init_dma(struct cas *cp) | |
2951 | { | |
2952 | cas_init_tx_dma(cp); | |
2953 | cas_init_rx_dma(cp); | |
2954 | } | |
2955 | ||
d7b855c2 JP |
2956 | static void cas_process_mc_list(struct cas *cp) |
2957 | { | |
2958 | u16 hash_table[16]; | |
2959 | u32 crc; | |
22bedad3 | 2960 | struct netdev_hw_addr *ha; |
d7b855c2 JP |
2961 | int i = 1; |
2962 | ||
2963 | memset(hash_table, 0, sizeof(hash_table)); | |
22bedad3 | 2964 | netdev_for_each_mc_addr(ha, cp->dev) { |
d7b855c2 JP |
2965 | if (i <= CAS_MC_EXACT_MATCH_SIZE) { |
2966 | /* use the alternate mac address registers for the | |
2967 | * first 15 multicast addresses | |
2968 | */ | |
22bedad3 | 2969 | writel((ha->addr[4] << 8) | ha->addr[5], |
d7b855c2 | 2970 | cp->regs + REG_MAC_ADDRN(i*3 + 0)); |
22bedad3 | 2971 | writel((ha->addr[2] << 8) | ha->addr[3], |
d7b855c2 | 2972 | cp->regs + REG_MAC_ADDRN(i*3 + 1)); |
22bedad3 | 2973 | writel((ha->addr[0] << 8) | ha->addr[1], |
d7b855c2 JP |
2974 | cp->regs + REG_MAC_ADDRN(i*3 + 2)); |
2975 | i++; | |
2976 | } | |
2977 | else { | |
2978 | /* use hw hash table for the next series of | |
2979 | * multicast addresses | |
2980 | */ | |
22bedad3 | 2981 | crc = ether_crc_le(ETH_ALEN, ha->addr); |
d7b855c2 JP |
2982 | crc >>= 24; |
2983 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
2984 | } | |
2985 | } | |
2986 | for (i = 0; i < 16; i++) | |
2987 | writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i)); | |
2988 | } | |
2989 | ||
1f26dac3 DM |
2990 | /* Must be invoked under cp->lock. */ |
2991 | static u32 cas_setup_multicast(struct cas *cp) | |
2992 | { | |
2993 | u32 rxcfg = 0; | |
2994 | int i; | |
6aa20a22 | 2995 | |
1f26dac3 DM |
2996 | if (cp->dev->flags & IFF_PROMISC) { |
2997 | rxcfg |= MAC_RX_CFG_PROMISC_EN; | |
2998 | ||
2999 | } else if (cp->dev->flags & IFF_ALLMULTI) { | |
3000 | for (i=0; i < 16; i++) | |
3001 | writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); | |
3002 | rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; | |
3003 | ||
3004 | } else { | |
d7b855c2 | 3005 | cas_process_mc_list(cp); |
1f26dac3 DM |
3006 | rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; |
3007 | } | |
3008 | ||
3009 | return rxcfg; | |
3010 | } | |
3011 | ||
3012 | /* must be invoked under cp->stat_lock[N_TX_RINGS] */ | |
3013 | static void cas_clear_mac_err(struct cas *cp) | |
3014 | { | |
3015 | writel(0, cp->regs + REG_MAC_COLL_NORMAL); | |
3016 | writel(0, cp->regs + REG_MAC_COLL_FIRST); | |
3017 | writel(0, cp->regs + REG_MAC_COLL_EXCESS); | |
3018 | writel(0, cp->regs + REG_MAC_COLL_LATE); | |
3019 | writel(0, cp->regs + REG_MAC_TIMER_DEFER); | |
3020 | writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); | |
3021 | writel(0, cp->regs + REG_MAC_RECV_FRAME); | |
3022 | writel(0, cp->regs + REG_MAC_LEN_ERR); | |
3023 | writel(0, cp->regs + REG_MAC_ALIGN_ERR); | |
3024 | writel(0, cp->regs + REG_MAC_FCS_ERR); | |
3025 | writel(0, cp->regs + REG_MAC_RX_CODE_ERR); | |
3026 | } | |
3027 | ||
3028 | ||
3029 | static void cas_mac_reset(struct cas *cp) | |
3030 | { | |
3031 | int i; | |
3032 | ||
3033 | /* do both TX and RX reset */ | |
3034 | writel(0x1, cp->regs + REG_MAC_TX_RESET); | |
3035 | writel(0x1, cp->regs + REG_MAC_RX_RESET); | |
3036 | ||
3037 | /* wait for TX */ | |
3038 | i = STOP_TRIES; | |
3039 | while (i-- > 0) { | |
3040 | if (readl(cp->regs + REG_MAC_TX_RESET) == 0) | |
3041 | break; | |
3042 | udelay(10); | |
3043 | } | |
3044 | ||
3045 | /* wait for RX */ | |
3046 | i = STOP_TRIES; | |
3047 | while (i-- > 0) { | |
3048 | if (readl(cp->regs + REG_MAC_RX_RESET) == 0) | |
3049 | break; | |
3050 | udelay(10); | |
3051 | } | |
3052 | ||
3053 | if (readl(cp->regs + REG_MAC_TX_RESET) | | |
3054 | readl(cp->regs + REG_MAC_RX_RESET)) | |
436d27d1 JP |
3055 | netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n", |
3056 | readl(cp->regs + REG_MAC_TX_RESET), | |
3057 | readl(cp->regs + REG_MAC_RX_RESET), | |
3058 | readl(cp->regs + REG_MAC_STATE_MACHINE)); | |
1f26dac3 DM |
3059 | } |
3060 | ||
3061 | ||
3062 | /* Must be invoked under cp->lock. */ | |
3063 | static void cas_init_mac(struct cas *cp) | |
3064 | { | |
3065 | unsigned char *e = &cp->dev->dev_addr[0]; | |
3066 | int i; | |
3067 | #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE | |
3068 | u32 rxcfg; | |
3069 | #endif | |
3070 | cas_mac_reset(cp); | |
3071 | ||
3072 | /* setup core arbitration weight register */ | |
3073 | writel(CAWR_RR_DIS, cp->regs + REG_CAWR); | |
3074 | ||
3075 | /* XXX Use pci_dma_burst_advice() */ | |
3076 | #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) | |
3077 | /* set the infinite burst register for chips that don't have | |
3078 | * pci issues. | |
3079 | */ | |
3080 | if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0) | |
3081 | writel(INF_BURST_EN, cp->regs + REG_INF_BURST); | |
3082 | #endif | |
3083 | ||
3084 | writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); | |
3085 | ||
3086 | writel(0x00, cp->regs + REG_MAC_IPG0); | |
3087 | writel(0x08, cp->regs + REG_MAC_IPG1); | |
3088 | writel(0x04, cp->regs + REG_MAC_IPG2); | |
6aa20a22 | 3089 | |
1f26dac3 | 3090 | /* change later for 802.3z */ |
6aa20a22 | 3091 | writel(0x40, cp->regs + REG_MAC_SLOT_TIME); |
1f26dac3 DM |
3092 | |
3093 | /* min frame + FCS */ | |
3094 | writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); | |
3095 | ||
3096 | /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we | |
6aa20a22 | 3097 | * specify the maximum frame size to prevent RX tag errors on |
1f26dac3 DM |
3098 | * oversized frames. |
3099 | */ | |
3100 | writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) | | |
6aa20a22 JG |
3101 | CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, |
3102 | (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), | |
1f26dac3 DM |
3103 | cp->regs + REG_MAC_FRAMESIZE_MAX); |
3104 | ||
6aa20a22 | 3105 | /* NOTE: crc_size is used as a surrogate for half-duplex. |
1f26dac3 DM |
3106 | * workaround saturn half-duplex issue by increasing preamble |
3107 | * size to 65 bytes. | |
3108 | */ | |
3109 | if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size) | |
3110 | writel(0x41, cp->regs + REG_MAC_PA_SIZE); | |
3111 | else | |
3112 | writel(0x07, cp->regs + REG_MAC_PA_SIZE); | |
3113 | writel(0x04, cp->regs + REG_MAC_JAM_SIZE); | |
3114 | writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); | |
3115 | writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); | |
3116 | ||
3117 | writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); | |
3118 | ||
3119 | writel(0, cp->regs + REG_MAC_ADDR_FILTER0); | |
3120 | writel(0, cp->regs + REG_MAC_ADDR_FILTER1); | |
3121 | writel(0, cp->regs + REG_MAC_ADDR_FILTER2); | |
3122 | writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); | |
3123 | writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); | |
3124 | ||
3125 | /* setup mac address in perfect filter array */ | |
3126 | for (i = 0; i < 45; i++) | |
3127 | writel(0x0, cp->regs + REG_MAC_ADDRN(i)); | |
3128 | ||
3129 | writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); | |
3130 | writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); | |
3131 | writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); | |
3132 | ||
3133 | writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); | |
3134 | writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); | |
3135 | writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); | |
3136 | ||
3137 | #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE | |
3138 | cp->mac_rx_cfg = cas_setup_multicast(cp); | |
3139 | #else | |
3140 | /* WTZ: Do what Adrian did in cas_set_multicast. Doing | |
3141 | * a writel does not seem to be necessary because Cassini | |
3142 | * seems to preserve the configuration when we do the reset. | |
3143 | * If the chip is in trouble, though, it is not clear if we | |
3144 | * can really count on this behavior. cas_set_multicast uses | |
3145 | * spin_lock_irqsave, but we are called only in cas_init_hw and | |
3146 | * cas_init_hw is protected by cas_lock_all, which calls | |
3147 | * spin_lock_irq (so it doesn't need to save the flags, and | |
6aa20a22 | 3148 | * we should be OK for the writel, as that is the only |
1f26dac3 DM |
3149 | * difference). |
3150 | */ | |
3151 | cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp); | |
3152 | writel(rxcfg, cp->regs + REG_MAC_RX_CFG); | |
3153 | #endif | |
3154 | spin_lock(&cp->stat_lock[N_TX_RINGS]); | |
3155 | cas_clear_mac_err(cp); | |
3156 | spin_unlock(&cp->stat_lock[N_TX_RINGS]); | |
3157 | ||
3158 | /* Setup MAC interrupts. We want to get all of the interesting | |
3159 | * counter expiration events, but we do not want to hear about | |
3160 | * normal rx/tx as the DMA engine tells us that. | |
3161 | */ | |
3162 | writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); | |
3163 | writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); | |
3164 | ||
3165 | /* Don't enable even the PAUSE interrupts for now, we | |
3166 | * make no use of those events other than to record them. | |
3167 | */ | |
3168 | writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); | |
3169 | } | |
3170 | ||
3171 | /* Must be invoked under cp->lock. */ | |
3172 | static void cas_init_pause_thresholds(struct cas *cp) | |
3173 | { | |
3174 | /* Calculate pause thresholds. Setting the OFF threshold to the | |
3175 | * full RX fifo size effectively disables PAUSE generation | |
3176 | */ | |
3177 | if (cp->rx_fifo_size <= (2 * 1024)) { | |
3178 | cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size; | |
3179 | } else { | |
3180 | int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63; | |
3181 | if (max_frame * 3 > cp->rx_fifo_size) { | |
3182 | cp->rx_pause_off = 7104; | |
3183 | cp->rx_pause_on = 960; | |
3184 | } else { | |
3185 | int off = (cp->rx_fifo_size - (max_frame * 2)); | |
3186 | int on = off - max_frame; | |
3187 | cp->rx_pause_off = off; | |
3188 | cp->rx_pause_on = on; | |
3189 | } | |
3190 | } | |
3191 | } | |
3192 | ||
3193 | static int cas_vpd_match(const void __iomem *p, const char *str) | |
3194 | { | |
3195 | int len = strlen(str) + 1; | |
3196 | int i; | |
6aa20a22 | 3197 | |
1f26dac3 DM |
3198 | for (i = 0; i < len; i++) { |
3199 | if (readb(p + i) != str[i]) | |
3200 | return 0; | |
3201 | } | |
3202 | return 1; | |
3203 | } | |
3204 | ||
3205 | ||
3206 | /* get the mac address by reading the vpd information in the rom. | |
3207 | * also get the phy type and determine if there's an entropy generator. | |
3208 | * NOTE: this is a bit convoluted for the following reasons: | |
3209 | * 1) vpd info has order-dependent mac addresses for multinic cards | |
3210 | * 2) the only way to determine the nic order is to use the slot | |
3211 | * number. | |
3212 | * 3) fiber cards don't have bridges, so their slot numbers don't | |
3213 | * mean anything. | |
6aa20a22 | 3214 | * 4) we don't actually know we have a fiber card until after |
1f26dac3 DM |
3215 | * the mac addresses are parsed. |
3216 | */ | |
3217 | static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr, | |
3218 | const int offset) | |
3219 | { | |
3220 | void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START; | |
3221 | void __iomem *base, *kstart; | |
3222 | int i, len; | |
3223 | int found = 0; | |
3224 | #define VPD_FOUND_MAC 0x01 | |
3225 | #define VPD_FOUND_PHY 0x02 | |
3226 | ||
3227 | int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */ | |
3228 | int mac_off = 0; | |
3229 | ||
3230 | /* give us access to the PROM */ | |
3231 | writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD, | |
3232 | cp->regs + REG_BIM_LOCAL_DEV_EN); | |
3233 | ||
3234 | /* check for an expansion rom */ | |
3235 | if (readb(p) != 0x55 || readb(p + 1) != 0xaa) | |
3236 | goto use_random_mac_addr; | |
3237 | ||
3238 | /* search for beginning of vpd */ | |
46d7031e | 3239 | base = NULL; |
1f26dac3 DM |
3240 | for (i = 2; i < EXPANSION_ROM_SIZE; i++) { |
3241 | /* check for PCIR */ | |
3242 | if ((readb(p + i + 0) == 0x50) && | |
3243 | (readb(p + i + 1) == 0x43) && | |
3244 | (readb(p + i + 2) == 0x49) && | |
3245 | (readb(p + i + 3) == 0x52)) { | |
6aa20a22 | 3246 | base = p + (readb(p + i + 8) | |
1f26dac3 DM |
3247 | (readb(p + i + 9) << 8)); |
3248 | break; | |
6aa20a22 | 3249 | } |
1f26dac3 DM |
3250 | } |
3251 | ||
3252 | if (!base || (readb(base) != 0x82)) | |
3253 | goto use_random_mac_addr; | |
6aa20a22 | 3254 | |
1f26dac3 DM |
3255 | i = (readb(base + 1) | (readb(base + 2) << 8)) + 3; |
3256 | while (i < EXPANSION_ROM_SIZE) { | |
3257 | if (readb(base + i) != 0x90) /* no vpd found */ | |
3258 | goto use_random_mac_addr; | |
3259 | ||
3260 | /* found a vpd field */ | |
3261 | len = readb(base + i + 1) | (readb(base + i + 2) << 8); | |
3262 | ||
3263 | /* extract keywords */ | |
3264 | kstart = base + i + 3; | |
3265 | p = kstart; | |
3266 | while ((p - kstart) < len) { | |
3267 | int klen = readb(p + 2); | |
3268 | int j; | |
3269 | char type; | |
3270 | ||
3271 | p += 3; | |
6aa20a22 | 3272 | |
1f26dac3 DM |
3273 | /* look for the following things: |
3274 | * -- correct length == 29 | |
6aa20a22 JG |
3275 | * 3 (type) + 2 (size) + |
3276 | * 18 (strlen("local-mac-address") + 1) + | |
3277 | * 6 (mac addr) | |
1f26dac3 DM |
3278 | * -- VPD Instance 'I' |
3279 | * -- VPD Type Bytes 'B' | |
3280 | * -- VPD data length == 6 | |
3281 | * -- property string == local-mac-address | |
6aa20a22 | 3282 | * |
1f26dac3 | 3283 | * -- correct length == 24 |
6aa20a22 JG |
3284 | * 3 (type) + 2 (size) + |
3285 | * 12 (strlen("entropy-dev") + 1) + | |
1f26dac3 DM |
3286 | * 7 (strlen("vms110") + 1) |
3287 | * -- VPD Instance 'I' | |
3288 | * -- VPD Type String 'B' | |
3289 | * -- VPD data length == 7 | |
3290 | * -- property string == entropy-dev | |
3291 | * | |
3292 | * -- correct length == 18 | |
6aa20a22 JG |
3293 | * 3 (type) + 2 (size) + |
3294 | * 9 (strlen("phy-type") + 1) + | |
1f26dac3 DM |
3295 | * 4 (strlen("pcs") + 1) |
3296 | * -- VPD Instance 'I' | |
3297 | * -- VPD Type String 'S' | |
3298 | * -- VPD data length == 4 | |
3299 | * -- property string == phy-type | |
6aa20a22 | 3300 | * |
1f26dac3 | 3301 | * -- correct length == 23 |
6aa20a22 JG |
3302 | * 3 (type) + 2 (size) + |
3303 | * 14 (strlen("phy-interface") + 1) + | |
1f26dac3 DM |
3304 | * 4 (strlen("pcs") + 1) |
3305 | * -- VPD Instance 'I' | |
3306 | * -- VPD Type String 'S' | |
3307 | * -- VPD data length == 4 | |
3308 | * -- property string == phy-interface | |
3309 | */ | |
3310 | if (readb(p) != 'I') | |
3311 | goto next; | |
3312 | ||
3313 | /* finally, check string and length */ | |
3314 | type = readb(p + 3); | |
3315 | if (type == 'B') { | |
3316 | if ((klen == 29) && readb(p + 4) == 6 && | |
6aa20a22 | 3317 | cas_vpd_match(p + 5, |
1f26dac3 | 3318 | "local-mac-address")) { |
6aa20a22 | 3319 | if (mac_off++ > offset) |
1f26dac3 DM |
3320 | goto next; |
3321 | ||
3322 | /* set mac address */ | |
6aa20a22 JG |
3323 | for (j = 0; j < 6; j++) |
3324 | dev_addr[j] = | |
1f26dac3 DM |
3325 | readb(p + 23 + j); |
3326 | goto found_mac; | |
3327 | } | |
3328 | } | |
3329 | ||
3330 | if (type != 'S') | |
3331 | goto next; | |
3332 | ||
3333 | #ifdef USE_ENTROPY_DEV | |
6aa20a22 | 3334 | if ((klen == 24) && |
1f26dac3 DM |
3335 | cas_vpd_match(p + 5, "entropy-dev") && |
3336 | cas_vpd_match(p + 17, "vms110")) { | |
3337 | cp->cas_flags |= CAS_FLAG_ENTROPY_DEV; | |
3338 | goto next; | |
3339 | } | |
3340 | #endif | |
3341 | ||
3342 | if (found & VPD_FOUND_PHY) | |
3343 | goto next; | |
3344 | ||
3345 | if ((klen == 18) && readb(p + 4) == 4 && | |
3346 | cas_vpd_match(p + 5, "phy-type")) { | |
3347 | if (cas_vpd_match(p + 14, "pcs")) { | |
3348 | phy_type = CAS_PHY_SERDES; | |
3349 | goto found_phy; | |
3350 | } | |
3351 | } | |
6aa20a22 | 3352 | |
1f26dac3 DM |
3353 | if ((klen == 23) && readb(p + 4) == 4 && |
3354 | cas_vpd_match(p + 5, "phy-interface")) { | |
3355 | if (cas_vpd_match(p + 19, "pcs")) { | |
3356 | phy_type = CAS_PHY_SERDES; | |
3357 | goto found_phy; | |
3358 | } | |
3359 | } | |
3360 | found_mac: | |
3361 | found |= VPD_FOUND_MAC; | |
3362 | goto next; | |
3363 | ||
3364 | found_phy: | |
3365 | found |= VPD_FOUND_PHY; | |
3366 | ||
3367 | next: | |
3368 | p += klen; | |
3369 | } | |
3370 | i += len + 3; | |
3371 | } | |
3372 | ||
3373 | use_random_mac_addr: | |
3374 | if (found & VPD_FOUND_MAC) | |
3375 | goto done; | |
3376 | ||
3377 | /* Sun MAC prefix then 3 random bytes. */ | |
436d27d1 | 3378 | pr_info("MAC address not found in ROM VPD\n"); |
1f26dac3 DM |
3379 | dev_addr[0] = 0x08; |
3380 | dev_addr[1] = 0x00; | |
3381 | dev_addr[2] = 0x20; | |
3382 | get_random_bytes(dev_addr + 3, 3); | |
3383 | ||
3384 | done: | |
3385 | writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); | |
3386 | return phy_type; | |
3387 | } | |
3388 | ||
3389 | /* check pci invariants */ | |
3390 | static void cas_check_pci_invariants(struct cas *cp) | |
3391 | { | |
3392 | struct pci_dev *pdev = cp->pdev; | |
1f26dac3 DM |
3393 | |
3394 | cp->cas_flags = 0; | |
1f26dac3 DM |
3395 | if ((pdev->vendor == PCI_VENDOR_ID_SUN) && |
3396 | (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) { | |
44c10138 | 3397 | if (pdev->revision >= CAS_ID_REVPLUS) |
1f26dac3 | 3398 | cp->cas_flags |= CAS_FLAG_REG_PLUS; |
44c10138 | 3399 | if (pdev->revision < CAS_ID_REVPLUS02u) |
1f26dac3 DM |
3400 | cp->cas_flags |= CAS_FLAG_TARGET_ABORT; |
3401 | ||
3402 | /* Original Cassini supports HW CSUM, but it's not | |
3403 | * enabled by default as it can trigger TX hangs. | |
3404 | */ | |
44c10138 | 3405 | if (pdev->revision < CAS_ID_REV2) |
1f26dac3 DM |
3406 | cp->cas_flags |= CAS_FLAG_NO_HW_CSUM; |
3407 | } else { | |
3408 | /* Only sun has original cassini chips. */ | |
3409 | cp->cas_flags |= CAS_FLAG_REG_PLUS; | |
3410 | ||
3411 | /* We use a flag because the same phy might be externally | |
3412 | * connected. | |
3413 | */ | |
3414 | if ((pdev->vendor == PCI_VENDOR_ID_NS) && | |
3415 | (pdev->device == PCI_DEVICE_ID_NS_SATURN)) | |
3416 | cp->cas_flags |= CAS_FLAG_SATURN; | |
3417 | } | |
3418 | } | |
3419 | ||
3420 | ||
3421 | static int cas_check_invariants(struct cas *cp) | |
3422 | { | |
3423 | struct pci_dev *pdev = cp->pdev; | |
3424 | u32 cfg; | |
3425 | int i; | |
3426 | ||
3427 | /* get page size for rx buffers. */ | |
6aa20a22 | 3428 | cp->page_order = 0; |
1f26dac3 DM |
3429 | #ifdef USE_PAGE_ORDER |
3430 | if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) { | |
3431 | /* see if we can allocate larger pages */ | |
6aa20a22 JG |
3432 | struct page *page = alloc_pages(GFP_ATOMIC, |
3433 | CAS_JUMBO_PAGE_SHIFT - | |
1f26dac3 DM |
3434 | PAGE_SHIFT); |
3435 | if (page) { | |
3436 | __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT); | |
3437 | cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT; | |
3438 | } else { | |
436d27d1 | 3439 | printk("MTU limited to %d bytes\n", CAS_MAX_MTU); |
1f26dac3 DM |
3440 | } |
3441 | } | |
3442 | #endif | |
3443 | cp->page_size = (PAGE_SIZE << cp->page_order); | |
3444 | ||
3445 | /* Fetch the FIFO configurations. */ | |
3446 | cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; | |
3447 | cp->rx_fifo_size = RX_FIFO_SIZE; | |
3448 | ||
6aa20a22 | 3449 | /* finish phy determination. MDIO1 takes precedence over MDIO0 if |
1f26dac3 DM |
3450 | * they're both connected. |
3451 | */ | |
6aa20a22 | 3452 | cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr, |
1f26dac3 DM |
3453 | PCI_SLOT(pdev->devfn)); |
3454 | if (cp->phy_type & CAS_PHY_SERDES) { | |
3455 | cp->cas_flags |= CAS_FLAG_1000MB_CAP; | |
3456 | return 0; /* no more checking needed */ | |
6aa20a22 | 3457 | } |
1f26dac3 DM |
3458 | |
3459 | /* MII */ | |
3460 | cfg = readl(cp->regs + REG_MIF_CFG); | |
3461 | if (cfg & MIF_CFG_MDIO_1) { | |
3462 | cp->phy_type = CAS_PHY_MII_MDIO1; | |
3463 | } else if (cfg & MIF_CFG_MDIO_0) { | |
3464 | cp->phy_type = CAS_PHY_MII_MDIO0; | |
3465 | } | |
3466 | ||
3467 | cas_mif_poll(cp, 0); | |
3468 | writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); | |
3469 | ||
3470 | for (i = 0; i < 32; i++) { | |
3471 | u32 phy_id; | |
3472 | int j; | |
3473 | ||
3474 | for (j = 0; j < 3; j++) { | |
3475 | cp->phy_addr = i; | |
3476 | phy_id = cas_phy_read(cp, MII_PHYSID1) << 16; | |
3477 | phy_id |= cas_phy_read(cp, MII_PHYSID2); | |
3478 | if (phy_id && (phy_id != 0xFFFFFFFF)) { | |
3479 | cp->phy_id = phy_id; | |
3480 | goto done; | |
3481 | } | |
3482 | } | |
3483 | } | |
436d27d1 | 3484 | pr_err("MII phy did not respond [%08x]\n", |
1f26dac3 DM |
3485 | readl(cp->regs + REG_MIF_STATE_MACHINE)); |
3486 | return -1; | |
3487 | ||
3488 | done: | |
3489 | /* see if we can do gigabit */ | |
3490 | cfg = cas_phy_read(cp, MII_BMSR); | |
6aa20a22 | 3491 | if ((cfg & CAS_BMSR_1000_EXTEND) && |
1f26dac3 DM |
3492 | cas_phy_read(cp, CAS_MII_1000_EXTEND)) |
3493 | cp->cas_flags |= CAS_FLAG_1000MB_CAP; | |
3494 | return 0; | |
3495 | } | |
3496 | ||
3497 | /* Must be invoked under cp->lock. */ | |
3498 | static inline void cas_start_dma(struct cas *cp) | |
3499 | { | |
3500 | int i; | |
3501 | u32 val; | |
3502 | int txfailed = 0; | |
6aa20a22 | 3503 | |
1f26dac3 DM |
3504 | /* enable dma */ |
3505 | val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; | |
3506 | writel(val, cp->regs + REG_TX_CFG); | |
3507 | val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; | |
3508 | writel(val, cp->regs + REG_RX_CFG); | |
3509 | ||
3510 | /* enable the mac */ | |
3511 | val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; | |
3512 | writel(val, cp->regs + REG_MAC_TX_CFG); | |
3513 | val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; | |
3514 | writel(val, cp->regs + REG_MAC_RX_CFG); | |
3515 | ||
3516 | i = STOP_TRIES; | |
3517 | while (i-- > 0) { | |
3518 | val = readl(cp->regs + REG_MAC_TX_CFG); | |
3519 | if ((val & MAC_TX_CFG_EN)) | |
3520 | break; | |
3521 | udelay(10); | |
3522 | } | |
3523 | if (i < 0) txfailed = 1; | |
3524 | i = STOP_TRIES; | |
3525 | while (i-- > 0) { | |
3526 | val = readl(cp->regs + REG_MAC_RX_CFG); | |
3527 | if ((val & MAC_RX_CFG_EN)) { | |
3528 | if (txfailed) { | |
436d27d1 JP |
3529 | netdev_err(cp->dev, |
3530 | "enabling mac failed [tx:%08x:%08x]\n", | |
3531 | readl(cp->regs + REG_MIF_STATE_MACHINE), | |
3532 | readl(cp->regs + REG_MAC_STATE_MACHINE)); | |
1f26dac3 DM |
3533 | } |
3534 | goto enable_rx_done; | |
3535 | } | |
3536 | udelay(10); | |
3537 | } | |
436d27d1 JP |
3538 | netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n", |
3539 | (txfailed ? "tx,rx" : "rx"), | |
3540 | readl(cp->regs + REG_MIF_STATE_MACHINE), | |
3541 | readl(cp->regs + REG_MAC_STATE_MACHINE)); | |
1f26dac3 DM |
3542 | |
3543 | enable_rx_done: | |
3544 | cas_unmask_intr(cp); /* enable interrupts */ | |
3545 | writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); | |
3546 | writel(0, cp->regs + REG_RX_COMP_TAIL); | |
3547 | ||
3548 | if (cp->cas_flags & CAS_FLAG_REG_PLUS) { | |
6aa20a22 JG |
3549 | if (N_RX_DESC_RINGS > 1) |
3550 | writel(RX_DESC_RINGN_SIZE(1) - 4, | |
1f26dac3 DM |
3551 | cp->regs + REG_PLUS_RX_KICK1); |
3552 | ||
6aa20a22 | 3553 | for (i = 1; i < N_RX_COMP_RINGS; i++) |
1f26dac3 DM |
3554 | writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i)); |
3555 | } | |
3556 | } | |
3557 | ||
3558 | /* Must be invoked under cp->lock. */ | |
3559 | static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd, | |
3560 | int *pause) | |
3561 | { | |
3562 | u32 val = readl(cp->regs + REG_PCS_MII_LPA); | |
3563 | *fd = (val & PCS_MII_LPA_FD) ? 1 : 0; | |
3564 | *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00; | |
3565 | if (val & PCS_MII_LPA_ASYM_PAUSE) | |
3566 | *pause |= 0x10; | |
3567 | *spd = 1000; | |
3568 | } | |
3569 | ||
3570 | /* Must be invoked under cp->lock. */ | |
3571 | static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd, | |
3572 | int *pause) | |
3573 | { | |
3574 | u32 val; | |
3575 | ||
3576 | *fd = 0; | |
3577 | *spd = 10; | |
3578 | *pause = 0; | |
6aa20a22 | 3579 | |
1f26dac3 DM |
3580 | /* use GMII registers */ |
3581 | val = cas_phy_read(cp, MII_LPA); | |
3582 | if (val & CAS_LPA_PAUSE) | |
3583 | *pause = 0x01; | |
3584 | ||
3585 | if (val & CAS_LPA_ASYM_PAUSE) | |
3586 | *pause |= 0x10; | |
3587 | ||
3588 | if (val & LPA_DUPLEX) | |
3589 | *fd = 1; | |
3590 | if (val & LPA_100) | |
3591 | *spd = 100; | |
3592 | ||
3593 | if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { | |
3594 | val = cas_phy_read(cp, CAS_MII_1000_STATUS); | |
3595 | if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF)) | |
3596 | *spd = 1000; | |
3597 | if (val & CAS_LPA_1000FULL) | |
3598 | *fd = 1; | |
3599 | } | |
3600 | } | |
3601 | ||
3602 | /* A link-up condition has occurred, initialize and enable the | |
3603 | * rest of the chip. | |
3604 | * | |
3605 | * Must be invoked under cp->lock. | |
3606 | */ | |
3607 | static void cas_set_link_modes(struct cas *cp) | |
3608 | { | |
3609 | u32 val; | |
3610 | int full_duplex, speed, pause; | |
3611 | ||
3612 | full_duplex = 0; | |
3613 | speed = 10; | |
3614 | pause = 0; | |
3615 | ||
3616 | if (CAS_PHY_MII(cp->phy_type)) { | |
3617 | cas_mif_poll(cp, 0); | |
3618 | val = cas_phy_read(cp, MII_BMCR); | |
3619 | if (val & BMCR_ANENABLE) { | |
6aa20a22 | 3620 | cas_read_mii_link_mode(cp, &full_duplex, &speed, |
1f26dac3 DM |
3621 | &pause); |
3622 | } else { | |
3623 | if (val & BMCR_FULLDPLX) | |
3624 | full_duplex = 1; | |
3625 | ||
3626 | if (val & BMCR_SPEED100) | |
3627 | speed = 100; | |
3628 | else if (val & CAS_BMCR_SPEED1000) | |
3629 | speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? | |
3630 | 1000 : 100; | |
3631 | } | |
3632 | cas_mif_poll(cp, 1); | |
3633 | ||
3634 | } else { | |
3635 | val = readl(cp->regs + REG_PCS_MII_CTRL); | |
3636 | cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause); | |
3637 | if ((val & PCS_MII_AUTONEG_EN) == 0) { | |
3638 | if (val & PCS_MII_CTRL_DUPLEX) | |
3639 | full_duplex = 1; | |
3640 | } | |
3641 | } | |
3642 | ||
436d27d1 JP |
3643 | netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n", |
3644 | speed, full_duplex ? "full" : "half"); | |
1f26dac3 DM |
3645 | |
3646 | val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED; | |
3647 | if (CAS_PHY_MII(cp->phy_type)) { | |
3648 | val |= MAC_XIF_MII_BUFFER_OUTPUT_EN; | |
3649 | if (!full_duplex) | |
3650 | val |= MAC_XIF_DISABLE_ECHO; | |
3651 | } | |
6aa20a22 | 3652 | if (full_duplex) |
1f26dac3 DM |
3653 | val |= MAC_XIF_FDPLX_LED; |
3654 | if (speed == 1000) | |
3655 | val |= MAC_XIF_GMII_MODE; | |
3656 | writel(val, cp->regs + REG_MAC_XIF_CFG); | |
3657 | ||
3658 | /* deal with carrier and collision detect. */ | |
3659 | val = MAC_TX_CFG_IPG_EN; | |
3660 | if (full_duplex) { | |
3661 | val |= MAC_TX_CFG_IGNORE_CARRIER; | |
3662 | val |= MAC_TX_CFG_IGNORE_COLL; | |
3663 | } else { | |
3664 | #ifndef USE_CSMA_CD_PROTO | |
3665 | val |= MAC_TX_CFG_NEVER_GIVE_UP_EN; | |
3666 | val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM; | |
3667 | #endif | |
3668 | } | |
3669 | /* val now set up for REG_MAC_TX_CFG */ | |
3670 | ||
3671 | /* If gigabit and half-duplex, enable carrier extension | |
6aa20a22 | 3672 | * mode. increase slot time to 512 bytes as well. |
1f26dac3 DM |
3673 | * else, disable it and make sure slot time is 64 bytes. |
3674 | * also activate checksum bug workaround | |
3675 | */ | |
3676 | if ((speed == 1000) && !full_duplex) { | |
6aa20a22 | 3677 | writel(val | MAC_TX_CFG_CARRIER_EXTEND, |
1f26dac3 DM |
3678 | cp->regs + REG_MAC_TX_CFG); |
3679 | ||
3680 | val = readl(cp->regs + REG_MAC_RX_CFG); | |
3681 | val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */ | |
6aa20a22 | 3682 | writel(val | MAC_RX_CFG_CARRIER_EXTEND, |
1f26dac3 DM |
3683 | cp->regs + REG_MAC_RX_CFG); |
3684 | ||
3685 | writel(0x200, cp->regs + REG_MAC_SLOT_TIME); | |
3686 | ||
3687 | cp->crc_size = 4; | |
3688 | /* minimum size gigabit frame at half duplex */ | |
3689 | cp->min_frame_size = CAS_1000MB_MIN_FRAME; | |
3690 | ||
3691 | } else { | |
3692 | writel(val, cp->regs + REG_MAC_TX_CFG); | |
3693 | ||
6aa20a22 | 3694 | /* checksum bug workaround. don't strip FCS when in |
1f26dac3 DM |
3695 | * half-duplex mode |
3696 | */ | |
3697 | val = readl(cp->regs + REG_MAC_RX_CFG); | |
3698 | if (full_duplex) { | |
3699 | val |= MAC_RX_CFG_STRIP_FCS; | |
3700 | cp->crc_size = 0; | |
3701 | cp->min_frame_size = CAS_MIN_MTU; | |
3702 | } else { | |
3703 | val &= ~MAC_RX_CFG_STRIP_FCS; | |
3704 | cp->crc_size = 4; | |
3705 | cp->min_frame_size = CAS_MIN_FRAME; | |
3706 | } | |
6aa20a22 | 3707 | writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, |
1f26dac3 DM |
3708 | cp->regs + REG_MAC_RX_CFG); |
3709 | writel(0x40, cp->regs + REG_MAC_SLOT_TIME); | |
3710 | } | |
3711 | ||
3712 | if (netif_msg_link(cp)) { | |
3713 | if (pause & 0x01) { | |
436d27d1 JP |
3714 | netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n", |
3715 | cp->rx_fifo_size, | |
3716 | cp->rx_pause_off, | |
3717 | cp->rx_pause_on); | |
1f26dac3 | 3718 | } else if (pause & 0x10) { |
436d27d1 | 3719 | netdev_info(cp->dev, "TX pause enabled\n"); |
1f26dac3 | 3720 | } else { |
436d27d1 | 3721 | netdev_info(cp->dev, "Pause is disabled\n"); |
1f26dac3 DM |
3722 | } |
3723 | } | |
3724 | ||
3725 | val = readl(cp->regs + REG_MAC_CTRL_CFG); | |
3726 | val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN); | |
3727 | if (pause) { /* symmetric or asymmetric pause */ | |
3728 | val |= MAC_CTRL_CFG_SEND_PAUSE_EN; | |
3729 | if (pause & 0x01) { /* symmetric pause */ | |
3730 | val |= MAC_CTRL_CFG_RECV_PAUSE_EN; | |
6aa20a22 | 3731 | } |
1f26dac3 DM |
3732 | } |
3733 | writel(val, cp->regs + REG_MAC_CTRL_CFG); | |
3734 | cas_start_dma(cp); | |
3735 | } | |
3736 | ||
3737 | /* Must be invoked under cp->lock. */ | |
3738 | static void cas_init_hw(struct cas *cp, int restart_link) | |
3739 | { | |
3740 | if (restart_link) | |
3741 | cas_phy_init(cp); | |
3742 | ||
3743 | cas_init_pause_thresholds(cp); | |
3744 | cas_init_mac(cp); | |
3745 | cas_init_dma(cp); | |
3746 | ||
3747 | if (restart_link) { | |
3748 | /* Default aneg parameters */ | |
3749 | cp->timer_ticks = 0; | |
3750 | cas_begin_auto_negotiation(cp, NULL); | |
3751 | } else if (cp->lstate == link_up) { | |
3752 | cas_set_link_modes(cp); | |
3753 | netif_carrier_on(cp->dev); | |
3754 | } | |
3755 | } | |
3756 | ||
3757 | /* Must be invoked under cp->lock. on earlier cassini boards, | |
3758 | * SOFT_0 is tied to PCI reset. we use this to force a pci reset, | |
3759 | * let it settle out, and then restore pci state. | |
3760 | */ | |
3761 | static void cas_hard_reset(struct cas *cp) | |
3762 | { | |
6aa20a22 | 3763 | writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); |
1f26dac3 DM |
3764 | udelay(20); |
3765 | pci_restore_state(cp->pdev); | |
3766 | } | |
3767 | ||
3768 | ||
3769 | static void cas_global_reset(struct cas *cp, int blkflag) | |
3770 | { | |
3771 | int limit; | |
3772 | ||
3773 | /* issue a global reset. don't use RSTOUT. */ | |
3774 | if (blkflag && !CAS_PHY_MII(cp->phy_type)) { | |
3775 | /* For PCS, when the blkflag is set, we should set the | |
3776 | * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of | |
3777 | * the last autonegotiation from being cleared. We'll | |
3778 | * need some special handling if the chip is set into a | |
3779 | * loopback mode. | |
3780 | */ | |
6aa20a22 | 3781 | writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), |
1f26dac3 DM |
3782 | cp->regs + REG_SW_RESET); |
3783 | } else { | |
3784 | writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); | |
3785 | } | |
3786 | ||
3787 | /* need to wait at least 3ms before polling register */ | |
3788 | mdelay(3); | |
3789 | ||
3790 | limit = STOP_TRIES; | |
3791 | while (limit-- > 0) { | |
3792 | u32 val = readl(cp->regs + REG_SW_RESET); | |
3793 | if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0) | |
3794 | goto done; | |
3795 | udelay(10); | |
3796 | } | |
436d27d1 | 3797 | netdev_err(cp->dev, "sw reset failed\n"); |
1f26dac3 DM |
3798 | |
3799 | done: | |
3800 | /* enable various BIM interrupts */ | |
6aa20a22 | 3801 | writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | |
1f26dac3 DM |
3802 | BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG); |
3803 | ||
3804 | /* clear out pci error status mask for handled errors. | |
3805 | * we don't deal with DMA counter overflows as they happen | |
3806 | * all the time. | |
3807 | */ | |
6aa20a22 JG |
3808 | writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | |
3809 | PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE | | |
3810 | PCI_ERR_BIM_DMA_READ), cp->regs + | |
1f26dac3 DM |
3811 | REG_PCI_ERR_STATUS_MASK); |
3812 | ||
3813 | /* set up for MII by default to address mac rx reset timeout | |
3814 | * issue | |
3815 | */ | |
3816 | writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); | |
3817 | } | |
3818 | ||
3819 | static void cas_reset(struct cas *cp, int blkflag) | |
3820 | { | |
3821 | u32 val; | |
3822 | ||
3823 | cas_mask_intr(cp); | |
3824 | cas_global_reset(cp, blkflag); | |
3825 | cas_mac_reset(cp); | |
3826 | cas_entropy_reset(cp); | |
3827 | ||
3828 | /* disable dma engines. */ | |
3829 | val = readl(cp->regs + REG_TX_CFG); | |
3830 | val &= ~TX_CFG_DMA_EN; | |
3831 | writel(val, cp->regs + REG_TX_CFG); | |
3832 | ||
3833 | val = readl(cp->regs + REG_RX_CFG); | |
3834 | val &= ~RX_CFG_DMA_EN; | |
3835 | writel(val, cp->regs + REG_RX_CFG); | |
3836 | ||
3837 | /* program header parser */ | |
3838 | if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || | |
3839 | (CAS_HP_ALT_FIRMWARE == cas_prog_null)) { | |
3840 | cas_load_firmware(cp, CAS_HP_FIRMWARE); | |
3841 | } else { | |
3842 | cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); | |
3843 | } | |
3844 | ||
3845 | /* clear out error registers */ | |
3846 | spin_lock(&cp->stat_lock[N_TX_RINGS]); | |
3847 | cas_clear_mac_err(cp); | |
3848 | spin_unlock(&cp->stat_lock[N_TX_RINGS]); | |
3849 | } | |
3850 | ||
758df69e | 3851 | /* Shut down the chip, must be called with pm_mutex held. */ |
1f26dac3 DM |
3852 | static void cas_shutdown(struct cas *cp) |
3853 | { | |
3854 | unsigned long flags; | |
3855 | ||
3856 | /* Make us not-running to avoid timers respawning */ | |
3857 | cp->hw_running = 0; | |
3858 | ||
3859 | del_timer_sync(&cp->link_timer); | |
3860 | ||
3861 | /* Stop the reset task */ | |
3862 | #if 0 | |
3863 | while (atomic_read(&cp->reset_task_pending_mtu) || | |
3864 | atomic_read(&cp->reset_task_pending_spare) || | |
3865 | atomic_read(&cp->reset_task_pending_all)) | |
3866 | schedule(); | |
3867 | ||
3868 | #else | |
3869 | while (atomic_read(&cp->reset_task_pending)) | |
3870 | schedule(); | |
6aa20a22 | 3871 | #endif |
1f26dac3 DM |
3872 | /* Actually stop the chip */ |
3873 | cas_lock_all_save(cp, flags); | |
3874 | cas_reset(cp, 0); | |
3875 | if (cp->cas_flags & CAS_FLAG_SATURN) | |
3876 | cas_phy_powerdown(cp); | |
3877 | cas_unlock_all_restore(cp, flags); | |
3878 | } | |
3879 | ||
3880 | static int cas_change_mtu(struct net_device *dev, int new_mtu) | |
3881 | { | |
3882 | struct cas *cp = netdev_priv(dev); | |
3883 | ||
3884 | if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU) | |
3885 | return -EINVAL; | |
3886 | ||
3887 | dev->mtu = new_mtu; | |
3888 | if (!netif_running(dev) || !netif_device_present(dev)) | |
3889 | return 0; | |
3890 | ||
3891 | /* let the reset task handle it */ | |
3892 | #if 1 | |
3893 | atomic_inc(&cp->reset_task_pending); | |
3894 | if ((cp->phy_type & CAS_PHY_SERDES)) { | |
3895 | atomic_inc(&cp->reset_task_pending_all); | |
3896 | } else { | |
3897 | atomic_inc(&cp->reset_task_pending_mtu); | |
3898 | } | |
3899 | schedule_work(&cp->reset_task); | |
3900 | #else | |
6aa20a22 | 3901 | atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ? |
1f26dac3 | 3902 | CAS_RESET_ALL : CAS_RESET_MTU); |
436d27d1 | 3903 | pr_err("reset called in cas_change_mtu\n"); |
1f26dac3 DM |
3904 | schedule_work(&cp->reset_task); |
3905 | #endif | |
3906 | ||
3907 | flush_scheduled_work(); | |
3908 | return 0; | |
3909 | } | |
3910 | ||
3911 | static void cas_clean_txd(struct cas *cp, int ring) | |
3912 | { | |
3913 | struct cas_tx_desc *txd = cp->init_txds[ring]; | |
3914 | struct sk_buff *skb, **skbs = cp->tx_skbs[ring]; | |
3915 | u64 daddr, dlen; | |
3916 | int i, size; | |
3917 | ||
3918 | size = TX_DESC_RINGN_SIZE(ring); | |
3919 | for (i = 0; i < size; i++) { | |
3920 | int frag; | |
3921 | ||
3922 | if (skbs[i] == NULL) | |
3923 | continue; | |
3924 | ||
3925 | skb = skbs[i]; | |
3926 | skbs[i] = NULL; | |
3927 | ||
3928 | for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { | |
3929 | int ent = i & (size - 1); | |
3930 | ||
3931 | /* first buffer is never a tiny buffer and so | |
3932 | * needs to be unmapped. | |
3933 | */ | |
3934 | daddr = le64_to_cpu(txd[ent].buffer); | |
6aa20a22 | 3935 | dlen = CAS_VAL(TX_DESC_BUFLEN, |
1f26dac3 DM |
3936 | le64_to_cpu(txd[ent].control)); |
3937 | pci_unmap_page(cp->pdev, daddr, dlen, | |
3938 | PCI_DMA_TODEVICE); | |
3939 | ||
3940 | if (frag != skb_shinfo(skb)->nr_frags) { | |
3941 | i++; | |
3942 | ||
3943 | /* next buffer might by a tiny buffer. | |
3944 | * skip past it. | |
3945 | */ | |
3946 | ent = i & (size - 1); | |
3947 | if (cp->tx_tiny_use[ring][ent].used) | |
3948 | i++; | |
3949 | } | |
3950 | } | |
3951 | dev_kfree_skb_any(skb); | |
3952 | } | |
3953 | ||
3954 | /* zero out tiny buf usage */ | |
3955 | memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring])); | |
3956 | } | |
3957 | ||
3958 | /* freed on close */ | |
3959 | static inline void cas_free_rx_desc(struct cas *cp, int ring) | |
3960 | { | |
3961 | cas_page_t **page = cp->rx_pages[ring]; | |
3962 | int i, size; | |
3963 | ||
3964 | size = RX_DESC_RINGN_SIZE(ring); | |
3965 | for (i = 0; i < size; i++) { | |
3966 | if (page[i]) { | |
3967 | cas_page_free(cp, page[i]); | |
3968 | page[i] = NULL; | |
3969 | } | |
3970 | } | |
3971 | } | |
3972 | ||
3973 | static void cas_free_rxds(struct cas *cp) | |
3974 | { | |
3975 | int i; | |
3976 | ||
3977 | for (i = 0; i < N_RX_DESC_RINGS; i++) | |
3978 | cas_free_rx_desc(cp, i); | |
3979 | } | |
3980 | ||
3981 | /* Must be invoked under cp->lock. */ | |
3982 | static void cas_clean_rings(struct cas *cp) | |
3983 | { | |
3984 | int i; | |
3985 | ||
3986 | /* need to clean all tx rings */ | |
3987 | memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS); | |
3988 | memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS); | |
3989 | for (i = 0; i < N_TX_RINGS; i++) | |
3990 | cas_clean_txd(cp, i); | |
3991 | ||
3992 | /* zero out init block */ | |
3993 | memset(cp->init_block, 0, sizeof(struct cas_init_block)); | |
3994 | cas_clean_rxds(cp); | |
3995 | cas_clean_rxcs(cp); | |
3996 | } | |
3997 | ||
3998 | /* allocated on open */ | |
3999 | static inline int cas_alloc_rx_desc(struct cas *cp, int ring) | |
4000 | { | |
4001 | cas_page_t **page = cp->rx_pages[ring]; | |
4002 | int size, i = 0; | |
4003 | ||
4004 | size = RX_DESC_RINGN_SIZE(ring); | |
4005 | for (i = 0; i < size; i++) { | |
6aa20a22 | 4006 | if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL) |
1f26dac3 DM |
4007 | return -1; |
4008 | } | |
4009 | return 0; | |
4010 | } | |
4011 | ||
4012 | static int cas_alloc_rxds(struct cas *cp) | |
4013 | { | |
4014 | int i; | |
4015 | ||
4016 | for (i = 0; i < N_RX_DESC_RINGS; i++) { | |
4017 | if (cas_alloc_rx_desc(cp, i) < 0) { | |
4018 | cas_free_rxds(cp); | |
4019 | return -1; | |
4020 | } | |
4021 | } | |
4022 | return 0; | |
4023 | } | |
4024 | ||
c4028958 | 4025 | static void cas_reset_task(struct work_struct *work) |
1f26dac3 | 4026 | { |
c4028958 | 4027 | struct cas *cp = container_of(work, struct cas, reset_task); |
1f26dac3 DM |
4028 | #if 0 |
4029 | int pending = atomic_read(&cp->reset_task_pending); | |
4030 | #else | |
4031 | int pending_all = atomic_read(&cp->reset_task_pending_all); | |
4032 | int pending_spare = atomic_read(&cp->reset_task_pending_spare); | |
4033 | int pending_mtu = atomic_read(&cp->reset_task_pending_mtu); | |
4034 | ||
4035 | if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) { | |
4036 | /* We can have more tasks scheduled than actually | |
4037 | * needed. | |
4038 | */ | |
4039 | atomic_dec(&cp->reset_task_pending); | |
4040 | return; | |
4041 | } | |
4042 | #endif | |
4043 | /* The link went down, we reset the ring, but keep | |
4044 | * DMA stopped. Use this function for reset | |
4045 | * on error as well. | |
4046 | */ | |
4047 | if (cp->hw_running) { | |
4048 | unsigned long flags; | |
4049 | ||
4050 | /* Make sure we don't get interrupts or tx packets */ | |
4051 | netif_device_detach(cp->dev); | |
4052 | cas_lock_all_save(cp, flags); | |
4053 | ||
4054 | if (cp->opened) { | |
4055 | /* We call cas_spare_recover when we call cas_open. | |
4056 | * but we do not initialize the lists cas_spare_recover | |
4057 | * uses until cas_open is called. | |
4058 | */ | |
4059 | cas_spare_recover(cp, GFP_ATOMIC); | |
4060 | } | |
4061 | #if 1 | |
4062 | /* test => only pending_spare set */ | |
4063 | if (!pending_all && !pending_mtu) | |
4064 | goto done; | |
4065 | #else | |
4066 | if (pending == CAS_RESET_SPARE) | |
4067 | goto done; | |
4068 | #endif | |
4069 | /* when pending == CAS_RESET_ALL, the following | |
4070 | * call to cas_init_hw will restart auto negotiation. | |
4071 | * Setting the second argument of cas_reset to | |
4072 | * !(pending == CAS_RESET_ALL) will set this argument | |
6aa20a22 | 4073 | * to 1 (avoiding reinitializing the PHY for the normal |
1f26dac3 DM |
4074 | * PCS case) when auto negotiation is not restarted. |
4075 | */ | |
4076 | #if 1 | |
4077 | cas_reset(cp, !(pending_all > 0)); | |
4078 | if (cp->opened) | |
4079 | cas_clean_rings(cp); | |
4080 | cas_init_hw(cp, (pending_all > 0)); | |
4081 | #else | |
4082 | cas_reset(cp, !(pending == CAS_RESET_ALL)); | |
4083 | if (cp->opened) | |
4084 | cas_clean_rings(cp); | |
4085 | cas_init_hw(cp, pending == CAS_RESET_ALL); | |
4086 | #endif | |
4087 | ||
4088 | done: | |
4089 | cas_unlock_all_restore(cp, flags); | |
4090 | netif_device_attach(cp->dev); | |
4091 | } | |
4092 | #if 1 | |
4093 | atomic_sub(pending_all, &cp->reset_task_pending_all); | |
4094 | atomic_sub(pending_spare, &cp->reset_task_pending_spare); | |
4095 | atomic_sub(pending_mtu, &cp->reset_task_pending_mtu); | |
4096 | atomic_dec(&cp->reset_task_pending); | |
4097 | #else | |
4098 | atomic_set(&cp->reset_task_pending, 0); | |
4099 | #endif | |
4100 | } | |
4101 | ||
4102 | static void cas_link_timer(unsigned long data) | |
4103 | { | |
4104 | struct cas *cp = (struct cas *) data; | |
4105 | int mask, pending = 0, reset = 0; | |
4106 | unsigned long flags; | |
4107 | ||
4108 | if (link_transition_timeout != 0 && | |
4109 | cp->link_transition_jiffies_valid && | |
6aa20a22 | 4110 | ((jiffies - cp->link_transition_jiffies) > |
1f26dac3 | 4111 | (link_transition_timeout))) { |
6aa20a22 | 4112 | /* One-second counter so link-down workaround doesn't |
1f26dac3 DM |
4113 | * cause resets to occur so fast as to fool the switch |
4114 | * into thinking the link is down. | |
4115 | */ | |
4116 | cp->link_transition_jiffies_valid = 0; | |
4117 | } | |
4118 | ||
4119 | if (!cp->hw_running) | |
4120 | return; | |
4121 | ||
4122 | spin_lock_irqsave(&cp->lock, flags); | |
4123 | cas_lock_tx(cp); | |
4124 | cas_entropy_gather(cp); | |
4125 | ||
4126 | /* If the link task is still pending, we just | |
4127 | * reschedule the link timer | |
4128 | */ | |
4129 | #if 1 | |
4130 | if (atomic_read(&cp->reset_task_pending_all) || | |
4131 | atomic_read(&cp->reset_task_pending_spare) || | |
6aa20a22 | 4132 | atomic_read(&cp->reset_task_pending_mtu)) |
1f26dac3 DM |
4133 | goto done; |
4134 | #else | |
6aa20a22 | 4135 | if (atomic_read(&cp->reset_task_pending)) |
1f26dac3 DM |
4136 | goto done; |
4137 | #endif | |
4138 | ||
4139 | /* check for rx cleaning */ | |
4140 | if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { | |
4141 | int i, rmask; | |
4142 | ||
4143 | for (i = 0; i < MAX_RX_DESC_RINGS; i++) { | |
4144 | rmask = CAS_FLAG_RXD_POST(i); | |
4145 | if ((mask & rmask) == 0) | |
4146 | continue; | |
4147 | ||
4148 | /* post_rxds will do a mod_timer */ | |
4149 | if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) { | |
4150 | pending = 1; | |
4151 | continue; | |
4152 | } | |
4153 | cp->cas_flags &= ~rmask; | |
4154 | } | |
4155 | } | |
4156 | ||
4157 | if (CAS_PHY_MII(cp->phy_type)) { | |
4158 | u16 bmsr; | |
4159 | cas_mif_poll(cp, 0); | |
4160 | bmsr = cas_phy_read(cp, MII_BMSR); | |
4161 | /* WTZ: Solaris driver reads this twice, but that | |
4162 | * may be due to the PCS case and the use of a | |
4163 | * common implementation. Read it twice here to be | |
4164 | * safe. | |
4165 | */ | |
4166 | bmsr = cas_phy_read(cp, MII_BMSR); | |
4167 | cas_mif_poll(cp, 1); | |
4168 | readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ | |
4169 | reset = cas_mii_link_check(cp, bmsr); | |
4170 | } else { | |
4171 | reset = cas_pcs_link_check(cp); | |
4172 | } | |
4173 | ||
4174 | if (reset) | |
4175 | goto done; | |
4176 | ||
4177 | /* check for tx state machine confusion */ | |
4178 | if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { | |
4179 | u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); | |
4180 | u32 wptr, rptr; | |
4181 | int tlm = CAS_VAL(MAC_SM_TLM, val); | |
4182 | ||
4183 | if (((tlm == 0x5) || (tlm == 0x3)) && | |
4184 | (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) { | |
436d27d1 JP |
4185 | netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, |
4186 | "tx err: MAC_STATE[%08x]\n", val); | |
1f26dac3 DM |
4187 | reset = 1; |
4188 | goto done; | |
4189 | } | |
4190 | ||
4191 | val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); | |
4192 | wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); | |
4193 | rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); | |
4194 | if ((val == 0) && (wptr != rptr)) { | |
436d27d1 JP |
4195 | netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, |
4196 | "tx err: TX_FIFO[%08x:%08x:%08x]\n", | |
4197 | val, wptr, rptr); | |
1f26dac3 DM |
4198 | reset = 1; |
4199 | } | |
4200 | ||
4201 | if (reset) | |
4202 | cas_hard_reset(cp); | |
4203 | } | |
4204 | ||
4205 | done: | |
4206 | if (reset) { | |
4207 | #if 1 | |
4208 | atomic_inc(&cp->reset_task_pending); | |
4209 | atomic_inc(&cp->reset_task_pending_all); | |
4210 | schedule_work(&cp->reset_task); | |
4211 | #else | |
4212 | atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); | |
436d27d1 | 4213 | pr_err("reset called in cas_link_timer\n"); |
1f26dac3 DM |
4214 | schedule_work(&cp->reset_task); |
4215 | #endif | |
4216 | } | |
4217 | ||
4218 | if (!pending) | |
4219 | mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); | |
4220 | cas_unlock_tx(cp); | |
4221 | spin_unlock_irqrestore(&cp->lock, flags); | |
4222 | } | |
4223 | ||
6aa20a22 | 4224 | /* tiny buffers are used to avoid target abort issues with |
1f26dac3 DM |
4225 | * older cassini's |
4226 | */ | |
4227 | static void cas_tx_tiny_free(struct cas *cp) | |
4228 | { | |
4229 | struct pci_dev *pdev = cp->pdev; | |
4230 | int i; | |
4231 | ||
4232 | for (i = 0; i < N_TX_RINGS; i++) { | |
4233 | if (!cp->tx_tiny_bufs[i]) | |
4234 | continue; | |
4235 | ||
6aa20a22 | 4236 | pci_free_consistent(pdev, TX_TINY_BUF_BLOCK, |
1f26dac3 DM |
4237 | cp->tx_tiny_bufs[i], |
4238 | cp->tx_tiny_dvma[i]); | |
4239 | cp->tx_tiny_bufs[i] = NULL; | |
4240 | } | |
4241 | } | |
4242 | ||
4243 | static int cas_tx_tiny_alloc(struct cas *cp) | |
4244 | { | |
4245 | struct pci_dev *pdev = cp->pdev; | |
4246 | int i; | |
4247 | ||
4248 | for (i = 0; i < N_TX_RINGS; i++) { | |
6aa20a22 | 4249 | cp->tx_tiny_bufs[i] = |
1f26dac3 DM |
4250 | pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK, |
4251 | &cp->tx_tiny_dvma[i]); | |
4252 | if (!cp->tx_tiny_bufs[i]) { | |
4253 | cas_tx_tiny_free(cp); | |
4254 | return -1; | |
4255 | } | |
4256 | } | |
4257 | return 0; | |
4258 | } | |
4259 | ||
4260 | ||
4261 | static int cas_open(struct net_device *dev) | |
4262 | { | |
4263 | struct cas *cp = netdev_priv(dev); | |
4264 | int hw_was_up, err; | |
4265 | unsigned long flags; | |
4266 | ||
758df69e | 4267 | mutex_lock(&cp->pm_mutex); |
1f26dac3 DM |
4268 | |
4269 | hw_was_up = cp->hw_running; | |
4270 | ||
758df69e | 4271 | /* The power-management mutex protects the hw_running |
1f26dac3 DM |
4272 | * etc. state so it is safe to do this bit without cp->lock |
4273 | */ | |
4274 | if (!cp->hw_running) { | |
4275 | /* Reset the chip */ | |
4276 | cas_lock_all_save(cp, flags); | |
4277 | /* We set the second arg to cas_reset to zero | |
6aa20a22 | 4278 | * because cas_init_hw below will have its second |
1f26dac3 DM |
4279 | * argument set to non-zero, which will force |
4280 | * autonegotiation to start. | |
4281 | */ | |
4282 | cas_reset(cp, 0); | |
4283 | cp->hw_running = 1; | |
4284 | cas_unlock_all_restore(cp, flags); | |
4285 | } | |
4286 | ||
87d75b52 | 4287 | err = -ENOMEM; |
1f26dac3 | 4288 | if (cas_tx_tiny_alloc(cp) < 0) |
87d75b52 | 4289 | goto err_unlock; |
1f26dac3 DM |
4290 | |
4291 | /* alloc rx descriptors */ | |
1f26dac3 DM |
4292 | if (cas_alloc_rxds(cp) < 0) |
4293 | goto err_tx_tiny; | |
6aa20a22 | 4294 | |
1f26dac3 DM |
4295 | /* allocate spares */ |
4296 | cas_spare_init(cp); | |
4297 | cas_spare_recover(cp, GFP_KERNEL); | |
4298 | ||
4299 | /* We can now request the interrupt as we know it's masked | |
4300 | * on the controller. cassini+ has up to 4 interrupts | |
6aa20a22 | 4301 | * that can be used, but you need to do explicit pci interrupt |
1f26dac3 DM |
4302 | * mapping to expose them |
4303 | */ | |
4304 | if (request_irq(cp->pdev->irq, cas_interrupt, | |
1fb9df5d | 4305 | IRQF_SHARED, dev->name, (void *) dev)) { |
436d27d1 | 4306 | netdev_err(cp->dev, "failed to request irq !\n"); |
1f26dac3 DM |
4307 | err = -EAGAIN; |
4308 | goto err_spare; | |
4309 | } | |
4310 | ||
bea3348e SH |
4311 | #ifdef USE_NAPI |
4312 | napi_enable(&cp->napi); | |
4313 | #endif | |
1f26dac3 DM |
4314 | /* init hw */ |
4315 | cas_lock_all_save(cp, flags); | |
4316 | cas_clean_rings(cp); | |
4317 | cas_init_hw(cp, !hw_was_up); | |
4318 | cp->opened = 1; | |
4319 | cas_unlock_all_restore(cp, flags); | |
4320 | ||
4321 | netif_start_queue(dev); | |
758df69e | 4322 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
4323 | return 0; |
4324 | ||
4325 | err_spare: | |
4326 | cas_spare_free(cp); | |
4327 | cas_free_rxds(cp); | |
4328 | err_tx_tiny: | |
4329 | cas_tx_tiny_free(cp); | |
87d75b52 | 4330 | err_unlock: |
758df69e | 4331 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
4332 | return err; |
4333 | } | |
4334 | ||
4335 | static int cas_close(struct net_device *dev) | |
4336 | { | |
4337 | unsigned long flags; | |
4338 | struct cas *cp = netdev_priv(dev); | |
4339 | ||
bea3348e | 4340 | #ifdef USE_NAPI |
86216268 | 4341 | napi_disable(&cp->napi); |
bea3348e | 4342 | #endif |
1f26dac3 | 4343 | /* Make sure we don't get distracted by suspend/resume */ |
758df69e | 4344 | mutex_lock(&cp->pm_mutex); |
1f26dac3 DM |
4345 | |
4346 | netif_stop_queue(dev); | |
4347 | ||
4348 | /* Stop traffic, mark us closed */ | |
4349 | cas_lock_all_save(cp, flags); | |
6aa20a22 | 4350 | cp->opened = 0; |
1f26dac3 | 4351 | cas_reset(cp, 0); |
6aa20a22 | 4352 | cas_phy_init(cp); |
1f26dac3 DM |
4353 | cas_begin_auto_negotiation(cp, NULL); |
4354 | cas_clean_rings(cp); | |
4355 | cas_unlock_all_restore(cp, flags); | |
4356 | ||
4357 | free_irq(cp->pdev->irq, (void *) dev); | |
4358 | cas_spare_free(cp); | |
4359 | cas_free_rxds(cp); | |
4360 | cas_tx_tiny_free(cp); | |
758df69e | 4361 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
4362 | return 0; |
4363 | } | |
4364 | ||
4365 | static struct { | |
4366 | const char name[ETH_GSTRING_LEN]; | |
4367 | } ethtool_cassini_statnames[] = { | |
4368 | {"collisions"}, | |
4369 | {"rx_bytes"}, | |
4370 | {"rx_crc_errors"}, | |
4371 | {"rx_dropped"}, | |
4372 | {"rx_errors"}, | |
4373 | {"rx_fifo_errors"}, | |
4374 | {"rx_frame_errors"}, | |
4375 | {"rx_length_errors"}, | |
4376 | {"rx_over_errors"}, | |
4377 | {"rx_packets"}, | |
4378 | {"tx_aborted_errors"}, | |
4379 | {"tx_bytes"}, | |
4380 | {"tx_dropped"}, | |
4381 | {"tx_errors"}, | |
4382 | {"tx_fifo_errors"}, | |
4383 | {"tx_packets"} | |
4384 | }; | |
4c3616cd | 4385 | #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames) |
1f26dac3 DM |
4386 | |
4387 | static struct { | |
4388 | const int offsets; /* neg. values for 2nd arg to cas_read_phy */ | |
4389 | } ethtool_register_table[] = { | |
4390 | {-MII_BMSR}, | |
4391 | {-MII_BMCR}, | |
4392 | {REG_CAWR}, | |
4393 | {REG_INF_BURST}, | |
4394 | {REG_BIM_CFG}, | |
4395 | {REG_RX_CFG}, | |
4396 | {REG_HP_CFG}, | |
4397 | {REG_MAC_TX_CFG}, | |
4398 | {REG_MAC_RX_CFG}, | |
4399 | {REG_MAC_CTRL_CFG}, | |
4400 | {REG_MAC_XIF_CFG}, | |
4401 | {REG_MIF_CFG}, | |
4402 | {REG_PCS_CFG}, | |
4403 | {REG_SATURN_PCFG}, | |
4404 | {REG_PCS_MII_STATUS}, | |
4405 | {REG_PCS_STATE_MACHINE}, | |
4406 | {REG_MAC_COLL_EXCESS}, | |
4407 | {REG_MAC_COLL_LATE} | |
4408 | }; | |
e9edda69 | 4409 | #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table) |
1f26dac3 DM |
4410 | #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN) |
4411 | ||
a232f767 | 4412 | static void cas_read_regs(struct cas *cp, u8 *ptr, int len) |
1f26dac3 | 4413 | { |
1f26dac3 DM |
4414 | u8 *p; |
4415 | int i; | |
4416 | unsigned long flags; | |
4417 | ||
1f26dac3 | 4418 | spin_lock_irqsave(&cp->lock, flags); |
a232f767 | 4419 | for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) { |
1f26dac3 DM |
4420 | u16 hval; |
4421 | u32 val; | |
4422 | if (ethtool_register_table[i].offsets < 0) { | |
4423 | hval = cas_phy_read(cp, | |
4424 | -ethtool_register_table[i].offsets); | |
4425 | val = hval; | |
4426 | } else { | |
4427 | val= readl(cp->regs+ethtool_register_table[i].offsets); | |
4428 | } | |
4429 | memcpy(p, (u8 *)&val, sizeof(u32)); | |
4430 | } | |
4431 | spin_unlock_irqrestore(&cp->lock, flags); | |
1f26dac3 DM |
4432 | } |
4433 | ||
4434 | static struct net_device_stats *cas_get_stats(struct net_device *dev) | |
4435 | { | |
4436 | struct cas *cp = netdev_priv(dev); | |
4437 | struct net_device_stats *stats = cp->net_stats; | |
4438 | unsigned long flags; | |
4439 | int i; | |
4440 | unsigned long tmp; | |
4441 | ||
4442 | /* we collate all of the stats into net_stats[N_TX_RING] */ | |
4443 | if (!cp->hw_running) | |
4444 | return stats + N_TX_RINGS; | |
6aa20a22 | 4445 | |
1f26dac3 DM |
4446 | /* collect outstanding stats */ |
4447 | /* WTZ: the Cassini spec gives these as 16 bit counters but | |
4448 | * stored in 32-bit words. Added a mask of 0xffff to be safe, | |
4449 | * in case the chip somehow puts any garbage in the other bits. | |
4450 | * Also, counter usage didn't seem to mach what Adrian did | |
4451 | * in the parts of the code that set these quantities. Made | |
4452 | * that consistent. | |
4453 | */ | |
4454 | spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags); | |
6aa20a22 | 4455 | stats[N_TX_RINGS].rx_crc_errors += |
1f26dac3 | 4456 | readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; |
6aa20a22 | 4457 | stats[N_TX_RINGS].rx_frame_errors += |
1f26dac3 | 4458 | readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; |
6aa20a22 | 4459 | stats[N_TX_RINGS].rx_length_errors += |
1f26dac3 DM |
4460 | readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; |
4461 | #if 1 | |
4462 | tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + | |
4463 | (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); | |
4464 | stats[N_TX_RINGS].tx_aborted_errors += tmp; | |
4465 | stats[N_TX_RINGS].collisions += | |
4466 | tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); | |
4467 | #else | |
6aa20a22 | 4468 | stats[N_TX_RINGS].tx_aborted_errors += |
1f26dac3 DM |
4469 | readl(cp->regs + REG_MAC_COLL_EXCESS); |
4470 | stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) + | |
4471 | readl(cp->regs + REG_MAC_COLL_LATE); | |
4472 | #endif | |
4473 | cas_clear_mac_err(cp); | |
4474 | ||
4475 | /* saved bits that are unique to ring 0 */ | |
4476 | spin_lock(&cp->stat_lock[0]); | |
4477 | stats[N_TX_RINGS].collisions += stats[0].collisions; | |
4478 | stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors; | |
4479 | stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors; | |
4480 | stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors; | |
4481 | stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors; | |
4482 | stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors; | |
4483 | spin_unlock(&cp->stat_lock[0]); | |
4484 | ||
4485 | for (i = 0; i < N_TX_RINGS; i++) { | |
4486 | spin_lock(&cp->stat_lock[i]); | |
6aa20a22 | 4487 | stats[N_TX_RINGS].rx_length_errors += |
1f26dac3 DM |
4488 | stats[i].rx_length_errors; |
4489 | stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors; | |
4490 | stats[N_TX_RINGS].rx_packets += stats[i].rx_packets; | |
4491 | stats[N_TX_RINGS].tx_packets += stats[i].tx_packets; | |
4492 | stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes; | |
4493 | stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes; | |
4494 | stats[N_TX_RINGS].rx_errors += stats[i].rx_errors; | |
4495 | stats[N_TX_RINGS].tx_errors += stats[i].tx_errors; | |
4496 | stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped; | |
4497 | stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped; | |
4498 | memset(stats + i, 0, sizeof(struct net_device_stats)); | |
4499 | spin_unlock(&cp->stat_lock[i]); | |
4500 | } | |
4501 | spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags); | |
4502 | return stats + N_TX_RINGS; | |
4503 | } | |
4504 | ||
4505 | ||
4506 | static void cas_set_multicast(struct net_device *dev) | |
4507 | { | |
4508 | struct cas *cp = netdev_priv(dev); | |
4509 | u32 rxcfg, rxcfg_new; | |
4510 | unsigned long flags; | |
4511 | int limit = STOP_TRIES; | |
6aa20a22 | 4512 | |
1f26dac3 DM |
4513 | if (!cp->hw_running) |
4514 | return; | |
6aa20a22 | 4515 | |
1f26dac3 DM |
4516 | spin_lock_irqsave(&cp->lock, flags); |
4517 | rxcfg = readl(cp->regs + REG_MAC_RX_CFG); | |
4518 | ||
4519 | /* disable RX MAC and wait for completion */ | |
4520 | writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); | |
4521 | while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { | |
4522 | if (!limit--) | |
4523 | break; | |
4524 | udelay(10); | |
4525 | } | |
4526 | ||
4527 | /* disable hash filter and wait for completion */ | |
4528 | limit = STOP_TRIES; | |
4529 | rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN); | |
4530 | writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); | |
4531 | while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { | |
4532 | if (!limit--) | |
4533 | break; | |
4534 | udelay(10); | |
4535 | } | |
4536 | ||
4537 | /* program hash filters */ | |
4538 | cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp); | |
4539 | rxcfg |= rxcfg_new; | |
4540 | writel(rxcfg, cp->regs + REG_MAC_RX_CFG); | |
4541 | spin_unlock_irqrestore(&cp->lock, flags); | |
4542 | } | |
4543 | ||
a232f767 AV |
4544 | static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4545 | { | |
4546 | struct cas *cp = netdev_priv(dev); | |
4547 | strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN); | |
4548 | strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN); | |
4549 | info->fw_version[0] = '\0'; | |
4550 | strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN); | |
4551 | info->regdump_len = cp->casreg_len < CAS_MAX_REGS ? | |
4552 | cp->casreg_len : CAS_MAX_REGS; | |
4553 | info->n_stats = CAS_NUM_STAT_KEYS; | |
4554 | } | |
4555 | ||
4556 | static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1f26dac3 DM |
4557 | { |
4558 | struct cas *cp = netdev_priv(dev); | |
4559 | u16 bmcr; | |
4560 | int full_duplex, speed, pause; | |
1f26dac3 DM |
4561 | unsigned long flags; |
4562 | enum link_state linkstate = link_up; | |
4563 | ||
a232f767 AV |
4564 | cmd->advertising = 0; |
4565 | cmd->supported = SUPPORTED_Autoneg; | |
4566 | if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { | |
4567 | cmd->supported |= SUPPORTED_1000baseT_Full; | |
4568 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
1f26dac3 DM |
4569 | } |
4570 | ||
a232f767 AV |
4571 | /* Record PHY settings if HW is on. */ |
4572 | spin_lock_irqsave(&cp->lock, flags); | |
4573 | bmcr = 0; | |
4574 | linkstate = cp->lstate; | |
4575 | if (CAS_PHY_MII(cp->phy_type)) { | |
4576 | cmd->port = PORT_MII; | |
4577 | cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ? | |
4578 | XCVR_INTERNAL : XCVR_EXTERNAL; | |
4579 | cmd->phy_address = cp->phy_addr; | |
4580 | cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII | | |
6aa20a22 JG |
4581 | ADVERTISED_10baseT_Half | |
4582 | ADVERTISED_10baseT_Full | | |
4583 | ADVERTISED_100baseT_Half | | |
a232f767 AV |
4584 | ADVERTISED_100baseT_Full; |
4585 | ||
4586 | cmd->supported |= | |
6aa20a22 | 4587 | (SUPPORTED_10baseT_Half | |
a232f767 | 4588 | SUPPORTED_10baseT_Full | |
6aa20a22 | 4589 | SUPPORTED_100baseT_Half | |
a232f767 AV |
4590 | SUPPORTED_100baseT_Full | |
4591 | SUPPORTED_TP | SUPPORTED_MII); | |
4592 | ||
4593 | if (cp->hw_running) { | |
4594 | cas_mif_poll(cp, 0); | |
4595 | bmcr = cas_phy_read(cp, MII_BMCR); | |
6aa20a22 | 4596 | cas_read_mii_link_mode(cp, &full_duplex, |
a232f767 AV |
4597 | &speed, &pause); |
4598 | cas_mif_poll(cp, 1); | |
1f26dac3 DM |
4599 | } |
4600 | ||
a232f767 AV |
4601 | } else { |
4602 | cmd->port = PORT_FIBRE; | |
4603 | cmd->transceiver = XCVR_INTERNAL; | |
4604 | cmd->phy_address = 0; | |
4605 | cmd->supported |= SUPPORTED_FIBRE; | |
4606 | cmd->advertising |= ADVERTISED_FIBRE; | |
4607 | ||
4608 | if (cp->hw_running) { | |
6aa20a22 | 4609 | /* pcs uses the same bits as mii */ |
a232f767 | 4610 | bmcr = readl(cp->regs + REG_PCS_MII_CTRL); |
6aa20a22 | 4611 | cas_read_pcs_link_mode(cp, &full_duplex, |
a232f767 | 4612 | &speed, &pause); |
1f26dac3 | 4613 | } |
a232f767 AV |
4614 | } |
4615 | spin_unlock_irqrestore(&cp->lock, flags); | |
1f26dac3 | 4616 | |
a232f767 AV |
4617 | if (bmcr & BMCR_ANENABLE) { |
4618 | cmd->advertising |= ADVERTISED_Autoneg; | |
4619 | cmd->autoneg = AUTONEG_ENABLE; | |
4620 | cmd->speed = ((speed == 10) ? | |
4621 | SPEED_10 : | |
4622 | ((speed == 1000) ? | |
4623 | SPEED_1000 : SPEED_100)); | |
4624 | cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; | |
4625 | } else { | |
4626 | cmd->autoneg = AUTONEG_DISABLE; | |
4627 | cmd->speed = | |
4628 | (bmcr & CAS_BMCR_SPEED1000) ? | |
6aa20a22 JG |
4629 | SPEED_1000 : |
4630 | ((bmcr & BMCR_SPEED100) ? SPEED_100: | |
a232f767 AV |
4631 | SPEED_10); |
4632 | cmd->duplex = | |
4633 | (bmcr & BMCR_FULLDPLX) ? | |
4634 | DUPLEX_FULL : DUPLEX_HALF; | |
4635 | } | |
4636 | if (linkstate != link_up) { | |
4637 | /* Force these to "unknown" if the link is not up and | |
6aa20a22 | 4638 | * autonogotiation in enabled. We can set the link |
a232f767 AV |
4639 | * speed to 0, but not cmd->duplex, |
4640 | * because its legal values are 0 and 1. Ethtool will | |
4641 | * print the value reported in parentheses after the | |
4642 | * word "Unknown" for unrecognized values. | |
4643 | * | |
4644 | * If in forced mode, we report the speed and duplex | |
4645 | * settings that we configured. | |
4646 | */ | |
4647 | if (cp->link_cntl & BMCR_ANENABLE) { | |
4648 | cmd->speed = 0; | |
4649 | cmd->duplex = 0xff; | |
1f26dac3 | 4650 | } else { |
a232f767 AV |
4651 | cmd->speed = SPEED_10; |
4652 | if (cp->link_cntl & BMCR_SPEED100) { | |
4653 | cmd->speed = SPEED_100; | |
4654 | } else if (cp->link_cntl & CAS_BMCR_SPEED1000) { | |
4655 | cmd->speed = SPEED_1000; | |
1f26dac3 | 4656 | } |
a232f767 AV |
4657 | cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)? |
4658 | DUPLEX_FULL : DUPLEX_HALF; | |
1f26dac3 | 4659 | } |
a232f767 AV |
4660 | } |
4661 | return 0; | |
4662 | } | |
1f26dac3 | 4663 | |
a232f767 AV |
4664 | static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
4665 | { | |
4666 | struct cas *cp = netdev_priv(dev); | |
4667 | unsigned long flags; | |
1f26dac3 | 4668 | |
a232f767 AV |
4669 | /* Verify the settings we care about. */ |
4670 | if (cmd->autoneg != AUTONEG_ENABLE && | |
4671 | cmd->autoneg != AUTONEG_DISABLE) | |
4672 | return -EINVAL; | |
1f26dac3 | 4673 | |
a232f767 AV |
4674 | if (cmd->autoneg == AUTONEG_DISABLE && |
4675 | ((cmd->speed != SPEED_1000 && | |
4676 | cmd->speed != SPEED_100 && | |
4677 | cmd->speed != SPEED_10) || | |
4678 | (cmd->duplex != DUPLEX_HALF && | |
4679 | cmd->duplex != DUPLEX_FULL))) | |
4680 | return -EINVAL; | |
1f26dac3 | 4681 | |
a232f767 AV |
4682 | /* Apply settings and restart link process. */ |
4683 | spin_lock_irqsave(&cp->lock, flags); | |
4684 | cas_begin_auto_negotiation(cp, cmd); | |
4685 | spin_unlock_irqrestore(&cp->lock, flags); | |
4686 | return 0; | |
4687 | } | |
1f26dac3 | 4688 | |
a232f767 AV |
4689 | static int cas_nway_reset(struct net_device *dev) |
4690 | { | |
4691 | struct cas *cp = netdev_priv(dev); | |
4692 | unsigned long flags; | |
1f26dac3 | 4693 | |
a232f767 AV |
4694 | if ((cp->link_cntl & BMCR_ANENABLE) == 0) |
4695 | return -EINVAL; | |
1f26dac3 | 4696 | |
a232f767 AV |
4697 | /* Restart link process. */ |
4698 | spin_lock_irqsave(&cp->lock, flags); | |
4699 | cas_begin_auto_negotiation(cp, NULL); | |
4700 | spin_unlock_irqrestore(&cp->lock, flags); | |
1f26dac3 | 4701 | |
a232f767 AV |
4702 | return 0; |
4703 | } | |
1f26dac3 | 4704 | |
a232f767 AV |
4705 | static u32 cas_get_link(struct net_device *dev) |
4706 | { | |
4707 | struct cas *cp = netdev_priv(dev); | |
4708 | return cp->lstate == link_up; | |
4709 | } | |
1f26dac3 | 4710 | |
a232f767 AV |
4711 | static u32 cas_get_msglevel(struct net_device *dev) |
4712 | { | |
4713 | struct cas *cp = netdev_priv(dev); | |
4714 | return cp->msg_enable; | |
4715 | } | |
1f26dac3 | 4716 | |
a232f767 AV |
4717 | static void cas_set_msglevel(struct net_device *dev, u32 value) |
4718 | { | |
4719 | struct cas *cp = netdev_priv(dev); | |
4720 | cp->msg_enable = value; | |
4721 | } | |
1f26dac3 | 4722 | |
a232f767 AV |
4723 | static int cas_get_regs_len(struct net_device *dev) |
4724 | { | |
4725 | struct cas *cp = netdev_priv(dev); | |
4726 | return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS; | |
4727 | } | |
1f26dac3 | 4728 | |
a232f767 AV |
4729 | static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
4730 | void *p) | |
4731 | { | |
4732 | struct cas *cp = netdev_priv(dev); | |
4733 | regs->version = 0; | |
4734 | /* cas_read_regs handles locks (cp->lock). */ | |
4735 | cas_read_regs(cp, p, regs->len / sizeof(u32)); | |
4736 | } | |
1f26dac3 | 4737 | |
b9f2c044 | 4738 | static int cas_get_sset_count(struct net_device *dev, int sset) |
a232f767 | 4739 | { |
b9f2c044 JG |
4740 | switch (sset) { |
4741 | case ETH_SS_STATS: | |
4742 | return CAS_NUM_STAT_KEYS; | |
4743 | default: | |
4744 | return -EOPNOTSUPP; | |
4745 | } | |
a232f767 | 4746 | } |
1f26dac3 | 4747 | |
a232f767 AV |
4748 | static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
4749 | { | |
6aa20a22 | 4750 | memcpy(data, ðtool_cassini_statnames, |
a232f767 AV |
4751 | CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN); |
4752 | } | |
1f26dac3 | 4753 | |
a232f767 AV |
4754 | static void cas_get_ethtool_stats(struct net_device *dev, |
4755 | struct ethtool_stats *estats, u64 *data) | |
4756 | { | |
4757 | struct cas *cp = netdev_priv(dev); | |
4758 | struct net_device_stats *stats = cas_get_stats(cp->dev); | |
4759 | int i = 0; | |
4760 | data[i++] = stats->collisions; | |
4761 | data[i++] = stats->rx_bytes; | |
4762 | data[i++] = stats->rx_crc_errors; | |
4763 | data[i++] = stats->rx_dropped; | |
4764 | data[i++] = stats->rx_errors; | |
4765 | data[i++] = stats->rx_fifo_errors; | |
4766 | data[i++] = stats->rx_frame_errors; | |
4767 | data[i++] = stats->rx_length_errors; | |
4768 | data[i++] = stats->rx_over_errors; | |
4769 | data[i++] = stats->rx_packets; | |
4770 | data[i++] = stats->tx_aborted_errors; | |
4771 | data[i++] = stats->tx_bytes; | |
4772 | data[i++] = stats->tx_dropped; | |
4773 | data[i++] = stats->tx_errors; | |
4774 | data[i++] = stats->tx_fifo_errors; | |
4775 | data[i++] = stats->tx_packets; | |
4776 | BUG_ON(i != CAS_NUM_STAT_KEYS); | |
1f26dac3 DM |
4777 | } |
4778 | ||
7282d491 | 4779 | static const struct ethtool_ops cas_ethtool_ops = { |
a232f767 AV |
4780 | .get_drvinfo = cas_get_drvinfo, |
4781 | .get_settings = cas_get_settings, | |
4782 | .set_settings = cas_set_settings, | |
4783 | .nway_reset = cas_nway_reset, | |
4784 | .get_link = cas_get_link, | |
4785 | .get_msglevel = cas_get_msglevel, | |
4786 | .set_msglevel = cas_set_msglevel, | |
4787 | .get_regs_len = cas_get_regs_len, | |
4788 | .get_regs = cas_get_regs, | |
b9f2c044 | 4789 | .get_sset_count = cas_get_sset_count, |
a232f767 AV |
4790 | .get_strings = cas_get_strings, |
4791 | .get_ethtool_stats = cas_get_ethtool_stats, | |
4792 | }; | |
4793 | ||
1f26dac3 DM |
4794 | static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
4795 | { | |
4796 | struct cas *cp = netdev_priv(dev); | |
46d7031e | 4797 | struct mii_ioctl_data *data = if_mii(ifr); |
1f26dac3 DM |
4798 | unsigned long flags; |
4799 | int rc = -EOPNOTSUPP; | |
6aa20a22 | 4800 | |
758df69e | 4801 | /* Hold the PM mutex while doing ioctl's or we may collide |
1f26dac3 DM |
4802 | * with open/close and power management and oops. |
4803 | */ | |
758df69e | 4804 | mutex_lock(&cp->pm_mutex); |
1f26dac3 | 4805 | switch (cmd) { |
1f26dac3 DM |
4806 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ |
4807 | data->phy_id = cp->phy_addr; | |
4808 | /* Fallthrough... */ | |
4809 | ||
4810 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
4811 | spin_lock_irqsave(&cp->lock, flags); | |
4812 | cas_mif_poll(cp, 0); | |
4813 | data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); | |
4814 | cas_mif_poll(cp, 1); | |
4815 | spin_unlock_irqrestore(&cp->lock, flags); | |
4816 | rc = 0; | |
4817 | break; | |
4818 | ||
4819 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
1f26dac3 DM |
4820 | spin_lock_irqsave(&cp->lock, flags); |
4821 | cas_mif_poll(cp, 0); | |
4822 | rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); | |
4823 | cas_mif_poll(cp, 1); | |
4824 | spin_unlock_irqrestore(&cp->lock, flags); | |
4825 | break; | |
4826 | default: | |
4827 | break; | |
4828 | }; | |
4829 | ||
758df69e | 4830 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
4831 | return rc; |
4832 | } | |
4833 | ||
9e1848b6 DM |
4834 | /* When this chip sits underneath an Intel 31154 bridge, it is the |
4835 | * only subordinate device and we can tweak the bridge settings to | |
4836 | * reflect that fact. | |
4837 | */ | |
4838 | static void __devinit cas_program_bridge(struct pci_dev *cas_pdev) | |
4839 | { | |
4840 | struct pci_dev *pdev = cas_pdev->bus->self; | |
4841 | u32 val; | |
4842 | ||
4843 | if (!pdev) | |
4844 | return; | |
4845 | ||
4846 | if (pdev->vendor != 0x8086 || pdev->device != 0x537c) | |
4847 | return; | |
4848 | ||
4849 | /* Clear bit 10 (Bus Parking Control) in the Secondary | |
4850 | * Arbiter Control/Status Register which lives at offset | |
4851 | * 0x41. Using a 32-bit word read/modify/write at 0x40 | |
4852 | * is much simpler so that's how we do this. | |
4853 | */ | |
4854 | pci_read_config_dword(pdev, 0x40, &val); | |
4855 | val &= ~0x00040000; | |
4856 | pci_write_config_dword(pdev, 0x40, val); | |
4857 | ||
4858 | /* Max out the Multi-Transaction Timer settings since | |
4859 | * Cassini is the only device present. | |
4860 | * | |
4861 | * The register is 16-bit and lives at 0x50. When the | |
4862 | * settings are enabled, it extends the GRANT# signal | |
4863 | * for a requestor after a transaction is complete. This | |
4864 | * allows the next request to run without first needing | |
4865 | * to negotiate the GRANT# signal back. | |
4866 | * | |
4867 | * Bits 12:10 define the grant duration: | |
4868 | * | |
4869 | * 1 -- 16 clocks | |
4870 | * 2 -- 32 clocks | |
4871 | * 3 -- 64 clocks | |
4872 | * 4 -- 128 clocks | |
4873 | * 5 -- 256 clocks | |
4874 | * | |
4875 | * All other values are illegal. | |
4876 | * | |
4877 | * Bits 09:00 define which REQ/GNT signal pairs get the | |
4878 | * GRANT# signal treatment. We set them all. | |
4879 | */ | |
4880 | pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff); | |
4881 | ||
4882 | /* The Read Prefecth Policy register is 16-bit and sits at | |
4883 | * offset 0x52. It enables a "smart" pre-fetch policy. We | |
4884 | * enable it and max out all of the settings since only one | |
4885 | * device is sitting underneath and thus bandwidth sharing is | |
4886 | * not an issue. | |
4887 | * | |
4888 | * The register has several 3 bit fields, which indicates a | |
4889 | * multiplier applied to the base amount of prefetching the | |
4890 | * chip would do. These fields are at: | |
4891 | * | |
4892 | * 15:13 --- ReRead Primary Bus | |
4893 | * 12:10 --- FirstRead Primary Bus | |
4894 | * 09:07 --- ReRead Secondary Bus | |
4895 | * 06:04 --- FirstRead Secondary Bus | |
4896 | * | |
4897 | * Bits 03:00 control which REQ/GNT pairs the prefetch settings | |
4898 | * get enabled on. Bit 3 is a grouped enabler which controls | |
4899 | * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control | |
4900 | * the individual REQ/GNT pairs [2:0]. | |
4901 | */ | |
4902 | pci_write_config_word(pdev, 0x52, | |
4903 | (0x7 << 13) | | |
4904 | (0x7 << 10) | | |
4905 | (0x7 << 7) | | |
4906 | (0x7 << 4) | | |
4907 | (0xf << 0)); | |
4908 | ||
4909 | /* Force cacheline size to 0x8 */ | |
4910 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
4911 | ||
4912 | /* Force latency timer to maximum setting so Cassini can | |
4913 | * sit on the bus as long as it likes. | |
4914 | */ | |
4915 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff); | |
4916 | } | |
4917 | ||
83d6f035 SH |
4918 | static const struct net_device_ops cas_netdev_ops = { |
4919 | .ndo_open = cas_open, | |
4920 | .ndo_stop = cas_close, | |
4921 | .ndo_start_xmit = cas_start_xmit, | |
4922 | .ndo_get_stats = cas_get_stats, | |
4923 | .ndo_set_multicast_list = cas_set_multicast, | |
4924 | .ndo_do_ioctl = cas_ioctl, | |
4925 | .ndo_tx_timeout = cas_tx_timeout, | |
4926 | .ndo_change_mtu = cas_change_mtu, | |
4927 | .ndo_set_mac_address = eth_mac_addr, | |
4928 | .ndo_validate_addr = eth_validate_addr, | |
4929 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4930 | .ndo_poll_controller = cas_netpoll, | |
4931 | #endif | |
4932 | }; | |
4933 | ||
1f26dac3 DM |
4934 | static int __devinit cas_init_one(struct pci_dev *pdev, |
4935 | const struct pci_device_id *ent) | |
4936 | { | |
4937 | static int cas_version_printed = 0; | |
18e37f2a | 4938 | unsigned long casreg_len; |
1f26dac3 DM |
4939 | struct net_device *dev; |
4940 | struct cas *cp; | |
4941 | int i, err, pci_using_dac; | |
4942 | u16 pci_cmd; | |
4943 | u8 orig_cacheline_size = 0, cas_cacheline_size = 0; | |
4944 | ||
4945 | if (cas_version_printed++ == 0) | |
436d27d1 | 4946 | pr_info("%s", version); |
1f26dac3 DM |
4947 | |
4948 | err = pci_enable_device(pdev); | |
4949 | if (err) { | |
436d27d1 | 4950 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1f26dac3 DM |
4951 | return err; |
4952 | } | |
4953 | ||
4954 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
9b91cf9d | 4955 | dev_err(&pdev->dev, "Cannot find proper PCI device " |
436d27d1 | 4956 | "base address, aborting\n"); |
1f26dac3 DM |
4957 | err = -ENODEV; |
4958 | goto err_out_disable_pdev; | |
4959 | } | |
4960 | ||
4961 | dev = alloc_etherdev(sizeof(*cp)); | |
4962 | if (!dev) { | |
436d27d1 | 4963 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1f26dac3 DM |
4964 | err = -ENOMEM; |
4965 | goto err_out_disable_pdev; | |
4966 | } | |
1f26dac3 DM |
4967 | SET_NETDEV_DEV(dev, &pdev->dev); |
4968 | ||
4969 | err = pci_request_regions(pdev, dev->name); | |
4970 | if (err) { | |
436d27d1 | 4971 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1f26dac3 DM |
4972 | goto err_out_free_netdev; |
4973 | } | |
4974 | pci_set_master(pdev); | |
4975 | ||
4976 | /* we must always turn on parity response or else parity | |
4977 | * doesn't get generated properly. disable SERR/PERR as well. | |
4978 | * in addition, we want to turn MWI on. | |
4979 | */ | |
4980 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
4981 | pci_cmd &= ~PCI_COMMAND_SERR; | |
4982 | pci_cmd |= PCI_COMMAND_PARITY; | |
4983 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
694625c0 | 4984 | if (pci_try_set_mwi(pdev)) |
436d27d1 | 4985 | pr_warning("Could not enable MWI for %s\n", pci_name(pdev)); |
04efb878 | 4986 | |
9e1848b6 DM |
4987 | cas_program_bridge(pdev); |
4988 | ||
1f26dac3 DM |
4989 | /* |
4990 | * On some architectures, the default cache line size set | |
694625c0 | 4991 | * by pci_try_set_mwi reduces perforamnce. We have to increase |
1f26dac3 DM |
4992 | * it for this case. To start, we'll print some configuration |
4993 | * data. | |
4994 | */ | |
4995 | #if 1 | |
4996 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, | |
4997 | &orig_cacheline_size); | |
4998 | if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) { | |
6aa20a22 JG |
4999 | cas_cacheline_size = |
5000 | (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ? | |
1f26dac3 | 5001 | CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES; |
6aa20a22 JG |
5002 | if (pci_write_config_byte(pdev, |
5003 | PCI_CACHE_LINE_SIZE, | |
1f26dac3 | 5004 | cas_cacheline_size)) { |
9b91cf9d | 5005 | dev_err(&pdev->dev, "Could not set PCI cache " |
1f26dac3 DM |
5006 | "line size\n"); |
5007 | goto err_write_cacheline; | |
5008 | } | |
5009 | } | |
5010 | #endif | |
5011 | ||
5012 | ||
5013 | /* Configure DMA attributes. */ | |
6a35528a | 5014 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
1f26dac3 DM |
5015 | pci_using_dac = 1; |
5016 | err = pci_set_consistent_dma_mask(pdev, | |
6a35528a | 5017 | DMA_BIT_MASK(64)); |
1f26dac3 | 5018 | if (err < 0) { |
9b91cf9d | 5019 | dev_err(&pdev->dev, "Unable to obtain 64-bit DMA " |
1f26dac3 DM |
5020 | "for consistent allocations\n"); |
5021 | goto err_out_free_res; | |
5022 | } | |
5023 | ||
5024 | } else { | |
284901a9 | 5025 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1f26dac3 | 5026 | if (err) { |
9b91cf9d | 5027 | dev_err(&pdev->dev, "No usable DMA configuration, " |
436d27d1 | 5028 | "aborting\n"); |
1f26dac3 DM |
5029 | goto err_out_free_res; |
5030 | } | |
5031 | pci_using_dac = 0; | |
5032 | } | |
5033 | ||
1f26dac3 DM |
5034 | casreg_len = pci_resource_len(pdev, 0); |
5035 | ||
5036 | cp = netdev_priv(dev); | |
5037 | cp->pdev = pdev; | |
5038 | #if 1 | |
5039 | /* A value of 0 indicates we never explicitly set it */ | |
5040 | cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0; | |
5041 | #endif | |
5042 | cp->dev = dev; | |
6aa20a22 | 5043 | cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : |
1f26dac3 DM |
5044 | cassini_debug; |
5045 | ||
5046 | cp->link_transition = LINK_TRANSITION_UNKNOWN; | |
5047 | cp->link_transition_jiffies_valid = 0; | |
5048 | ||
5049 | spin_lock_init(&cp->lock); | |
5050 | spin_lock_init(&cp->rx_inuse_lock); | |
5051 | spin_lock_init(&cp->rx_spare_lock); | |
5052 | for (i = 0; i < N_TX_RINGS; i++) { | |
5053 | spin_lock_init(&cp->stat_lock[i]); | |
5054 | spin_lock_init(&cp->tx_lock[i]); | |
5055 | } | |
5056 | spin_lock_init(&cp->stat_lock[N_TX_RINGS]); | |
758df69e | 5057 | mutex_init(&cp->pm_mutex); |
1f26dac3 DM |
5058 | |
5059 | init_timer(&cp->link_timer); | |
5060 | cp->link_timer.function = cas_link_timer; | |
5061 | cp->link_timer.data = (unsigned long) cp; | |
5062 | ||
5063 | #if 1 | |
5064 | /* Just in case the implementation of atomic operations | |
5065 | * change so that an explicit initialization is necessary. | |
5066 | */ | |
5067 | atomic_set(&cp->reset_task_pending, 0); | |
5068 | atomic_set(&cp->reset_task_pending_all, 0); | |
5069 | atomic_set(&cp->reset_task_pending_spare, 0); | |
5070 | atomic_set(&cp->reset_task_pending_mtu, 0); | |
5071 | #endif | |
c4028958 | 5072 | INIT_WORK(&cp->reset_task, cas_reset_task); |
1f26dac3 DM |
5073 | |
5074 | /* Default link parameters */ | |
bf829370 | 5075 | if (link_mode >= 0 && link_mode < 6) |
1f26dac3 DM |
5076 | cp->link_cntl = link_modes[link_mode]; |
5077 | else | |
5078 | cp->link_cntl = BMCR_ANENABLE; | |
5079 | cp->lstate = link_down; | |
5080 | cp->link_transition = LINK_TRANSITION_LINK_DOWN; | |
5081 | netif_carrier_off(cp->dev); | |
5082 | cp->timer_ticks = 0; | |
5083 | ||
5084 | /* give us access to cassini registers */ | |
18e37f2a | 5085 | cp->regs = pci_iomap(pdev, 0, casreg_len); |
79ea13ce | 5086 | if (!cp->regs) { |
436d27d1 | 5087 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1f26dac3 DM |
5088 | goto err_out_free_res; |
5089 | } | |
5090 | cp->casreg_len = casreg_len; | |
5091 | ||
5092 | pci_save_state(pdev); | |
5093 | cas_check_pci_invariants(cp); | |
5094 | cas_hard_reset(cp); | |
5095 | cas_reset(cp, 0); | |
5096 | if (cas_check_invariants(cp)) | |
5097 | goto err_out_iounmap; | |
fcaa4066 JS |
5098 | if (cp->cas_flags & CAS_FLAG_SATURN) |
5099 | if (cas_saturn_firmware_init(cp)) | |
5100 | goto err_out_iounmap; | |
1f26dac3 DM |
5101 | |
5102 | cp->init_block = (struct cas_init_block *) | |
5103 | pci_alloc_consistent(pdev, sizeof(struct cas_init_block), | |
5104 | &cp->block_dvma); | |
5105 | if (!cp->init_block) { | |
436d27d1 | 5106 | dev_err(&pdev->dev, "Cannot allocate init block, aborting\n"); |
1f26dac3 DM |
5107 | goto err_out_iounmap; |
5108 | } | |
5109 | ||
6aa20a22 | 5110 | for (i = 0; i < N_TX_RINGS; i++) |
1f26dac3 DM |
5111 | cp->init_txds[i] = cp->init_block->txds[i]; |
5112 | ||
6aa20a22 | 5113 | for (i = 0; i < N_RX_DESC_RINGS; i++) |
1f26dac3 DM |
5114 | cp->init_rxds[i] = cp->init_block->rxds[i]; |
5115 | ||
6aa20a22 | 5116 | for (i = 0; i < N_RX_COMP_RINGS; i++) |
1f26dac3 DM |
5117 | cp->init_rxcs[i] = cp->init_block->rxcs[i]; |
5118 | ||
5119 | for (i = 0; i < N_RX_FLOWS; i++) | |
5120 | skb_queue_head_init(&cp->rx_flows[i]); | |
5121 | ||
83d6f035 | 5122 | dev->netdev_ops = &cas_netdev_ops; |
a232f767 | 5123 | dev->ethtool_ops = &cas_ethtool_ops; |
1f26dac3 | 5124 | dev->watchdog_timeo = CAS_TX_TIMEOUT; |
83d6f035 | 5125 | |
1f26dac3 | 5126 | #ifdef USE_NAPI |
bea3348e | 5127 | netif_napi_add(dev, &cp->napi, cas_poll, 64); |
1f26dac3 DM |
5128 | #endif |
5129 | dev->irq = pdev->irq; | |
5130 | dev->dma = 0; | |
5131 | ||
5132 | /* Cassini features. */ | |
5133 | if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0) | |
5134 | dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; | |
5135 | ||
5136 | if (pci_using_dac) | |
5137 | dev->features |= NETIF_F_HIGHDMA; | |
5138 | ||
5139 | if (register_netdev(dev)) { | |
436d27d1 | 5140 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
1f26dac3 DM |
5141 | goto err_out_free_consistent; |
5142 | } | |
5143 | ||
5144 | i = readl(cp->regs + REG_BIM_CFG); | |
436d27d1 JP |
5145 | netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n", |
5146 | (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", | |
5147 | (i & BIM_CFG_32BIT) ? "32" : "64", | |
5148 | (i & BIM_CFG_66MHZ) ? "66" : "33", | |
5149 | (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq, | |
5150 | dev->dev_addr); | |
1f26dac3 DM |
5151 | |
5152 | pci_set_drvdata(pdev, dev); | |
5153 | cp->hw_running = 1; | |
5154 | cas_entropy_reset(cp); | |
5155 | cas_phy_init(cp); | |
5156 | cas_begin_auto_negotiation(cp, NULL); | |
5157 | return 0; | |
5158 | ||
5159 | err_out_free_consistent: | |
5160 | pci_free_consistent(pdev, sizeof(struct cas_init_block), | |
5161 | cp->init_block, cp->block_dvma); | |
5162 | ||
5163 | err_out_iounmap: | |
758df69e | 5164 | mutex_lock(&cp->pm_mutex); |
1f26dac3 DM |
5165 | if (cp->hw_running) |
5166 | cas_shutdown(cp); | |
758df69e | 5167 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 | 5168 | |
18e37f2a | 5169 | pci_iounmap(pdev, cp->regs); |
1f26dac3 DM |
5170 | |
5171 | ||
5172 | err_out_free_res: | |
5173 | pci_release_regions(pdev); | |
5174 | ||
5175 | err_write_cacheline: | |
5176 | /* Try to restore it in case the error occured after we | |
6aa20a22 | 5177 | * set it. |
1f26dac3 DM |
5178 | */ |
5179 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); | |
5180 | ||
5181 | err_out_free_netdev: | |
5182 | free_netdev(dev); | |
5183 | ||
5184 | err_out_disable_pdev: | |
5185 | pci_disable_device(pdev); | |
5186 | pci_set_drvdata(pdev, NULL); | |
5187 | return -ENODEV; | |
5188 | } | |
5189 | ||
5190 | static void __devexit cas_remove_one(struct pci_dev *pdev) | |
5191 | { | |
5192 | struct net_device *dev = pci_get_drvdata(pdev); | |
5193 | struct cas *cp; | |
5194 | if (!dev) | |
5195 | return; | |
5196 | ||
5197 | cp = netdev_priv(dev); | |
5198 | unregister_netdev(dev); | |
5199 | ||
fcaa4066 JS |
5200 | if (cp->fw_data) |
5201 | vfree(cp->fw_data); | |
5202 | ||
758df69e | 5203 | mutex_lock(&cp->pm_mutex); |
1f26dac3 DM |
5204 | flush_scheduled_work(); |
5205 | if (cp->hw_running) | |
5206 | cas_shutdown(cp); | |
758df69e | 5207 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
5208 | |
5209 | #if 1 | |
5210 | if (cp->orig_cacheline_size) { | |
5211 | /* Restore the cache line size if we had modified | |
5212 | * it. | |
5213 | */ | |
6aa20a22 | 5214 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, |
1f26dac3 DM |
5215 | cp->orig_cacheline_size); |
5216 | } | |
5217 | #endif | |
5218 | pci_free_consistent(pdev, sizeof(struct cas_init_block), | |
5219 | cp->init_block, cp->block_dvma); | |
18e37f2a | 5220 | pci_iounmap(pdev, cp->regs); |
1f26dac3 DM |
5221 | free_netdev(dev); |
5222 | pci_release_regions(pdev); | |
5223 | pci_disable_device(pdev); | |
5224 | pci_set_drvdata(pdev, NULL); | |
5225 | } | |
5226 | ||
5227 | #ifdef CONFIG_PM | |
46d7031e | 5228 | static int cas_suspend(struct pci_dev *pdev, pm_message_t state) |
1f26dac3 DM |
5229 | { |
5230 | struct net_device *dev = pci_get_drvdata(pdev); | |
5231 | struct cas *cp = netdev_priv(dev); | |
5232 | unsigned long flags; | |
5233 | ||
758df69e | 5234 | mutex_lock(&cp->pm_mutex); |
6aa20a22 | 5235 | |
1f26dac3 DM |
5236 | /* If the driver is opened, we stop the DMA */ |
5237 | if (cp->opened) { | |
5238 | netif_device_detach(dev); | |
5239 | ||
5240 | cas_lock_all_save(cp, flags); | |
5241 | ||
5242 | /* We can set the second arg of cas_reset to 0 | |
5243 | * because on resume, we'll call cas_init_hw with | |
5244 | * its second arg set so that autonegotiation is | |
5245 | * restarted. | |
5246 | */ | |
5247 | cas_reset(cp, 0); | |
5248 | cas_clean_rings(cp); | |
5249 | cas_unlock_all_restore(cp, flags); | |
5250 | } | |
5251 | ||
5252 | if (cp->hw_running) | |
5253 | cas_shutdown(cp); | |
758df69e | 5254 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
5255 | |
5256 | return 0; | |
5257 | } | |
5258 | ||
5259 | static int cas_resume(struct pci_dev *pdev) | |
5260 | { | |
5261 | struct net_device *dev = pci_get_drvdata(pdev); | |
5262 | struct cas *cp = netdev_priv(dev); | |
5263 | ||
436d27d1 | 5264 | netdev_info(dev, "resuming\n"); |
1f26dac3 | 5265 | |
758df69e | 5266 | mutex_lock(&cp->pm_mutex); |
1f26dac3 DM |
5267 | cas_hard_reset(cp); |
5268 | if (cp->opened) { | |
5269 | unsigned long flags; | |
5270 | cas_lock_all_save(cp, flags); | |
5271 | cas_reset(cp, 0); | |
5272 | cp->hw_running = 1; | |
5273 | cas_clean_rings(cp); | |
5274 | cas_init_hw(cp, 1); | |
5275 | cas_unlock_all_restore(cp, flags); | |
5276 | ||
5277 | netif_device_attach(dev); | |
5278 | } | |
758df69e | 5279 | mutex_unlock(&cp->pm_mutex); |
1f26dac3 DM |
5280 | return 0; |
5281 | } | |
5282 | #endif /* CONFIG_PM */ | |
5283 | ||
5284 | static struct pci_driver cas_driver = { | |
5285 | .name = DRV_MODULE_NAME, | |
5286 | .id_table = cas_pci_tbl, | |
5287 | .probe = cas_init_one, | |
5288 | .remove = __devexit_p(cas_remove_one), | |
5289 | #ifdef CONFIG_PM | |
5290 | .suspend = cas_suspend, | |
5291 | .resume = cas_resume | |
5292 | #endif | |
5293 | }; | |
5294 | ||
5295 | static int __init cas_init(void) | |
5296 | { | |
5297 | if (linkdown_timeout > 0) | |
5298 | link_transition_timeout = linkdown_timeout * HZ; | |
5299 | else | |
5300 | link_transition_timeout = 0; | |
5301 | ||
29917620 | 5302 | return pci_register_driver(&cas_driver); |
1f26dac3 DM |
5303 | } |
5304 | ||
5305 | static void __exit cas_cleanup(void) | |
5306 | { | |
5307 | pci_unregister_driver(&cas_driver); | |
5308 | } | |
5309 | ||
5310 | module_init(cas_init); | |
5311 | module_exit(cas_cleanup); |