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can: xilinx_can: fix recovery from error states not being propagated
[linux-block.git] / drivers / net / can / xilinx_can.c
CommitLineData
b1201e44
KA		 1/* Xilinx CAN device driver
2 *
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
877e0b75 5 * Copyright (C) 2017 Sandvik Mining and Construction Oy
b1201e44
KA		 6 *
7 * Description:
8 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/clk.h>
21#include <linux/errno.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/netdevice.h>
28#include <linux/of.h>
29#include <linux/platform_device.h>
30#include <linux/skbuff.h>
31#include <linux/string.h>
32#include <linux/types.h>
33#include <linux/can/dev.h>
34#include <linux/can/error.h>
35#include <linux/can/led.h>
4716620d 36#include <linux/pm_runtime.h>
b1201e44
KA		 37
38#define DRIVER_NAME "xilinx_can"
39
40/* CAN registers set */
41enum xcan_reg {
42 XCAN_SRR_OFFSET = 0x00, /* Software reset */
43 XCAN_MSR_OFFSET = 0x04, /* Mode select */
44 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
45 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
46 XCAN_ECR_OFFSET = 0x10, /* Error counter */
47 XCAN_ESR_OFFSET = 0x14, /* Error status */
48 XCAN_SR_OFFSET = 0x18, /* Status */
49 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
50 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
51 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
52 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
53 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
54 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
55 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
56 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
57 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
58 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
59 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
60};
61
62/* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
63#define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
64#define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
65#define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
66#define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
67#define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
68#define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
69#define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
70#define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
71#define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
72#define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
73#define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
74#define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
75#define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
76#define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
77#define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
78#define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
79#define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
80#define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
81#define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
82#define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
83#define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
84#define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
85#define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
86#define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
87#define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
88#define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
89#define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
90#define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
91#define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
92#define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
93#define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
94#define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
95#define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
96#define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
97#define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
98#define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
99#define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
100#define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
101
102#define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
103 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
104 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
32852c56 105 XCAN_IXR_ARBLST_MASK)
b1201e44
KA		 106
107/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
108#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
109#define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
110#define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
111#define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
112#define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
113#define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
114
115/* CAN frame length constants */
116#define XCAN_FRAME_MAX_DATA_LEN 8
117#define XCAN_TIMEOUT (1 * HZ)
118
119/**
120 * struct xcan_priv - This definition define CAN driver instance
121 * @can: CAN private data structure.
122 * @tx_head: Tx CAN packets ready to send on the queue
123 * @tx_tail: Tx CAN packets successfully sended on the queue
124 * @tx_max: Maximum number packets the driver can send
125 * @napi: NAPI structure
126 * @read_reg: For reading data from CAN registers
127 * @write_reg: For writing data to CAN registers
128 * @dev: Network device data structure
129 * @reg_base: Ioremapped address to registers
130 * @irq_flags: For request_irq()
131 * @bus_clk: Pointer to struct clk
132 * @can_clk: Pointer to struct clk
133 */
134struct xcan_priv {
135 struct can_priv can;
136 unsigned int tx_head;
137 unsigned int tx_tail;
138 unsigned int tx_max;
139 struct napi_struct napi;
140 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
141 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
142 u32 val);
4716620d 143 struct device *dev;
b1201e44
KA		 144 void __iomem *reg_base;
145 unsigned long irq_flags;
146 struct clk *bus_clk;
147 struct clk *can_clk;
148};
149
150/* CAN Bittiming constants as per Xilinx CAN specs */
151static const struct can_bittiming_const xcan_bittiming_const = {
152 .name = DRIVER_NAME,
153 .tseg1_min = 1,
154 .tseg1_max = 16,
155 .tseg2_min = 1,
156 .tseg2_max = 8,
157 .sjw_max = 4,
158 .brp_min = 1,
159 .brp_max = 256,
160 .brp_inc = 1,
161};
162
163/**
164 * xcan_write_reg_le - Write a value to the device register little endian
165 * @priv: Driver private data structure
166 * @reg: Register offset
167 * @val: Value to write at the Register offset
168 *
169 * Write data to the paricular CAN register
170 */
171static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
172 u32 val)
173{
174 iowrite32(val, priv->reg_base + reg);
175}
176
177/**
178 * xcan_read_reg_le - Read a value from the device register little endian
179 * @priv: Driver private data structure
180 * @reg: Register offset
181 *
182 * Read data from the particular CAN register
183 * Return: value read from the CAN register
184 */
185static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
186{
187 return ioread32(priv->reg_base + reg);
188}
189
190/**
191 * xcan_write_reg_be - Write a value to the device register big endian
192 * @priv: Driver private data structure
193 * @reg: Register offset
194 * @val: Value to write at the Register offset
195 *
196 * Write data to the paricular CAN register
197 */
198static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
199 u32 val)
200{
201 iowrite32be(val, priv->reg_base + reg);
202}
203
204/**
205 * xcan_read_reg_be - Read a value from the device register big endian
206 * @priv: Driver private data structure
207 * @reg: Register offset
208 *
209 * Read data from the particular CAN register
210 * Return: value read from the CAN register
211 */
212static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
213{
214 return ioread32be(priv->reg_base + reg);
215}
216
217/**
218 * set_reset_mode - Resets the CAN device mode
219 * @ndev: Pointer to net_device structure
220 *
221 * This is the driver reset mode routine.The driver
222 * enters into configuration mode.
223 *
224 * Return: 0 on success and failure value on error
225 */
226static int set_reset_mode(struct net_device *ndev)
227{
228 struct xcan_priv *priv = netdev_priv(ndev);
229 unsigned long timeout;
230
231 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
232
233 timeout = jiffies + XCAN_TIMEOUT;
234 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
235 if (time_after(jiffies, timeout)) {
236 netdev_warn(ndev, "timed out for config mode\n");
237 return -ETIMEDOUT;
238 }
239 usleep_range(500, 10000);
240 }
241
242 return 0;
243}
244
245/**
246 * xcan_set_bittiming - CAN set bit timing routine
247 * @ndev: Pointer to net_device structure
248 *
249 * This is the driver set bittiming routine.
250 * Return: 0 on success and failure value on error
251 */
252static int xcan_set_bittiming(struct net_device *ndev)
253{
254 struct xcan_priv *priv = netdev_priv(ndev);
255 struct can_bittiming *bt = &priv->can.bittiming;
256 u32 btr0, btr1;
257 u32 is_config_mode;
258
259 /* Check whether Xilinx CAN is in configuration mode.
260 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
261 */
262 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
263 XCAN_SR_CONFIG_MASK;
264 if (!is_config_mode) {
265 netdev_alert(ndev,
266 "BUG! Cannot set bittiming - CAN is not in config mode\n");
267 return -EPERM;
268 }
269
270 /* Setting Baud Rate prescalar value in BRPR Register */
271 btr0 = (bt->brp - 1);
272
273 /* Setting Time Segment 1 in BTR Register */
274 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
275
276 /* Setting Time Segment 2 in BTR Register */
277 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
278
279 /* Setting Synchronous jump width in BTR Register */
280 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
281
282 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
283 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
284
285 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
286 priv->read_reg(priv, XCAN_BRPR_OFFSET),
287 priv->read_reg(priv, XCAN_BTR_OFFSET));
288
289 return 0;
290}
291
292/**
293 * xcan_chip_start - This the drivers start routine
294 * @ndev: Pointer to net_device structure
295 *
296 * This is the drivers start routine.
297 * Based on the State of the CAN device it puts
298 * the CAN device into a proper mode.
299 *
300 * Return: 0 on success and failure value on error
301 */
302static int xcan_chip_start(struct net_device *ndev)
303{
304 struct xcan_priv *priv = netdev_priv(ndev);
fb3ec7ba
SM		 305 u32 reg_msr, reg_sr_mask;
306 int err;
b1201e44
KA		 307 unsigned long timeout;
308
309 /* Check if it is in reset mode */
310 err = set_reset_mode(ndev);
311 if (err < 0)
312 return err;
313
314 err = xcan_set_bittiming(ndev);
315 if (err < 0)
316 return err;
317
318 /* Enable interrupts */
319 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
320
321 /* Check whether it is loopback mode or normal mode */
322 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
323 reg_msr = XCAN_MSR_LBACK_MASK;
324 reg_sr_mask = XCAN_SR_LBACK_MASK;
325 } else {
326 reg_msr = 0x0;
327 reg_sr_mask = XCAN_SR_NORMAL_MASK;
328 }
329
330 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
331 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
332
333 timeout = jiffies + XCAN_TIMEOUT;
334 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
335 if (time_after(jiffies, timeout)) {
336 netdev_warn(ndev,
337 "timed out for correct mode\n");
338 return -ETIMEDOUT;
339 }
340 }
341 netdev_dbg(ndev, "status:#x%08x\n",
342 priv->read_reg(priv, XCAN_SR_OFFSET));
343
344 priv->can.state = CAN_STATE_ERROR_ACTIVE;
345 return 0;
346}
347
348/**
349 * xcan_do_set_mode - This sets the mode of the driver
350 * @ndev: Pointer to net_device structure
351 * @mode: Tells the mode of the driver
352 *
353 * This check the drivers state and calls the
354 * the corresponding modes to set.
355 *
356 * Return: 0 on success and failure value on error
357 */
358static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
359{
360 int ret;
361
362 switch (mode) {
363 case CAN_MODE_START:
364 ret = xcan_chip_start(ndev);
365 if (ret < 0) {
366 netdev_err(ndev, "xcan_chip_start failed!\n");
367 return ret;
368 }
369 netif_wake_queue(ndev);
370 break;
371 default:
372 ret = -EOPNOTSUPP;
373 break;
374 }
375
376 return ret;
377}
378
379/**
380 * xcan_start_xmit - Starts the transmission
381 * @skb: sk_buff pointer that contains data to be Txed
382 * @ndev: Pointer to net_device structure
383 *
384 * This function is invoked from upper layers to initiate transmission. This
385 * function uses the next available free txbuff and populates their fields to
386 * start the transmission.
387 *
388 * Return: 0 on success and failure value on error
389 */
390static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
391{
392 struct xcan_priv *priv = netdev_priv(ndev);
393 struct net_device_stats *stats = &ndev->stats;
394 struct can_frame *cf = (struct can_frame *)skb->data;
395 u32 id, dlc, data[2] = {0, 0};
396
397 if (can_dropped_invalid_skb(ndev, skb))
398 return NETDEV_TX_OK;
399
400 /* Check if the TX buffer is full */
401 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
402 XCAN_SR_TXFLL_MASK)) {
403 netif_stop_queue(ndev);
404 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
405 return NETDEV_TX_BUSY;
406 }
407
408 /* Watch carefully on the bit sequence */
409 if (cf->can_id & CAN_EFF_FLAG) {
410 /* Extended CAN ID format */
411 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
412 XCAN_IDR_ID2_MASK;
413 id |= (((cf->can_id & CAN_EFF_MASK) >>
414 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
415 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
416
417 /* The substibute remote TX request bit should be "1"
418 * for extended frames as in the Xilinx CAN datasheet
419 */
420 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
421
422 if (cf->can_id & CAN_RTR_FLAG)
423 /* Extended frames remote TX request */
424 id |= XCAN_IDR_RTR_MASK;
425 } else {
426 /* Standard CAN ID format */
427 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
428 XCAN_IDR_ID1_MASK;
429
430 if (cf->can_id & CAN_RTR_FLAG)
431 /* Standard frames remote TX request */
432 id |= XCAN_IDR_SRR_MASK;
433 }
434
435 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
436
437 if (cf->can_dlc > 0)
438 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
439 if (cf->can_dlc > 4)
440 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
441
442 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
443 priv->tx_head++;
444
445 /* Write the Frame to Xilinx CAN TX FIFO */
446 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
447 /* If the CAN frame is RTR frame this write triggers tranmission */
448 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
449 if (!(cf->can_id & CAN_RTR_FLAG)) {
450 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
451 /* If the CAN frame is Standard/Extended frame this
452 * write triggers tranmission
453 */
454 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
455 stats->tx_bytes += cf->can_dlc;
456 }
457
458 /* Check if the TX buffer is full */
459 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
460 netif_stop_queue(ndev);
461
462 return NETDEV_TX_OK;
463}
464
465/**
466 * xcan_rx - Is called from CAN isr to complete the received
467 * frame processing
468 * @ndev: Pointer to net_device structure
469 *
470 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
471 * does minimal processing and invokes "netif_receive_skb" to complete further
472 * processing.
473 * Return: 1 on success and 0 on failure.
474 */
475static int xcan_rx(struct net_device *ndev)
476{
477 struct xcan_priv *priv = netdev_priv(ndev);
478 struct net_device_stats *stats = &ndev->stats;
479 struct can_frame *cf;
480 struct sk_buff *skb;
481 u32 id_xcan, dlc, data[2] = {0, 0};
482
483 skb = alloc_can_skb(ndev, &cf);
484 if (unlikely(!skb)) {
485 stats->rx_dropped++;
486 return 0;
487 }
488
489 /* Read a frame from Xilinx zynq CANPS */
490 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
491 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
492 XCAN_DLCR_DLC_SHIFT;
493
494 /* Change Xilinx CAN data length format to socketCAN data format */
495 cf->can_dlc = get_can_dlc(dlc);
496
497 /* Change Xilinx CAN ID format to socketCAN ID format */
498 if (id_xcan & XCAN_IDR_IDE_MASK) {
499 /* The received frame is an Extended format frame */
500 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
501 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
502 XCAN_IDR_ID2_SHIFT;
503 cf->can_id |= CAN_EFF_FLAG;
504 if (id_xcan & XCAN_IDR_RTR_MASK)
505 cf->can_id |= CAN_RTR_FLAG;
506 } else {
507 /* The received frame is a standard format frame */
508 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
509 XCAN_IDR_ID1_SHIFT;
510 if (id_xcan & XCAN_IDR_SRR_MASK)
511 cf->can_id |= CAN_RTR_FLAG;
512 }
513
5793affe
JLP		 514 /* DW1/DW2 must always be read to remove message from RXFIFO */
515 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
516 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
b1201e44 517
5793affe 518 if (!(cf->can_id & CAN_RTR_FLAG)) {
b1201e44
KA		 519 /* Change Xilinx CAN data format to socketCAN data format */
520 if (cf->can_dlc > 0)
521 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
522 if (cf->can_dlc > 4)
523 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
524 }
525
526 stats->rx_bytes += cf->can_dlc;
527 stats->rx_packets++;
528 netif_receive_skb(skb);
529
530 return 1;
531}
532
877e0b75
AH		 533/**
534 * xcan_current_error_state - Get current error state from HW
535 * @ndev: Pointer to net_device structure
536 *
537 * Checks the current CAN error state from the HW. Note that this
538 * only checks for ERROR_PASSIVE and ERROR_WARNING.
539 *
540 * Return:
541 * ERROR_PASSIVE or ERROR_WARNING if either is active, ERROR_ACTIVE
542 * otherwise.
543 */
544static enum can_state xcan_current_error_state(struct net_device *ndev)
545{
546 struct xcan_priv *priv = netdev_priv(ndev);
547 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET);
548
549 if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK)
550 return CAN_STATE_ERROR_PASSIVE;
551 else if (status & XCAN_SR_ERRWRN_MASK)
552 return CAN_STATE_ERROR_WARNING;
553 else
554 return CAN_STATE_ERROR_ACTIVE;
555}
556
557/**
558 * xcan_set_error_state - Set new CAN error state
559 * @ndev: Pointer to net_device structure
560 * @new_state: The new CAN state to be set
561 * @cf: Error frame to be populated or NULL
562 *
563 * Set new CAN error state for the device, updating statistics and
564 * populating the error frame if given.
565 */
566static void xcan_set_error_state(struct net_device *ndev,
567 enum can_state new_state,
568 struct can_frame *cf)
569{
570 struct xcan_priv *priv = netdev_priv(ndev);
571 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET);
572 u32 txerr = ecr & XCAN_ECR_TEC_MASK;
573 u32 rxerr = (ecr & XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT;
574
575 priv->can.state = new_state;
576
577 if (cf) {
578 cf->can_id |= CAN_ERR_CRTL;
579 cf->data[6] = txerr;
580 cf->data[7] = rxerr;
581 }
582
583 switch (new_state) {
584 case CAN_STATE_ERROR_PASSIVE:
585 priv->can.can_stats.error_passive++;
586 if (cf)
587 cf->data[1] = (rxerr > 127) ?
588 CAN_ERR_CRTL_RX_PASSIVE :
589 CAN_ERR_CRTL_TX_PASSIVE;
590 break;
591 case CAN_STATE_ERROR_WARNING:
592 priv->can.can_stats.error_warning++;
593 if (cf)
594 cf->data[1] |= (txerr > rxerr) ?
595 CAN_ERR_CRTL_TX_WARNING :
596 CAN_ERR_CRTL_RX_WARNING;
597 break;
598 case CAN_STATE_ERROR_ACTIVE:
599 if (cf)
600 cf->data[1] |= CAN_ERR_CRTL_ACTIVE;
601 break;
602 default:
603 /* non-ERROR states are handled elsewhere */
604 WARN_ON(1);
605 break;
606 }
607}
608
609/**
610 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
611 * @ndev: Pointer to net_device structure
612 *
613 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
614 * the performed RX/TX has caused it to drop to a lesser state and set
615 * the interface state accordingly.
616 */
617static void xcan_update_error_state_after_rxtx(struct net_device *ndev)
618{
619 struct xcan_priv *priv = netdev_priv(ndev);
620 enum can_state old_state = priv->can.state;
621 enum can_state new_state;
622
623 /* changing error state due to successful frame RX/TX can only
624 * occur from these states
625 */
626 if (old_state != CAN_STATE_ERROR_WARNING &&
627 old_state != CAN_STATE_ERROR_PASSIVE)
628 return;
629
630 new_state = xcan_current_error_state(ndev);
631
632 if (new_state != old_state) {
633 struct sk_buff *skb;
634 struct can_frame *cf;
635
636 skb = alloc_can_err_skb(ndev, &cf);
637
638 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
639
640 if (skb) {
641 struct net_device_stats *stats = &ndev->stats;
642
643 stats->rx_packets++;
644 stats->rx_bytes += cf->can_dlc;
645 netif_rx(skb);
646 }
647 }
648}
649
b1201e44
KA		 650/**
651 * xcan_err_interrupt - error frame Isr
652 * @ndev: net_device pointer
653 * @isr: interrupt status register value
654 *
655 * This is the CAN error interrupt and it will
656 * check the the type of error and forward the error
657 * frame to upper layers.
658 */
659static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
660{
661 struct xcan_priv *priv = netdev_priv(ndev);
662 struct net_device_stats *stats = &ndev->stats;
663 struct can_frame *cf;
664 struct sk_buff *skb;
877e0b75 665 u32 err_status;
b1201e44
KA		 666
667 skb = alloc_can_err_skb(ndev, &cf);
668
669 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
670 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
b1201e44
KA		 671
672 if (isr & XCAN_IXR_BSOFF_MASK) {
673 priv->can.state = CAN_STATE_BUS_OFF;
674 priv->can.can_stats.bus_off++;
675 /* Leave device in Config Mode in bus-off state */
676 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
677 can_bus_off(ndev);
678 if (skb)
679 cf->can_id |= CAN_ERR_BUSOFF;
877e0b75
AH		 680 } else {
681 enum can_state new_state = xcan_current_error_state(ndev);
682
683 xcan_set_error_state(ndev, new_state, skb ? cf : NULL);
b1201e44
KA		 684 }
685
686 /* Check for Arbitration lost interrupt */
687 if (isr & XCAN_IXR_ARBLST_MASK) {
688 priv->can.can_stats.arbitration_lost++;
689 if (skb) {
690 cf->can_id |= CAN_ERR_LOSTARB;
691 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
692 }
693 }
694
695 /* Check for RX FIFO Overflow interrupt */
696 if (isr & XCAN_IXR_RXOFLW_MASK) {
697 stats->rx_over_errors++;
698 stats->rx_errors++;
b1201e44
KA		 699 if (skb) {
700 cf->can_id |= CAN_ERR_CRTL;
701 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
702 }
703 }
704
705 /* Check for error interrupt */
706 if (isr & XCAN_IXR_ERROR_MASK) {
a2ec19f8 707 if (skb)
b1201e44 708 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
b1201e44
KA		 709
710 /* Check for Ack error interrupt */
711 if (err_status & XCAN_ESR_ACKER_MASK) {
712 stats->tx_errors++;
713 if (skb) {
714 cf->can_id |= CAN_ERR_ACK;
ffd461f8 715 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
b1201e44
KA		 716 }
717 }
718
719 /* Check for Bit error interrupt */
720 if (err_status & XCAN_ESR_BERR_MASK) {
721 stats->tx_errors++;
722 if (skb) {
723 cf->can_id |= CAN_ERR_PROT;
724 cf->data[2] = CAN_ERR_PROT_BIT;
725 }
726 }
727
728 /* Check for Stuff error interrupt */
729 if (err_status & XCAN_ESR_STER_MASK) {
730 stats->rx_errors++;
731 if (skb) {
732 cf->can_id |= CAN_ERR_PROT;
733 cf->data[2] = CAN_ERR_PROT_STUFF;
734 }
735 }
736
737 /* Check for Form error interrupt */
738 if (err_status & XCAN_ESR_FMER_MASK) {
739 stats->rx_errors++;
740 if (skb) {
741 cf->can_id |= CAN_ERR_PROT;
742 cf->data[2] = CAN_ERR_PROT_FORM;
743 }
744 }
745
746 /* Check for CRC error interrupt */
747 if (err_status & XCAN_ESR_CRCER_MASK) {
748 stats->rx_errors++;
749 if (skb) {
750 cf->can_id |= CAN_ERR_PROT;
ffd461f8 751 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
b1201e44
KA		 752 }
753 }
754 priv->can.can_stats.bus_error++;
755 }
756
757 if (skb) {
758 stats->rx_packets++;
759 stats->rx_bytes += cf->can_dlc;
760 netif_rx(skb);
761 }
762
763 netdev_dbg(ndev, "%s: error status register:0x%x\n",
764 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
765}
766
767/**
768 * xcan_state_interrupt - It will check the state of the CAN device
769 * @ndev: net_device pointer
770 * @isr: interrupt status register value
771 *
772 * This will checks the state of the CAN device
773 * and puts the device into appropriate state.
774 */
775static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
776{
777 struct xcan_priv *priv = netdev_priv(ndev);
778
779 /* Check for Sleep interrupt if set put CAN device in sleep state */
780 if (isr & XCAN_IXR_SLP_MASK)
781 priv->can.state = CAN_STATE_SLEEPING;
782
783 /* Check for Wake up interrupt if set put CAN device in Active state */
784 if (isr & XCAN_IXR_WKUP_MASK)
785 priv->can.state = CAN_STATE_ERROR_ACTIVE;
786}
787
788/**
789 * xcan_rx_poll - Poll routine for rx packets (NAPI)
790 * @napi: napi structure pointer
791 * @quota: Max number of rx packets to be processed.
792 *
793 * This is the poll routine for rx part.
794 * It will process the packets maximux quota value.
795 *
796 * Return: number of packets received
797 */
798static int xcan_rx_poll(struct napi_struct *napi, int quota)
799{
800 struct net_device *ndev = napi->dev;
801 struct xcan_priv *priv = netdev_priv(ndev);
802 u32 isr, ier;
803 int work_done = 0;
804
805 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
806 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
32852c56 807 work_done += xcan_rx(ndev);
b1201e44
KA		 808 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
809 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
810 }
811
877e0b75 812 if (work_done) {
b1201e44 813 can_led_event(ndev, CAN_LED_EVENT_RX);
877e0b75
AH		 814 xcan_update_error_state_after_rxtx(ndev);
815 }
b1201e44
KA		 816
817 if (work_done < quota) {
6ad20165 818 napi_complete_done(napi, work_done);
b1201e44 819 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
32852c56 820 ier |= XCAN_IXR_RXNEMP_MASK;
b1201e44
KA		 821 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
822 }
823 return work_done;
824}
825
826/**
827 * xcan_tx_interrupt - Tx Done Isr
828 * @ndev: net_device pointer
829 * @isr: Interrupt status register value
830 */
831static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
832{
833 struct xcan_priv *priv = netdev_priv(ndev);
834 struct net_device_stats *stats = &ndev->stats;
835
836 while ((priv->tx_head - priv->tx_tail > 0) &&
837 (isr & XCAN_IXR_TXOK_MASK)) {
838 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
839 can_get_echo_skb(ndev, priv->tx_tail %
840 priv->tx_max);
841 priv->tx_tail++;
842 stats->tx_packets++;
843 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
844 }
845 can_led_event(ndev, CAN_LED_EVENT_TX);
877e0b75 846 xcan_update_error_state_after_rxtx(ndev);
b1201e44
KA		 847 netif_wake_queue(ndev);
848}
849
850/**
851 * xcan_interrupt - CAN Isr
852 * @irq: irq number
853 * @dev_id: device id poniter
854 *
855 * This is the xilinx CAN Isr. It checks for the type of interrupt
856 * and invokes the corresponding ISR.
857 *
858 * Return:
859 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
860 */
861static irqreturn_t xcan_interrupt(int irq, void *dev_id)
862{
863 struct net_device *ndev = (struct net_device *)dev_id;
864 struct xcan_priv *priv = netdev_priv(ndev);
865 u32 isr, ier;
866
867 /* Get the interrupt status from Xilinx CAN */
868 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
869 if (!isr)
870 return IRQ_NONE;
871
872 /* Check for the type of interrupt and Processing it */
873 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
874 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
875 XCAN_IXR_WKUP_MASK));
876 xcan_state_interrupt(ndev, isr);
877 }
878
879 /* Check for Tx interrupt and Processing it */
880 if (isr & XCAN_IXR_TXOK_MASK)
881 xcan_tx_interrupt(ndev, isr);
882
883 /* Check for the type of error interrupt and Processing it */
884 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
885 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
886 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
887 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
888 XCAN_IXR_ARBLST_MASK));
889 xcan_err_interrupt(ndev, isr);
890 }
891
892 /* Check for the type of receive interrupt and Processing it */
32852c56 893 if (isr & XCAN_IXR_RXNEMP_MASK) {
b1201e44 894 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
32852c56 895 ier &= ~XCAN_IXR_RXNEMP_MASK;
b1201e44
KA		 896 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
897 napi_schedule(&priv->napi);
898 }
899 return IRQ_HANDLED;
900}
901
902/**
903 * xcan_chip_stop - Driver stop routine
904 * @ndev: Pointer to net_device structure
905 *
906 * This is the drivers stop routine. It will disable the
907 * interrupts and put the device into configuration mode.
908 */
909static void xcan_chip_stop(struct net_device *ndev)
910{
911 struct xcan_priv *priv = netdev_priv(ndev);
912 u32 ier;
913
914 /* Disable interrupts and leave the can in configuration mode */
915 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
916 ier &= ~XCAN_INTR_ALL;
917 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
918 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
919 priv->can.state = CAN_STATE_STOPPED;
920}
921
922/**
923 * xcan_open - Driver open routine
924 * @ndev: Pointer to net_device structure
925 *
926 * This is the driver open routine.
927 * Return: 0 on success and failure value on error
928 */
929static int xcan_open(struct net_device *ndev)
930{
931 struct xcan_priv *priv = netdev_priv(ndev);
932 int ret;
933
4716620d
KA		 934 ret = pm_runtime_get_sync(priv->dev);
935 if (ret < 0) {
936 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
937 __func__, ret);
938 return ret;
939 }
940
b1201e44
KA		 941 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
942 ndev->name, ndev);
943 if (ret < 0) {
944 netdev_err(ndev, "irq allocation for CAN failed\n");
945 goto err;
946 }
947
b1201e44
KA		 948 /* Set chip into reset mode */
949 ret = set_reset_mode(ndev);
950 if (ret < 0) {
951 netdev_err(ndev, "mode resetting failed!\n");
4716620d 952 goto err_irq;
b1201e44
KA		 953 }
954
955 /* Common open */
956 ret = open_candev(ndev);
957 if (ret)
4716620d 958 goto err_irq;
b1201e44
KA		 959
960 ret = xcan_chip_start(ndev);
961 if (ret < 0) {
962 netdev_err(ndev, "xcan_chip_start failed!\n");
963 goto err_candev;
964 }
965
966 can_led_event(ndev, CAN_LED_EVENT_OPEN);
967 napi_enable(&priv->napi);
968 netif_start_queue(ndev);
969
970 return 0;
971
972err_candev:
973 close_candev(ndev);
b1201e44
KA		 974err_irq:
975 free_irq(ndev->irq, ndev);
976err:
4716620d
KA		 977 pm_runtime_put(priv->dev);
978
b1201e44
KA		 979 return ret;
980}
981
982/**
983 * xcan_close - Driver close routine
984 * @ndev: Pointer to net_device structure
985 *
986 * Return: 0 always
987 */
988static int xcan_close(struct net_device *ndev)
989{
990 struct xcan_priv *priv = netdev_priv(ndev);
991
992 netif_stop_queue(ndev);
993 napi_disable(&priv->napi);
994 xcan_chip_stop(ndev);
b1201e44
KA		 995 free_irq(ndev->irq, ndev);
996 close_candev(ndev);
997
998 can_led_event(ndev, CAN_LED_EVENT_STOP);
4716620d 999 pm_runtime_put(priv->dev);
b1201e44
KA		 1000
1001 return 0;
1002}
1003
1004/**
1005 * xcan_get_berr_counter - error counter routine
1006 * @ndev: Pointer to net_device structure
1007 * @bec: Pointer to can_berr_counter structure
1008 *
1009 * This is the driver error counter routine.
1010 * Return: 0 on success and failure value on error
1011 */
1012static int xcan_get_berr_counter(const struct net_device *ndev,
1013 struct can_berr_counter *bec)
1014{
1015 struct xcan_priv *priv = netdev_priv(ndev);
1016 int ret;
1017
4716620d
KA		 1018 ret = pm_runtime_get_sync(priv->dev);
1019 if (ret < 0) {
1020 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1021 __func__, ret);
1022 return ret;
1023 }
b1201e44
KA		 1024
1025 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
1026 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
1027 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
1028
4716620d 1029 pm_runtime_put(priv->dev);
b1201e44
KA		 1030
1031 return 0;
b1201e44
KA		 1032}
1033
1034
1035static const struct net_device_ops xcan_netdev_ops = {
1036 .ndo_open = xcan_open,
1037 .ndo_stop = xcan_close,
1038 .ndo_start_xmit = xcan_start_xmit,
92593a03 1039 .ndo_change_mtu = can_change_mtu,
b1201e44
KA		 1040};
1041
1042/**
1043 * xcan_suspend - Suspend method for the driver
4716620d 1044 * @dev: Address of the device structure
b1201e44
KA		 1045 *
1046 * Put the driver into low power mode.
4716620d 1047 * Return: 0 on success and failure value on error
b1201e44
KA		 1048 */
1049static int __maybe_unused xcan_suspend(struct device *dev)
1050{
4716620d
KA		 1051 if (!device_may_wakeup(dev))
1052 return pm_runtime_force_suspend(dev);
1053
1054 return 0;
1055}
1056
1057/**
1058 * xcan_resume - Resume from suspend
1059 * @dev: Address of the device structure
1060 *
1061 * Resume operation after suspend.
1062 * Return: 0 on success and failure value on error
1063 */
1064static int __maybe_unused xcan_resume(struct device *dev)
1065{
1066 if (!device_may_wakeup(dev))
1067 return pm_runtime_force_resume(dev);
1068
1069 return 0;
1070
1071}
1072
1073/**
1074 * xcan_runtime_suspend - Runtime suspend method for the driver
1075 * @dev: Address of the device structure
1076 *
1077 * Put the driver into low power mode.
1078 * Return: 0 always
1079 */
1080static int __maybe_unused xcan_runtime_suspend(struct device *dev)
1081{
1082 struct net_device *ndev = dev_get_drvdata(dev);
b1201e44
KA		 1083 struct xcan_priv *priv = netdev_priv(ndev);
1084
1085 if (netif_running(ndev)) {
1086 netif_stop_queue(ndev);
1087 netif_device_detach(ndev);
1088 }
1089
1090 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
1091 priv->can.state = CAN_STATE_SLEEPING;
1092
4716620d
KA		 1093 clk_disable_unprepare(priv->bus_clk);
1094 clk_disable_unprepare(priv->can_clk);
b1201e44
KA		 1095
1096 return 0;
1097}
1098
1099/**
4716620d
KA		 1100 * xcan_runtime_resume - Runtime resume from suspend
1101 * @dev: Address of the device structure
b1201e44
KA		 1102 *
1103 * Resume operation after suspend.
1104 * Return: 0 on success and failure value on error
1105 */
4716620d 1106static int __maybe_unused xcan_runtime_resume(struct device *dev)
b1201e44 1107{
4716620d 1108 struct net_device *ndev = dev_get_drvdata(dev);
b1201e44
KA		 1109 struct xcan_priv *priv = netdev_priv(ndev);
1110 int ret;
4716620d 1111 u32 isr, status;
b1201e44 1112
4716620d 1113 ret = clk_prepare_enable(priv->bus_clk);
b1201e44
KA		 1114 if (ret) {
1115 dev_err(dev, "Cannot enable clock.\n");
1116 return ret;
1117 }
4716620d 1118 ret = clk_prepare_enable(priv->can_clk);
b1201e44
KA		 1119 if (ret) {
1120 dev_err(dev, "Cannot enable clock.\n");
1121 clk_disable_unprepare(priv->bus_clk);
1122 return ret;
1123 }
1124
4716620d
KA		 1125 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
1126 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
1127 status = priv->read_reg(priv, XCAN_SR_OFFSET);
b1201e44
KA		 1128
1129 if (netif_running(ndev)) {
4716620d
KA		 1130 if (isr & XCAN_IXR_BSOFF_MASK) {
1131 priv->can.state = CAN_STATE_BUS_OFF;
1132 priv->write_reg(priv, XCAN_SRR_OFFSET,
1133 XCAN_SRR_RESET_MASK);
1134 } else if ((status & XCAN_SR_ESTAT_MASK) ==
1135 XCAN_SR_ESTAT_MASK) {
1136 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1137 } else if (status & XCAN_SR_ERRWRN_MASK) {
1138 priv->can.state = CAN_STATE_ERROR_WARNING;
1139 } else {
1140 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1141 }
b1201e44
KA		 1142 netif_device_attach(ndev);
1143 netif_start_queue(ndev);
1144 }
1145
1146 return 0;
1147}
1148
4716620d
KA		 1149static const struct dev_pm_ops xcan_dev_pm_ops = {
1150 SET_SYSTEM_SLEEP_PM_OPS(xcan_suspend, xcan_resume)
1151 SET_RUNTIME_PM_OPS(xcan_runtime_suspend, xcan_runtime_resume, NULL)
1152};
b1201e44
KA		 1153
1154/**
1155 * xcan_probe - Platform registration call
1156 * @pdev: Handle to the platform device structure
1157 *
1158 * This function does all the memory allocation and registration for the CAN
1159 * device.
1160 *
1161 * Return: 0 on success and failure value on error
1162 */
1163static int xcan_probe(struct platform_device *pdev)
1164{
1165 struct resource *res; /* IO mem resources */
1166 struct net_device *ndev;
1167 struct xcan_priv *priv;
1168 void __iomem *addr;
1169 int ret, rx_max, tx_max;
1170
1171 /* Get the virtual base address for the device */
1172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1173 addr = devm_ioremap_resource(&pdev->dev, res);
1174 if (IS_ERR(addr)) {
1175 ret = PTR_ERR(addr);
1176 goto err;
1177 }
1178
1179 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1180 if (ret < 0)
1181 goto err;
1182
1183 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1184 if (ret < 0)
1185 goto err;
1186
1187 /* Create a CAN device instance */
1188 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1189 if (!ndev)
1190 return -ENOMEM;
1191
1192 priv = netdev_priv(ndev);
4716620d 1193 priv->dev = &pdev->dev;
b1201e44
KA		 1194 priv->can.bittiming_const = &xcan_bittiming_const;
1195 priv->can.do_set_mode = xcan_do_set_mode;
1196 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1197 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1198 CAN_CTRLMODE_BERR_REPORTING;
1199 priv->reg_base = addr;
1200 priv->tx_max = tx_max;
1201
1202 /* Get IRQ for the device */
1203 ndev->irq = platform_get_irq(pdev, 0);
1204 ndev->flags |= IFF_ECHO; /* We support local echo */
1205
1206 platform_set_drvdata(pdev, ndev);
1207 SET_NETDEV_DEV(ndev, &pdev->dev);
1208 ndev->netdev_ops = &xcan_netdev_ops;
1209
1210 /* Getting the CAN can_clk info */
1211 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1212 if (IS_ERR(priv->can_clk)) {
1213 dev_err(&pdev->dev, "Device clock not found.\n");
1214 ret = PTR_ERR(priv->can_clk);
1215 goto err_free;
1216 }
1217 /* Check for type of CAN device */
1218 if (of_device_is_compatible(pdev->dev.of_node,
1219 "xlnx,zynq-can-1.0")) {
1220 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1221 if (IS_ERR(priv->bus_clk)) {
1222 dev_err(&pdev->dev, "bus clock not found\n");
1223 ret = PTR_ERR(priv->bus_clk);
1224 goto err_free;
1225 }
1226 } else {
1227 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1228 if (IS_ERR(priv->bus_clk)) {
1229 dev_err(&pdev->dev, "bus clock not found\n");
1230 ret = PTR_ERR(priv->bus_clk);
1231 goto err_free;
1232 }
1233 }
1234
b1201e44
KA		 1235 priv->write_reg = xcan_write_reg_le;
1236 priv->read_reg = xcan_read_reg_le;
1237
4716620d
KA		 1238 pm_runtime_enable(&pdev->dev);
1239 ret = pm_runtime_get_sync(&pdev->dev);
1240 if (ret < 0) {
1241 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
1242 __func__, ret);
1243 goto err_pmdisable;
1244 }
1245
b1201e44
KA		 1246 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1247 priv->write_reg = xcan_write_reg_be;
1248 priv->read_reg = xcan_read_reg_be;
1249 }
1250
1251 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1252
1253 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1254
1255 ret = register_candev(ndev);
1256 if (ret) {
1257 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
4716620d 1258 goto err_disableclks;
b1201e44
KA		 1259 }
1260
1261 devm_can_led_init(ndev);
4716620d
KA		 1262
1263 pm_runtime_put(&pdev->dev);
1264
b1201e44
KA		 1265 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1266 priv->reg_base, ndev->irq, priv->can.clock.freq,
1267 priv->tx_max);
1268
1269 return 0;
1270
4716620d
KA		 1271err_disableclks:
1272 pm_runtime_put(priv->dev);
1273err_pmdisable:
1274 pm_runtime_disable(&pdev->dev);
b1201e44
KA		 1275err_free:
1276 free_candev(ndev);
1277err:
1278 return ret;
1279}
1280
1281/**
1282 * xcan_remove - Unregister the device after releasing the resources
1283 * @pdev: Handle to the platform device structure
1284 *
1285 * This function frees all the resources allocated to the device.
1286 * Return: 0 always
1287 */
1288static int xcan_remove(struct platform_device *pdev)
1289{
1290 struct net_device *ndev = platform_get_drvdata(pdev);
1291 struct xcan_priv *priv = netdev_priv(ndev);
1292
b1201e44 1293 unregister_candev(ndev);
4716620d 1294 pm_runtime_disable(&pdev->dev);
b1201e44
KA		 1295 netif_napi_del(&priv->napi);
1296 free_candev(ndev);
1297
1298 return 0;
1299}
1300
1301/* Match table for OF platform binding */
486e9570 1302static const struct of_device_id xcan_of_match[] = {
b1201e44
KA		 1303 { .compatible = "xlnx,zynq-can-1.0", },
1304 { .compatible = "xlnx,axi-can-1.00.a", },
1305 { /* end of list */ },
1306};
1307MODULE_DEVICE_TABLE(of, xcan_of_match);
1308
1309static struct platform_driver xcan_driver = {
1310 .probe = xcan_probe,
1311 .remove = xcan_remove,
1312 .driver = {
b1201e44
KA		 1313 .name = DRIVER_NAME,
1314 .pm = &xcan_dev_pm_ops,
1315 .of_match_table = xcan_of_match,
1316 },
1317};
1318
1319module_platform_driver(xcan_driver);
1320
1321MODULE_LICENSE("GPL");
1322MODULE_AUTHOR("Xilinx Inc");
1323MODULE_DESCRIPTION("Xilinx CAN interface");
Linux 6.x block layer and io_uring tree(s)