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can: remove unused variable
[linux-block.git] / drivers / net / can / xilinx_can.c
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b1201e44
KA		 1/* Xilinx CAN device driver
2 *
3 * Copyright (C) 2012 - 2014 Xilinx, Inc.
4 * Copyright (C) 2009 PetaLogix. All rights reserved.
5 *
6 * Description:
7 * This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/clk.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/netdevice.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/skbuff.h>
30#include <linux/string.h>
31#include <linux/types.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34#include <linux/can/led.h>
35
36#define DRIVER_NAME "xilinx_can"
37
38/* CAN registers set */
39enum xcan_reg {
40 XCAN_SRR_OFFSET = 0x00, /* Software reset */
41 XCAN_MSR_OFFSET = 0x04, /* Mode select */
42 XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
43 XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
44 XCAN_ECR_OFFSET = 0x10, /* Error counter */
45 XCAN_ESR_OFFSET = 0x14, /* Error status */
46 XCAN_SR_OFFSET = 0x18, /* Status */
47 XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
48 XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
49 XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
50 XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
51 XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
52 XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
53 XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
54 XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
55 XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
56 XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
57 XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
58};
59
60/* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
61#define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
62#define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
63#define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
64#define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
65#define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
66#define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
67#define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
68#define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
69#define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
70#define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
71#define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
72#define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
73#define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
74#define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
75#define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
76#define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
77#define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
78#define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
79#define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
80#define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
81#define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
82#define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
83#define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
84#define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
85#define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
86#define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
87#define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
88#define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
89#define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
90#define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
91#define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
92#define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
93#define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
94#define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
95#define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
96#define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
97#define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
98#define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
99
100#define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
101 XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
102 XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
103 XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
104
105/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
106#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
107#define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
108#define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
109#define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
110#define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
111#define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
112
113/* CAN frame length constants */
114#define XCAN_FRAME_MAX_DATA_LEN 8
115#define XCAN_TIMEOUT (1 * HZ)
116
117/**
118 * struct xcan_priv - This definition define CAN driver instance
119 * @can: CAN private data structure.
120 * @tx_head: Tx CAN packets ready to send on the queue
121 * @tx_tail: Tx CAN packets successfully sended on the queue
122 * @tx_max: Maximum number packets the driver can send
123 * @napi: NAPI structure
124 * @read_reg: For reading data from CAN registers
125 * @write_reg: For writing data to CAN registers
126 * @dev: Network device data structure
127 * @reg_base: Ioremapped address to registers
128 * @irq_flags: For request_irq()
129 * @bus_clk: Pointer to struct clk
130 * @can_clk: Pointer to struct clk
131 */
132struct xcan_priv {
133 struct can_priv can;
134 unsigned int tx_head;
135 unsigned int tx_tail;
136 unsigned int tx_max;
137 struct napi_struct napi;
138 u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
140 u32 val);
141 struct net_device *dev;
142 void __iomem *reg_base;
143 unsigned long irq_flags;
144 struct clk *bus_clk;
145 struct clk *can_clk;
146};
147
148/* CAN Bittiming constants as per Xilinx CAN specs */
149static const struct can_bittiming_const xcan_bittiming_const = {
150 .name = DRIVER_NAME,
151 .tseg1_min = 1,
152 .tseg1_max = 16,
153 .tseg2_min = 1,
154 .tseg2_max = 8,
155 .sjw_max = 4,
156 .brp_min = 1,
157 .brp_max = 256,
158 .brp_inc = 1,
159};
160
161/**
162 * xcan_write_reg_le - Write a value to the device register little endian
163 * @priv: Driver private data structure
164 * @reg: Register offset
165 * @val: Value to write at the Register offset
166 *
167 * Write data to the paricular CAN register
168 */
169static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
170 u32 val)
171{
172 iowrite32(val, priv->reg_base + reg);
173}
174
175/**
176 * xcan_read_reg_le - Read a value from the device register little endian
177 * @priv: Driver private data structure
178 * @reg: Register offset
179 *
180 * Read data from the particular CAN register
181 * Return: value read from the CAN register
182 */
183static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
184{
185 return ioread32(priv->reg_base + reg);
186}
187
188/**
189 * xcan_write_reg_be - Write a value to the device register big endian
190 * @priv: Driver private data structure
191 * @reg: Register offset
192 * @val: Value to write at the Register offset
193 *
194 * Write data to the paricular CAN register
195 */
196static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
197 u32 val)
198{
199 iowrite32be(val, priv->reg_base + reg);
200}
201
202/**
203 * xcan_read_reg_be - Read a value from the device register big endian
204 * @priv: Driver private data structure
205 * @reg: Register offset
206 *
207 * Read data from the particular CAN register
208 * Return: value read from the CAN register
209 */
210static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
211{
212 return ioread32be(priv->reg_base + reg);
213}
214
215/**
216 * set_reset_mode - Resets the CAN device mode
217 * @ndev: Pointer to net_device structure
218 *
219 * This is the driver reset mode routine.The driver
220 * enters into configuration mode.
221 *
222 * Return: 0 on success and failure value on error
223 */
224static int set_reset_mode(struct net_device *ndev)
225{
226 struct xcan_priv *priv = netdev_priv(ndev);
227 unsigned long timeout;
228
229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
230
231 timeout = jiffies + XCAN_TIMEOUT;
232 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
233 if (time_after(jiffies, timeout)) {
234 netdev_warn(ndev, "timed out for config mode\n");
235 return -ETIMEDOUT;
236 }
237 usleep_range(500, 10000);
238 }
239
240 return 0;
241}
242
243/**
244 * xcan_set_bittiming - CAN set bit timing routine
245 * @ndev: Pointer to net_device structure
246 *
247 * This is the driver set bittiming routine.
248 * Return: 0 on success and failure value on error
249 */
250static int xcan_set_bittiming(struct net_device *ndev)
251{
252 struct xcan_priv *priv = netdev_priv(ndev);
253 struct can_bittiming *bt = &priv->can.bittiming;
254 u32 btr0, btr1;
255 u32 is_config_mode;
256
257 /* Check whether Xilinx CAN is in configuration mode.
258 * It cannot set bit timing if Xilinx CAN is not in configuration mode.
259 */
260 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
261 XCAN_SR_CONFIG_MASK;
262 if (!is_config_mode) {
263 netdev_alert(ndev,
264 "BUG! Cannot set bittiming - CAN is not in config mode\n");
265 return -EPERM;
266 }
267
268 /* Setting Baud Rate prescalar value in BRPR Register */
269 btr0 = (bt->brp - 1);
270
271 /* Setting Time Segment 1 in BTR Register */
272 btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
273
274 /* Setting Time Segment 2 in BTR Register */
275 btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
276
277 /* Setting Synchronous jump width in BTR Register */
278 btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
279
280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
282
283 netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
284 priv->read_reg(priv, XCAN_BRPR_OFFSET),
285 priv->read_reg(priv, XCAN_BTR_OFFSET));
286
287 return 0;
288}
289
290/**
291 * xcan_chip_start - This the drivers start routine
292 * @ndev: Pointer to net_device structure
293 *
294 * This is the drivers start routine.
295 * Based on the State of the CAN device it puts
296 * the CAN device into a proper mode.
297 *
298 * Return: 0 on success and failure value on error
299 */
300static int xcan_chip_start(struct net_device *ndev)
301{
302 struct xcan_priv *priv = netdev_priv(ndev);
303 u32 err, reg_msr, reg_sr_mask;
304 unsigned long timeout;
305
306 /* Check if it is in reset mode */
307 err = set_reset_mode(ndev);
308 if (err < 0)
309 return err;
310
311 err = xcan_set_bittiming(ndev);
312 if (err < 0)
313 return err;
314
315 /* Enable interrupts */
316 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
317
318 /* Check whether it is loopback mode or normal mode */
319 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
320 reg_msr = XCAN_MSR_LBACK_MASK;
321 reg_sr_mask = XCAN_SR_LBACK_MASK;
322 } else {
323 reg_msr = 0x0;
324 reg_sr_mask = XCAN_SR_NORMAL_MASK;
325 }
326
327 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
328 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
329
330 timeout = jiffies + XCAN_TIMEOUT;
331 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
332 if (time_after(jiffies, timeout)) {
333 netdev_warn(ndev,
334 "timed out for correct mode\n");
335 return -ETIMEDOUT;
336 }
337 }
338 netdev_dbg(ndev, "status:#x%08x\n",
339 priv->read_reg(priv, XCAN_SR_OFFSET));
340
341 priv->can.state = CAN_STATE_ERROR_ACTIVE;
342 return 0;
343}
344
345/**
346 * xcan_do_set_mode - This sets the mode of the driver
347 * @ndev: Pointer to net_device structure
348 * @mode: Tells the mode of the driver
349 *
350 * This check the drivers state and calls the
351 * the corresponding modes to set.
352 *
353 * Return: 0 on success and failure value on error
354 */
355static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
356{
357 int ret;
358
359 switch (mode) {
360 case CAN_MODE_START:
361 ret = xcan_chip_start(ndev);
362 if (ret < 0) {
363 netdev_err(ndev, "xcan_chip_start failed!\n");
364 return ret;
365 }
366 netif_wake_queue(ndev);
367 break;
368 default:
369 ret = -EOPNOTSUPP;
370 break;
371 }
372
373 return ret;
374}
375
376/**
377 * xcan_start_xmit - Starts the transmission
378 * @skb: sk_buff pointer that contains data to be Txed
379 * @ndev: Pointer to net_device structure
380 *
381 * This function is invoked from upper layers to initiate transmission. This
382 * function uses the next available free txbuff and populates their fields to
383 * start the transmission.
384 *
385 * Return: 0 on success and failure value on error
386 */
387static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
388{
389 struct xcan_priv *priv = netdev_priv(ndev);
390 struct net_device_stats *stats = &ndev->stats;
391 struct can_frame *cf = (struct can_frame *)skb->data;
392 u32 id, dlc, data[2] = {0, 0};
393
394 if (can_dropped_invalid_skb(ndev, skb))
395 return NETDEV_TX_OK;
396
397 /* Check if the TX buffer is full */
398 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
399 XCAN_SR_TXFLL_MASK)) {
400 netif_stop_queue(ndev);
401 netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
402 return NETDEV_TX_BUSY;
403 }
404
405 /* Watch carefully on the bit sequence */
406 if (cf->can_id & CAN_EFF_FLAG) {
407 /* Extended CAN ID format */
408 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
409 XCAN_IDR_ID2_MASK;
410 id |= (((cf->can_id & CAN_EFF_MASK) >>
411 (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
412 XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
413
414 /* The substibute remote TX request bit should be "1"
415 * for extended frames as in the Xilinx CAN datasheet
416 */
417 id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
418
419 if (cf->can_id & CAN_RTR_FLAG)
420 /* Extended frames remote TX request */
421 id |= XCAN_IDR_RTR_MASK;
422 } else {
423 /* Standard CAN ID format */
424 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
425 XCAN_IDR_ID1_MASK;
426
427 if (cf->can_id & CAN_RTR_FLAG)
428 /* Standard frames remote TX request */
429 id |= XCAN_IDR_SRR_MASK;
430 }
431
432 dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
433
434 if (cf->can_dlc > 0)
435 data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
436 if (cf->can_dlc > 4)
437 data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
438
439 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
440 priv->tx_head++;
441
442 /* Write the Frame to Xilinx CAN TX FIFO */
443 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
444 /* If the CAN frame is RTR frame this write triggers tranmission */
445 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
446 if (!(cf->can_id & CAN_RTR_FLAG)) {
447 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
448 /* If the CAN frame is Standard/Extended frame this
449 * write triggers tranmission
450 */
451 priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
452 stats->tx_bytes += cf->can_dlc;
453 }
454
455 /* Check if the TX buffer is full */
456 if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
457 netif_stop_queue(ndev);
458
459 return NETDEV_TX_OK;
460}
461
462/**
463 * xcan_rx - Is called from CAN isr to complete the received
464 * frame processing
465 * @ndev: Pointer to net_device structure
466 *
467 * This function is invoked from the CAN isr(poll) to process the Rx frames. It
468 * does minimal processing and invokes "netif_receive_skb" to complete further
469 * processing.
470 * Return: 1 on success and 0 on failure.
471 */
472static int xcan_rx(struct net_device *ndev)
473{
474 struct xcan_priv *priv = netdev_priv(ndev);
475 struct net_device_stats *stats = &ndev->stats;
476 struct can_frame *cf;
477 struct sk_buff *skb;
478 u32 id_xcan, dlc, data[2] = {0, 0};
479
480 skb = alloc_can_skb(ndev, &cf);
481 if (unlikely(!skb)) {
482 stats->rx_dropped++;
483 return 0;
484 }
485
486 /* Read a frame from Xilinx zynq CANPS */
487 id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
488 dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
489 XCAN_DLCR_DLC_SHIFT;
490
491 /* Change Xilinx CAN data length format to socketCAN data format */
492 cf->can_dlc = get_can_dlc(dlc);
493
494 /* Change Xilinx CAN ID format to socketCAN ID format */
495 if (id_xcan & XCAN_IDR_IDE_MASK) {
496 /* The received frame is an Extended format frame */
497 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
498 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
499 XCAN_IDR_ID2_SHIFT;
500 cf->can_id |= CAN_EFF_FLAG;
501 if (id_xcan & XCAN_IDR_RTR_MASK)
502 cf->can_id |= CAN_RTR_FLAG;
503 } else {
504 /* The received frame is a standard format frame */
505 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
506 XCAN_IDR_ID1_SHIFT;
507 if (id_xcan & XCAN_IDR_SRR_MASK)
508 cf->can_id |= CAN_RTR_FLAG;
509 }
510
511 if (!(id_xcan & XCAN_IDR_SRR_MASK)) {
512 data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
513 data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
514
515 /* Change Xilinx CAN data format to socketCAN data format */
516 if (cf->can_dlc > 0)
517 *(__be32 *)(cf->data) = cpu_to_be32(data[0]);
518 if (cf->can_dlc > 4)
519 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
520 }
521
522 stats->rx_bytes += cf->can_dlc;
523 stats->rx_packets++;
524 netif_receive_skb(skb);
525
526 return 1;
527}
528
529/**
530 * xcan_err_interrupt - error frame Isr
531 * @ndev: net_device pointer
532 * @isr: interrupt status register value
533 *
534 * This is the CAN error interrupt and it will
535 * check the the type of error and forward the error
536 * frame to upper layers.
537 */
538static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
539{
540 struct xcan_priv *priv = netdev_priv(ndev);
541 struct net_device_stats *stats = &ndev->stats;
542 struct can_frame *cf;
543 struct sk_buff *skb;
544 u32 err_status, status, txerr = 0, rxerr = 0;
545
546 skb = alloc_can_err_skb(ndev, &cf);
547
548 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
549 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
550 txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
551 rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
552 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
553 status = priv->read_reg(priv, XCAN_SR_OFFSET);
554
555 if (isr & XCAN_IXR_BSOFF_MASK) {
556 priv->can.state = CAN_STATE_BUS_OFF;
557 priv->can.can_stats.bus_off++;
558 /* Leave device in Config Mode in bus-off state */
559 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
560 can_bus_off(ndev);
561 if (skb)
562 cf->can_id |= CAN_ERR_BUSOFF;
563 } else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
564 priv->can.state = CAN_STATE_ERROR_PASSIVE;
565 priv->can.can_stats.error_passive++;
566 if (skb) {
567 cf->can_id |= CAN_ERR_CRTL;
568 cf->data[1] = (rxerr > 127) ?
569 CAN_ERR_CRTL_RX_PASSIVE :
570 CAN_ERR_CRTL_TX_PASSIVE;
571 cf->data[6] = txerr;
572 cf->data[7] = rxerr;
573 }
574 } else if (status & XCAN_SR_ERRWRN_MASK) {
575 priv->can.state = CAN_STATE_ERROR_WARNING;
576 priv->can.can_stats.error_warning++;
577 if (skb) {
578 cf->can_id |= CAN_ERR_CRTL;
579 cf->data[1] |= (txerr > rxerr) ?
580 CAN_ERR_CRTL_TX_WARNING :
581 CAN_ERR_CRTL_RX_WARNING;
582 cf->data[6] = txerr;
583 cf->data[7] = rxerr;
584 }
585 }
586
587 /* Check for Arbitration lost interrupt */
588 if (isr & XCAN_IXR_ARBLST_MASK) {
589 priv->can.can_stats.arbitration_lost++;
590 if (skb) {
591 cf->can_id |= CAN_ERR_LOSTARB;
592 cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
593 }
594 }
595
596 /* Check for RX FIFO Overflow interrupt */
597 if (isr & XCAN_IXR_RXOFLW_MASK) {
598 stats->rx_over_errors++;
599 stats->rx_errors++;
600 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
601 if (skb) {
602 cf->can_id |= CAN_ERR_CRTL;
603 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
604 }
605 }
606
607 /* Check for error interrupt */
608 if (isr & XCAN_IXR_ERROR_MASK) {
609 if (skb) {
610 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
611 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
612 }
613
614 /* Check for Ack error interrupt */
615 if (err_status & XCAN_ESR_ACKER_MASK) {
616 stats->tx_errors++;
617 if (skb) {
618 cf->can_id |= CAN_ERR_ACK;
619 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
620 }
621 }
622
623 /* Check for Bit error interrupt */
624 if (err_status & XCAN_ESR_BERR_MASK) {
625 stats->tx_errors++;
626 if (skb) {
627 cf->can_id |= CAN_ERR_PROT;
628 cf->data[2] = CAN_ERR_PROT_BIT;
629 }
630 }
631
632 /* Check for Stuff error interrupt */
633 if (err_status & XCAN_ESR_STER_MASK) {
634 stats->rx_errors++;
635 if (skb) {
636 cf->can_id |= CAN_ERR_PROT;
637 cf->data[2] = CAN_ERR_PROT_STUFF;
638 }
639 }
640
641 /* Check for Form error interrupt */
642 if (err_status & XCAN_ESR_FMER_MASK) {
643 stats->rx_errors++;
644 if (skb) {
645 cf->can_id |= CAN_ERR_PROT;
646 cf->data[2] = CAN_ERR_PROT_FORM;
647 }
648 }
649
650 /* Check for CRC error interrupt */
651 if (err_status & XCAN_ESR_CRCER_MASK) {
652 stats->rx_errors++;
653 if (skb) {
654 cf->can_id |= CAN_ERR_PROT;
655 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ |
656 CAN_ERR_PROT_LOC_CRC_DEL;
657 }
658 }
659 priv->can.can_stats.bus_error++;
660 }
661
662 if (skb) {
663 stats->rx_packets++;
664 stats->rx_bytes += cf->can_dlc;
665 netif_rx(skb);
666 }
667
668 netdev_dbg(ndev, "%s: error status register:0x%x\n",
669 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
670}
671
672/**
673 * xcan_state_interrupt - It will check the state of the CAN device
674 * @ndev: net_device pointer
675 * @isr: interrupt status register value
676 *
677 * This will checks the state of the CAN device
678 * and puts the device into appropriate state.
679 */
680static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
681{
682 struct xcan_priv *priv = netdev_priv(ndev);
683
684 /* Check for Sleep interrupt if set put CAN device in sleep state */
685 if (isr & XCAN_IXR_SLP_MASK)
686 priv->can.state = CAN_STATE_SLEEPING;
687
688 /* Check for Wake up interrupt if set put CAN device in Active state */
689 if (isr & XCAN_IXR_WKUP_MASK)
690 priv->can.state = CAN_STATE_ERROR_ACTIVE;
691}
692
693/**
694 * xcan_rx_poll - Poll routine for rx packets (NAPI)
695 * @napi: napi structure pointer
696 * @quota: Max number of rx packets to be processed.
697 *
698 * This is the poll routine for rx part.
699 * It will process the packets maximux quota value.
700 *
701 * Return: number of packets received
702 */
703static int xcan_rx_poll(struct napi_struct *napi, int quota)
704{
705 struct net_device *ndev = napi->dev;
706 struct xcan_priv *priv = netdev_priv(ndev);
707 u32 isr, ier;
708 int work_done = 0;
709
710 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
711 while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
712 if (isr & XCAN_IXR_RXOK_MASK) {
713 priv->write_reg(priv, XCAN_ICR_OFFSET,
714 XCAN_IXR_RXOK_MASK);
715 work_done += xcan_rx(ndev);
716 } else {
717 priv->write_reg(priv, XCAN_ICR_OFFSET,
718 XCAN_IXR_RXNEMP_MASK);
719 break;
720 }
721 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
722 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
723 }
724
725 if (work_done)
726 can_led_event(ndev, CAN_LED_EVENT_RX);
727
728 if (work_done < quota) {
729 napi_complete(napi);
730 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
731 ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
732 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
733 }
734 return work_done;
735}
736
737/**
738 * xcan_tx_interrupt - Tx Done Isr
739 * @ndev: net_device pointer
740 * @isr: Interrupt status register value
741 */
742static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
743{
744 struct xcan_priv *priv = netdev_priv(ndev);
745 struct net_device_stats *stats = &ndev->stats;
746
747 while ((priv->tx_head - priv->tx_tail > 0) &&
748 (isr & XCAN_IXR_TXOK_MASK)) {
749 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
750 can_get_echo_skb(ndev, priv->tx_tail %
751 priv->tx_max);
752 priv->tx_tail++;
753 stats->tx_packets++;
754 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
755 }
756 can_led_event(ndev, CAN_LED_EVENT_TX);
757 netif_wake_queue(ndev);
758}
759
760/**
761 * xcan_interrupt - CAN Isr
762 * @irq: irq number
763 * @dev_id: device id poniter
764 *
765 * This is the xilinx CAN Isr. It checks for the type of interrupt
766 * and invokes the corresponding ISR.
767 *
768 * Return:
769 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
770 */
771static irqreturn_t xcan_interrupt(int irq, void *dev_id)
772{
773 struct net_device *ndev = (struct net_device *)dev_id;
774 struct xcan_priv *priv = netdev_priv(ndev);
775 u32 isr, ier;
776
777 /* Get the interrupt status from Xilinx CAN */
778 isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
779 if (!isr)
780 return IRQ_NONE;
781
782 /* Check for the type of interrupt and Processing it */
783 if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
784 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
785 XCAN_IXR_WKUP_MASK));
786 xcan_state_interrupt(ndev, isr);
787 }
788
789 /* Check for Tx interrupt and Processing it */
790 if (isr & XCAN_IXR_TXOK_MASK)
791 xcan_tx_interrupt(ndev, isr);
792
793 /* Check for the type of error interrupt and Processing it */
794 if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
795 XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
796 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
797 XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
798 XCAN_IXR_ARBLST_MASK));
799 xcan_err_interrupt(ndev, isr);
800 }
801
802 /* Check for the type of receive interrupt and Processing it */
803 if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
804 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
805 ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
806 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
807 napi_schedule(&priv->napi);
808 }
809 return IRQ_HANDLED;
810}
811
812/**
813 * xcan_chip_stop - Driver stop routine
814 * @ndev: Pointer to net_device structure
815 *
816 * This is the drivers stop routine. It will disable the
817 * interrupts and put the device into configuration mode.
818 */
819static void xcan_chip_stop(struct net_device *ndev)
820{
821 struct xcan_priv *priv = netdev_priv(ndev);
822 u32 ier;
823
824 /* Disable interrupts and leave the can in configuration mode */
825 ier = priv->read_reg(priv, XCAN_IER_OFFSET);
826 ier &= ~XCAN_INTR_ALL;
827 priv->write_reg(priv, XCAN_IER_OFFSET, ier);
828 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
829 priv->can.state = CAN_STATE_STOPPED;
830}
831
832/**
833 * xcan_open - Driver open routine
834 * @ndev: Pointer to net_device structure
835 *
836 * This is the driver open routine.
837 * Return: 0 on success and failure value on error
838 */
839static int xcan_open(struct net_device *ndev)
840{
841 struct xcan_priv *priv = netdev_priv(ndev);
842 int ret;
843
844 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
845 ndev->name, ndev);
846 if (ret < 0) {
847 netdev_err(ndev, "irq allocation for CAN failed\n");
848 goto err;
849 }
850
851 ret = clk_prepare_enable(priv->can_clk);
852 if (ret) {
853 netdev_err(ndev, "unable to enable device clock\n");
854 goto err_irq;
855 }
856
857 ret = clk_prepare_enable(priv->bus_clk);
858 if (ret) {
859 netdev_err(ndev, "unable to enable bus clock\n");
860 goto err_can_clk;
861 }
862
863 /* Set chip into reset mode */
864 ret = set_reset_mode(ndev);
865 if (ret < 0) {
866 netdev_err(ndev, "mode resetting failed!\n");
867 goto err_bus_clk;
868 }
869
870 /* Common open */
871 ret = open_candev(ndev);
872 if (ret)
873 goto err_bus_clk;
874
875 ret = xcan_chip_start(ndev);
876 if (ret < 0) {
877 netdev_err(ndev, "xcan_chip_start failed!\n");
878 goto err_candev;
879 }
880
881 can_led_event(ndev, CAN_LED_EVENT_OPEN);
882 napi_enable(&priv->napi);
883 netif_start_queue(ndev);
884
885 return 0;
886
887err_candev:
888 close_candev(ndev);
889err_bus_clk:
890 clk_disable_unprepare(priv->bus_clk);
891err_can_clk:
892 clk_disable_unprepare(priv->can_clk);
893err_irq:
894 free_irq(ndev->irq, ndev);
895err:
896 return ret;
897}
898
899/**
900 * xcan_close - Driver close routine
901 * @ndev: Pointer to net_device structure
902 *
903 * Return: 0 always
904 */
905static int xcan_close(struct net_device *ndev)
906{
907 struct xcan_priv *priv = netdev_priv(ndev);
908
909 netif_stop_queue(ndev);
910 napi_disable(&priv->napi);
911 xcan_chip_stop(ndev);
912 clk_disable_unprepare(priv->bus_clk);
913 clk_disable_unprepare(priv->can_clk);
914 free_irq(ndev->irq, ndev);
915 close_candev(ndev);
916
917 can_led_event(ndev, CAN_LED_EVENT_STOP);
918
919 return 0;
920}
921
922/**
923 * xcan_get_berr_counter - error counter routine
924 * @ndev: Pointer to net_device structure
925 * @bec: Pointer to can_berr_counter structure
926 *
927 * This is the driver error counter routine.
928 * Return: 0 on success and failure value on error
929 */
930static int xcan_get_berr_counter(const struct net_device *ndev,
931 struct can_berr_counter *bec)
932{
933 struct xcan_priv *priv = netdev_priv(ndev);
934 int ret;
935
936 ret = clk_prepare_enable(priv->can_clk);
937 if (ret)
938 goto err;
939
940 ret = clk_prepare_enable(priv->bus_clk);
941 if (ret)
942 goto err_clk;
943
944 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
945 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
946 XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
947
948 clk_disable_unprepare(priv->bus_clk);
949 clk_disable_unprepare(priv->can_clk);
950
951 return 0;
952
953err_clk:
954 clk_disable_unprepare(priv->can_clk);
955err:
956 return ret;
957}
958
959
960static const struct net_device_ops xcan_netdev_ops = {
961 .ndo_open = xcan_open,
962 .ndo_stop = xcan_close,
963 .ndo_start_xmit = xcan_start_xmit,
964};
965
966/**
967 * xcan_suspend - Suspend method for the driver
968 * @dev: Address of the platform_device structure
969 *
970 * Put the driver into low power mode.
971 * Return: 0 always
972 */
973static int __maybe_unused xcan_suspend(struct device *dev)
974{
975 struct platform_device *pdev = dev_get_drvdata(dev);
976 struct net_device *ndev = platform_get_drvdata(pdev);
977 struct xcan_priv *priv = netdev_priv(ndev);
978
979 if (netif_running(ndev)) {
980 netif_stop_queue(ndev);
981 netif_device_detach(ndev);
982 }
983
984 priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
985 priv->can.state = CAN_STATE_SLEEPING;
986
987 clk_disable(priv->bus_clk);
988 clk_disable(priv->can_clk);
989
990 return 0;
991}
992
993/**
994 * xcan_resume - Resume from suspend
995 * @dev: Address of the platformdevice structure
996 *
997 * Resume operation after suspend.
998 * Return: 0 on success and failure value on error
999 */
1000static int __maybe_unused xcan_resume(struct device *dev)
1001{
1002 struct platform_device *pdev = dev_get_drvdata(dev);
1003 struct net_device *ndev = platform_get_drvdata(pdev);
1004 struct xcan_priv *priv = netdev_priv(ndev);
1005 int ret;
1006
1007 ret = clk_enable(priv->bus_clk);
1008 if (ret) {
1009 dev_err(dev, "Cannot enable clock.\n");
1010 return ret;
1011 }
1012 ret = clk_enable(priv->can_clk);
1013 if (ret) {
1014 dev_err(dev, "Cannot enable clock.\n");
1015 clk_disable_unprepare(priv->bus_clk);
1016 return ret;
1017 }
1018
1019 priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
1020 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
1021 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1022
1023 if (netif_running(ndev)) {
1024 netif_device_attach(ndev);
1025 netif_start_queue(ndev);
1026 }
1027
1028 return 0;
1029}
1030
1031static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
1032
1033/**
1034 * xcan_probe - Platform registration call
1035 * @pdev: Handle to the platform device structure
1036 *
1037 * This function does all the memory allocation and registration for the CAN
1038 * device.
1039 *
1040 * Return: 0 on success and failure value on error
1041 */
1042static int xcan_probe(struct platform_device *pdev)
1043{
1044 struct resource *res; /* IO mem resources */
1045 struct net_device *ndev;
1046 struct xcan_priv *priv;
1047 void __iomem *addr;
1048 int ret, rx_max, tx_max;
1049
1050 /* Get the virtual base address for the device */
1051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052 addr = devm_ioremap_resource(&pdev->dev, res);
1053 if (IS_ERR(addr)) {
1054 ret = PTR_ERR(addr);
1055 goto err;
1056 }
1057
1058 ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
1059 if (ret < 0)
1060 goto err;
1061
1062 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
1063 if (ret < 0)
1064 goto err;
1065
1066 /* Create a CAN device instance */
1067 ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
1068 if (!ndev)
1069 return -ENOMEM;
1070
1071 priv = netdev_priv(ndev);
1072 priv->dev = ndev;
1073 priv->can.bittiming_const = &xcan_bittiming_const;
1074 priv->can.do_set_mode = xcan_do_set_mode;
1075 priv->can.do_get_berr_counter = xcan_get_berr_counter;
1076 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1077 CAN_CTRLMODE_BERR_REPORTING;
1078 priv->reg_base = addr;
1079 priv->tx_max = tx_max;
1080
1081 /* Get IRQ for the device */
1082 ndev->irq = platform_get_irq(pdev, 0);
1083 ndev->flags |= IFF_ECHO; /* We support local echo */
1084
1085 platform_set_drvdata(pdev, ndev);
1086 SET_NETDEV_DEV(ndev, &pdev->dev);
1087 ndev->netdev_ops = &xcan_netdev_ops;
1088
1089 /* Getting the CAN can_clk info */
1090 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1091 if (IS_ERR(priv->can_clk)) {
1092 dev_err(&pdev->dev, "Device clock not found.\n");
1093 ret = PTR_ERR(priv->can_clk);
1094 goto err_free;
1095 }
1096 /* Check for type of CAN device */
1097 if (of_device_is_compatible(pdev->dev.of_node,
1098 "xlnx,zynq-can-1.0")) {
1099 priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
1100 if (IS_ERR(priv->bus_clk)) {
1101 dev_err(&pdev->dev, "bus clock not found\n");
1102 ret = PTR_ERR(priv->bus_clk);
1103 goto err_free;
1104 }
1105 } else {
1106 priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
1107 if (IS_ERR(priv->bus_clk)) {
1108 dev_err(&pdev->dev, "bus clock not found\n");
1109 ret = PTR_ERR(priv->bus_clk);
1110 goto err_free;
1111 }
1112 }
1113
1114 ret = clk_prepare_enable(priv->can_clk);
1115 if (ret) {
1116 dev_err(&pdev->dev, "unable to enable device clock\n");
1117 goto err_free;
1118 }
1119
1120 ret = clk_prepare_enable(priv->bus_clk);
1121 if (ret) {
1122 dev_err(&pdev->dev, "unable to enable bus clock\n");
1123 goto err_unprepare_disable_dev;
1124 }
1125
1126 priv->write_reg = xcan_write_reg_le;
1127 priv->read_reg = xcan_read_reg_le;
1128
1129 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
1130 priv->write_reg = xcan_write_reg_be;
1131 priv->read_reg = xcan_read_reg_be;
1132 }
1133
1134 priv->can.clock.freq = clk_get_rate(priv->can_clk);
1135
1136 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
1137
1138 ret = register_candev(ndev);
1139 if (ret) {
1140 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
1141 goto err_unprepare_disable_busclk;
1142 }
1143
1144 devm_can_led_init(ndev);
1145 clk_disable_unprepare(priv->bus_clk);
1146 clk_disable_unprepare(priv->can_clk);
1147 netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
1148 priv->reg_base, ndev->irq, priv->can.clock.freq,
1149 priv->tx_max);
1150
1151 return 0;
1152
1153err_unprepare_disable_busclk:
1154 clk_disable_unprepare(priv->bus_clk);
1155err_unprepare_disable_dev:
1156 clk_disable_unprepare(priv->can_clk);
1157err_free:
1158 free_candev(ndev);
1159err:
1160 return ret;
1161}
1162
1163/**
1164 * xcan_remove - Unregister the device after releasing the resources
1165 * @pdev: Handle to the platform device structure
1166 *
1167 * This function frees all the resources allocated to the device.
1168 * Return: 0 always
1169 */
1170static int xcan_remove(struct platform_device *pdev)
1171{
1172 struct net_device *ndev = platform_get_drvdata(pdev);
1173 struct xcan_priv *priv = netdev_priv(ndev);
1174
1175 if (set_reset_mode(ndev) < 0)
1176 netdev_err(ndev, "mode resetting failed!\n");
1177
1178 unregister_candev(ndev);
1179 netif_napi_del(&priv->napi);
1180 free_candev(ndev);
1181
1182 return 0;
1183}
1184
1185/* Match table for OF platform binding */
1186static struct of_device_id xcan_of_match[] = {
1187 { .compatible = "xlnx,zynq-can-1.0", },
1188 { .compatible = "xlnx,axi-can-1.00.a", },
1189 { /* end of list */ },
1190};
1191MODULE_DEVICE_TABLE(of, xcan_of_match);
1192
1193static struct platform_driver xcan_driver = {
1194 .probe = xcan_probe,
1195 .remove = xcan_remove,
1196 .driver = {
1197 .owner = THIS_MODULE,
1198 .name = DRIVER_NAME,
1199 .pm = &xcan_dev_pm_ops,
1200 .of_match_table = xcan_of_match,
1201 },
1202};
1203
1204module_platform_driver(xcan_driver);
1205
1206MODULE_LICENSE("GPL");
1207MODULE_AUTHOR("Xilinx Inc");
1208MODULE_DESCRIPTION("Xilinx CAN interface");
Linux 6.x block layer and io_uring tree(s)