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55e5b97f MKB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
eb79a267 | 3 | // mcp251xfd - Microchip MCP251xFD Family CAN controller driver |
55e5b97f | 4 | // |
eb94b74c MKB |
5 | // Copyright (c) 2019, 2020, 2021 Pengutronix, |
6 | // Marc Kleine-Budde <kernel@pengutronix.de> | |
55e5b97f MKB |
7 | // |
8 | // Based on: | |
9 | // | |
10 | // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface | |
11 | // | |
12 | // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> | |
13 | // | |
14 | ||
1c0e78a2 | 15 | #include <asm/unaligned.h> |
55e5b97f MKB |
16 | #include <linux/bitfield.h> |
17 | #include <linux/clk.h> | |
18 | #include <linux/device.h> | |
71520f85 | 19 | #include <linux/mod_devicetable.h> |
55e5b97f | 20 | #include <linux/module.h> |
55e5b97f | 21 | #include <linux/pm_runtime.h> |
71520f85 | 22 | #include <linux/property.h> |
55e5b97f | 23 | |
1f0e21a0 | 24 | #include "mcp251xfd.h" |
55e5b97f | 25 | |
f4f77366 | 26 | #define DEVICE_NAME "mcp251xfd" |
55e5b97f | 27 | |
eb79a267 MKB |
28 | static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { |
29 | .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | | |
30 | MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | | |
31 | MCP251XFD_QUIRK_ECC, | |
32 | .model = MCP251XFD_MODEL_MCP2517FD, | |
55e5b97f MKB |
33 | }; |
34 | ||
eb79a267 MKB |
35 | static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { |
36 | .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | | |
37 | MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, | |
38 | .model = MCP251XFD_MODEL_MCP2518FD, | |
55e5b97f MKB |
39 | }; |
40 | ||
c6f2a617 MKB |
41 | static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = { |
42 | .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | | |
43 | MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, | |
44 | .model = MCP251XFD_MODEL_MCP251863, | |
45 | }; | |
46 | ||
55e5b97f | 47 | /* Autodetect model, start with CRC enabled. */ |
eb79a267 MKB |
48 | static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { |
49 | .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | | |
50 | MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, | |
51 | .model = MCP251XFD_MODEL_MCP251XFD, | |
55e5b97f MKB |
52 | }; |
53 | ||
eb79a267 | 54 | static const struct can_bittiming_const mcp251xfd_bittiming_const = { |
55e5b97f MKB |
55 | .name = DEVICE_NAME, |
56 | .tseg1_min = 2, | |
57 | .tseg1_max = 256, | |
58 | .tseg2_min = 1, | |
59 | .tseg2_max = 128, | |
60 | .sjw_max = 128, | |
61 | .brp_min = 1, | |
62 | .brp_max = 256, | |
63 | .brp_inc = 1, | |
64 | }; | |
65 | ||
eb79a267 | 66 | static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { |
55e5b97f MKB |
67 | .name = DEVICE_NAME, |
68 | .tseg1_min = 1, | |
69 | .tseg1_max = 32, | |
70 | .tseg2_min = 1, | |
71 | .tseg2_max = 16, | |
72 | .sjw_max = 16, | |
73 | .brp_min = 1, | |
74 | .brp_max = 256, | |
75 | .brp_inc = 1, | |
76 | }; | |
77 | ||
eb79a267 | 78 | static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) |
55e5b97f MKB |
79 | { |
80 | switch (model) { | |
eb79a267 | 81 | case MCP251XFD_MODEL_MCP2517FD: |
78db1aa8 | 82 | return "MCP2517FD"; |
eb79a267 | 83 | case MCP251XFD_MODEL_MCP2518FD: |
78db1aa8 | 84 | return "MCP2518FD"; |
c6f2a617 MKB |
85 | case MCP251XFD_MODEL_MCP251863: |
86 | return "MCP251863"; | |
eb79a267 | 87 | case MCP251XFD_MODEL_MCP251XFD: |
78db1aa8 | 88 | return "MCP251xFD"; |
55e5b97f MKB |
89 | } |
90 | ||
91 | return "<unknown>"; | |
92 | } | |
93 | ||
94 | static inline const char * | |
eb79a267 | 95 | mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) |
55e5b97f | 96 | { |
eb79a267 | 97 | return __mcp251xfd_get_model_str(priv->devtype_data.model); |
55e5b97f MKB |
98 | } |
99 | ||
eb79a267 | 100 | static const char *mcp251xfd_get_mode_str(const u8 mode) |
55e5b97f MKB |
101 | { |
102 | switch (mode) { | |
eb79a267 | 103 | case MCP251XFD_REG_CON_MODE_MIXED: |
78db1aa8 | 104 | return "Mixed (CAN FD/CAN 2.0)"; |
eb79a267 | 105 | case MCP251XFD_REG_CON_MODE_SLEEP: |
78db1aa8 | 106 | return "Sleep"; |
eb79a267 | 107 | case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: |
78db1aa8 | 108 | return "Internal Loopback"; |
eb79a267 | 109 | case MCP251XFD_REG_CON_MODE_LISTENONLY: |
78db1aa8 | 110 | return "Listen Only"; |
eb79a267 | 111 | case MCP251XFD_REG_CON_MODE_CONFIG: |
78db1aa8 | 112 | return "Configuration"; |
eb79a267 | 113 | case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: |
78db1aa8 | 114 | return "External Loopback"; |
eb79a267 | 115 | case MCP251XFD_REG_CON_MODE_CAN2_0: |
78db1aa8 | 116 | return "CAN 2.0"; |
eb79a267 | 117 | case MCP251XFD_REG_CON_MODE_RESTRICTED: |
78db1aa8 | 118 | return "Restricted Operation"; |
55e5b97f MKB |
119 | } |
120 | ||
121 | return "<unknown>"; | |
122 | } | |
123 | ||
06db5dbc MKB |
124 | static const char * |
125 | mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference) | |
126 | { | |
127 | switch (~osc & osc_reference & | |
128 | (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) { | |
129 | case MCP251XFD_REG_OSC_PLLRDY: | |
130 | return "PLL"; | |
131 | case MCP251XFD_REG_OSC_OSCRDY: | |
132 | return "Oscillator"; | |
133 | case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY: | |
134 | return "Oscillator/PLL"; | |
135 | } | |
136 | ||
137 | return "<unknown>"; | |
138 | } | |
139 | ||
eb79a267 | 140 | static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
141 | { |
142 | if (!priv->reg_vdd) | |
143 | return 0; | |
144 | ||
145 | return regulator_enable(priv->reg_vdd); | |
146 | } | |
147 | ||
eb79a267 | 148 | static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
149 | { |
150 | if (!priv->reg_vdd) | |
151 | return 0; | |
152 | ||
153 | return regulator_disable(priv->reg_vdd); | |
154 | } | |
155 | ||
156 | static inline int | |
eb79a267 | 157 | mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
158 | { |
159 | if (!priv->reg_xceiver) | |
160 | return 0; | |
161 | ||
162 | return regulator_enable(priv->reg_xceiver); | |
163 | } | |
164 | ||
165 | static inline int | |
eb79a267 | 166 | mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
167 | { |
168 | if (!priv->reg_xceiver) | |
169 | return 0; | |
170 | ||
171 | return regulator_disable(priv->reg_xceiver); | |
172 | } | |
173 | ||
eb79a267 | 174 | static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
175 | { |
176 | int err; | |
177 | ||
178 | err = clk_prepare_enable(priv->clk); | |
179 | if (err) | |
180 | return err; | |
181 | ||
eb79a267 | 182 | err = mcp251xfd_vdd_enable(priv); |
55e5b97f MKB |
183 | if (err) |
184 | clk_disable_unprepare(priv->clk); | |
185 | ||
186 | /* Wait for oscillator stabilisation time after power up */ | |
eb79a267 MKB |
187 | usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, |
188 | 2 * MCP251XFD_OSC_STAB_SLEEP_US); | |
55e5b97f MKB |
189 | |
190 | return err; | |
191 | } | |
192 | ||
eb79a267 | 193 | static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
194 | { |
195 | int err; | |
196 | ||
eb79a267 | 197 | err = mcp251xfd_vdd_disable(priv); |
55e5b97f MKB |
198 | if (err) |
199 | return err; | |
200 | ||
201 | clk_disable_unprepare(priv->clk); | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
3f5c91b4 MKB |
206 | static inline bool mcp251xfd_reg_invalid(u32 reg) |
207 | { | |
208 | return reg == 0x0 || reg == 0xffffffff; | |
209 | } | |
210 | ||
55e5b97f | 211 | static inline int |
eb79a267 | 212 | mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) |
55e5b97f MKB |
213 | { |
214 | u32 val; | |
215 | int err; | |
216 | ||
eb79a267 | 217 | err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); |
55e5b97f MKB |
218 | if (err) |
219 | return err; | |
220 | ||
eb79a267 | 221 | *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); |
55e5b97f MKB |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static int | |
eb79a267 | 227 | __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, |
55e5b97f MKB |
228 | const u8 mode_req, bool nowait) |
229 | { | |
a10fd91e MKB |
230 | u32 con = 0, con_reqop, osc = 0; |
231 | u8 mode; | |
55e5b97f MKB |
232 | int err; |
233 | ||
eb79a267 MKB |
234 | con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); |
235 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, | |
236 | MCP251XFD_REG_CON_REQOP_MASK, con_reqop); | |
a10fd91e MKB |
237 | if (err == -EBADMSG) { |
238 | netdev_err(priv->ndev, | |
239 | "Failed to set Requested Operation Mode.\n"); | |
240 | ||
241 | return -ENODEV; | |
242 | } else if (err) { | |
55e5b97f | 243 | return err; |
a10fd91e | 244 | } |
55e5b97f | 245 | |
eb79a267 | 246 | if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) |
55e5b97f MKB |
247 | return 0; |
248 | ||
eb79a267 | 249 | err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, |
a10fd91e | 250 | !mcp251xfd_reg_invalid(con) && |
eb79a267 | 251 | FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, |
55e5b97f | 252 | con) == mode_req, |
eb79a267 MKB |
253 | MCP251XFD_POLL_SLEEP_US, |
254 | MCP251XFD_POLL_TIMEOUT_US); | |
a10fd91e MKB |
255 | if (err != -ETIMEDOUT && err != -EBADMSG) |
256 | return err; | |
55e5b97f | 257 | |
a10fd91e MKB |
258 | /* Ignore return value. |
259 | * Print below error messages, even if this fails. | |
260 | */ | |
261 | regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); | |
262 | ||
263 | if (mcp251xfd_reg_invalid(con)) { | |
55e5b97f | 264 | netdev_err(priv->ndev, |
a10fd91e MKB |
265 | "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n", |
266 | con, osc); | |
267 | ||
268 | return -ENODEV; | |
55e5b97f MKB |
269 | } |
270 | ||
a10fd91e MKB |
271 | mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); |
272 | netdev_err(priv->ndev, | |
273 | "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n", | |
274 | mcp251xfd_get_mode_str(mode_req), mode_req, | |
275 | mcp251xfd_get_mode_str(mode), mode, | |
276 | con, osc); | |
277 | ||
278 | return -ETIMEDOUT; | |
55e5b97f MKB |
279 | } |
280 | ||
281 | static inline int | |
eb79a267 | 282 | mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, |
55e5b97f MKB |
283 | const u8 mode_req) |
284 | { | |
eb79a267 | 285 | return __mcp251xfd_chip_set_mode(priv, mode_req, false); |
55e5b97f MKB |
286 | } |
287 | ||
b558e200 | 288 | static inline int __maybe_unused |
eb79a267 | 289 | mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, |
55e5b97f MKB |
290 | const u8 mode_req) |
291 | { | |
eb79a267 | 292 | return __mcp251xfd_chip_set_mode(priv, mode_req, true); |
55e5b97f MKB |
293 | } |
294 | ||
0445e5ff MKB |
295 | static int |
296 | mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv, | |
297 | u32 osc_reference, u32 osc_mask) | |
298 | { | |
299 | u32 osc; | |
300 | int err; | |
301 | ||
302 | err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, | |
197656de | 303 | !mcp251xfd_reg_invalid(osc) && |
0445e5ff MKB |
304 | (osc & osc_mask) == osc_reference, |
305 | MCP251XFD_OSC_STAB_SLEEP_US, | |
306 | MCP251XFD_OSC_STAB_TIMEOUT_US); | |
197656de MKB |
307 | if (err != -ETIMEDOUT) |
308 | return err; | |
309 | ||
0445e5ff MKB |
310 | if (mcp251xfd_reg_invalid(osc)) { |
311 | netdev_err(priv->ndev, | |
197656de MKB |
312 | "Failed to read Oscillator Configuration Register (osc=0x%08x).\n", |
313 | osc); | |
0445e5ff | 314 | return -ENODEV; |
0445e5ff MKB |
315 | } |
316 | ||
197656de | 317 | netdev_err(priv->ndev, |
06db5dbc MKB |
318 | "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n", |
319 | mcp251xfd_get_osc_str(osc, osc_reference), | |
320 | osc, osc_reference, osc_mask); | |
197656de MKB |
321 | |
322 | return -ETIMEDOUT; | |
0445e5ff MKB |
323 | } |
324 | ||
1a4abba6 | 325 | static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
326 | { |
327 | u32 osc, osc_reference, osc_mask; | |
328 | int err; | |
329 | ||
1a4abba6 MKB |
330 | /* For normal sleep on MCP2517FD and MCP2518FD, clearing |
331 | * "Oscillator Disable" will wake the chip. For low power mode | |
332 | * on MCP2518FD, asserting the chip select will wake the | |
333 | * chip. Writing to the Oscillator register will wake it in | |
334 | * both cases. | |
55e5b97f | 335 | */ |
eb79a267 MKB |
336 | osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, |
337 | MCP251XFD_REG_OSC_CLKODIV_10); | |
2a68dd86 MKB |
338 | |
339 | /* We cannot check for the PLL ready bit (either set or | |
340 | * unset), as the PLL might be enabled. This can happen if the | |
341 | * system reboots, while the mcp251xfd stays powered. | |
342 | */ | |
eb79a267 | 343 | osc_reference = MCP251XFD_REG_OSC_OSCRDY; |
2a68dd86 | 344 | osc_mask = MCP251XFD_REG_OSC_OSCRDY; |
55e5b97f | 345 | |
1a4abba6 | 346 | /* If the controller is in Sleep Mode the following write only |
55e5b97f MKB |
347 | * removes the "Oscillator Disable" bit and powers it up. All |
348 | * other bits are unaffected. | |
349 | */ | |
eb79a267 | 350 | err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); |
55e5b97f MKB |
351 | if (err) |
352 | return err; | |
353 | ||
06db5dbc MKB |
354 | /* Sometimes the PLL is stuck enabled, the controller never |
355 | * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our | |
356 | * caller takes care of retry. | |
357 | */ | |
0445e5ff | 358 | return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); |
55e5b97f MKB |
359 | } |
360 | ||
1ba3690f MKB |
361 | static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv) |
362 | { | |
2a68dd86 MKB |
363 | if (priv->pll_enable) { |
364 | u32 osc; | |
365 | int err; | |
366 | ||
367 | /* Turn off PLL */ | |
368 | osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, | |
369 | MCP251XFD_REG_OSC_CLKODIV_10); | |
370 | err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); | |
371 | if (err) | |
372 | netdev_err(priv->ndev, | |
373 | "Failed to disable PLL.\n"); | |
374 | ||
375 | priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow; | |
376 | } | |
377 | ||
1ba3690f MKB |
378 | return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); |
379 | } | |
380 | ||
eb79a267 | 381 | static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) |
55e5b97f | 382 | { |
eb79a267 | 383 | const __be16 cmd = mcp251xfd_cmd_reset(); |
55e5b97f MKB |
384 | int err; |
385 | ||
1a4abba6 MKB |
386 | /* The Set Mode and SPI Reset command only works if the |
387 | * controller is not in Sleep Mode. | |
55e5b97f | 388 | */ |
1a4abba6 | 389 | err = mcp251xfd_chip_wake(priv); |
55e5b97f MKB |
390 | if (err) |
391 | return err; | |
392 | ||
eb79a267 | 393 | err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); |
55e5b97f MKB |
394 | if (err) |
395 | return err; | |
396 | ||
397 | /* spi_write_then_read() works with non DMA-safe buffers */ | |
398 | return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); | |
399 | } | |
400 | ||
eb79a267 | 401 | static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) |
55e5b97f | 402 | { |
01a80d68 | 403 | u32 osc_reference, osc_mask; |
55e5b97f MKB |
404 | u8 mode; |
405 | int err; | |
406 | ||
01a80d68 MKB |
407 | /* Check for reset defaults of OSC reg. |
408 | * This will take care of stabilization period. | |
409 | */ | |
eb79a267 MKB |
410 | osc_reference = MCP251XFD_REG_OSC_OSCRDY | |
411 | FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, | |
412 | MCP251XFD_REG_OSC_CLKODIV_10); | |
01a80d68 MKB |
413 | osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY; |
414 | err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); | |
415 | if (err) | |
416 | return err; | |
55e5b97f | 417 | |
01a80d68 | 418 | err = mcp251xfd_chip_get_mode(priv, &mode); |
55e5b97f MKB |
419 | if (err) |
420 | return err; | |
421 | ||
01a80d68 | 422 | if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { |
55e5b97f | 423 | netdev_info(priv->ndev, |
01a80d68 MKB |
424 | "Controller not in Config Mode after reset, but in %s Mode (%u).\n", |
425 | mcp251xfd_get_mode_str(mode), mode); | |
55e5b97f MKB |
426 | return -ETIMEDOUT; |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
eb79a267 | 432 | static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
433 | { |
434 | int err, i; | |
435 | ||
eb79a267 | 436 | for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { |
55e5b97f MKB |
437 | if (i) |
438 | netdev_info(priv->ndev, | |
f93486a7 | 439 | "Retrying to reset controller.\n"); |
55e5b97f | 440 | |
eb79a267 | 441 | err = mcp251xfd_chip_softreset_do(priv); |
55e5b97f MKB |
442 | if (err == -ETIMEDOUT) |
443 | continue; | |
444 | if (err) | |
445 | return err; | |
446 | ||
eb79a267 | 447 | err = mcp251xfd_chip_softreset_check(priv); |
55e5b97f MKB |
448 | if (err == -ETIMEDOUT) |
449 | continue; | |
450 | if (err) | |
451 | return err; | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
275f6010 | 456 | return err; |
55e5b97f MKB |
457 | } |
458 | ||
eb79a267 | 459 | static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) |
55e5b97f | 460 | { |
e39ea136 | 461 | u32 osc, osc_reference, osc_mask; |
55e5b97f MKB |
462 | int err; |
463 | ||
464 | /* Activate Low Power Mode on Oscillator Disable. This only | |
465 | * works on the MCP2518FD. The MCP2517FD will go into normal | |
466 | * Sleep Mode instead. | |
467 | */ | |
eb79a267 MKB |
468 | osc = MCP251XFD_REG_OSC_LPMEN | |
469 | FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, | |
470 | MCP251XFD_REG_OSC_CLKODIV_10); | |
e39ea136 MKB |
471 | osc_reference = MCP251XFD_REG_OSC_OSCRDY; |
472 | osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; | |
473 | ||
2a68dd86 MKB |
474 | if (priv->pll_enable) { |
475 | osc |= MCP251XFD_REG_OSC_PLLEN; | |
476 | osc_reference |= MCP251XFD_REG_OSC_PLLRDY; | |
477 | } | |
478 | ||
eb79a267 | 479 | err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); |
55e5b97f MKB |
480 | if (err) |
481 | return err; | |
482 | ||
e39ea136 MKB |
483 | err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); |
484 | if (err) | |
485 | return err; | |
486 | ||
2a68dd86 MKB |
487 | priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast; |
488 | ||
14193ea2 MKB |
489 | return 0; |
490 | } | |
491 | ||
492 | static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv) | |
493 | { | |
55e5b97f MKB |
494 | /* Set Time Base Counter Prescaler to 1. |
495 | * | |
496 | * This means an overflow of the 32 bit Time Base Counter | |
497 | * register at 40 MHz every 107 seconds. | |
498 | */ | |
eb79a267 MKB |
499 | return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, |
500 | MCP251XFD_REG_TSCON_TBCEN); | |
55e5b97f MKB |
501 | } |
502 | ||
eb79a267 | 503 | static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
504 | { |
505 | const struct can_bittiming *bt = &priv->can.bittiming; | |
506 | const struct can_bittiming *dbt = &priv->can.data_bittiming; | |
507 | u32 val = 0; | |
508 | s8 tdco; | |
509 | int err; | |
510 | ||
511 | /* CAN Control Register | |
512 | * | |
513 | * - no transmit bandwidth sharing | |
514 | * - config mode | |
515 | * - disable transmit queue | |
516 | * - store in transmit FIFO event | |
517 | * - transition to restricted operation mode on system error | |
518 | * - ESI is transmitted recessive when ESI of message is high or | |
519 | * CAN controller error passive | |
520 | * - restricted retransmission attempts, | |
521 | * use TQXCON_TXAT and FIFOCON_TXAT | |
522 | * - wake-up filter bits T11FILTER | |
523 | * - use CAN bus line filter for wakeup | |
524 | * - protocol exception is treated as a form error | |
525 | * - Do not compare data bytes | |
526 | */ | |
eb79a267 MKB |
527 | val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, |
528 | MCP251XFD_REG_CON_MODE_CONFIG) | | |
529 | MCP251XFD_REG_CON_STEF | | |
530 | MCP251XFD_REG_CON_ESIGM | | |
531 | MCP251XFD_REG_CON_RTXAT | | |
532 | FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, | |
533 | MCP251XFD_REG_CON_WFT_T11FILTER) | | |
534 | MCP251XFD_REG_CON_WAKFIL | | |
535 | MCP251XFD_REG_CON_PXEDIS; | |
55e5b97f MKB |
536 | |
537 | if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) | |
eb79a267 | 538 | val |= MCP251XFD_REG_CON_ISOCRCEN; |
55e5b97f | 539 | |
eb79a267 | 540 | err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); |
55e5b97f MKB |
541 | if (err) |
542 | return err; | |
543 | ||
544 | /* Nominal Bit Time */ | |
eb79a267 MKB |
545 | val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | |
546 | FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, | |
55e5b97f | 547 | bt->prop_seg + bt->phase_seg1 - 1) | |
eb79a267 | 548 | FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, |
55e5b97f | 549 | bt->phase_seg2 - 1) | |
eb79a267 | 550 | FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); |
55e5b97f | 551 | |
eb79a267 | 552 | err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); |
55e5b97f MKB |
553 | if (err) |
554 | return err; | |
555 | ||
556 | if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) | |
557 | return 0; | |
558 | ||
559 | /* Data Bit Time */ | |
eb79a267 MKB |
560 | val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | |
561 | FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, | |
55e5b97f | 562 | dbt->prop_seg + dbt->phase_seg1 - 1) | |
eb79a267 | 563 | FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, |
55e5b97f | 564 | dbt->phase_seg2 - 1) | |
eb79a267 | 565 | FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); |
55e5b97f | 566 | |
eb79a267 | 567 | err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); |
55e5b97f MKB |
568 | if (err) |
569 | return err; | |
570 | ||
571 | /* Transmitter Delay Compensation */ | |
572 | tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), | |
573 | -64, 63); | |
eb79a267 MKB |
574 | val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, |
575 | MCP251XFD_REG_TDC_TDCMOD_AUTO) | | |
576 | FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); | |
55e5b97f | 577 | |
eb79a267 | 578 | return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); |
55e5b97f MKB |
579 | } |
580 | ||
eb79a267 | 581 | static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
582 | { |
583 | u32 val; | |
584 | ||
585 | if (!priv->rx_int) | |
586 | return 0; | |
587 | ||
588 | /* Configure GPIOs: | |
589 | * - PIN0: GPIO Input | |
590 | * - PIN1: GPIO Input/RX Interrupt | |
591 | * | |
592 | * PIN1 must be Input, otherwise there is a glitch on the | |
593 | * rx-INT line. It happens between setting the PIN as output | |
594 | * (in the first byte of the SPI transfer) and configuring the | |
595 | * PIN as interrupt (in the last byte of the SPI transfer). | |
596 | */ | |
eb79a267 MKB |
597 | val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | |
598 | MCP251XFD_REG_IOCON_TRIS0; | |
599 | return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); | |
55e5b97f MKB |
600 | } |
601 | ||
eb79a267 | 602 | static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
603 | { |
604 | u32 val; | |
605 | ||
606 | if (!priv->rx_int) | |
607 | return 0; | |
608 | ||
609 | /* Configure GPIOs: | |
610 | * - PIN0: GPIO Input | |
611 | * - PIN1: GPIO Input | |
612 | */ | |
eb79a267 MKB |
613 | val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | |
614 | MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; | |
615 | return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); | |
55e5b97f MKB |
616 | } |
617 | ||
eb79a267 | 618 | static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) |
55e5b97f | 619 | { |
eb79a267 | 620 | struct mcp251xfd_ecc *ecc = &priv->ecc; |
55e5b97f MKB |
621 | void *ram; |
622 | u32 val = 0; | |
623 | int err; | |
624 | ||
625 | ecc->ecc_stat = 0; | |
626 | ||
eb79a267 MKB |
627 | if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) |
628 | val = MCP251XFD_REG_ECCCON_ECCEN; | |
55e5b97f | 629 | |
eb79a267 MKB |
630 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, |
631 | MCP251XFD_REG_ECCCON_ECCEN, val); | |
55e5b97f MKB |
632 | if (err) |
633 | return err; | |
634 | ||
eb79a267 | 635 | ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); |
55e5b97f MKB |
636 | if (!ram) |
637 | return -ENOMEM; | |
638 | ||
eb79a267 MKB |
639 | err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, |
640 | MCP251XFD_RAM_SIZE); | |
55e5b97f MKB |
641 | kfree(ram); |
642 | ||
643 | return err; | |
644 | } | |
645 | ||
eb79a267 | 646 | static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
647 | { |
648 | u8 mode; | |
649 | ||
ee42bedc MS |
650 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) |
651 | mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; | |
652 | else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
eb79a267 | 653 | mode = MCP251XFD_REG_CON_MODE_LISTENONLY; |
33ea42f6 | 654 | else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) |
eb79a267 | 655 | mode = MCP251XFD_REG_CON_MODE_MIXED; |
55e5b97f | 656 | else |
eb79a267 | 657 | mode = MCP251XFD_REG_CON_MODE_CAN2_0; |
55e5b97f MKB |
658 | |
659 | return mode; | |
660 | } | |
661 | ||
662 | static int | |
eb79a267 | 663 | __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, |
55e5b97f MKB |
664 | bool nowait) |
665 | { | |
666 | u8 mode; | |
667 | ||
eb79a267 | 668 | mode = mcp251xfd_get_normal_mode(priv); |
55e5b97f | 669 | |
eb79a267 | 670 | return __mcp251xfd_chip_set_mode(priv, mode, nowait); |
55e5b97f MKB |
671 | } |
672 | ||
673 | static inline int | |
eb79a267 | 674 | mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) |
55e5b97f | 675 | { |
eb79a267 | 676 | return __mcp251xfd_chip_set_normal_mode(priv, false); |
55e5b97f MKB |
677 | } |
678 | ||
679 | static inline int | |
eb79a267 | 680 | mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) |
55e5b97f | 681 | { |
eb79a267 | 682 | return __mcp251xfd_chip_set_normal_mode(priv, true); |
55e5b97f MKB |
683 | } |
684 | ||
eb79a267 | 685 | static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
686 | { |
687 | u32 val; | |
688 | int err; | |
689 | ||
eb79a267 MKB |
690 | val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; |
691 | err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); | |
55e5b97f MKB |
692 | if (err) |
693 | return err; | |
694 | ||
eb79a267 MKB |
695 | val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; |
696 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); | |
55e5b97f MKB |
697 | if (err) |
698 | return err; | |
699 | ||
eb79a267 MKB |
700 | val = MCP251XFD_REG_INT_CERRIE | |
701 | MCP251XFD_REG_INT_SERRIE | | |
702 | MCP251XFD_REG_INT_RXOVIE | | |
703 | MCP251XFD_REG_INT_TXATIE | | |
704 | MCP251XFD_REG_INT_SPICRCIE | | |
705 | MCP251XFD_REG_INT_ECCIE | | |
706 | MCP251XFD_REG_INT_TEFIE | | |
707 | MCP251XFD_REG_INT_MODIE | | |
708 | MCP251XFD_REG_INT_RXIE; | |
55e5b97f MKB |
709 | |
710 | if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | |
eb79a267 | 711 | val |= MCP251XFD_REG_INT_IVMIE; |
55e5b97f | 712 | |
eb79a267 | 713 | return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); |
55e5b97f MKB |
714 | } |
715 | ||
eb79a267 | 716 | static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) |
55e5b97f MKB |
717 | { |
718 | int err; | |
719 | u32 mask; | |
720 | ||
eb79a267 | 721 | err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); |
55e5b97f MKB |
722 | if (err) |
723 | return err; | |
724 | ||
eb79a267 MKB |
725 | mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; |
726 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, | |
55e5b97f MKB |
727 | mask, 0x0); |
728 | if (err) | |
729 | return err; | |
730 | ||
eb79a267 | 731 | return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); |
55e5b97f MKB |
732 | } |
733 | ||
13c54a1e MKB |
734 | static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, |
735 | const enum can_state state) | |
55e5b97f MKB |
736 | { |
737 | priv->can.state = state; | |
738 | ||
eb79a267 MKB |
739 | mcp251xfd_chip_interrupts_disable(priv); |
740 | mcp251xfd_chip_rx_int_disable(priv); | |
13c54a1e | 741 | mcp251xfd_chip_sleep(priv); |
55e5b97f MKB |
742 | } |
743 | ||
eb79a267 | 744 | static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
745 | { |
746 | int err; | |
747 | ||
eb79a267 | 748 | err = mcp251xfd_chip_softreset(priv); |
55e5b97f MKB |
749 | if (err) |
750 | goto out_chip_stop; | |
751 | ||
eb79a267 | 752 | err = mcp251xfd_chip_clock_init(priv); |
55e5b97f MKB |
753 | if (err) |
754 | goto out_chip_stop; | |
755 | ||
14193ea2 MKB |
756 | err = mcp251xfd_chip_timestamp_init(priv); |
757 | if (err) | |
758 | goto out_chip_stop; | |
759 | ||
eb79a267 | 760 | err = mcp251xfd_set_bittiming(priv); |
55e5b97f MKB |
761 | if (err) |
762 | goto out_chip_stop; | |
763 | ||
eb79a267 | 764 | err = mcp251xfd_chip_rx_int_enable(priv); |
55e5b97f | 765 | if (err) |
69c55f6e | 766 | goto out_chip_stop; |
55e5b97f | 767 | |
eb79a267 | 768 | err = mcp251xfd_chip_ecc_init(priv); |
55e5b97f MKB |
769 | if (err) |
770 | goto out_chip_stop; | |
771 | ||
fa0b68df MKB |
772 | err = mcp251xfd_ring_init(priv); |
773 | if (err) | |
774 | goto out_chip_stop; | |
55e5b97f | 775 | |
eb79a267 | 776 | err = mcp251xfd_chip_fifo_init(priv); |
55e5b97f MKB |
777 | if (err) |
778 | goto out_chip_stop; | |
779 | ||
780 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
781 | ||
eb79a267 | 782 | err = mcp251xfd_chip_set_normal_mode(priv); |
55e5b97f MKB |
783 | if (err) |
784 | goto out_chip_stop; | |
785 | ||
786 | return 0; | |
787 | ||
788 | out_chip_stop: | |
e0ab3dd5 | 789 | mcp251xfd_dump(priv); |
eb79a267 | 790 | mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); |
55e5b97f MKB |
791 | |
792 | return err; | |
793 | } | |
794 | ||
eb79a267 | 795 | static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) |
55e5b97f | 796 | { |
eb79a267 | 797 | struct mcp251xfd_priv *priv = netdev_priv(ndev); |
55e5b97f MKB |
798 | int err; |
799 | ||
800 | switch (mode) { | |
801 | case CAN_MODE_START: | |
eb79a267 | 802 | err = mcp251xfd_chip_start(priv); |
55e5b97f MKB |
803 | if (err) |
804 | return err; | |
805 | ||
eb79a267 | 806 | err = mcp251xfd_chip_interrupts_enable(priv); |
55e5b97f | 807 | if (err) { |
eb79a267 | 808 | mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); |
55e5b97f MKB |
809 | return err; |
810 | } | |
811 | ||
812 | netif_wake_queue(ndev); | |
813 | break; | |
814 | ||
815 | default: | |
816 | return -EOPNOTSUPP; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
eb79a267 | 822 | static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, |
55e5b97f MKB |
823 | struct can_berr_counter *bec) |
824 | { | |
eb79a267 | 825 | const struct mcp251xfd_priv *priv = netdev_priv(ndev); |
55e5b97f MKB |
826 | u32 trec; |
827 | int err; | |
828 | ||
eb79a267 | 829 | err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); |
55e5b97f MKB |
830 | if (err) |
831 | return err; | |
832 | ||
eb79a267 | 833 | if (trec & MCP251XFD_REG_TREC_TXBO) |
55e5b97f MKB |
834 | bec->txerr = 256; |
835 | else | |
eb79a267 MKB |
836 | bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); |
837 | bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); | |
55e5b97f MKB |
838 | |
839 | return 0; | |
840 | } | |
841 | ||
eb79a267 | 842 | static int mcp251xfd_get_berr_counter(const struct net_device *ndev, |
55e5b97f MKB |
843 | struct can_berr_counter *bec) |
844 | { | |
eb79a267 | 845 | const struct mcp251xfd_priv *priv = netdev_priv(ndev); |
55e5b97f MKB |
846 | |
847 | /* Avoid waking up the controller if the interface is down */ | |
848 | if (!(ndev->flags & IFF_UP)) | |
849 | return 0; | |
850 | ||
851 | /* The controller is powered down during Bus Off, use saved | |
852 | * bec values. | |
853 | */ | |
854 | if (priv->can.state == CAN_STATE_BUS_OFF) { | |
855 | *bec = priv->bec; | |
856 | return 0; | |
857 | } | |
858 | ||
eb79a267 | 859 | return __mcp251xfd_get_berr_counter(ndev, bec); |
55e5b97f MKB |
860 | } |
861 | ||
55e5b97f | 862 | static struct sk_buff * |
5f02a49c | 863 | mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv, |
55e5b97f MKB |
864 | struct can_frame **cf, u32 *timestamp) |
865 | { | |
5f02a49c | 866 | struct sk_buff *skb; |
55e5b97f MKB |
867 | int err; |
868 | ||
eb79a267 | 869 | err = mcp251xfd_get_timestamp(priv, timestamp); |
55e5b97f MKB |
870 | if (err) |
871 | return NULL; | |
872 | ||
5f02a49c MKB |
873 | skb = alloc_can_err_skb(priv->ndev, cf); |
874 | if (skb) | |
875 | mcp251xfd_skb_set_timestamp(priv, skb, *timestamp); | |
876 | ||
877 | return skb; | |
55e5b97f MKB |
878 | } |
879 | ||
eb79a267 | 880 | static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
881 | { |
882 | struct net_device_stats *stats = &priv->ndev->stats; | |
eb79a267 | 883 | struct mcp251xfd_rx_ring *ring; |
55e5b97f MKB |
884 | struct sk_buff *skb; |
885 | struct can_frame *cf; | |
886 | u32 timestamp, rxovif; | |
887 | int err, i; | |
888 | ||
889 | stats->rx_over_errors++; | |
890 | stats->rx_errors++; | |
891 | ||
eb79a267 | 892 | err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); |
55e5b97f MKB |
893 | if (err) |
894 | return err; | |
895 | ||
eb79a267 | 896 | mcp251xfd_for_each_rx_ring(priv, ring, i) { |
55e5b97f MKB |
897 | if (!(rxovif & BIT(ring->fifo_nr))) |
898 | continue; | |
899 | ||
900 | /* If SERRIF is active, there was a RX MAB overflow. */ | |
eb79a267 | 901 | if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { |
58d0b0a9 MKB |
902 | if (net_ratelimit()) |
903 | netdev_dbg(priv->ndev, | |
904 | "RX-%d: MAB overflow detected.\n", | |
905 | ring->nr); | |
55e5b97f | 906 | } else { |
58d0b0a9 MKB |
907 | if (net_ratelimit()) |
908 | netdev_dbg(priv->ndev, | |
909 | "RX-%d: FIFO overflow.\n", | |
910 | ring->nr); | |
55e5b97f MKB |
911 | } |
912 | ||
913 | err = regmap_update_bits(priv->map_reg, | |
eb79a267 MKB |
914 | MCP251XFD_REG_FIFOSTA(ring->fifo_nr), |
915 | MCP251XFD_REG_FIFOSTA_RXOVIF, | |
55e5b97f MKB |
916 | 0x0); |
917 | if (err) | |
918 | return err; | |
919 | } | |
920 | ||
eb79a267 | 921 | skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); |
55e5b97f MKB |
922 | if (!skb) |
923 | return 0; | |
924 | ||
925 | cf->can_id |= CAN_ERR_CRTL; | |
926 | cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
927 | ||
eb38c205 | 928 | err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); |
55e5b97f MKB |
929 | if (err) |
930 | stats->rx_fifo_errors++; | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
eb79a267 | 935 | static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
936 | { |
937 | netdev_info(priv->ndev, "%s\n", __func__); | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
eb79a267 | 942 | static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
943 | { |
944 | struct net_device_stats *stats = &priv->ndev->stats; | |
945 | u32 bdiag1, timestamp; | |
946 | struct sk_buff *skb; | |
947 | struct can_frame *cf = NULL; | |
948 | int err; | |
949 | ||
eb79a267 | 950 | err = mcp251xfd_get_timestamp(priv, ×tamp); |
55e5b97f MKB |
951 | if (err) |
952 | return err; | |
953 | ||
eb79a267 | 954 | err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); |
55e5b97f MKB |
955 | if (err) |
956 | return err; | |
957 | ||
958 | /* Write 0s to clear error bits, don't write 1s to non active | |
959 | * bits, as they will be set. | |
960 | */ | |
eb79a267 | 961 | err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); |
55e5b97f MKB |
962 | if (err) |
963 | return err; | |
964 | ||
965 | priv->can.can_stats.bus_error++; | |
966 | ||
967 | skb = alloc_can_err_skb(priv->ndev, &cf); | |
968 | if (cf) | |
969 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
970 | ||
971 | /* Controller misconfiguration */ | |
eb79a267 | 972 | if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) |
55e5b97f MKB |
973 | netdev_err(priv->ndev, |
974 | "recv'd DLC is larger than PLSIZE of FIFO element."); | |
975 | ||
976 | /* RX errors */ | |
eb79a267 MKB |
977 | if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | |
978 | MCP251XFD_REG_BDIAG1_NCRCERR)) { | |
55e5b97f MKB |
979 | netdev_dbg(priv->ndev, "CRC error\n"); |
980 | ||
981 | stats->rx_errors++; | |
982 | if (cf) | |
983 | cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; | |
984 | } | |
eb79a267 MKB |
985 | if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | |
986 | MCP251XFD_REG_BDIAG1_NSTUFERR)) { | |
55e5b97f MKB |
987 | netdev_dbg(priv->ndev, "Stuff error\n"); |
988 | ||
989 | stats->rx_errors++; | |
990 | if (cf) | |
991 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
992 | } | |
eb79a267 MKB |
993 | if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | |
994 | MCP251XFD_REG_BDIAG1_NFORMERR)) { | |
55e5b97f MKB |
995 | netdev_dbg(priv->ndev, "Format error\n"); |
996 | ||
997 | stats->rx_errors++; | |
998 | if (cf) | |
999 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
1000 | } | |
1001 | ||
1002 | /* TX errors */ | |
eb79a267 | 1003 | if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { |
55e5b97f MKB |
1004 | netdev_dbg(priv->ndev, "NACK error\n"); |
1005 | ||
1006 | stats->tx_errors++; | |
1007 | if (cf) { | |
1008 | cf->can_id |= CAN_ERR_ACK; | |
1009 | cf->data[2] |= CAN_ERR_PROT_TX; | |
1010 | } | |
1011 | } | |
eb79a267 MKB |
1012 | if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | |
1013 | MCP251XFD_REG_BDIAG1_NBIT1ERR)) { | |
55e5b97f MKB |
1014 | netdev_dbg(priv->ndev, "Bit1 error\n"); |
1015 | ||
1016 | stats->tx_errors++; | |
1017 | if (cf) | |
1018 | cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; | |
1019 | } | |
eb79a267 MKB |
1020 | if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | |
1021 | MCP251XFD_REG_BDIAG1_NBIT0ERR)) { | |
55e5b97f MKB |
1022 | netdev_dbg(priv->ndev, "Bit0 error\n"); |
1023 | ||
1024 | stats->tx_errors++; | |
1025 | if (cf) | |
1026 | cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; | |
1027 | } | |
1028 | ||
1029 | if (!cf) | |
1030 | return 0; | |
1031 | ||
5f02a49c | 1032 | mcp251xfd_skb_set_timestamp(priv, skb, timestamp); |
eb38c205 | 1033 | err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); |
55e5b97f MKB |
1034 | if (err) |
1035 | stats->rx_fifo_errors++; | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
eb79a267 | 1040 | static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1041 | { |
1042 | struct net_device_stats *stats = &priv->ndev->stats; | |
1043 | struct sk_buff *skb; | |
1044 | struct can_frame *cf = NULL; | |
1045 | enum can_state new_state, rx_state, tx_state; | |
1046 | u32 trec, timestamp; | |
1047 | int err; | |
1048 | ||
eb79a267 | 1049 | err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); |
55e5b97f MKB |
1050 | if (err) |
1051 | return err; | |
1052 | ||
eb79a267 | 1053 | if (trec & MCP251XFD_REG_TREC_TXBO) |
55e5b97f | 1054 | tx_state = CAN_STATE_BUS_OFF; |
eb79a267 | 1055 | else if (trec & MCP251XFD_REG_TREC_TXBP) |
55e5b97f | 1056 | tx_state = CAN_STATE_ERROR_PASSIVE; |
eb79a267 | 1057 | else if (trec & MCP251XFD_REG_TREC_TXWARN) |
55e5b97f MKB |
1058 | tx_state = CAN_STATE_ERROR_WARNING; |
1059 | else | |
1060 | tx_state = CAN_STATE_ERROR_ACTIVE; | |
1061 | ||
eb79a267 | 1062 | if (trec & MCP251XFD_REG_TREC_RXBP) |
55e5b97f | 1063 | rx_state = CAN_STATE_ERROR_PASSIVE; |
eb79a267 | 1064 | else if (trec & MCP251XFD_REG_TREC_RXWARN) |
55e5b97f MKB |
1065 | rx_state = CAN_STATE_ERROR_WARNING; |
1066 | else | |
1067 | rx_state = CAN_STATE_ERROR_ACTIVE; | |
1068 | ||
1069 | new_state = max(tx_state, rx_state); | |
1070 | if (new_state == priv->can.state) | |
1071 | return 0; | |
1072 | ||
1073 | /* The skb allocation might fail, but can_change_state() | |
1074 | * handles cf == NULL. | |
1075 | */ | |
eb79a267 | 1076 | skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); |
55e5b97f MKB |
1077 | can_change_state(priv->ndev, cf, tx_state, rx_state); |
1078 | ||
1079 | if (new_state == CAN_STATE_BUS_OFF) { | |
1080 | /* As we're going to switch off the chip now, let's | |
1081 | * save the error counters and return them to | |
1082 | * userspace, if do_get_berr_counter() is called while | |
1083 | * the chip is in Bus Off. | |
1084 | */ | |
eb79a267 | 1085 | err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); |
55e5b97f MKB |
1086 | if (err) |
1087 | return err; | |
1088 | ||
eb79a267 | 1089 | mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); |
55e5b97f MKB |
1090 | can_bus_off(priv->ndev); |
1091 | } | |
1092 | ||
1093 | if (!skb) | |
1094 | return 0; | |
1095 | ||
1096 | if (new_state != CAN_STATE_BUS_OFF) { | |
1097 | struct can_berr_counter bec; | |
1098 | ||
eb79a267 | 1099 | err = mcp251xfd_get_berr_counter(priv->ndev, &bec); |
55e5b97f MKB |
1100 | if (err) |
1101 | return err; | |
1102 | cf->data[6] = bec.txerr; | |
1103 | cf->data[7] = bec.rxerr; | |
1104 | } | |
1105 | ||
eb38c205 | 1106 | err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); |
55e5b97f MKB |
1107 | if (err) |
1108 | stats->rx_fifo_errors++; | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static int | |
eb79a267 | 1114 | mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) |
55e5b97f | 1115 | { |
eb79a267 | 1116 | const u8 mode_reference = mcp251xfd_get_normal_mode(priv); |
55e5b97f MKB |
1117 | u8 mode; |
1118 | int err; | |
1119 | ||
eb79a267 | 1120 | err = mcp251xfd_chip_get_mode(priv, &mode); |
55e5b97f MKB |
1121 | if (err) |
1122 | return err; | |
1123 | ||
1124 | if (mode == mode_reference) { | |
1125 | netdev_dbg(priv->ndev, | |
1126 | "Controller changed into %s Mode (%u).\n", | |
eb79a267 | 1127 | mcp251xfd_get_mode_str(mode), mode); |
55e5b97f MKB |
1128 | return 0; |
1129 | } | |
1130 | ||
1131 | /* According to MCP2517FD errata DS80000792B 1., during a TX | |
1132 | * MAB underflow, the controller will transition to Restricted | |
1133 | * Operation Mode or Listen Only Mode (depending on SERR2LOM). | |
1134 | * | |
1135 | * However this is not always the case. If SERR2LOM is | |
1136 | * configured for Restricted Operation Mode (SERR2LOM not set) | |
1137 | * the MCP2517FD will sometimes transition to Listen Only Mode | |
1138 | * first. When polling this bit we see that it will transition | |
1139 | * to Restricted Operation Mode shortly after. | |
1140 | */ | |
eb79a267 MKB |
1141 | if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && |
1142 | (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || | |
1143 | mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) | |
55e5b97f MKB |
1144 | netdev_dbg(priv->ndev, |
1145 | "Controller changed into %s Mode (%u).\n", | |
eb79a267 | 1146 | mcp251xfd_get_mode_str(mode), mode); |
55e5b97f MKB |
1147 | else |
1148 | netdev_err(priv->ndev, | |
1149 | "Controller changed into %s Mode (%u).\n", | |
eb79a267 | 1150 | mcp251xfd_get_mode_str(mode), mode); |
55e5b97f | 1151 | |
f93486a7 | 1152 | /* After the application requests Normal mode, the controller |
55e5b97f MKB |
1153 | * will automatically attempt to retransmit the message that |
1154 | * caused the TX MAB underflow. | |
1155 | * | |
1156 | * However, if there is an ECC error in the TX-RAM, we first | |
1157 | * have to reload the tx-object before requesting Normal | |
eb79a267 | 1158 | * mode. This is done later in mcp251xfd_handle_eccif(). |
55e5b97f | 1159 | */ |
eb79a267 | 1160 | if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { |
55e5b97f MKB |
1161 | *set_normal_mode = true; |
1162 | return 0; | |
1163 | } | |
1164 | ||
eb79a267 | 1165 | return mcp251xfd_chip_set_normal_mode_nowait(priv); |
55e5b97f MKB |
1166 | } |
1167 | ||
eb79a267 | 1168 | static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) |
55e5b97f | 1169 | { |
eb79a267 | 1170 | struct mcp251xfd_ecc *ecc = &priv->ecc; |
55e5b97f MKB |
1171 | struct net_device_stats *stats = &priv->ndev->stats; |
1172 | bool handled = false; | |
1173 | ||
1174 | /* TX MAB underflow | |
1175 | * | |
1176 | * According to MCP2517FD Errata DS80000792B 1. a TX MAB | |
1177 | * underflow is indicated by SERRIF and MODIF. | |
1178 | * | |
1179 | * In addition to the effects mentioned in the Errata, there | |
1180 | * are Bus Errors due to the aborted CAN frame, so a IVMIF | |
1181 | * will be seen as well. | |
1182 | * | |
1183 | * Sometimes there is an ECC error in the TX-RAM, which leads | |
1184 | * to a TX MAB underflow. | |
1185 | * | |
1186 | * However, probably due to a race condition, there is no | |
1187 | * associated MODIF pending. | |
1188 | * | |
1189 | * Further, there are situations, where the SERRIF is caused | |
1190 | * by an ECC error in the TX-RAM, but not even the ECCIF is | |
1191 | * set. This only seems to happen _after_ the first occurrence | |
1192 | * of a ECCIF (which is tracked in ecc->cnt). | |
1193 | * | |
1194 | * Treat all as a known system errors.. | |
1195 | */ | |
eb79a267 MKB |
1196 | if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && |
1197 | priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || | |
1198 | priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || | |
55e5b97f MKB |
1199 | ecc->cnt) { |
1200 | const char *msg; | |
1201 | ||
eb79a267 | 1202 | if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || |
55e5b97f MKB |
1203 | ecc->cnt) |
1204 | msg = "TX MAB underflow due to ECC error detected."; | |
1205 | else | |
1206 | msg = "TX MAB underflow detected."; | |
1207 | ||
eb79a267 | 1208 | if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) |
55e5b97f MKB |
1209 | netdev_dbg(priv->ndev, "%s\n", msg); |
1210 | else | |
1211 | netdev_info(priv->ndev, "%s\n", msg); | |
1212 | ||
1213 | stats->tx_aborted_errors++; | |
1214 | stats->tx_errors++; | |
1215 | handled = true; | |
1216 | } | |
1217 | ||
1218 | /* RX MAB overflow | |
1219 | * | |
1220 | * According to MCP2517FD Errata DS80000792B 1. a RX MAB | |
1221 | * overflow is indicated by SERRIF. | |
1222 | * | |
1223 | * In addition to the effects mentioned in the Errata, (most | |
1224 | * of the times) a RXOVIF is raised, if the FIFO that is being | |
1225 | * received into has the RXOVIE activated (and we have enabled | |
1226 | * RXOVIE on all FIFOs). | |
1227 | * | |
1228 | * Sometimes there is no RXOVIF just a RXIF is pending. | |
1229 | * | |
1230 | * Treat all as a known system errors.. | |
1231 | */ | |
eb79a267 MKB |
1232 | if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || |
1233 | priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { | |
55e5b97f MKB |
1234 | stats->rx_dropped++; |
1235 | handled = true; | |
1236 | } | |
1237 | ||
1238 | if (!handled) | |
1239 | netdev_err(priv->ndev, | |
1240 | "Unhandled System Error Interrupt (intf=0x%08x)!\n", | |
1241 | priv->regs_status.intf); | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static int | |
eb79a267 | 1247 | mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) |
55e5b97f | 1248 | { |
eb79a267 MKB |
1249 | struct mcp251xfd_tx_ring *tx_ring = priv->tx; |
1250 | struct mcp251xfd_ecc *ecc = &priv->ecc; | |
1251 | struct mcp251xfd_tx_obj *tx_obj; | |
55e5b97f MKB |
1252 | u8 chip_tx_tail, tx_tail, offset; |
1253 | u16 addr; | |
1254 | int err; | |
1255 | ||
eb79a267 | 1256 | addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); |
55e5b97f | 1257 | |
eb79a267 | 1258 | err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); |
55e5b97f MKB |
1259 | if (err) |
1260 | return err; | |
1261 | ||
eb79a267 | 1262 | tx_tail = mcp251xfd_get_tx_tail(tx_ring); |
55e5b97f MKB |
1263 | offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); |
1264 | ||
1265 | /* Bail out if one of the following is met: | |
1266 | * - tx_tail information is inconsistent | |
1267 | * - for mcp2517fd: offset not 0 | |
1268 | * - for mcp2518fd: offset not 0 or 1 | |
1269 | */ | |
1270 | if (chip_tx_tail != tx_tail || | |
c6f2a617 MKB |
1271 | !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) || |
1272 | mcp251xfd_is_251863(priv))))) { | |
55e5b97f MKB |
1273 | netdev_err(priv->ndev, |
1274 | "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", | |
1275 | addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, | |
1276 | offset); | |
1277 | return -EINVAL; | |
1278 | } | |
1279 | ||
1280 | netdev_info(priv->ndev, | |
1281 | "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", | |
eb79a267 | 1282 | ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? |
55e5b97f MKB |
1283 | "Single" : "Double", |
1284 | addr, nr, tx_ring->tail, tx_tail, offset); | |
1285 | ||
1286 | /* reload tx_obj into controller RAM ... */ | |
1287 | tx_obj = &tx_ring->obj[nr]; | |
1288 | err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); | |
1289 | if (err) | |
1290 | return err; | |
1291 | ||
1292 | /* ... and trigger retransmit */ | |
eb79a267 | 1293 | return mcp251xfd_chip_set_normal_mode(priv); |
55e5b97f MKB |
1294 | } |
1295 | ||
1296 | static int | |
eb79a267 | 1297 | mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) |
55e5b97f | 1298 | { |
eb79a267 | 1299 | struct mcp251xfd_ecc *ecc = &priv->ecc; |
55e5b97f MKB |
1300 | const char *msg; |
1301 | bool in_tx_ram; | |
1302 | u32 ecc_stat; | |
1303 | u16 addr; | |
1304 | u8 nr; | |
1305 | int err; | |
1306 | ||
eb79a267 | 1307 | err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); |
55e5b97f MKB |
1308 | if (err) |
1309 | return err; | |
1310 | ||
eb79a267 MKB |
1311 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, |
1312 | MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); | |
55e5b97f MKB |
1313 | if (err) |
1314 | return err; | |
1315 | ||
1316 | /* Check if ECC error occurred in TX-RAM */ | |
eb79a267 MKB |
1317 | addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); |
1318 | err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); | |
55e5b97f MKB |
1319 | if (!err) |
1320 | in_tx_ram = true; | |
1321 | else if (err == -ENOENT) | |
1322 | in_tx_ram = false; | |
1323 | else | |
1324 | return err; | |
1325 | ||
788b83ea TK |
1326 | /* Errata Reference: |
1327 | * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. | |
1328 | * | |
1329 | * ECC single error correction does not work in all cases: | |
1330 | * | |
1331 | * Fix/Work Around: | |
1332 | * Enable single error correction and double error detection | |
1333 | * interrupts by setting SECIE and DEDIE. Handle SECIF as a | |
1334 | * detection interrupt and do not rely on the error | |
1335 | * correction. Instead, handle both interrupts as a | |
1336 | * notification that the RAM word at ERRADDR was corrupted. | |
1337 | */ | |
eb79a267 | 1338 | if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) |
788b83ea | 1339 | msg = "Single ECC Error detected at address"; |
eb79a267 | 1340 | else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) |
55e5b97f MKB |
1341 | msg = "Double ECC Error detected at address"; |
1342 | else | |
1343 | return -EINVAL; | |
1344 | ||
1345 | if (!in_tx_ram) { | |
1346 | ecc->ecc_stat = 0; | |
1347 | ||
788b83ea | 1348 | netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); |
55e5b97f MKB |
1349 | } else { |
1350 | /* Re-occurring error? */ | |
1351 | if (ecc->ecc_stat == ecc_stat) { | |
1352 | ecc->cnt++; | |
1353 | } else { | |
1354 | ecc->ecc_stat = ecc_stat; | |
1355 | ecc->cnt = 1; | |
1356 | } | |
1357 | ||
1358 | netdev_info(priv->ndev, | |
1359 | "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", | |
1360 | msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); | |
1361 | ||
eb79a267 MKB |
1362 | if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) |
1363 | return mcp251xfd_handle_eccif_recover(priv, nr); | |
55e5b97f MKB |
1364 | } |
1365 | ||
1366 | if (set_normal_mode) | |
eb79a267 | 1367 | return mcp251xfd_chip_set_normal_mode_nowait(priv); |
55e5b97f MKB |
1368 | |
1369 | return 0; | |
1370 | } | |
1371 | ||
eb79a267 | 1372 | static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1373 | { |
1374 | int err; | |
1375 | u32 crc; | |
1376 | ||
eb79a267 | 1377 | err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); |
55e5b97f MKB |
1378 | if (err) |
1379 | return err; | |
1380 | ||
eb79a267 MKB |
1381 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, |
1382 | MCP251XFD_REG_CRC_IF_MASK, | |
55e5b97f MKB |
1383 | ~crc); |
1384 | if (err) | |
1385 | return err; | |
1386 | ||
eb79a267 | 1387 | if (crc & MCP251XFD_REG_CRC_FERRIF) |
55e5b97f | 1388 | netdev_notice(priv->ndev, "CRC write command format error.\n"); |
eb79a267 | 1389 | else if (crc & MCP251XFD_REG_CRC_CRCERRIF) |
55e5b97f MKB |
1390 | netdev_notice(priv->ndev, |
1391 | "CRC write error detected. CRC=0x%04lx.\n", | |
eb79a267 | 1392 | FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); |
55e5b97f MKB |
1393 | |
1394 | return 0; | |
1395 | } | |
1396 | ||
887e359d MKB |
1397 | static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv) |
1398 | { | |
1399 | const int val_bytes = regmap_get_val_bytes(priv->map_reg); | |
1400 | size_t len; | |
1401 | ||
1402 | if (priv->rx_ring_num == 1) | |
1403 | len = sizeof(priv->regs_status.intf); | |
1404 | else | |
1405 | len = sizeof(priv->regs_status); | |
1406 | ||
1407 | return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, | |
1408 | &priv->regs_status, len / val_bytes); | |
1409 | } | |
1410 | ||
eb79a267 | 1411 | #define mcp251xfd_handle(priv, irq, ...) \ |
55e5b97f | 1412 | ({ \ |
eb79a267 | 1413 | struct mcp251xfd_priv *_priv = (priv); \ |
55e5b97f MKB |
1414 | int err; \ |
1415 | \ | |
eb79a267 | 1416 | err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ |
55e5b97f MKB |
1417 | if (err) \ |
1418 | netdev_err(_priv->ndev, \ | |
eb79a267 | 1419 | "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ |
55e5b97f MKB |
1420 | __stringify(irq), err); \ |
1421 | err; \ | |
1422 | }) | |
1423 | ||
eb79a267 | 1424 | static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) |
55e5b97f | 1425 | { |
eb79a267 | 1426 | struct mcp251xfd_priv *priv = dev_id; |
55e5b97f MKB |
1427 | irqreturn_t handled = IRQ_NONE; |
1428 | int err; | |
1429 | ||
1430 | if (priv->rx_int) | |
1431 | do { | |
1432 | int rx_pending; | |
1433 | ||
1434 | rx_pending = gpiod_get_value_cansleep(priv->rx_int); | |
1435 | if (!rx_pending) | |
1436 | break; | |
1437 | ||
887e359d MKB |
1438 | /* Assume 1st RX-FIFO pending, if other FIFOs |
1439 | * are pending the main IRQ handler will take | |
1440 | * care. | |
1441 | */ | |
1442 | priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr); | |
eb79a267 | 1443 | err = mcp251xfd_handle(priv, rxif); |
55e5b97f MKB |
1444 | if (err) |
1445 | goto out_fail; | |
1446 | ||
1447 | handled = IRQ_HANDLED; | |
887e359d MKB |
1448 | |
1449 | /* We don't know which RX-FIFO is pending, but only | |
1450 | * handle the 1st RX-FIFO. Leave loop here if we have | |
1451 | * more than 1 RX-FIFO to avoid starvation. | |
1452 | */ | |
1453 | } while (priv->rx_ring_num == 1); | |
55e5b97f MKB |
1454 | |
1455 | do { | |
1456 | u32 intf_pending, intf_pending_clearable; | |
727fba74 | 1457 | bool set_normal_mode = false; |
55e5b97f | 1458 | |
887e359d | 1459 | err = mcp251xfd_read_regs_status(priv); |
55e5b97f MKB |
1460 | if (err) |
1461 | goto out_fail; | |
1462 | ||
eb79a267 | 1463 | intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, |
55e5b97f | 1464 | priv->regs_status.intf) & |
eb79a267 | 1465 | FIELD_GET(MCP251XFD_REG_INT_IE_MASK, |
55e5b97f MKB |
1466 | priv->regs_status.intf); |
1467 | ||
c757096e | 1468 | if (!(intf_pending)) { |
30bfec4f | 1469 | can_rx_offload_threaded_irq_finish(&priv->offload); |
55e5b97f | 1470 | return handled; |
c757096e | 1471 | } |
55e5b97f MKB |
1472 | |
1473 | /* Some interrupts must be ACKed in the | |
eb79a267 | 1474 | * MCP251XFD_REG_INT register. |
55e5b97f MKB |
1475 | * - First ACK then handle, to avoid lost-IRQ race |
1476 | * condition on fast re-occurring interrupts. | |
1477 | * - Write "0" to clear active IRQs, "1" to all other, | |
1478 | * to avoid r/m/w race condition on the | |
eb79a267 | 1479 | * MCP251XFD_REG_INT register. |
55e5b97f MKB |
1480 | */ |
1481 | intf_pending_clearable = intf_pending & | |
eb79a267 | 1482 | MCP251XFD_REG_INT_IF_CLEARABLE_MASK; |
55e5b97f MKB |
1483 | if (intf_pending_clearable) { |
1484 | err = regmap_update_bits(priv->map_reg, | |
eb79a267 MKB |
1485 | MCP251XFD_REG_INT, |
1486 | MCP251XFD_REG_INT_IF_MASK, | |
55e5b97f MKB |
1487 | ~intf_pending_clearable); |
1488 | if (err) | |
1489 | goto out_fail; | |
1490 | } | |
1491 | ||
eb79a267 MKB |
1492 | if (intf_pending & MCP251XFD_REG_INT_MODIF) { |
1493 | err = mcp251xfd_handle(priv, modif, &set_normal_mode); | |
55e5b97f MKB |
1494 | if (err) |
1495 | goto out_fail; | |
1496 | } | |
1497 | ||
eb79a267 MKB |
1498 | if (intf_pending & MCP251XFD_REG_INT_RXIF) { |
1499 | err = mcp251xfd_handle(priv, rxif); | |
55e5b97f MKB |
1500 | if (err) |
1501 | goto out_fail; | |
1502 | } | |
1503 | ||
eb79a267 MKB |
1504 | if (intf_pending & MCP251XFD_REG_INT_TEFIF) { |
1505 | err = mcp251xfd_handle(priv, tefif); | |
55e5b97f MKB |
1506 | if (err) |
1507 | goto out_fail; | |
1508 | } | |
1509 | ||
eb79a267 MKB |
1510 | if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { |
1511 | err = mcp251xfd_handle(priv, rxovif); | |
55e5b97f MKB |
1512 | if (err) |
1513 | goto out_fail; | |
1514 | } | |
1515 | ||
eb79a267 MKB |
1516 | if (intf_pending & MCP251XFD_REG_INT_TXATIF) { |
1517 | err = mcp251xfd_handle(priv, txatif); | |
55e5b97f MKB |
1518 | if (err) |
1519 | goto out_fail; | |
1520 | } | |
1521 | ||
eb79a267 MKB |
1522 | if (intf_pending & MCP251XFD_REG_INT_IVMIF) { |
1523 | err = mcp251xfd_handle(priv, ivmif); | |
55e5b97f MKB |
1524 | if (err) |
1525 | goto out_fail; | |
1526 | } | |
1527 | ||
eb79a267 MKB |
1528 | if (intf_pending & MCP251XFD_REG_INT_SERRIF) { |
1529 | err = mcp251xfd_handle(priv, serrif); | |
55e5b97f MKB |
1530 | if (err) |
1531 | goto out_fail; | |
1532 | } | |
1533 | ||
eb79a267 MKB |
1534 | if (intf_pending & MCP251XFD_REG_INT_ECCIF) { |
1535 | err = mcp251xfd_handle(priv, eccif, set_normal_mode); | |
55e5b97f MKB |
1536 | if (err) |
1537 | goto out_fail; | |
1538 | } | |
1539 | ||
eb79a267 MKB |
1540 | if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { |
1541 | err = mcp251xfd_handle(priv, spicrcif); | |
55e5b97f MKB |
1542 | if (err) |
1543 | goto out_fail; | |
1544 | } | |
1545 | ||
1546 | /* On the MCP2527FD and MCP2518FD, we don't get a | |
1547 | * CERRIF IRQ on the transition TX ERROR_WARNING -> TX | |
1548 | * ERROR_ACTIVE. | |
1549 | */ | |
eb79a267 | 1550 | if (intf_pending & MCP251XFD_REG_INT_CERRIF || |
55e5b97f | 1551 | priv->can.state > CAN_STATE_ERROR_ACTIVE) { |
eb79a267 | 1552 | err = mcp251xfd_handle(priv, cerrif); |
55e5b97f MKB |
1553 | if (err) |
1554 | goto out_fail; | |
1555 | ||
1556 | /* In Bus Off we completely shut down the | |
1557 | * controller. Every subsequent register read | |
1558 | * will read bogus data, and if | |
eb79a267 | 1559 | * MCP251XFD_QUIRK_CRC_REG is enabled the CRC |
55e5b97f MKB |
1560 | * check will fail, too. So leave IRQ handler |
1561 | * directly. | |
1562 | */ | |
691204bd MKB |
1563 | if (priv->can.state == CAN_STATE_BUS_OFF) { |
1564 | can_rx_offload_threaded_irq_finish(&priv->offload); | |
55e5b97f | 1565 | return IRQ_HANDLED; |
691204bd | 1566 | } |
55e5b97f MKB |
1567 | } |
1568 | ||
1569 | handled = IRQ_HANDLED; | |
1570 | } while (1); | |
1571 | ||
1572 | out_fail: | |
30bfec4f | 1573 | can_rx_offload_threaded_irq_finish(&priv->offload); |
c757096e | 1574 | |
55e5b97f MKB |
1575 | netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", |
1576 | err, priv->regs_status.intf); | |
e0ab3dd5 | 1577 | mcp251xfd_dump(priv); |
eb79a267 | 1578 | mcp251xfd_chip_interrupts_disable(priv); |
ef68a717 | 1579 | mcp251xfd_timestamp_stop(priv); |
55e5b97f MKB |
1580 | |
1581 | return handled; | |
1582 | } | |
1583 | ||
eb79a267 | 1584 | static int mcp251xfd_open(struct net_device *ndev) |
55e5b97f | 1585 | { |
eb79a267 | 1586 | struct mcp251xfd_priv *priv = netdev_priv(ndev); |
55e5b97f MKB |
1587 | const struct spi_device *spi = priv->spi; |
1588 | int err; | |
1589 | ||
e91aae8e MKB |
1590 | err = open_candev(ndev); |
1591 | if (err) | |
1592 | return err; | |
1593 | ||
d84ca221 MKB |
1594 | err = pm_runtime_resume_and_get(ndev->dev.parent); |
1595 | if (err) | |
e91aae8e | 1596 | goto out_close_candev; |
55e5b97f | 1597 | |
eb79a267 | 1598 | err = mcp251xfd_ring_alloc(priv); |
55e5b97f | 1599 | if (err) |
e91aae8e | 1600 | goto out_pm_runtime_put; |
55e5b97f | 1601 | |
eb79a267 | 1602 | err = mcp251xfd_transceiver_enable(priv); |
55e5b97f | 1603 | if (err) |
eb79a267 | 1604 | goto out_mcp251xfd_ring_free; |
55e5b97f | 1605 | |
eb79a267 | 1606 | err = mcp251xfd_chip_start(priv); |
55e5b97f MKB |
1607 | if (err) |
1608 | goto out_transceiver_disable; | |
1609 | ||
efd8d98d | 1610 | mcp251xfd_timestamp_init(priv); |
60a848c5 | 1611 | clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags); |
55e5b97f MKB |
1612 | can_rx_offload_enable(&priv->offload); |
1613 | ||
eb79a267 | 1614 | err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, |
cb6adfe2 MKB |
1615 | IRQF_SHARED | IRQF_ONESHOT, |
1616 | dev_name(&spi->dev), priv); | |
55e5b97f MKB |
1617 | if (err) |
1618 | goto out_can_rx_offload_disable; | |
1619 | ||
eb79a267 | 1620 | err = mcp251xfd_chip_interrupts_enable(priv); |
55e5b97f MKB |
1621 | if (err) |
1622 | goto out_free_irq; | |
1623 | ||
1624 | netif_start_queue(ndev); | |
1625 | ||
1626 | return 0; | |
1627 | ||
1628 | out_free_irq: | |
1629 | free_irq(spi->irq, priv); | |
1630 | out_can_rx_offload_disable: | |
1631 | can_rx_offload_disable(&priv->offload); | |
60a848c5 | 1632 | set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); |
efd8d98d | 1633 | mcp251xfd_timestamp_stop(priv); |
55e5b97f | 1634 | out_transceiver_disable: |
eb79a267 MKB |
1635 | mcp251xfd_transceiver_disable(priv); |
1636 | out_mcp251xfd_ring_free: | |
1637 | mcp251xfd_ring_free(priv); | |
55e5b97f | 1638 | out_pm_runtime_put: |
eb79a267 | 1639 | mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); |
55e5b97f | 1640 | pm_runtime_put(ndev->dev.parent); |
e91aae8e MKB |
1641 | out_close_candev: |
1642 | close_candev(ndev); | |
55e5b97f MKB |
1643 | |
1644 | return err; | |
1645 | } | |
1646 | ||
eb79a267 | 1647 | static int mcp251xfd_stop(struct net_device *ndev) |
55e5b97f | 1648 | { |
eb79a267 | 1649 | struct mcp251xfd_priv *priv = netdev_priv(ndev); |
55e5b97f MKB |
1650 | |
1651 | netif_stop_queue(ndev); | |
60a848c5 MKB |
1652 | set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); |
1653 | hrtimer_cancel(&priv->rx_irq_timer); | |
d5a972f5 | 1654 | hrtimer_cancel(&priv->tx_irq_timer); |
eb79a267 | 1655 | mcp251xfd_chip_interrupts_disable(priv); |
55e5b97f MKB |
1656 | free_irq(ndev->irq, priv); |
1657 | can_rx_offload_disable(&priv->offload); | |
efd8d98d | 1658 | mcp251xfd_timestamp_stop(priv); |
eb79a267 MKB |
1659 | mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); |
1660 | mcp251xfd_transceiver_disable(priv); | |
1661 | mcp251xfd_ring_free(priv); | |
55e5b97f MKB |
1662 | close_candev(ndev); |
1663 | ||
1664 | pm_runtime_put(ndev->dev.parent); | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | ||
eb79a267 MKB |
1669 | static const struct net_device_ops mcp251xfd_netdev_ops = { |
1670 | .ndo_open = mcp251xfd_open, | |
1671 | .ndo_stop = mcp251xfd_stop, | |
1672 | .ndo_start_xmit = mcp251xfd_start_xmit, | |
55e5b97f MKB |
1673 | .ndo_change_mtu = can_change_mtu, |
1674 | }; | |
1675 | ||
1676 | static void | |
eb79a267 | 1677 | mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1678 | { |
1679 | const struct spi_device *spi = priv->spi; | |
1680 | const struct spi_controller *ctlr = spi->controller; | |
1681 | ||
1682 | if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) | |
eb79a267 | 1683 | priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; |
55e5b97f MKB |
1684 | } |
1685 | ||
eb79a267 | 1686 | static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1687 | { |
1688 | const struct net_device *ndev = priv->ndev; | |
eb79a267 | 1689 | const struct mcp251xfd_devtype_data *devtype_data; |
55e5b97f MKB |
1690 | u32 osc; |
1691 | int err; | |
1692 | ||
db87c005 MKB |
1693 | /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863, |
1694 | * so use it to autodetect the model. | |
55e5b97f | 1695 | */ |
eb79a267 MKB |
1696 | err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, |
1697 | MCP251XFD_REG_OSC_LPMEN, | |
1698 | MCP251XFD_REG_OSC_LPMEN); | |
55e5b97f MKB |
1699 | if (err) |
1700 | return err; | |
1701 | ||
eb79a267 | 1702 | err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); |
55e5b97f MKB |
1703 | if (err) |
1704 | return err; | |
1705 | ||
db87c005 MKB |
1706 | if (osc & MCP251XFD_REG_OSC_LPMEN) { |
1707 | /* We cannot distinguish between MCP2518FD and | |
1708 | * MCP251863. If firmware specifies MCP251863, keep | |
1709 | * it, otherwise set to MCP2518FD. | |
1710 | */ | |
1711 | if (mcp251xfd_is_251863(priv)) | |
1712 | devtype_data = &mcp251xfd_devtype_data_mcp251863; | |
1713 | else | |
1714 | devtype_data = &mcp251xfd_devtype_data_mcp2518fd; | |
1715 | } else { | |
eb79a267 | 1716 | devtype_data = &mcp251xfd_devtype_data_mcp2517fd; |
db87c005 | 1717 | } |
55e5b97f | 1718 | |
c6f2a617 | 1719 | if (!mcp251xfd_is_251XFD(priv) && |
55e5b97f MKB |
1720 | priv->devtype_data.model != devtype_data->model) { |
1721 | netdev_info(ndev, | |
3bd9d8ce | 1722 | "Detected %s, but firmware specifies a %s. Fixing up.\n", |
eb79a267 MKB |
1723 | __mcp251xfd_get_model_str(devtype_data->model), |
1724 | mcp251xfd_get_model_str(priv)); | |
55e5b97f MKB |
1725 | } |
1726 | priv->devtype_data = *devtype_data; | |
1727 | ||
1728 | /* We need to preserve the Half Duplex Quirk. */ | |
eb79a267 | 1729 | mcp251xfd_register_quirks(priv); |
55e5b97f MKB |
1730 | |
1731 | /* Re-init regmap with quirks of detected model. */ | |
eb79a267 | 1732 | return mcp251xfd_regmap_init(priv); |
55e5b97f MKB |
1733 | } |
1734 | ||
eb79a267 | 1735 | static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1736 | { |
1737 | int err, rx_pending; | |
1738 | ||
1739 | if (!priv->rx_int) | |
1740 | return 0; | |
1741 | ||
eb79a267 | 1742 | err = mcp251xfd_chip_rx_int_enable(priv); |
55e5b97f MKB |
1743 | if (err) |
1744 | return err; | |
1745 | ||
1746 | /* Check if RX_INT is properly working. The RX_INT should not | |
1747 | * be active after a softreset. | |
1748 | */ | |
1749 | rx_pending = gpiod_get_value_cansleep(priv->rx_int); | |
1750 | ||
eb79a267 | 1751 | err = mcp251xfd_chip_rx_int_disable(priv); |
55e5b97f MKB |
1752 | if (err) |
1753 | return err; | |
1754 | ||
1755 | if (!rx_pending) | |
1756 | return 0; | |
1757 | ||
1758 | netdev_info(priv->ndev, | |
3bd9d8ce | 1759 | "RX_INT active after softreset, disabling RX_INT support.\n"); |
55e5b97f MKB |
1760 | devm_gpiod_put(&priv->spi->dev, priv->rx_int); |
1761 | priv->rx_int = NULL; | |
1762 | ||
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | static int | |
2a68dd86 MKB |
1767 | mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id, |
1768 | u32 *effective_speed_hz_slow, | |
1769 | u32 *effective_speed_hz_fast) | |
55e5b97f | 1770 | { |
eb79a267 MKB |
1771 | struct mcp251xfd_map_buf_nocrc *buf_rx; |
1772 | struct mcp251xfd_map_buf_nocrc *buf_tx; | |
55e5b97f MKB |
1773 | struct spi_transfer xfer[2] = { }; |
1774 | int err; | |
1775 | ||
1776 | buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); | |
1777 | if (!buf_rx) | |
1778 | return -ENOMEM; | |
1779 | ||
1780 | buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); | |
1781 | if (!buf_tx) { | |
1782 | err = -ENOMEM; | |
1783 | goto out_kfree_buf_rx; | |
1784 | } | |
1785 | ||
1786 | xfer[0].tx_buf = buf_tx; | |
1787 | xfer[0].len = sizeof(buf_tx->cmd); | |
2a68dd86 | 1788 | xfer[0].speed_hz = priv->spi_max_speed_hz_slow; |
55e5b97f | 1789 | xfer[1].rx_buf = buf_rx->data; |
0ff32bfa | 1790 | xfer[1].len = sizeof(*dev_id); |
2a68dd86 | 1791 | xfer[1].speed_hz = priv->spi_max_speed_hz_fast; |
55e5b97f | 1792 | |
eb79a267 | 1793 | mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); |
2a68dd86 | 1794 | |
55e5b97f MKB |
1795 | err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); |
1796 | if (err) | |
1797 | goto out_kfree_buf_tx; | |
1798 | ||
1c0e78a2 | 1799 | *dev_id = get_unaligned_le32(buf_rx->data); |
2a68dd86 MKB |
1800 | *effective_speed_hz_slow = xfer[0].effective_speed_hz; |
1801 | *effective_speed_hz_fast = xfer[1].effective_speed_hz; | |
55e5b97f MKB |
1802 | |
1803 | out_kfree_buf_tx: | |
1804 | kfree(buf_tx); | |
1805 | out_kfree_buf_rx: | |
1806 | kfree(buf_rx); | |
1807 | ||
fa7b514d | 1808 | return err; |
55e5b97f MKB |
1809 | } |
1810 | ||
eb79a267 MKB |
1811 | #define MCP251XFD_QUIRK_ACTIVE(quirk) \ |
1812 | (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') | |
55e5b97f MKB |
1813 | |
1814 | static int | |
eb79a267 | 1815 | mcp251xfd_register_done(const struct mcp251xfd_priv *priv) |
55e5b97f | 1816 | { |
2a68dd86 MKB |
1817 | u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast; |
1818 | unsigned long clk_rate; | |
55e5b97f MKB |
1819 | int err; |
1820 | ||
eb79a267 | 1821 | err = mcp251xfd_register_get_dev_id(priv, &dev_id, |
2a68dd86 MKB |
1822 | &effective_speed_hz_slow, |
1823 | &effective_speed_hz_fast); | |
55e5b97f MKB |
1824 | if (err) |
1825 | return err; | |
1826 | ||
2a68dd86 MKB |
1827 | clk_rate = clk_get_rate(priv->clk); |
1828 | ||
55e5b97f | 1829 | netdev_info(priv->ndev, |
2a68dd86 | 1830 | "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n", |
eb79a267 MKB |
1831 | mcp251xfd_get_model_str(priv), |
1832 | FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), | |
1833 | FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), | |
55e5b97f | 1834 | priv->rx_int ? '+' : '-', |
2a68dd86 | 1835 | priv->pll_enable ? '+' : '-', |
eb79a267 MKB |
1836 | MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), |
1837 | MCP251XFD_QUIRK_ACTIVE(CRC_REG), | |
1838 | MCP251XFD_QUIRK_ACTIVE(CRC_RX), | |
1839 | MCP251XFD_QUIRK_ACTIVE(CRC_TX), | |
1840 | MCP251XFD_QUIRK_ACTIVE(ECC), | |
1841 | MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), | |
2a68dd86 MKB |
1842 | clk_rate / 1000000, |
1843 | clk_rate % 1000000 / 1000 / 10, | |
55e5b97f MKB |
1844 | priv->can.clock.freq / 1000000, |
1845 | priv->can.clock.freq % 1000000 / 1000 / 10, | |
1846 | priv->spi_max_speed_hz_orig / 1000000, | |
1847 | priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, | |
2a68dd86 MKB |
1848 | priv->spi_max_speed_hz_slow / 1000000, |
1849 | priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10, | |
1850 | effective_speed_hz_slow / 1000000, | |
1851 | effective_speed_hz_slow % 1000000 / 1000 / 10, | |
1852 | priv->spi_max_speed_hz_fast / 1000000, | |
1853 | priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10, | |
1854 | effective_speed_hz_fast / 1000000, | |
1855 | effective_speed_hz_fast % 1000000 / 1000 / 10); | |
55e5b97f MKB |
1856 | |
1857 | return 0; | |
1858 | } | |
1859 | ||
eb79a267 | 1860 | static int mcp251xfd_register(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1861 | { |
1862 | struct net_device *ndev = priv->ndev; | |
1863 | int err; | |
1864 | ||
eb79a267 | 1865 | err = mcp251xfd_clks_and_vdd_enable(priv); |
55e5b97f MKB |
1866 | if (err) |
1867 | return err; | |
1868 | ||
1869 | pm_runtime_get_noresume(ndev->dev.parent); | |
1870 | err = pm_runtime_set_active(ndev->dev.parent); | |
1871 | if (err) | |
1872 | goto out_runtime_put_noidle; | |
1873 | pm_runtime_enable(ndev->dev.parent); | |
1874 | ||
eb79a267 | 1875 | mcp251xfd_register_quirks(priv); |
55e5b97f | 1876 | |
eb79a267 | 1877 | err = mcp251xfd_chip_softreset(priv); |
55e5b97f MKB |
1878 | if (err == -ENODEV) |
1879 | goto out_runtime_disable; | |
1880 | if (err) | |
1ba3690f | 1881 | goto out_chip_sleep; |
445dd72a MKB |
1882 | |
1883 | err = mcp251xfd_chip_clock_init(priv); | |
1884 | if (err == -ENODEV) | |
1885 | goto out_runtime_disable; | |
1886 | if (err) | |
1887 | goto out_chip_sleep; | |
55e5b97f | 1888 | |
eb79a267 | 1889 | err = mcp251xfd_register_chip_detect(priv); |
55e5b97f | 1890 | if (err) |
1ba3690f | 1891 | goto out_chip_sleep; |
55e5b97f | 1892 | |
eb79a267 | 1893 | err = mcp251xfd_register_check_rx_int(priv); |
55e5b97f | 1894 | if (err) |
1ba3690f | 1895 | goto out_chip_sleep; |
55e5b97f | 1896 | |
d86ba8db MKB |
1897 | mcp251xfd_ethtool_init(priv); |
1898 | ||
55e5b97f MKB |
1899 | err = register_candev(ndev); |
1900 | if (err) | |
1ba3690f | 1901 | goto out_chip_sleep; |
55e5b97f | 1902 | |
eb79a267 | 1903 | err = mcp251xfd_register_done(priv); |
55e5b97f MKB |
1904 | if (err) |
1905 | goto out_unregister_candev; | |
1906 | ||
1907 | /* Put controller into sleep mode and let pm_runtime_put() | |
1908 | * disable the clocks and vdd. If CONFIG_PM is not enabled, | |
1909 | * the clocks and vdd will stay powered. | |
1910 | */ | |
1ba3690f | 1911 | err = mcp251xfd_chip_sleep(priv); |
55e5b97f MKB |
1912 | if (err) |
1913 | goto out_unregister_candev; | |
1914 | ||
1915 | pm_runtime_put(ndev->dev.parent); | |
1916 | ||
1917 | return 0; | |
1918 | ||
1919 | out_unregister_candev: | |
1920 | unregister_candev(ndev); | |
1ba3690f MKB |
1921 | out_chip_sleep: |
1922 | mcp251xfd_chip_sleep(priv); | |
55e5b97f MKB |
1923 | out_runtime_disable: |
1924 | pm_runtime_disable(ndev->dev.parent); | |
1925 | out_runtime_put_noidle: | |
1926 | pm_runtime_put_noidle(ndev->dev.parent); | |
eb79a267 | 1927 | mcp251xfd_clks_and_vdd_disable(priv); |
55e5b97f MKB |
1928 | |
1929 | return err; | |
1930 | } | |
1931 | ||
eb79a267 | 1932 | static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) |
55e5b97f MKB |
1933 | { |
1934 | struct net_device *ndev = priv->ndev; | |
1935 | ||
1936 | unregister_candev(ndev); | |
1937 | ||
72362dcd MKB |
1938 | if (pm_runtime_enabled(ndev->dev.parent)) |
1939 | pm_runtime_disable(ndev->dev.parent); | |
1940 | else | |
1941 | mcp251xfd_clks_and_vdd_disable(priv); | |
55e5b97f MKB |
1942 | } |
1943 | ||
eb79a267 | 1944 | static const struct of_device_id mcp251xfd_of_match[] = { |
55e5b97f MKB |
1945 | { |
1946 | .compatible = "microchip,mcp2517fd", | |
eb79a267 | 1947 | .data = &mcp251xfd_devtype_data_mcp2517fd, |
55e5b97f MKB |
1948 | }, { |
1949 | .compatible = "microchip,mcp2518fd", | |
eb79a267 | 1950 | .data = &mcp251xfd_devtype_data_mcp2518fd, |
c6f2a617 MKB |
1951 | }, { |
1952 | .compatible = "microchip,mcp251863", | |
1953 | .data = &mcp251xfd_devtype_data_mcp251863, | |
55e5b97f | 1954 | }, { |
dba1572c | 1955 | .compatible = "microchip,mcp251xfd", |
eb79a267 | 1956 | .data = &mcp251xfd_devtype_data_mcp251xfd, |
55e5b97f MKB |
1957 | }, { |
1958 | /* sentinel */ | |
1959 | }, | |
1960 | }; | |
eb79a267 | 1961 | MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); |
55e5b97f | 1962 | |
eb79a267 | 1963 | static const struct spi_device_id mcp251xfd_id_table[] = { |
55e5b97f MKB |
1964 | { |
1965 | .name = "mcp2517fd", | |
eb79a267 | 1966 | .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, |
55e5b97f MKB |
1967 | }, { |
1968 | .name = "mcp2518fd", | |
eb79a267 | 1969 | .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, |
c6f2a617 MKB |
1970 | }, { |
1971 | .name = "mcp251863", | |
1972 | .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863, | |
55e5b97f | 1973 | }, { |
dba1572c | 1974 | .name = "mcp251xfd", |
eb79a267 | 1975 | .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, |
55e5b97f MKB |
1976 | }, { |
1977 | /* sentinel */ | |
1978 | }, | |
1979 | }; | |
eb79a267 | 1980 | MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); |
55e5b97f | 1981 | |
eb79a267 | 1982 | static int mcp251xfd_probe(struct spi_device *spi) |
55e5b97f MKB |
1983 | { |
1984 | const void *match; | |
1985 | struct net_device *ndev; | |
eb79a267 | 1986 | struct mcp251xfd_priv *priv; |
55e5b97f MKB |
1987 | struct gpio_desc *rx_int; |
1988 | struct regulator *reg_vdd, *reg_xceiver; | |
1989 | struct clk *clk; | |
2a68dd86 | 1990 | bool pll_enable = false; |
74f89cf1 | 1991 | u32 freq = 0; |
55e5b97f MKB |
1992 | int err; |
1993 | ||
1a1c436b MKB |
1994 | if (!spi->irq) |
1995 | return dev_err_probe(&spi->dev, -ENXIO, | |
1996 | "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); | |
1997 | ||
55e5b97f MKB |
1998 | rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", |
1999 | GPIOD_IN); | |
cf8ee6de MKB |
2000 | if (IS_ERR(rx_int)) |
2001 | return dev_err_probe(&spi->dev, PTR_ERR(rx_int), | |
2002 | "Failed to get RX-INT!\n"); | |
55e5b97f MKB |
2003 | |
2004 | reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); | |
cf8ee6de | 2005 | if (PTR_ERR(reg_vdd) == -ENODEV) |
55e5b97f MKB |
2006 | reg_vdd = NULL; |
2007 | else if (IS_ERR(reg_vdd)) | |
cf8ee6de MKB |
2008 | return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd), |
2009 | "Failed to get VDD regulator!\n"); | |
55e5b97f MKB |
2010 | |
2011 | reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); | |
cf8ee6de | 2012 | if (PTR_ERR(reg_xceiver) == -ENODEV) |
55e5b97f MKB |
2013 | reg_xceiver = NULL; |
2014 | else if (IS_ERR(reg_xceiver)) | |
cf8ee6de MKB |
2015 | return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver), |
2016 | "Failed to get Transceiver regulator!\n"); | |
55e5b97f | 2017 | |
74f89cf1 | 2018 | clk = devm_clk_get_optional(&spi->dev, NULL); |
cf8ee6de | 2019 | if (IS_ERR(clk)) |
4cc7faa4 DC |
2020 | return dev_err_probe(&spi->dev, PTR_ERR(clk), |
2021 | "Failed to get Oscillator (clock)!\n"); | |
74f89cf1 AS |
2022 | if (clk) { |
2023 | freq = clk_get_rate(clk); | |
2024 | } else { | |
2025 | err = device_property_read_u32(&spi->dev, "clock-frequency", | |
2026 | &freq); | |
2027 | if (err) | |
2028 | return dev_err_probe(&spi->dev, err, | |
2029 | "Failed to get clock-frequency!\n"); | |
2030 | } | |
55e5b97f MKB |
2031 | |
2032 | /* Sanity check */ | |
eb79a267 MKB |
2033 | if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || |
2034 | freq > MCP251XFD_SYSCLOCK_HZ_MAX) { | |
55e5b97f MKB |
2035 | dev_err(&spi->dev, |
2036 | "Oscillator frequency (%u Hz) is too low or high.\n", | |
2037 | freq); | |
2038 | return -ERANGE; | |
2039 | } | |
2040 | ||
2a68dd86 MKB |
2041 | if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) |
2042 | pll_enable = true; | |
55e5b97f | 2043 | |
eb79a267 MKB |
2044 | ndev = alloc_candev(sizeof(struct mcp251xfd_priv), |
2045 | MCP251XFD_TX_OBJ_NUM_MAX); | |
55e5b97f MKB |
2046 | if (!ndev) |
2047 | return -ENOMEM; | |
2048 | ||
2049 | SET_NETDEV_DEV(ndev, &spi->dev); | |
2050 | ||
eb79a267 | 2051 | ndev->netdev_ops = &mcp251xfd_netdev_ops; |
55e5b97f MKB |
2052 | ndev->irq = spi->irq; |
2053 | ndev->flags |= IFF_ECHO; | |
2054 | ||
2055 | priv = netdev_priv(ndev); | |
2056 | spi_set_drvdata(spi, priv); | |
2057 | priv->can.clock.freq = freq; | |
2a68dd86 MKB |
2058 | if (pll_enable) |
2059 | priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER; | |
eb79a267 MKB |
2060 | priv->can.do_set_mode = mcp251xfd_set_mode; |
2061 | priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; | |
2062 | priv->can.bittiming_const = &mcp251xfd_bittiming_const; | |
2063 | priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; | |
ee42bedc MS |
2064 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | |
2065 | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | | |
86f1e3b1 MKB |
2066 | CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO | |
2067 | CAN_CTRLMODE_CC_LEN8_DLC; | |
60a848c5 | 2068 | set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); |
55e5b97f MKB |
2069 | priv->ndev = ndev; |
2070 | priv->spi = spi; | |
2071 | priv->rx_int = rx_int; | |
2072 | priv->clk = clk; | |
2a68dd86 | 2073 | priv->pll_enable = pll_enable; |
55e5b97f MKB |
2074 | priv->reg_vdd = reg_vdd; |
2075 | priv->reg_xceiver = reg_xceiver; | |
2076 | ||
2077 | match = device_get_match_data(&spi->dev); | |
2078 | if (match) | |
eb79a267 | 2079 | priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; |
55e5b97f | 2080 | else |
eb79a267 | 2081 | priv->devtype_data = *(struct mcp251xfd_devtype_data *) |
55e5b97f MKB |
2082 | spi_get_device_id(spi)->driver_data; |
2083 | ||
f5b84ded | 2084 | /* Errata Reference: |
28eb119c | 2085 | * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4. |
f5b84ded TK |
2086 | * |
2087 | * The SPI can write corrupted data to the RAM at fast SPI | |
2088 | * speeds: | |
2089 | * | |
2090 | * Simultaneous activity on the CAN bus while writing data to | |
2091 | * RAM via the SPI interface, with high SCK frequency, can | |
2092 | * lead to corrupted data being written to RAM. | |
2093 | * | |
2094 | * Fix/Work Around: | |
2095 | * Ensure that FSCK is less than or equal to 0.85 * | |
2096 | * (FSYSCLK/2). | |
55e5b97f | 2097 | * |
01b2a0e5 | 2098 | * Known good combinations are: |
55e5b97f | 2099 | * |
01b2a0e5 | 2100 | * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config |
55e5b97f | 2101 | * |
01b2a0e5 MKB |
2102 | * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> |
2103 | * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> | |
2104 | * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default | |
2105 | * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default | |
9f1fbc1c | 2106 | * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default |
01b2a0e5 | 2107 | * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> |
55e5b97f | 2108 | * |
55e5b97f MKB |
2109 | */ |
2110 | priv->spi_max_speed_hz_orig = spi->max_speed_hz; | |
2a68dd86 MKB |
2111 | priv->spi_max_speed_hz_slow = min(spi->max_speed_hz, |
2112 | freq / 2 / 1000 * 850); | |
2113 | if (priv->pll_enable) | |
2114 | priv->spi_max_speed_hz_fast = min(spi->max_speed_hz, | |
2115 | freq * | |
2116 | MCP251XFD_OSC_PLL_MULTIPLIER / | |
2117 | 2 / 1000 * 850); | |
2118 | else | |
2119 | priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow; | |
2120 | spi->max_speed_hz = priv->spi_max_speed_hz_slow; | |
55e5b97f MKB |
2121 | spi->bits_per_word = 8; |
2122 | spi->rt = true; | |
2123 | err = spi_setup(spi); | |
2124 | if (err) | |
2125 | goto out_free_candev; | |
2126 | ||
eb79a267 | 2127 | err = mcp251xfd_regmap_init(priv); |
55e5b97f MKB |
2128 | if (err) |
2129 | goto out_free_candev; | |
2130 | ||
2131 | err = can_rx_offload_add_manual(ndev, &priv->offload, | |
eb79a267 | 2132 | MCP251XFD_NAPI_WEIGHT); |
55e5b97f MKB |
2133 | if (err) |
2134 | goto out_free_candev; | |
2135 | ||
eb79a267 | 2136 | err = mcp251xfd_register(priv); |
197656de MKB |
2137 | if (err) { |
2138 | dev_err_probe(&spi->dev, err, "Failed to detect %s.\n", | |
2139 | mcp251xfd_get_model_str(priv)); | |
4376ea42 | 2140 | goto out_can_rx_offload_del; |
197656de | 2141 | } |
55e5b97f MKB |
2142 | |
2143 | return 0; | |
2144 | ||
4376ea42 MKB |
2145 | out_can_rx_offload_del: |
2146 | can_rx_offload_del(&priv->offload); | |
55e5b97f MKB |
2147 | out_free_candev: |
2148 | spi->max_speed_hz = priv->spi_max_speed_hz_orig; | |
2149 | ||
2150 | free_candev(ndev); | |
2151 | ||
2152 | return err; | |
2153 | } | |
2154 | ||
a0386bba | 2155 | static void mcp251xfd_remove(struct spi_device *spi) |
55e5b97f | 2156 | { |
eb79a267 | 2157 | struct mcp251xfd_priv *priv = spi_get_drvdata(spi); |
55e5b97f MKB |
2158 | struct net_device *ndev = priv->ndev; |
2159 | ||
2160 | can_rx_offload_del(&priv->offload); | |
eb79a267 | 2161 | mcp251xfd_unregister(priv); |
55e5b97f MKB |
2162 | spi->max_speed_hz = priv->spi_max_speed_hz_orig; |
2163 | free_candev(ndev); | |
55e5b97f MKB |
2164 | } |
2165 | ||
eb79a267 | 2166 | static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) |
55e5b97f | 2167 | { |
eb79a267 | 2168 | const struct mcp251xfd_priv *priv = dev_get_drvdata(device); |
55e5b97f | 2169 | |
eb79a267 | 2170 | return mcp251xfd_clks_and_vdd_disable(priv); |
55e5b97f MKB |
2171 | } |
2172 | ||
eb79a267 | 2173 | static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) |
55e5b97f | 2174 | { |
eb79a267 | 2175 | const struct mcp251xfd_priv *priv = dev_get_drvdata(device); |
55e5b97f | 2176 | |
eb79a267 | 2177 | return mcp251xfd_clks_and_vdd_enable(priv); |
55e5b97f MKB |
2178 | } |
2179 | ||
eb79a267 MKB |
2180 | static const struct dev_pm_ops mcp251xfd_pm_ops = { |
2181 | SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, | |
2182 | mcp251xfd_runtime_resume, NULL) | |
55e5b97f MKB |
2183 | }; |
2184 | ||
eb79a267 | 2185 | static struct spi_driver mcp251xfd_driver = { |
55e5b97f MKB |
2186 | .driver = { |
2187 | .name = DEVICE_NAME, | |
eb79a267 MKB |
2188 | .pm = &mcp251xfd_pm_ops, |
2189 | .of_match_table = mcp251xfd_of_match, | |
55e5b97f | 2190 | }, |
eb79a267 MKB |
2191 | .probe = mcp251xfd_probe, |
2192 | .remove = mcp251xfd_remove, | |
2193 | .id_table = mcp251xfd_id_table, | |
55e5b97f | 2194 | }; |
eb79a267 | 2195 | module_spi_driver(mcp251xfd_driver); |
55e5b97f MKB |
2196 | |
2197 | MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); | |
f4f77366 | 2198 | MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); |
55e5b97f | 2199 | MODULE_LICENSE("GPL v2"); |