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aaa7cb26 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2b61972b SG |
2 | /* |
3 | * Copyright (C) 2010-2012 Stephane Grosjean <s.grosjean@peak-system.com> | |
4 | * | |
5 | * CAN driver for PEAK-System PCAN-PC Card | |
6 | * Derived from the PCAN project file driver/src/pcan_pccard.c | |
7 | * Copyright (C) 2006-2010 PEAK System-Technik GmbH | |
2b61972b SG |
8 | */ |
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/netdevice.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/io.h> | |
16 | #include <pcmcia/cistpl.h> | |
17 | #include <pcmcia/ds.h> | |
18 | #include <linux/can.h> | |
19 | #include <linux/can/dev.h> | |
20 | #include "sja1000.h" | |
21 | ||
22 | MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); | |
23 | MODULE_DESCRIPTION("CAN driver for PEAK-System PCAN-PC Cards"); | |
24 | MODULE_LICENSE("GPL v2"); | |
25 | MODULE_SUPPORTED_DEVICE("PEAK PCAN-PC Card"); | |
26 | ||
27 | /* PEAK-System PCMCIA driver name */ | |
28 | #define PCC_NAME "peak_pcmcia" | |
29 | ||
30 | #define PCC_CHAN_MAX 2 | |
31 | ||
32 | #define PCC_CAN_CLOCK (16000000 / 2) | |
33 | ||
34 | #define PCC_MANF_ID 0x0377 | |
35 | #define PCC_CARD_ID 0x0001 | |
36 | ||
37 | #define PCC_CHAN_SIZE 0x20 | |
38 | #define PCC_CHAN_OFF(c) ((c) * PCC_CHAN_SIZE) | |
39 | #define PCC_COMN_OFF (PCC_CHAN_OFF(PCC_CHAN_MAX)) | |
40 | #define PCC_COMN_SIZE 0x40 | |
41 | ||
42 | /* common area registers */ | |
43 | #define PCC_CCR 0x00 | |
44 | #define PCC_CSR 0x02 | |
45 | #define PCC_CPR 0x04 | |
46 | #define PCC_SPI_DIR 0x06 | |
47 | #define PCC_SPI_DOR 0x08 | |
48 | #define PCC_SPI_ADR 0x0a | |
49 | #define PCC_SPI_IR 0x0c | |
50 | #define PCC_FW_MAJOR 0x10 | |
51 | #define PCC_FW_MINOR 0x12 | |
52 | ||
53 | /* CCR bits */ | |
54 | #define PCC_CCR_CLK_16 0x00 | |
55 | #define PCC_CCR_CLK_10 0x01 | |
56 | #define PCC_CCR_CLK_21 0x02 | |
57 | #define PCC_CCR_CLK_8 0x03 | |
58 | #define PCC_CCR_CLK_MASK PCC_CCR_CLK_8 | |
59 | ||
60 | #define PCC_CCR_RST_CHAN(c) (0x01 << ((c) + 2)) | |
61 | #define PCC_CCR_RST_ALL (PCC_CCR_RST_CHAN(0) | PCC_CCR_RST_CHAN(1)) | |
62 | #define PCC_CCR_RST_MASK PCC_CCR_RST_ALL | |
63 | ||
64 | /* led selection bits */ | |
65 | #define PCC_LED(c) (1 << (c)) | |
66 | #define PCC_LED_ALL (PCC_LED(0) | PCC_LED(1)) | |
67 | ||
68 | /* led state value */ | |
69 | #define PCC_LED_ON 0x00 | |
70 | #define PCC_LED_FAST 0x01 | |
71 | #define PCC_LED_SLOW 0x02 | |
72 | #define PCC_LED_OFF 0x03 | |
73 | ||
74 | #define PCC_CCR_LED_CHAN(s, c) ((s) << (((c) + 2) << 1)) | |
75 | ||
76 | #define PCC_CCR_LED_ON_CHAN(c) PCC_CCR_LED_CHAN(PCC_LED_ON, c) | |
77 | #define PCC_CCR_LED_FAST_CHAN(c) PCC_CCR_LED_CHAN(PCC_LED_FAST, c) | |
78 | #define PCC_CCR_LED_SLOW_CHAN(c) PCC_CCR_LED_CHAN(PCC_LED_SLOW, c) | |
79 | #define PCC_CCR_LED_OFF_CHAN(c) PCC_CCR_LED_CHAN(PCC_LED_OFF, c) | |
80 | #define PCC_CCR_LED_MASK_CHAN(c) PCC_CCR_LED_OFF_CHAN(c) | |
81 | #define PCC_CCR_LED_OFF_ALL (PCC_CCR_LED_OFF_CHAN(0) | \ | |
82 | PCC_CCR_LED_OFF_CHAN(1)) | |
83 | #define PCC_CCR_LED_MASK PCC_CCR_LED_OFF_ALL | |
84 | ||
85 | #define PCC_CCR_INIT (PCC_CCR_CLK_16 | PCC_CCR_RST_ALL | PCC_CCR_LED_OFF_ALL) | |
86 | ||
87 | /* CSR bits */ | |
88 | #define PCC_CSR_SPI_BUSY 0x04 | |
89 | ||
90 | /* time waiting for SPI busy (prevent from infinite loop) */ | |
91 | #define PCC_SPI_MAX_BUSY_WAIT_MS 3 | |
92 | ||
93 | /* max count of reading the SPI status register waiting for a change */ | |
94 | /* (prevent from infinite loop) */ | |
95 | #define PCC_WRITE_MAX_LOOP 1000 | |
96 | ||
97 | /* max nb of int handled by that isr in one shot (prevent from infinite loop) */ | |
98 | #define PCC_ISR_MAX_LOOP 10 | |
99 | ||
100 | /* EEPROM chip instruction set */ | |
101 | /* note: EEPROM Read/Write instructions include A8 bit */ | |
102 | #define PCC_EEP_WRITE(a) (0x02 | (((a) & 0x100) >> 5)) | |
103 | #define PCC_EEP_READ(a) (0x03 | (((a) & 0x100) >> 5)) | |
104 | #define PCC_EEP_WRDI 0x04 /* EEPROM Write Disable */ | |
105 | #define PCC_EEP_RDSR 0x05 /* EEPROM Read Status Register */ | |
106 | #define PCC_EEP_WREN 0x06 /* EEPROM Write Enable */ | |
107 | ||
108 | /* EEPROM Status Register bits */ | |
109 | #define PCC_EEP_SR_WEN 0x02 /* EEPROM SR Write Enable bit */ | |
110 | #define PCC_EEP_SR_WIP 0x01 /* EEPROM SR Write In Progress bit */ | |
111 | ||
112 | /* | |
113 | * The board configuration is probably following: | |
114 | * RX1 is connected to ground. | |
115 | * TX1 is not connected. | |
116 | * CLKO is not connected. | |
117 | * Setting the OCR register to 0xDA is a good idea. | |
118 | * This means normal output mode, push-pull and the correct polarity. | |
119 | */ | |
120 | #define PCC_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) | |
121 | ||
122 | /* | |
123 | * In the CDR register, you should set CBP to 1. | |
124 | * You will probably also want to set the clock divider value to 7 | |
125 | * (meaning direct oscillator output) because the second SJA1000 chip | |
126 | * is driven by the first one CLKOUT output. | |
127 | */ | |
128 | #define PCC_CDR (CDR_CBP | CDR_CLKOUT_MASK) | |
129 | ||
130 | struct pcan_channel { | |
131 | struct net_device *netdev; | |
132 | unsigned long prev_rx_bytes; | |
133 | unsigned long prev_tx_bytes; | |
134 | }; | |
135 | ||
136 | /* PCAN-PC Card private structure */ | |
137 | struct pcan_pccard { | |
138 | struct pcmcia_device *pdev; | |
139 | int chan_count; | |
140 | struct pcan_channel channel[PCC_CHAN_MAX]; | |
141 | u8 ccr; | |
142 | u8 fw_major; | |
143 | u8 fw_minor; | |
144 | void __iomem *ioport_addr; | |
145 | struct timer_list led_timer; | |
146 | }; | |
147 | ||
148 | static struct pcmcia_device_id pcan_table[] = { | |
149 | PCMCIA_DEVICE_MANF_CARD(PCC_MANF_ID, PCC_CARD_ID), | |
150 | PCMCIA_DEVICE_NULL, | |
151 | }; | |
152 | ||
153 | MODULE_DEVICE_TABLE(pcmcia, pcan_table); | |
154 | ||
155 | static void pcan_set_leds(struct pcan_pccard *card, u8 mask, u8 state); | |
156 | ||
157 | /* | |
158 | * start timer which controls leds state | |
159 | */ | |
160 | static void pcan_start_led_timer(struct pcan_pccard *card) | |
161 | { | |
162 | if (!timer_pending(&card->led_timer)) | |
163 | mod_timer(&card->led_timer, jiffies + HZ); | |
164 | } | |
165 | ||
166 | /* | |
167 | * stop the timer which controls leds state | |
168 | */ | |
169 | static void pcan_stop_led_timer(struct pcan_pccard *card) | |
170 | { | |
171 | del_timer_sync(&card->led_timer); | |
172 | } | |
173 | ||
174 | /* | |
175 | * read a sja1000 register | |
176 | */ | |
177 | static u8 pcan_read_canreg(const struct sja1000_priv *priv, int port) | |
178 | { | |
179 | return ioread8(priv->reg_base + port); | |
180 | } | |
181 | ||
182 | /* | |
183 | * write a sja1000 register | |
184 | */ | |
185 | static void pcan_write_canreg(const struct sja1000_priv *priv, int port, u8 v) | |
186 | { | |
187 | struct pcan_pccard *card = priv->priv; | |
188 | int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE; | |
189 | ||
190 | /* sja1000 register changes control the leds state */ | |
06e1d1d7 | 191 | if (port == SJA1000_MOD) |
2b61972b SG |
192 | switch (v) { |
193 | case MOD_RM: | |
194 | /* Reset Mode: set led on */ | |
195 | pcan_set_leds(card, PCC_LED(c), PCC_LED_ON); | |
196 | break; | |
197 | case 0x00: | |
198 | /* Normal Mode: led slow blinking and start led timer */ | |
199 | pcan_set_leds(card, PCC_LED(c), PCC_LED_SLOW); | |
200 | pcan_start_led_timer(card); | |
201 | break; | |
202 | default: | |
203 | break; | |
204 | } | |
205 | ||
206 | iowrite8(v, priv->reg_base + port); | |
207 | } | |
208 | ||
209 | /* | |
210 | * read a register from the common area | |
211 | */ | |
212 | static u8 pcan_read_reg(struct pcan_pccard *card, int port) | |
213 | { | |
214 | return ioread8(card->ioport_addr + PCC_COMN_OFF + port); | |
215 | } | |
216 | ||
217 | /* | |
218 | * write a register into the common area | |
219 | */ | |
220 | static void pcan_write_reg(struct pcan_pccard *card, int port, u8 v) | |
221 | { | |
222 | /* cache ccr value */ | |
223 | if (port == PCC_CCR) { | |
224 | if (card->ccr == v) | |
225 | return; | |
226 | card->ccr = v; | |
227 | } | |
228 | ||
229 | iowrite8(v, card->ioport_addr + PCC_COMN_OFF + port); | |
230 | } | |
231 | ||
232 | /* | |
233 | * check whether the card is present by checking its fw version numbers | |
234 | * against values read at probing time. | |
235 | */ | |
236 | static inline int pcan_pccard_present(struct pcan_pccard *card) | |
237 | { | |
238 | return ((pcan_read_reg(card, PCC_FW_MAJOR) == card->fw_major) && | |
239 | (pcan_read_reg(card, PCC_FW_MINOR) == card->fw_minor)); | |
240 | } | |
241 | ||
242 | /* | |
243 | * wait for SPI engine while it is busy | |
244 | */ | |
245 | static int pcan_wait_spi_busy(struct pcan_pccard *card) | |
246 | { | |
247 | unsigned long timeout = jiffies + | |
248 | msecs_to_jiffies(PCC_SPI_MAX_BUSY_WAIT_MS) + 1; | |
249 | ||
250 | /* be sure to read status at least once after sleeping */ | |
251 | while (pcan_read_reg(card, PCC_CSR) & PCC_CSR_SPI_BUSY) { | |
252 | if (time_after(jiffies, timeout)) | |
253 | return -EBUSY; | |
254 | schedule(); | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | /* | |
261 | * write data in device eeprom | |
262 | */ | |
263 | static int pcan_write_eeprom(struct pcan_pccard *card, u16 addr, u8 v) | |
264 | { | |
265 | u8 status; | |
266 | int err, i; | |
267 | ||
268 | /* write instruction enabling write */ | |
269 | pcan_write_reg(card, PCC_SPI_IR, PCC_EEP_WREN); | |
270 | err = pcan_wait_spi_busy(card); | |
271 | if (err) | |
272 | goto we_spi_err; | |
273 | ||
274 | /* wait until write enabled */ | |
275 | for (i = 0; i < PCC_WRITE_MAX_LOOP; i++) { | |
276 | /* write instruction reading the status register */ | |
277 | pcan_write_reg(card, PCC_SPI_IR, PCC_EEP_RDSR); | |
278 | err = pcan_wait_spi_busy(card); | |
279 | if (err) | |
280 | goto we_spi_err; | |
281 | ||
282 | /* get status register value and check write enable bit */ | |
283 | status = pcan_read_reg(card, PCC_SPI_DIR); | |
284 | if (status & PCC_EEP_SR_WEN) | |
285 | break; | |
286 | } | |
287 | ||
288 | if (i >= PCC_WRITE_MAX_LOOP) { | |
289 | dev_err(&card->pdev->dev, | |
290 | "stop waiting to be allowed to write in eeprom\n"); | |
291 | return -EIO; | |
292 | } | |
293 | ||
294 | /* set address and data */ | |
295 | pcan_write_reg(card, PCC_SPI_ADR, addr & 0xff); | |
296 | pcan_write_reg(card, PCC_SPI_DOR, v); | |
297 | ||
298 | /* | |
299 | * write instruction with bit[3] set according to address value: | |
300 | * if addr refers to upper half of the memory array: bit[3] = 1 | |
301 | */ | |
302 | pcan_write_reg(card, PCC_SPI_IR, PCC_EEP_WRITE(addr)); | |
303 | err = pcan_wait_spi_busy(card); | |
304 | if (err) | |
305 | goto we_spi_err; | |
306 | ||
307 | /* wait while write in progress */ | |
308 | for (i = 0; i < PCC_WRITE_MAX_LOOP; i++) { | |
309 | /* write instruction reading the status register */ | |
310 | pcan_write_reg(card, PCC_SPI_IR, PCC_EEP_RDSR); | |
311 | err = pcan_wait_spi_busy(card); | |
312 | if (err) | |
313 | goto we_spi_err; | |
314 | ||
315 | /* get status register value and check write in progress bit */ | |
316 | status = pcan_read_reg(card, PCC_SPI_DIR); | |
317 | if (!(status & PCC_EEP_SR_WIP)) | |
318 | break; | |
319 | } | |
320 | ||
321 | if (i >= PCC_WRITE_MAX_LOOP) { | |
322 | dev_err(&card->pdev->dev, | |
323 | "stop waiting for write in eeprom to complete\n"); | |
324 | return -EIO; | |
325 | } | |
326 | ||
327 | /* write instruction disabling write */ | |
328 | pcan_write_reg(card, PCC_SPI_IR, PCC_EEP_WRDI); | |
329 | err = pcan_wait_spi_busy(card); | |
330 | if (err) | |
331 | goto we_spi_err; | |
332 | ||
333 | return 0; | |
334 | ||
335 | we_spi_err: | |
336 | dev_err(&card->pdev->dev, | |
337 | "stop waiting (spi engine always busy) err %d\n", err); | |
338 | ||
339 | return err; | |
340 | } | |
341 | ||
342 | static void pcan_set_leds(struct pcan_pccard *card, u8 led_mask, u8 state) | |
343 | { | |
344 | u8 ccr = card->ccr; | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < card->chan_count; i++) | |
348 | if (led_mask & PCC_LED(i)) { | |
349 | /* clear corresponding led bits in ccr */ | |
350 | ccr &= ~PCC_CCR_LED_MASK_CHAN(i); | |
351 | /* then set new bits */ | |
352 | ccr |= PCC_CCR_LED_CHAN(state, i); | |
353 | } | |
354 | ||
355 | /* real write only if something has changed in ccr */ | |
356 | pcan_write_reg(card, PCC_CCR, ccr); | |
357 | } | |
358 | ||
359 | /* | |
360 | * enable/disable CAN connectors power | |
361 | */ | |
362 | static inline void pcan_set_can_power(struct pcan_pccard *card, int onoff) | |
363 | { | |
364 | int err; | |
365 | ||
366 | err = pcan_write_eeprom(card, 0, !!onoff); | |
367 | if (err) | |
368 | dev_err(&card->pdev->dev, | |
369 | "failed setting power %s to can connectors (err %d)\n", | |
370 | (onoff) ? "on" : "off", err); | |
371 | } | |
372 | ||
373 | /* | |
374 | * set leds state according to channel activity | |
375 | */ | |
550acfb3 | 376 | static void pcan_led_timer(struct timer_list *t) |
2b61972b | 377 | { |
550acfb3 | 378 | struct pcan_pccard *card = from_timer(card, t, led_timer); |
2b61972b SG |
379 | struct net_device *netdev; |
380 | int i, up_count = 0; | |
381 | u8 ccr; | |
382 | ||
383 | ccr = card->ccr; | |
384 | for (i = 0; i < card->chan_count; i++) { | |
385 | /* default is: not configured */ | |
386 | ccr &= ~PCC_CCR_LED_MASK_CHAN(i); | |
387 | ccr |= PCC_CCR_LED_ON_CHAN(i); | |
388 | ||
389 | netdev = card->channel[i].netdev; | |
390 | if (!netdev || !(netdev->flags & IFF_UP)) | |
391 | continue; | |
392 | ||
393 | up_count++; | |
394 | ||
395 | /* no activity (but configured) */ | |
396 | ccr &= ~PCC_CCR_LED_MASK_CHAN(i); | |
397 | ccr |= PCC_CCR_LED_SLOW_CHAN(i); | |
398 | ||
399 | /* if bytes counters changed, set fast blinking led */ | |
400 | if (netdev->stats.rx_bytes != card->channel[i].prev_rx_bytes) { | |
401 | card->channel[i].prev_rx_bytes = netdev->stats.rx_bytes; | |
402 | ccr &= ~PCC_CCR_LED_MASK_CHAN(i); | |
403 | ccr |= PCC_CCR_LED_FAST_CHAN(i); | |
404 | } | |
405 | if (netdev->stats.tx_bytes != card->channel[i].prev_tx_bytes) { | |
406 | card->channel[i].prev_tx_bytes = netdev->stats.tx_bytes; | |
407 | ccr &= ~PCC_CCR_LED_MASK_CHAN(i); | |
408 | ccr |= PCC_CCR_LED_FAST_CHAN(i); | |
409 | } | |
410 | } | |
411 | ||
412 | /* write the new leds state */ | |
413 | pcan_write_reg(card, PCC_CCR, ccr); | |
414 | ||
415 | /* restart timer (except if no more configured channels) */ | |
416 | if (up_count) | |
417 | mod_timer(&card->led_timer, jiffies + HZ); | |
418 | } | |
419 | ||
420 | /* | |
421 | * interrupt service routine | |
422 | */ | |
423 | static irqreturn_t pcan_isr(int irq, void *dev_id) | |
424 | { | |
425 | struct pcan_pccard *card = dev_id; | |
426 | int irq_handled; | |
427 | ||
428 | /* prevent from infinite loop */ | |
429 | for (irq_handled = 0; irq_handled < PCC_ISR_MAX_LOOP; irq_handled++) { | |
430 | /* handle shared interrupt and next loop */ | |
431 | int nothing_to_handle = 1; | |
432 | int i; | |
433 | ||
434 | /* check interrupt for each channel */ | |
435 | for (i = 0; i < card->chan_count; i++) { | |
436 | struct net_device *netdev; | |
437 | ||
438 | /* | |
439 | * check whether the card is present before calling | |
440 | * sja1000_interrupt() to speed up hotplug detection | |
441 | */ | |
442 | if (!pcan_pccard_present(card)) { | |
443 | /* card unplugged during isr */ | |
444 | return IRQ_NONE; | |
445 | } | |
446 | ||
447 | /* | |
448 | * should check whether all or SJA1000_MAX_IRQ | |
449 | * interrupts have been handled: loop again to be sure. | |
450 | */ | |
451 | netdev = card->channel[i].netdev; | |
452 | if (netdev && | |
453 | sja1000_interrupt(irq, netdev) == IRQ_HANDLED) | |
454 | nothing_to_handle = 0; | |
455 | } | |
456 | ||
457 | if (nothing_to_handle) | |
458 | break; | |
459 | } | |
460 | ||
461 | return (irq_handled) ? IRQ_HANDLED : IRQ_NONE; | |
462 | } | |
463 | ||
464 | /* | |
465 | * free all resources used by the channels and switch off leds and can power | |
466 | */ | |
467 | static void pcan_free_channels(struct pcan_pccard *card) | |
468 | { | |
469 | int i; | |
470 | u8 led_mask = 0; | |
471 | ||
472 | for (i = 0; i < card->chan_count; i++) { | |
473 | struct net_device *netdev; | |
474 | char name[IFNAMSIZ]; | |
475 | ||
476 | led_mask |= PCC_LED(i); | |
477 | ||
478 | netdev = card->channel[i].netdev; | |
479 | if (!netdev) | |
480 | continue; | |
481 | ||
cd28aa2e | 482 | strlcpy(name, netdev->name, IFNAMSIZ); |
2b61972b SG |
483 | |
484 | unregister_sja1000dev(netdev); | |
485 | ||
486 | free_sja1000dev(netdev); | |
487 | ||
488 | dev_info(&card->pdev->dev, "%s removed\n", name); | |
489 | } | |
490 | ||
491 | /* do it only if device not removed */ | |
492 | if (pcan_pccard_present(card)) { | |
493 | pcan_set_leds(card, led_mask, PCC_LED_OFF); | |
494 | pcan_set_can_power(card, 0); | |
495 | } | |
496 | } | |
497 | ||
498 | /* | |
499 | * check if a CAN controller is present at the specified location | |
500 | */ | |
501 | static inline int pcan_channel_present(struct sja1000_priv *priv) | |
502 | { | |
503 | /* make sure SJA1000 is in reset mode */ | |
06e1d1d7 OH |
504 | pcan_write_canreg(priv, SJA1000_MOD, 1); |
505 | pcan_write_canreg(priv, SJA1000_CDR, CDR_PELICAN); | |
2b61972b SG |
506 | |
507 | /* read reset-values */ | |
06e1d1d7 | 508 | if (pcan_read_canreg(priv, SJA1000_CDR) == CDR_PELICAN) |
2b61972b SG |
509 | return 1; |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static int pcan_add_channels(struct pcan_pccard *card) | |
515 | { | |
516 | struct pcmcia_device *pdev = card->pdev; | |
517 | int i, err = 0; | |
518 | u8 ccr = PCC_CCR_INIT; | |
519 | ||
520 | /* init common registers (reset channels and leds off) */ | |
521 | card->ccr = ~ccr; | |
522 | pcan_write_reg(card, PCC_CCR, ccr); | |
523 | ||
524 | /* wait 2ms before unresetting channels */ | |
c8d4dea2 | 525 | usleep_range(2000, 3000); |
2b61972b SG |
526 | |
527 | ccr &= ~PCC_CCR_RST_ALL; | |
528 | pcan_write_reg(card, PCC_CCR, ccr); | |
529 | ||
530 | /* create one network device per channel detected */ | |
531 | for (i = 0; i < ARRAY_SIZE(card->channel); i++) { | |
532 | struct net_device *netdev; | |
533 | struct sja1000_priv *priv; | |
534 | ||
535 | netdev = alloc_sja1000dev(0); | |
536 | if (!netdev) { | |
537 | err = -ENOMEM; | |
538 | break; | |
539 | } | |
540 | ||
541 | /* update linkages */ | |
542 | priv = netdev_priv(netdev); | |
543 | priv->priv = card; | |
544 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
3e66d013 | 545 | netdev->dev_id = i; |
2b61972b SG |
546 | |
547 | priv->irq_flags = IRQF_SHARED; | |
548 | netdev->irq = pdev->irq; | |
549 | priv->reg_base = card->ioport_addr + PCC_CHAN_OFF(i); | |
550 | ||
551 | /* check if channel is present */ | |
552 | if (!pcan_channel_present(priv)) { | |
553 | dev_err(&pdev->dev, "channel %d not present\n", i); | |
554 | free_sja1000dev(netdev); | |
555 | continue; | |
556 | } | |
557 | ||
558 | priv->read_reg = pcan_read_canreg; | |
559 | priv->write_reg = pcan_write_canreg; | |
560 | priv->can.clock.freq = PCC_CAN_CLOCK; | |
561 | priv->ocr = PCC_OCR; | |
562 | priv->cdr = PCC_CDR; | |
563 | ||
564 | /* Neither a slave device distributes the clock */ | |
565 | if (i > 0) | |
566 | priv->cdr |= CDR_CLK_OFF; | |
567 | ||
568 | priv->flags |= SJA1000_CUSTOM_IRQ_HANDLER; | |
569 | ||
570 | /* register SJA1000 device */ | |
571 | err = register_sja1000dev(netdev); | |
572 | if (err) { | |
573 | free_sja1000dev(netdev); | |
574 | continue; | |
575 | } | |
576 | ||
577 | card->channel[i].netdev = netdev; | |
578 | card->chan_count++; | |
579 | ||
580 | /* set corresponding led on in the new ccr */ | |
581 | ccr &= ~PCC_CCR_LED_OFF_CHAN(i); | |
582 | ||
583 | dev_info(&pdev->dev, | |
584 | "%s on channel %d at 0x%p irq %d\n", | |
585 | netdev->name, i, priv->reg_base, pdev->irq); | |
586 | } | |
587 | ||
588 | /* write new ccr (change leds state) */ | |
589 | pcan_write_reg(card, PCC_CCR, ccr); | |
590 | ||
591 | return err; | |
592 | } | |
593 | ||
594 | static int pcan_conf_check(struct pcmcia_device *pdev, void *priv_data) | |
595 | { | |
596 | pdev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH; | |
597 | pdev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8; /* only */ | |
598 | pdev->io_lines = 10; | |
599 | ||
600 | /* This reserves IO space but doesn't actually enable it */ | |
601 | return pcmcia_request_io(pdev); | |
602 | } | |
603 | ||
604 | /* | |
605 | * free all resources used by the device | |
606 | */ | |
607 | static void pcan_free(struct pcmcia_device *pdev) | |
608 | { | |
609 | struct pcan_pccard *card = pdev->priv; | |
610 | ||
611 | if (!card) | |
612 | return; | |
613 | ||
614 | free_irq(pdev->irq, card); | |
615 | pcan_stop_led_timer(card); | |
616 | ||
617 | pcan_free_channels(card); | |
618 | ||
619 | ioport_unmap(card->ioport_addr); | |
620 | ||
621 | kfree(card); | |
622 | pdev->priv = NULL; | |
623 | } | |
624 | ||
625 | /* | |
626 | * setup PCMCIA socket and probe for PEAK-System PC-CARD | |
627 | */ | |
3c8ac0f2 | 628 | static int pcan_probe(struct pcmcia_device *pdev) |
2b61972b SG |
629 | { |
630 | struct pcan_pccard *card; | |
631 | int err; | |
632 | ||
633 | pdev->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO; | |
634 | ||
635 | err = pcmcia_loop_config(pdev, pcan_conf_check, NULL); | |
636 | if (err) { | |
637 | dev_err(&pdev->dev, "pcmcia_loop_config() error %d\n", err); | |
638 | goto probe_err_1; | |
639 | } | |
640 | ||
641 | if (!pdev->irq) { | |
642 | dev_err(&pdev->dev, "no irq assigned\n"); | |
643 | err = -ENODEV; | |
644 | goto probe_err_1; | |
645 | } | |
646 | ||
647 | err = pcmcia_enable_device(pdev); | |
648 | if (err) { | |
649 | dev_err(&pdev->dev, "pcmcia_enable_device failed err=%d\n", | |
650 | err); | |
651 | goto probe_err_1; | |
652 | } | |
653 | ||
654 | card = kzalloc(sizeof(struct pcan_pccard), GFP_KERNEL); | |
655 | if (!card) { | |
2b61972b SG |
656 | err = -ENOMEM; |
657 | goto probe_err_2; | |
658 | } | |
659 | ||
660 | card->pdev = pdev; | |
661 | pdev->priv = card; | |
662 | ||
663 | /* sja1000 api uses iomem */ | |
664 | card->ioport_addr = ioport_map(pdev->resource[0]->start, | |
665 | resource_size(pdev->resource[0])); | |
666 | if (!card->ioport_addr) { | |
667 | dev_err(&pdev->dev, "couldn't map io port into io memory\n"); | |
668 | err = -ENOMEM; | |
669 | goto probe_err_3; | |
670 | } | |
671 | card->fw_major = pcan_read_reg(card, PCC_FW_MAJOR); | |
672 | card->fw_minor = pcan_read_reg(card, PCC_FW_MINOR); | |
673 | ||
674 | /* display board name and firware version */ | |
675 | dev_info(&pdev->dev, "PEAK-System pcmcia card %s fw %d.%d\n", | |
676 | pdev->prod_id[1] ? pdev->prod_id[1] : "PCAN-PC Card", | |
677 | card->fw_major, card->fw_minor); | |
678 | ||
679 | /* detect available channels */ | |
680 | pcan_add_channels(card); | |
ba9b6f9f PST |
681 | if (!card->chan_count) { |
682 | err = -ENOMEM; | |
2b61972b | 683 | goto probe_err_4; |
ba9b6f9f | 684 | } |
2b61972b SG |
685 | |
686 | /* init the timer which controls the leds */ | |
550acfb3 | 687 | timer_setup(&card->led_timer, pcan_led_timer, 0); |
2b61972b SG |
688 | |
689 | /* request the given irq */ | |
690 | err = request_irq(pdev->irq, &pcan_isr, IRQF_SHARED, PCC_NAME, card); | |
691 | if (err) { | |
692 | dev_err(&pdev->dev, "couldn't request irq%d\n", pdev->irq); | |
693 | goto probe_err_5; | |
694 | } | |
695 | ||
696 | /* power on the connectors */ | |
697 | pcan_set_can_power(card, 1); | |
698 | ||
699 | return 0; | |
700 | ||
701 | probe_err_5: | |
702 | /* unregister can devices from network */ | |
703 | pcan_free_channels(card); | |
704 | ||
705 | probe_err_4: | |
706 | ioport_unmap(card->ioport_addr); | |
707 | ||
708 | probe_err_3: | |
709 | kfree(card); | |
710 | pdev->priv = NULL; | |
711 | ||
712 | probe_err_2: | |
713 | pcmcia_disable_device(pdev); | |
714 | ||
715 | probe_err_1: | |
716 | return err; | |
717 | } | |
718 | ||
719 | /* | |
720 | * release claimed resources | |
721 | */ | |
722 | static void pcan_remove(struct pcmcia_device *pdev) | |
723 | { | |
724 | pcan_free(pdev); | |
725 | pcmcia_disable_device(pdev); | |
726 | } | |
727 | ||
728 | static struct pcmcia_driver pcan_driver = { | |
729 | .name = PCC_NAME, | |
730 | .probe = pcan_probe, | |
731 | .remove = pcan_remove, | |
732 | .id_table = pcan_table, | |
733 | }; | |
fdd3f29e | 734 | module_pcmcia_driver(pcan_driver); |