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pch_can: Comment optimization
[linux-2.6-block.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
e91530ea 3 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
b21d18b5
MO		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
0a80410d
T		 35#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
36#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
37#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
38#define PCH_CTRL_CCE BIT(6)
39#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
40#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
41#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
42
086b5650
T		 43#define PCH_CMASK_RX_TX_SET 0x00f3
44#define PCH_CMASK_RX_TX_GET 0x0073
45#define PCH_CMASK_ALL 0xff
0a80410d
T		 46#define PCH_CMASK_NEWDAT BIT(2)
47#define PCH_CMASK_CLRINTPND BIT(3)
48#define PCH_CMASK_CTRL BIT(4)
49#define PCH_CMASK_ARB BIT(5)
50#define PCH_CMASK_MASK BIT(6)
51#define PCH_CMASK_RDWR BIT(7)
52#define PCH_IF_MCONT_NEWDAT BIT(15)
53#define PCH_IF_MCONT_MSGLOST BIT(14)
54#define PCH_IF_MCONT_INTPND BIT(13)
55#define PCH_IF_MCONT_UMASK BIT(12)
56#define PCH_IF_MCONT_TXIE BIT(11)
57#define PCH_IF_MCONT_RXIE BIT(10)
58#define PCH_IF_MCONT_RMTEN BIT(9)
59#define PCH_IF_MCONT_TXRQXT BIT(8)
60#define PCH_IF_MCONT_EOB BIT(7)
61#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
62#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
63#define PCH_ID2_DIR BIT(13)
64#define PCH_ID2_XTD BIT(14)
65#define PCH_ID_MSGVAL BIT(15)
66#define PCH_IF_CREQ_BUSY BIT(15)
086b5650
T		 67
68#define PCH_STATUS_INT 0x8000
69#define PCH_REC 0x00007f00
70#define PCH_TEC 0x000000ff
b21d18b5 71
0a80410d
T		 72#define PCH_TX_OK BIT(3)
73#define PCH_RX_OK BIT(4)
74#define PCH_EPASSIV BIT(5)
75#define PCH_EWARN BIT(6)
76#define PCH_BUS_OFF BIT(7)
b21d18b5
MO		 77
78/* bit position of certain controller bits. */
bd58cbc3
T		 79#define PCH_BIT_BRP_SHIFT 0
80#define PCH_BIT_SJW_SHIFT 6
81#define PCH_BIT_TSEG1_SHIFT 8
82#define PCH_BIT_TSEG2_SHIFT 12
83#define PCH_BIT_BRPE_BRPE_SHIFT 6
84
086b5650
T		 85#define PCH_MSK_BITT_BRP 0x3f
86#define PCH_MSK_BRPE_BRPE 0x3c0
87#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
88#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 89
90#define PCH_CAN_CLK 50000000 /* 50MHz */
91
9388b166
T		 92/*
93 * Define the number of message object.
b21d18b5 94 * PCH CAN communications are done via Message RAM.
9388b166
T		 95 * The Message RAM consists of 32 message objects.
96 */
15ffc8fd
T		 97#define PCH_RX_OBJ_NUM 26
98#define PCH_TX_OBJ_NUM 6
99#define PCH_RX_OBJ_START 1
100#define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
101#define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
102#define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
b21d18b5
MO		 103
104#define PCH_FIFO_THRESH 16
105
76d94b23
T		 106/* TxRqst2 show status of MsgObjNo.17~32 */
107#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
108 (PCH_RX_OBJ_END - 16))
109
8339a7ed
T		 110enum pch_ifreg {
111 PCH_RX_IFREG,
112 PCH_TX_IFREG,
113};
114
d68f6837
T		 115enum pch_can_err {
116 PCH_STUF_ERR = 1,
117 PCH_FORM_ERR,
118 PCH_ACK_ERR,
119 PCH_BIT1_ERR,
120 PCH_BIT0_ERR,
121 PCH_CRC_ERR,
122 PCH_LEC_ALL,
123};
124
b21d18b5
MO		 125enum pch_can_mode {
126 PCH_CAN_ENABLE,
127 PCH_CAN_DISABLE,
128 PCH_CAN_ALL,
129 PCH_CAN_NONE,
130 PCH_CAN_STOP,
9388b166 131 PCH_CAN_RUN,
b21d18b5
MO		 132};
133
8339a7ed
T		 134struct pch_can_if_regs {
135 u32 creq;
136 u32 cmask;
137 u32 mask1;
138 u32 mask2;
139 u32 id1;
140 u32 id2;
141 u32 mcont;
8ac9702b 142 u32 data[4];
8339a7ed
T		 143 u32 rsv[13];
144};
145
b21d18b5
MO		 146struct pch_can_regs {
147 u32 cont;
148 u32 stat;
149 u32 errc;
150 u32 bitt;
151 u32 intr;
152 u32 opt;
153 u32 brpe;
8339a7ed
T		 154 u32 reserve;
155 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
156 u32 reserve1[8];
b21d18b5
MO		 157 u32 treq1;
158 u32 treq2;
8339a7ed
T		 159 u32 reserve2[6];
160 u32 data1;
161 u32 data2;
162 u32 reserve3[6];
163 u32 canipend1;
164 u32 canipend2;
165 u32 reserve4[6];
166 u32 canmval1;
167 u32 canmval2;
168 u32 reserve5[37];
b21d18b5
MO		 169 u32 srst;
170};
171
172struct pch_can_priv {
173 struct can_priv can;
b21d18b5 174 struct pci_dev *dev;
bd58cbc3
T		 175 u32 tx_enable[PCH_TX_OBJ_END];
176 u32 rx_enable[PCH_TX_OBJ_END];
177 u32 rx_link[PCH_TX_OBJ_END];
178 u32 int_enables;
b21d18b5 179 struct net_device *ndev;
b21d18b5
MO		 180 struct pch_can_regs __iomem *regs;
181 struct napi_struct napi;
bd58cbc3
T		 182 int tx_obj; /* Point next Tx Obj index */
183 int use_msi;
b21d18b5
MO		 184};
185
186static struct can_bittiming_const pch_can_bittiming_const = {
187 .name = KBUILD_MODNAME,
188 .tseg1_min = 1,
189 .tseg1_max = 16,
190 .tseg2_min = 1,
191 .tseg2_max = 8,
192 .sjw_max = 4,
193 .brp_min = 1,
194 .brp_max = 1024, /* 6bit + extended 4bit */
195 .brp_inc = 1,
196};
197
198static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
199 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
200 {0,}
201};
202MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
203
526de53c 204static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 205{
206 iowrite32(ioread32(addr) | mask, addr);
207}
208
526de53c 209static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 210{
211 iowrite32(ioread32(addr) & ~mask, addr);
212}
213
214static void pch_can_set_run_mode(struct pch_can_priv *priv,
215 enum pch_can_mode mode)
216{
217 switch (mode) {
218 case PCH_CAN_RUN:
086b5650 219 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 220 break;
221
222 case PCH_CAN_STOP:
086b5650 223 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 224 break;
225
226 default:
435b4efe 227 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
b21d18b5
MO		 228 break;
229 }
230}
231
232static void pch_can_set_optmode(struct pch_can_priv *priv)
233{
234 u32 reg_val = ioread32(&priv->regs->opt);
235
236 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 237 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 238
239 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 240 reg_val |= PCH_OPT_LBACK;
b21d18b5 241
086b5650 242 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 243 iowrite32(reg_val, &priv->regs->opt);
244}
245
bd58cbc3
T		 246static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
247{
248 int counter = PCH_COUNTER_LIMIT;
249 u32 ifx_creq;
250
251 iowrite32(num, creq_addr);
252 while (counter) {
253 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
254 if (!ifx_creq)
255 break;
256 counter--;
257 udelay(1);
258 }
259 if (!counter)
260 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
261}
262
b21d18b5
MO		 263static void pch_can_set_int_enables(struct pch_can_priv *priv,
264 enum pch_can_mode interrupt_no)
265{
266 switch (interrupt_no) {
b21d18b5 267 case PCH_CAN_DISABLE:
086b5650 268 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 269 break;
270
271 case PCH_CAN_ALL:
086b5650 272 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 273 break;
274
275 case PCH_CAN_NONE:
086b5650 276 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 277 break;
278
279 default:
435b4efe 280 netdev_err(priv->ndev, "Invalid interrupt number.\n");
b21d18b5
MO		 281 break;
282 }
283}
284
8339a7ed 285static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
bd58cbc3 286 int set, enum pch_ifreg dir)
b21d18b5 287{
8339a7ed
T		 288 u32 ie;
289
290 if (dir)
291 ie = PCH_IF_MCONT_TXIE;
292 else
293 ie = PCH_IF_MCONT_RXIE;
b21d18b5 294
c7551456 295 /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
8339a7ed 296 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 297 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5 298
9388b166 299 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
086b5650 300 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 301 &priv->regs->ifregs[dir].cmask);
b21d18b5 302
bd58cbc3 303 if (set) {
9388b166 304 /* Setting the MsgVal and RxIE/TxIE bits */
8339a7ed
T		 305 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
306 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
bd58cbc3 307 } else {
9388b166 308 /* Clearing the MsgVal and RxIE/TxIE bits */
8339a7ed
T		 309 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
310 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5
MO		 311 }
312
bd58cbc3 313 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 314}
315
bd58cbc3 316static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 317{
318 int i;
319
320 /* Traversing to obtain the object configured as receivers. */
15ffc8fd
T		 321 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
322 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
b21d18b5
MO		 323}
324
bd58cbc3 325static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
b21d18b5
MO		 326{
327 int i;
328
329 /* Traversing to obtain the object configured as transmit object. */
15ffc8fd
T		 330 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
331 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
b21d18b5
MO		 332}
333
bd58cbc3 334static u32 pch_can_int_pending(struct pch_can_priv *priv)
b21d18b5
MO		 335{
336 return ioread32(&priv->regs->intr) & 0xffff;
337}
338
bd58cbc3 339static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
b21d18b5 340{
bd58cbc3 341 int i; /* Msg Obj ID (1~32) */
b21d18b5 342
bd58cbc3 343 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
8339a7ed
T		 344 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
345 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
346 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
347 iowrite32(0x0, &priv->regs->ifregs[0].id1);
348 iowrite32(0x0, &priv->regs->ifregs[0].id2);
349 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
8ac9702b
T		 350 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
351 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
352 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
353 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
086b5650
T		 354 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
355 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 356 &priv->regs->ifregs[0].cmask);
bd58cbc3 357 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5
MO		 358 }
359}
360
361static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
362{
363 int i;
b21d18b5 364
15ffc8fd 365 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
9388b166 366 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 367 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
b21d18b5 368
15ffc8fd
T		 369 iowrite32(0x0, &priv->regs->ifregs[0].id1);
370 iowrite32(0x0, &priv->regs->ifregs[0].id2);
b21d18b5 371
15ffc8fd
T		 372 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
373 PCH_IF_MCONT_UMASK);
b21d18b5 374
15ffc8fd
T		 375 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
376 if (i == PCH_RX_OBJ_END)
377 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
bd58cbc3
T		 378 PCH_IF_MCONT_EOB);
379 else
380 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 381 PCH_IF_MCONT_EOB);
b21d18b5 382
15ffc8fd
T		 383 iowrite32(0, &priv->regs->ifregs[0].mask1);
384 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
385 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5 386
15ffc8fd 387 /* Setting CMASK for writing */
9388b166
T		 388 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
389 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
b21d18b5 390
bd58cbc3 391 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
15ffc8fd 392 }
b21d18b5 393
15ffc8fd 394 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
9388b166 395 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
bd58cbc3 396 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 397
15ffc8fd
T		 398 /* Resetting DIR bit for reception */
399 iowrite32(0x0, &priv->regs->ifregs[1].id1);
44c9aa89 400 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
b21d18b5 401
15ffc8fd 402 /* Setting EOB bit for transmitter */
44c9aa89
T		 403 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
404 &priv->regs->ifregs[1].mcont);
15ffc8fd
T		 405
406 iowrite32(0, &priv->regs->ifregs[1].mask1);
407 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
408
409 /* Setting CMASK for writing */
9388b166
T		 410 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
411 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
15ffc8fd 412
bd58cbc3 413 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
b21d18b5 414 }
b21d18b5
MO		 415}
416
417static void pch_can_init(struct pch_can_priv *priv)
418{
419 /* Stopping the Can device. */
420 pch_can_set_run_mode(priv, PCH_CAN_STOP);
421
422 /* Clearing all the message object buffers. */
bd58cbc3 423 pch_can_clear_if_buffers(priv);
b21d18b5
MO		 424
425 /* Configuring the respective message object as either rx/tx object. */
426 pch_can_config_rx_tx_buffers(priv);
427
428 /* Enabling the interrupts. */
429 pch_can_set_int_enables(priv, PCH_CAN_ALL);
430}
431
432static void pch_can_release(struct pch_can_priv *priv)
433{
434 /* Stooping the CAN device. */
435 pch_can_set_run_mode(priv, PCH_CAN_STOP);
436
437 /* Disabling the interrupts. */
438 pch_can_set_int_enables(priv, PCH_CAN_NONE);
439
440 /* Disabling all the receive object. */
8339a7ed 441 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 442
443 /* Disabling all the transmit object. */
8339a7ed 444 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 445}
446
447/* This function clears interrupt(s) from the CAN device. */
448static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
449{
b21d18b5 450 /* Clear interrupt for transmit object */
15ffc8fd
T		 451 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
452 /* Setting CMASK for clearing the reception interrupts. */
453 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
454 &priv->regs->ifregs[0].cmask);
455
456 /* Clearing the Dir bit. */
457 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
458
459 /* Clearing NewDat & IntPnd */
460 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
461 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
462
bd58cbc3 463 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
15ffc8fd 464 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
9388b166
T		 465 /*
466 * Setting CMASK for clearing interrupts for frame transmission.
467 */
086b5650 468 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 469 &priv->regs->ifregs[1].cmask);
b21d18b5
MO		 470
471 /* Resetting the ID registers. */
8339a7ed 472 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 473 PCH_ID2_DIR | (0x7ff << 2));
8339a7ed 474 iowrite32(0x0, &priv->regs->ifregs[1].id1);
b21d18b5
MO		 475
476 /* Claring NewDat, TxRqst & IntPnd */
8339a7ed 477 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 478 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
479 PCH_IF_MCONT_TXRQXT);
bd58cbc3 480 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
b21d18b5
MO		 481 }
482}
483
b21d18b5
MO		 484static void pch_can_reset(struct pch_can_priv *priv)
485{
486 /* write to sw reset register */
487 iowrite32(1, &priv->regs->srst);
488 iowrite32(0, &priv->regs->srst);
489}
490
491static void pch_can_error(struct net_device *ndev, u32 status)
492{
493 struct sk_buff *skb;
494 struct pch_can_priv *priv = netdev_priv(ndev);
495 struct can_frame *cf;
d68f6837 496 u32 errc, lec;
b21d18b5
MO		 497 struct net_device_stats *stats = &(priv->ndev->stats);
498 enum can_state state = priv->can.state;
499
500 skb = alloc_can_err_skb(ndev, &cf);
501 if (!skb)
502 return;
503
504 if (status & PCH_BUS_OFF) {
8339a7ed
T		 505 pch_can_set_tx_all(priv, 0);
506 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 507 state = CAN_STATE_BUS_OFF;
508 cf->can_id |= CAN_ERR_BUSOFF;
509 can_bus_off(ndev);
b21d18b5
MO		 510 }
511
44c9aa89 512 errc = ioread32(&priv->regs->errc);
b21d18b5
MO		 513 /* Warning interrupt. */
514 if (status & PCH_EWARN) {
515 state = CAN_STATE_ERROR_WARNING;
516 priv->can.can_stats.error_warning++;
517 cf->can_id |= CAN_ERR_CRTL;
086b5650 518 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 519 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 520 if ((errc & PCH_TEC) > 96)
b21d18b5 521 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
435b4efe 522 netdev_dbg(ndev,
b21d18b5
MO		 523 "%s -> Error Counter is more than 96.\n", __func__);
524 }
525 /* Error passive interrupt. */
526 if (status & PCH_EPASSIV) {
527 priv->can.can_stats.error_passive++;
528 state = CAN_STATE_ERROR_PASSIVE;
529 cf->can_id |= CAN_ERR_CRTL;
086b5650 530 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 531 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 532 if ((errc & PCH_TEC) > 127)
b21d18b5 533 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
435b4efe 534 netdev_dbg(ndev,
b21d18b5
MO		 535 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
536 }
537
d68f6837
T		 538 lec = status & PCH_LEC_ALL;
539 switch (lec) {
540 case PCH_STUF_ERR:
541 cf->data[2] |= CAN_ERR_PROT_STUFF;
b21d18b5
MO		 542 priv->can.can_stats.bus_error++;
543 stats->rx_errors++;
d68f6837
T		 544 break;
545 case PCH_FORM_ERR:
546 cf->data[2] |= CAN_ERR_PROT_FORM;
547 priv->can.can_stats.bus_error++;
548 stats->rx_errors++;
549 break;
550 case PCH_ACK_ERR:
551 cf->can_id |= CAN_ERR_ACK;
552 priv->can.can_stats.bus_error++;
553 stats->rx_errors++;
554 break;
555 case PCH_BIT1_ERR:
556 case PCH_BIT0_ERR:
557 cf->data[2] |= CAN_ERR_PROT_BIT;
558 priv->can.can_stats.bus_error++;
559 stats->rx_errors++;
560 break;
561 case PCH_CRC_ERR:
562 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
563 CAN_ERR_PROT_LOC_CRC_DEL;
564 priv->can.can_stats.bus_error++;
565 stats->rx_errors++;
566 break;
567 case PCH_LEC_ALL: /* Written by CPU. No error status */
568 break;
b21d18b5
MO		 569 }
570
571 priv->can.state = state;
572 netif_rx(skb);
573
574 stats->rx_packets++;
575 stats->rx_bytes += cf->can_dlc;
576}
577
578static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
579{
580 struct net_device *ndev = (struct net_device *)dev_id;
581 struct pch_can_priv *priv = netdev_priv(ndev);
582
583 pch_can_set_int_enables(priv, PCH_CAN_NONE);
b21d18b5
MO		 584 napi_schedule(&priv->napi);
585
586 return IRQ_HANDLED;
587}
588
1d5b4b27
T		 589static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
590{
591 if (obj_id < PCH_FIFO_THRESH) {
592 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
593 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
594
595 /* Clearing the Dir bit. */
596 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
597
598 /* Clearing NewDat & IntPnd */
599 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
600 PCH_IF_MCONT_INTPND);
bd58cbc3 601 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 602 } else if (obj_id > PCH_FIFO_THRESH) {
603 pch_can_int_clr(priv, obj_id);
604 } else if (obj_id == PCH_FIFO_THRESH) {
605 int cnt;
606 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
607 pch_can_int_clr(priv, cnt + 1);
608 }
609}
610
611static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
612{
613 struct pch_can_priv *priv = netdev_priv(ndev);
614 struct net_device_stats *stats = &(priv->ndev->stats);
615 struct sk_buff *skb;
616 struct can_frame *cf;
617
618 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
619 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
620 PCH_IF_MCONT_MSGLOST);
621 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
622 &priv->regs->ifregs[0].cmask);
bd58cbc3 623 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
1d5b4b27
T		 624
625 skb = alloc_can_err_skb(ndev, &cf);
626 if (!skb)
627 return;
628
629 cf->can_id |= CAN_ERR_CRTL;
630 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
631 stats->rx_over_errors++;
632 stats->rx_errors++;
633
634 netif_receive_skb(skb);
635}
636
637static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
b21d18b5
MO		 638{
639 u32 reg;
640 canid_t id;
b21d18b5
MO		 641 int rcv_pkts = 0;
642 struct sk_buff *skb;
643 struct can_frame *cf;
644 struct pch_can_priv *priv = netdev_priv(ndev);
645 struct net_device_stats *stats = &(priv->ndev->stats);
1d5b4b27
T		 646 int i;
647 u32 id2;
8ac9702b 648 u16 data_reg;
b21d18b5 649
1d5b4b27
T		 650 do {
651 /* Reading the messsage object from the Message RAM */
652 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 653 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
b21d18b5 654
1d5b4b27
T		 655 /* Reading the MCONT register. */
656 reg = ioread32(&priv->regs->ifregs[0].mcont);
657
658 if (reg & PCH_IF_MCONT_EOB)
659 break;
b21d18b5 660
b21d18b5 661 /* If MsgLost bit set. */
086b5650 662 if (reg & PCH_IF_MCONT_MSGLOST) {
1d5b4b27 663 pch_can_rx_msg_lost(ndev, obj_num);
b21d18b5 664 rcv_pkts++;
1d5b4b27
T		 665 quota--;
666 obj_num++;
667 continue;
668 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
669 obj_num++;
670 continue;
b21d18b5 671 }
b21d18b5
MO		 672
673 skb = alloc_can_skb(priv->ndev, &cf);
674 if (!skb)
675 return -ENOMEM;
676
677 /* Get Received data */
1d5b4b27
T		 678 id2 = ioread32(&priv->regs->ifregs[0].id2);
679 if (id2 & PCH_ID2_XTD) {
8339a7ed 680 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
1d5b4b27
T		 681 id |= (((id2) & 0x1fff) << 16);
682 cf->can_id = id | CAN_EFF_FLAG;
b21d18b5 683 } else {
1d5b4b27
T		 684 id = (id2 >> 2) & CAN_SFF_MASK;
685 cf->can_id = id;
b21d18b5
MO		 686 }
687
1d5b4b27 688 if (id2 & PCH_ID2_DIR)
b21d18b5 689 cf->can_id |= CAN_RTR_FLAG;
1d5b4b27
T		 690
691 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
692 ifregs[0].mcont)) & 0xF);
b21d18b5 693
8ac9702b
T		 694 for (i = 0; i < cf->can_dlc; i += 2) {
695 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
696 cf->data[i] = data_reg;
697 cf->data[i + 1] = data_reg >> 8;
b21d18b5
MO		 698 }
699
700 netif_receive_skb(skb);
701 rcv_pkts++;
702 stats->rx_packets++;
1d5b4b27 703 quota--;
b21d18b5
MO		 704 stats->rx_bytes += cf->can_dlc;
705
1d5b4b27
T		 706 pch_fifo_thresh(priv, obj_num);
707 obj_num++;
708 } while (quota > 0);
b21d18b5
MO		 709
710 return rcv_pkts;
711}
e489cceb
T		 712
713static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
b21d18b5 714{
b21d18b5
MO		 715 struct pch_can_priv *priv = netdev_priv(ndev);
716 struct net_device_stats *stats = &(priv->ndev->stats);
717 u32 dlc;
e489cceb
T		 718
719 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
720 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
721 &priv->regs->ifregs[1].cmask);
bd58cbc3 722 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
e489cceb
T		 723 dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
724 PCH_IF_MCONT_DLC);
725 stats->tx_bytes += dlc;
726 stats->tx_packets++;
727 if (int_stat == PCH_TX_OBJ_END)
728 netif_wake_queue(ndev);
729}
730
bd58cbc3 731static int pch_can_poll(struct napi_struct *napi, int quota)
e489cceb
T		 732{
733 struct net_device *ndev = napi->dev;
734 struct pch_can_priv *priv = netdev_priv(ndev);
b21d18b5
MO		 735 u32 int_stat;
736 int rcv_pkts = 0;
737 u32 reg_stat;
b21d18b5
MO		 738
739 int_stat = pch_can_int_pending(priv);
740 if (!int_stat)
e489cceb 741 goto end;
b21d18b5 742
8714fcac 743 if (int_stat == PCH_STATUS_INT) {
b21d18b5
MO		 744 reg_stat = ioread32(&priv->regs->stat);
745 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
e489cceb
T		 746 if (reg_stat & PCH_BUS_OFF ||
747 (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
b21d18b5 748 pch_can_error(ndev, reg_stat);
e489cceb
T		 749 quota--;
750 }
b21d18b5
MO		 751 }
752
e489cceb 753 if (reg_stat & PCH_TX_OK)
b21d18b5 754 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
b21d18b5
MO		 755
756 if (reg_stat & PCH_RX_OK)
757 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
758
759 int_stat = pch_can_int_pending(priv);
b21d18b5
MO		 760 }
761
e489cceb
T		 762 if (quota == 0)
763 goto end;
764
15ffc8fd 765 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
1d5b4b27 766 rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
e489cceb
T		 767 quota -= rcv_pkts;
768 if (quota < 0)
769 goto end;
15ffc8fd
T		 770 } else if ((int_stat >= PCH_TX_OBJ_START) &&
771 (int_stat <= PCH_TX_OBJ_END)) {
772 /* Handle transmission interrupt */
e489cceb 773 pch_can_tx_complete(ndev, int_stat);
b21d18b5
MO		 774 }
775
e489cceb 776end:
b21d18b5
MO		 777 napi_complete(napi);
778 pch_can_set_int_enables(priv, PCH_CAN_ALL);
779
780 return rcv_pkts;
781}
782
783static int pch_set_bittiming(struct net_device *ndev)
784{
785 struct pch_can_priv *priv = netdev_priv(ndev);
786 const struct can_bittiming *bt = &priv->can.bittiming;
787 u32 canbit;
788 u32 bepe;
b21d18b5
MO		 789
790 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 791 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5 792
0e0805c4 793 canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
bd58cbc3
T		 794 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
795 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
796 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
0e0805c4 797 bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
b21d18b5
MO		 798 iowrite32(canbit, &priv->regs->bitt);
799 iowrite32(bepe, &priv->regs->brpe);
086b5650 800 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 801
802 return 0;
803}
804
805static void pch_can_start(struct net_device *ndev)
806{
807 struct pch_can_priv *priv = netdev_priv(ndev);
808
809 if (priv->can.state != CAN_STATE_STOPPED)
810 pch_can_reset(priv);
811
812 pch_set_bittiming(ndev);
813 pch_can_set_optmode(priv);
814
8339a7ed
T		 815 pch_can_set_tx_all(priv, 1);
816 pch_can_set_rx_all(priv, 1);
b21d18b5
MO		 817
818 /* Setting the CAN to run mode. */
819 pch_can_set_run_mode(priv, PCH_CAN_RUN);
820
821 priv->can.state = CAN_STATE_ERROR_ACTIVE;
822
823 return;
824}
825
826static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
827{
828 int ret = 0;
829
830 switch (mode) {
831 case CAN_MODE_START:
832 pch_can_start(ndev);
833 netif_wake_queue(ndev);
834 break;
835 default:
836 ret = -EOPNOTSUPP;
837 break;
838 }
839
840 return ret;
841}
842
843static int pch_can_open(struct net_device *ndev)
844{
845 struct pch_can_priv *priv = netdev_priv(ndev);
846 int retval;
847
848 retval = pci_enable_msi(priv->dev);
849 if (retval) {
435b4efe 850 netdev_err(ndev, "PCH CAN opened without MSI\n");
b21d18b5
MO		 851 priv->use_msi = 0;
852 } else {
435b4efe 853 netdev_err(ndev, "PCH CAN opened with MSI\n");
b21d18b5
MO		 854 priv->use_msi = 1;
855 }
856
c7551456 857 /* Regstering the interrupt. */
b21d18b5
MO		 858 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
859 ndev->name, ndev);
860 if (retval) {
435b4efe 861 netdev_err(ndev, "request_irq failed.\n");
b21d18b5
MO		 862 goto req_irq_err;
863 }
864
865 /* Open common can device */
866 retval = open_candev(ndev);
867 if (retval) {
435b4efe 868 netdev_err(ndev, "open_candev() failed %d\n", retval);
b21d18b5
MO		 869 goto err_open_candev;
870 }
871
872 pch_can_init(priv);
873 pch_can_start(ndev);
874 napi_enable(&priv->napi);
875 netif_start_queue(ndev);
876
877 return 0;
878
879err_open_candev:
880 free_irq(priv->dev->irq, ndev);
881req_irq_err:
882 if (priv->use_msi)
883 pci_disable_msi(priv->dev);
884
885 pch_can_release(priv);
886
887 return retval;
888}
889
890static int pch_close(struct net_device *ndev)
891{
892 struct pch_can_priv *priv = netdev_priv(ndev);
893
894 netif_stop_queue(ndev);
895 napi_disable(&priv->napi);
896 pch_can_release(priv);
897 free_irq(priv->dev->irq, ndev);
898 if (priv->use_msi)
899 pci_disable_msi(priv->dev);
900 close_candev(ndev);
901 priv->can.state = CAN_STATE_STOPPED;
902 return 0;
903}
904
b21d18b5
MO		 905static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
906{
b21d18b5
MO		 907 struct pch_can_priv *priv = netdev_priv(ndev);
908 struct can_frame *cf = (struct can_frame *)skb->data;
bd58cbc3 909 int tx_obj_no;
8ac9702b 910 int i;
44c9aa89 911 u32 id2;
b21d18b5
MO		 912
913 if (can_dropped_invalid_skb(ndev, skb))
914 return NETDEV_TX_OK;
915
76d94b23
T		 916 if (priv->tx_obj == PCH_TX_OBJ_END) {
917 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
918 netif_stop_queue(ndev);
b21d18b5 919
bd58cbc3 920 tx_obj_no = priv->tx_obj;
76d94b23 921 priv->tx_obj = PCH_TX_OBJ_START;
b21d18b5 922 } else {
bd58cbc3 923 tx_obj_no = priv->tx_obj;
76d94b23 924 priv->tx_obj++;
b21d18b5 925 }
b21d18b5 926
b21d18b5 927 /* Setting the CMASK register. */
8339a7ed 928 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
b21d18b5
MO		 929
930 /* If ID extended is set. */
b21d18b5 931 if (cf->can_id & CAN_EFF_FLAG) {
44c9aa89
T		 932 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
933 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
b21d18b5 934 } else {
44c9aa89
T		 935 iowrite32(0, &priv->regs->ifregs[1].id1);
936 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
b21d18b5
MO		 937 }
938
44c9aa89
T		 939 id2 |= PCH_ID_MSGVAL;
940
b21d18b5
MO		 941 /* If remote frame has to be transmitted.. */
942 if (cf->can_id & CAN_RTR_FLAG)
44c9aa89
T		 943 id2 &= ~PCH_ID2_DIR;
944 else
945 id2 |= PCH_ID2_DIR;
946
947 iowrite32(id2, &priv->regs->ifregs[1].id2);
b21d18b5 948
8ac9702b
T		 949 /* Copy data to register */
950 for (i = 0; i < cf->can_dlc; i += 2) {
951 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
952 &priv->regs->ifregs[1].data[i / 2]);
b21d18b5
MO		 953 }
954
bd58cbc3 955 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
b21d18b5 956
c7551456 957 /* Set the size of the data. Update if2_mcont */
44c9aa89
T		 958 iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
959 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
b21d18b5 960
bd58cbc3 961 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
b21d18b5 962
b21d18b5
MO		 963 return NETDEV_TX_OK;
964}
965
966static const struct net_device_ops pch_can_netdev_ops = {
967 .ndo_open = pch_can_open,
968 .ndo_stop = pch_close,
969 .ndo_start_xmit = pch_xmit,
970};
971
972static void __devexit pch_can_remove(struct pci_dev *pdev)
973{
974 struct net_device *ndev = pci_get_drvdata(pdev);
975 struct pch_can_priv *priv = netdev_priv(ndev);
976
977 unregister_candev(priv->ndev);
978 free_candev(priv->ndev);
979 pci_iounmap(pdev, priv->regs);
980 pci_release_regions(pdev);
981 pci_disable_device(pdev);
982 pci_set_drvdata(pdev, NULL);
983 pch_can_reset(priv);
984}
985
986#ifdef CONFIG_PM
7f2bc50e
T		 987static void pch_can_set_int_custom(struct pch_can_priv *priv)
988{
989 /* Clearing the IE, SIE and EIE bits of Can control register. */
990 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
991
992 /* Appropriately setting them. */
993 pch_can_bit_set(&priv->regs->cont,
994 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
995}
996
997/* This function retrieves interrupt enabled for the CAN device. */
ca2b004e 998static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
7f2bc50e
T		 999{
1000 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
ca2b004e 1001 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
7f2bc50e
T		 1002}
1003
1004static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
1005 enum pch_ifreg dir)
1006{
1007 u32 ie, enable;
1008
1009 if (dir)
1010 ie = PCH_IF_MCONT_RXIE;
1011 else
1012 ie = PCH_IF_MCONT_TXIE;
1013
1014 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
bd58cbc3 1015 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
7f2bc50e
T		 1016
1017 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
9388b166 1018 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
7f2bc50e 1019 enable = 1;
9388b166 1020 else
7f2bc50e 1021 enable = 0;
9388b166 1022
7f2bc50e
T		 1023 return enable;
1024}
1025
1026static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
bd58cbc3 1027 u32 buffer_num, int set)
7f2bc50e
T		 1028{
1029 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1030 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1031 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1032 &priv->regs->ifregs[0].cmask);
bd58cbc3 1033 if (set)
7f2bc50e
T		 1034 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1035 PCH_IF_MCONT_EOB);
1036 else
1037 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1038
bd58cbc3 1039 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1040}
1041
ca2b004e 1042static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
7f2bc50e 1043{
ca2b004e
T		 1044 u32 link;
1045
7f2bc50e 1046 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
bd58cbc3 1047 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
7f2bc50e
T		 1048
1049 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
ca2b004e 1050 link = 0;
7f2bc50e 1051 else
ca2b004e
T		 1052 link = 1;
1053 return link;
7f2bc50e
T		 1054}
1055
1056static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1057{
1058 return (ioread32(&priv->regs->treq1) & 0xffff) |
bd58cbc3 1059 (ioread32(&priv->regs->treq2) << 16);
7f2bc50e
T		 1060}
1061
b21d18b5
MO		 1062static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1063{
c7551456
T		 1064 int i;
1065 int retval;
b21d18b5 1066 u32 buf_stat; /* Variable for reading the transmit buffer status. */
bd58cbc3 1067 int counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 1068
1069 struct net_device *dev = pci_get_drvdata(pdev);
1070 struct pch_can_priv *priv = netdev_priv(dev);
1071
1072 /* Stop the CAN controller */
1073 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1074
1075 /* Indicate that we are aboutto/in suspend */
d06848be 1076 priv->can.state = CAN_STATE_STOPPED;
b21d18b5
MO		 1077
1078 /* Waiting for all transmission to complete. */
1079 while (counter) {
1080 buf_stat = pch_can_get_buffer_status(priv);
1081 if (!buf_stat)
1082 break;
1083 counter--;
1084 udelay(1);
1085 }
1086 if (!counter)
1087 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1088
1089 /* Save interrupt configuration and then disable them */
ca2b004e 1090 priv->int_enables = pch_can_get_int_enables(priv);
b21d18b5
MO		 1091 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1092
1093 /* Save Tx buffer enable state */
15ffc8fd
T		 1094 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1095 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG);
b21d18b5
MO		 1096
1097 /* Disable all Transmit buffers */
8339a7ed 1098 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 1099
1100 /* Save Rx buffer enable state */
15ffc8fd
T		 1101 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1102 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
ca2b004e 1103 priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
b21d18b5
MO		 1104 }
1105
1106 /* Disable all Receive buffers */
8339a7ed 1107 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 1108 retval = pci_save_state(pdev);
1109 if (retval) {
1110 dev_err(&pdev->dev, "pci_save_state failed.\n");
1111 } else {
1112 pci_enable_wake(pdev, PCI_D3hot, 0);
1113 pci_disable_device(pdev);
1114 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1115 }
1116
1117 return retval;
1118}
1119
1120static int pch_can_resume(struct pci_dev *pdev)
1121{
c7551456
T		 1122 int i;
1123 int retval;
b21d18b5
MO		 1124 struct net_device *dev = pci_get_drvdata(pdev);
1125 struct pch_can_priv *priv = netdev_priv(dev);
1126
1127 pci_set_power_state(pdev, PCI_D0);
1128 pci_restore_state(pdev);
1129 retval = pci_enable_device(pdev);
1130 if (retval) {
1131 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1132 return retval;
1133 }
1134
1135 pci_enable_wake(pdev, PCI_D3hot, 0);
1136
1137 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1138
1139 /* Disabling all interrupts. */
1140 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1141
1142 /* Setting the CAN device in Stop Mode. */
1143 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1144
1145 /* Configuring the transmit and receive buffers. */
1146 pch_can_config_rx_tx_buffers(priv);
1147
1148 /* Restore the CAN state */
1149 pch_set_bittiming(dev);
1150
1151 /* Listen/Active */
1152 pch_can_set_optmode(priv);
1153
1154 /* Enabling the transmit buffer. */
15ffc8fd
T		 1155 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1156 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG);
b21d18b5
MO		 1157
1158 /* Configuring the receive buffer and enabling them. */
15ffc8fd
T		 1159 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1160 /* Restore buffer link */
1161 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
b21d18b5 1162
15ffc8fd
T		 1163 /* Restore buffer enables */
1164 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG);
b21d18b5
MO		 1165 }
1166
1167 /* Enable CAN Interrupts */
1168 pch_can_set_int_custom(priv);
1169
1170 /* Restore Run Mode */
1171 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1172
1173 return retval;
1174}
1175#else
1176#define pch_can_suspend NULL
1177#define pch_can_resume NULL
1178#endif
1179
1180static int pch_can_get_berr_counter(const struct net_device *dev,
1181 struct can_berr_counter *bec)
1182{
1183 struct pch_can_priv *priv = netdev_priv(dev);
44c9aa89 1184 u32 errc = ioread32(&priv->regs->errc);
b21d18b5 1185
44c9aa89
T		 1186 bec->txerr = errc & PCH_TEC;
1187 bec->rxerr = (errc & PCH_REC) >> 8;
b21d18b5
MO		 1188
1189 return 0;
1190}
1191
1192static int __devinit pch_can_probe(struct pci_dev *pdev,
1193 const struct pci_device_id *id)
1194{
1195 struct net_device *ndev;
1196 struct pch_can_priv *priv;
1197 int rc;
b21d18b5
MO		 1198 void __iomem *addr;
1199
1200 rc = pci_enable_device(pdev);
1201 if (rc) {
1202 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1203 goto probe_exit_endev;
1204 }
1205
1206 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1207 if (rc) {
1208 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1209 goto probe_exit_pcireq;
1210 }
1211
1212 addr = pci_iomap(pdev, 1, 0);
1213 if (!addr) {
1214 rc = -EIO;
1215 dev_err(&pdev->dev, "Failed pci_iomap\n");
1216 goto probe_exit_ipmap;
1217 }
1218
15ffc8fd 1219 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
b21d18b5
MO		 1220 if (!ndev) {
1221 rc = -ENOMEM;
1222 dev_err(&pdev->dev, "Failed alloc_candev\n");
1223 goto probe_exit_alloc_candev;
1224 }
1225
1226 priv = netdev_priv(ndev);
1227 priv->ndev = ndev;
1228 priv->regs = addr;
1229 priv->dev = pdev;
1230 priv->can.bittiming_const = &pch_can_bittiming_const;
1231 priv->can.do_set_mode = pch_can_do_set_mode;
1232 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1233 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1234 CAN_CTRLMODE_LOOPBACK;
15ffc8fd 1235 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
b21d18b5
MO		 1236
1237 ndev->irq = pdev->irq;
1238 ndev->flags |= IFF_ECHO;
1239
1240 pci_set_drvdata(pdev, ndev);
1241 SET_NETDEV_DEV(ndev, &pdev->dev);
1242 ndev->netdev_ops = &pch_can_netdev_ops;
b21d18b5 1243 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
b21d18b5 1244
bd58cbc3 1245 netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
b21d18b5
MO		 1246
1247 rc = register_candev(ndev);
1248 if (rc) {
1249 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1250 goto probe_exit_reg_candev;
1251 }
1252
1253 return 0;
1254
1255probe_exit_reg_candev:
1256 free_candev(ndev);
1257probe_exit_alloc_candev:
1258 pci_iounmap(pdev, addr);
1259probe_exit_ipmap:
1260 pci_release_regions(pdev);
1261probe_exit_pcireq:
1262 pci_disable_device(pdev);
1263probe_exit_endev:
1264 return rc;
1265}
1266
bdfa3d8f 1267static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1268 .name = "pch_can",
1269 .id_table = pch_pci_tbl,
1270 .probe = pch_can_probe,
1271 .remove = __devexit_p(pch_can_remove),
1272 .suspend = pch_can_suspend,
1273 .resume = pch_can_resume,
1274};
1275
1276static int __init pch_can_pci_init(void)
1277{
bdfa3d8f 1278 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1279}
1280module_init(pch_can_pci_init);
1281
1282static void __exit pch_can_pci_exit(void)
1283{
bdfa3d8f 1284 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1285}
1286module_exit(pch_can_pci_exit);
1287
e91530ea 1288MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
b21d18b5
MO		 1289MODULE_LICENSE("GPL v2");
1290MODULE_VERSION("0.94");
Linux 6.x block layer and io_uring tree(s)