projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
can: EG20T PCH: Separate Interface Register(IF1/IF2)
[linux-2.6-block.git] / drivers / net / can / pch_can.c
CommitLineData
b21d18b5
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/errno.h>
29#include <linux/netdevice.h>
30#include <linux/skbuff.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34
086b5650
T		 35#define PCH_MAX_MSG_OBJ 32
36#define PCH_MSG_OBJ_RX 0 /* The receive message object flag. */
37#define PCH_MSG_OBJ_TX 1 /* The transmit message object flag. */
38
39#define PCH_ENABLE 1 /* The enable flag */
40#define PCH_DISABLE 0 /* The disable flag */
0a80410d
T		 41#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
42#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
43#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
44#define PCH_CTRL_CCE BIT(6)
45#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
46#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
47#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
48
086b5650
T		 49#define PCH_CMASK_RX_TX_SET 0x00f3
50#define PCH_CMASK_RX_TX_GET 0x0073
51#define PCH_CMASK_ALL 0xff
0a80410d
T		 52#define PCH_CMASK_NEWDAT BIT(2)
53#define PCH_CMASK_CLRINTPND BIT(3)
54#define PCH_CMASK_CTRL BIT(4)
55#define PCH_CMASK_ARB BIT(5)
56#define PCH_CMASK_MASK BIT(6)
57#define PCH_CMASK_RDWR BIT(7)
58#define PCH_IF_MCONT_NEWDAT BIT(15)
59#define PCH_IF_MCONT_MSGLOST BIT(14)
60#define PCH_IF_MCONT_INTPND BIT(13)
61#define PCH_IF_MCONT_UMASK BIT(12)
62#define PCH_IF_MCONT_TXIE BIT(11)
63#define PCH_IF_MCONT_RXIE BIT(10)
64#define PCH_IF_MCONT_RMTEN BIT(9)
65#define PCH_IF_MCONT_TXRQXT BIT(8)
66#define PCH_IF_MCONT_EOB BIT(7)
67#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
68#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
69#define PCH_ID2_DIR BIT(13)
70#define PCH_ID2_XTD BIT(14)
71#define PCH_ID_MSGVAL BIT(15)
72#define PCH_IF_CREQ_BUSY BIT(15)
086b5650
T		 73
74#define PCH_STATUS_INT 0x8000
75#define PCH_REC 0x00007f00
76#define PCH_TEC 0x000000ff
b21d18b5 77
0a80410d
T		 78#define PCH_TX_OK BIT(3)
79#define PCH_RX_OK BIT(4)
80#define PCH_EPASSIV BIT(5)
81#define PCH_EWARN BIT(6)
82#define PCH_BUS_OFF BIT(7)
83#define PCH_LEC0 BIT(0)
84#define PCH_LEC1 BIT(1)
85#define PCH_LEC2 BIT(2)
b21d18b5
MO		 86#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
87#define PCH_STUF_ERR PCH_LEC0
88#define PCH_FORM_ERR PCH_LEC1
89#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
90#define PCH_BIT1_ERR PCH_LEC2
91#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
92#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
93
94/* bit position of certain controller bits. */
086b5650
T		 95#define PCH_BIT_BRP 0
96#define PCH_BIT_SJW 6
97#define PCH_BIT_TSEG1 8
98#define PCH_BIT_TSEG2 12
99#define PCH_BIT_BRPE_BRPE 6
100#define PCH_MSK_BITT_BRP 0x3f
101#define PCH_MSK_BRPE_BRPE 0x3c0
102#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
103#define PCH_COUNTER_LIMIT 10
b21d18b5
MO		 104
105#define PCH_CAN_CLK 50000000 /* 50MHz */
106
107/* Define the number of message object.
108 * PCH CAN communications are done via Message RAM.
109 * The Message RAM consists of 32 message objects. */
110#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
111#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
112#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
113
114#define PCH_FIFO_THRESH 16
115
8339a7ed
T		 116enum pch_ifreg {
117 PCH_RX_IFREG,
118 PCH_TX_IFREG,
119};
120
b21d18b5
MO		 121enum pch_can_mode {
122 PCH_CAN_ENABLE,
123 PCH_CAN_DISABLE,
124 PCH_CAN_ALL,
125 PCH_CAN_NONE,
126 PCH_CAN_STOP,
127 PCH_CAN_RUN
128};
129
8339a7ed
T		 130struct pch_can_if_regs {
131 u32 creq;
132 u32 cmask;
133 u32 mask1;
134 u32 mask2;
135 u32 id1;
136 u32 id2;
137 u32 mcont;
138 u32 dataa1;
139 u32 dataa2;
140 u32 datab1;
141 u32 datab2;
142 u32 rsv[13];
143};
144
b21d18b5
MO		 145struct pch_can_regs {
146 u32 cont;
147 u32 stat;
148 u32 errc;
149 u32 bitt;
150 u32 intr;
151 u32 opt;
152 u32 brpe;
8339a7ed
T		 153 u32 reserve;
154 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
155 u32 reserve1[8];
b21d18b5
MO		 156 u32 treq1;
157 u32 treq2;
8339a7ed
T		 158 u32 reserve2[6];
159 u32 data1;
160 u32 data2;
161 u32 reserve3[6];
162 u32 canipend1;
163 u32 canipend2;
164 u32 reserve4[6];
165 u32 canmval1;
166 u32 canmval2;
167 u32 reserve5[37];
b21d18b5
MO		 168 u32 srst;
169};
170
171struct pch_can_priv {
172 struct can_priv can;
173 unsigned int can_num;
174 struct pci_dev *dev;
086b5650
T		 175 unsigned int tx_enable[PCH_MAX_MSG_OBJ];
176 unsigned int rx_enable[PCH_MAX_MSG_OBJ];
177 unsigned int rx_link[PCH_MAX_MSG_OBJ];
b21d18b5
MO		 178 unsigned int int_enables;
179 unsigned int int_stat;
180 struct net_device *ndev;
181 spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
086b5650 182 unsigned int msg_obj[PCH_MAX_MSG_OBJ];
b21d18b5
MO		 183 struct pch_can_regs __iomem *regs;
184 struct napi_struct napi;
185 unsigned int tx_obj; /* Point next Tx Obj index */
186 unsigned int use_msi;
187};
188
189static struct can_bittiming_const pch_can_bittiming_const = {
190 .name = KBUILD_MODNAME,
191 .tseg1_min = 1,
192 .tseg1_max = 16,
193 .tseg2_min = 1,
194 .tseg2_max = 8,
195 .sjw_max = 4,
196 .brp_min = 1,
197 .brp_max = 1024, /* 6bit + extended 4bit */
198 .brp_inc = 1,
199};
200
201static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
202 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
203 {0,}
204};
205MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
206
526de53c 207static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
b21d18b5
MO		 208{
209 iowrite32(ioread32(addr) | mask, addr);
210}
211
526de53c 212static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
b21d18b5
MO		 213{
214 iowrite32(ioread32(addr) & ~mask, addr);
215}
216
217static void pch_can_set_run_mode(struct pch_can_priv *priv,
218 enum pch_can_mode mode)
219{
220 switch (mode) {
221 case PCH_CAN_RUN:
086b5650 222 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 223 break;
224
225 case PCH_CAN_STOP:
086b5650 226 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
b21d18b5
MO		 227 break;
228
229 default:
230 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
231 break;
232 }
233}
234
235static void pch_can_set_optmode(struct pch_can_priv *priv)
236{
237 u32 reg_val = ioread32(&priv->regs->opt);
238
239 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
086b5650 240 reg_val |= PCH_OPT_SILENT;
b21d18b5
MO		 241
242 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
086b5650 243 reg_val |= PCH_OPT_LBACK;
b21d18b5 244
086b5650 245 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
b21d18b5
MO		 246 iowrite32(reg_val, &priv->regs->opt);
247}
248
249static void pch_can_set_int_custom(struct pch_can_priv *priv)
250{
251 /* Clearing the IE, SIE and EIE bits of Can control register. */
086b5650 252 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 253
254 /* Appropriately setting them. */
255 pch_can_bit_set(&priv->regs->cont,
086b5650 256 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
b21d18b5
MO		 257}
258
259/* This function retrieves interrupt enabled for the CAN device. */
260static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
261{
262 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
086b5650 263 *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
b21d18b5
MO		 264}
265
266static void pch_can_set_int_enables(struct pch_can_priv *priv,
267 enum pch_can_mode interrupt_no)
268{
269 switch (interrupt_no) {
270 case PCH_CAN_ENABLE:
086b5650 271 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 272 break;
273
274 case PCH_CAN_DISABLE:
086b5650 275 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
b21d18b5
MO		 276 break;
277
278 case PCH_CAN_ALL:
086b5650 279 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 280 break;
281
282 case PCH_CAN_NONE:
086b5650 283 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
b21d18b5
MO		 284 break;
285
286 default:
287 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
288 break;
289 }
290}
291
292static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
293{
086b5650 294 u32 counter = PCH_COUNTER_LIMIT;
b21d18b5
MO		 295 u32 ifx_creq;
296
297 iowrite32(num, creq_addr);
298 while (counter) {
086b5650 299 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
b21d18b5
MO		 300 if (!ifx_creq)
301 break;
302 counter--;
303 udelay(1);
304 }
305 if (!counter)
306 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
307}
308
8339a7ed
T		 309static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
310 u32 set, enum pch_ifreg dir)
b21d18b5
MO		 311{
312 unsigned long flags;
8339a7ed
T		 313 u32 ie;
314
315 if (dir)
316 ie = PCH_IF_MCONT_TXIE;
317 else
318 ie = PCH_IF_MCONT_RXIE;
b21d18b5
MO		 319
320 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
321 /* Reading the receive buffer data from RAM to Interface1 registers */
8339a7ed
T		 322 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
323 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 324
325 /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
086b5650 326 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 327 &priv->regs->ifregs[dir].cmask);
b21d18b5 328
086b5650 329 if (set == PCH_ENABLE) {
b21d18b5 330 /* Setting the MsgVal and RxIE bits */
8339a7ed
T		 331 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
332 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5 333
086b5650 334 } else if (set == PCH_DISABLE) {
b21d18b5 335 /* Resetting the MsgVal and RxIE bits */
8339a7ed
T		 336 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
337 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
b21d18b5
MO		 338 }
339
8339a7ed 340 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5
MO		 341 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
342}
343
b21d18b5 344
8339a7ed 345static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
b21d18b5
MO		 346{
347 int i;
348
349 /* Traversing to obtain the object configured as receivers. */
350 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 351 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
8339a7ed 352 pch_can_set_rxtx(priv, i + 1, set, PCH_RX_IFREG);
b21d18b5
MO		 353 }
354}
355
8339a7ed 356static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
b21d18b5
MO		 357{
358 int i;
359
360 /* Traversing to obtain the object configured as transmit object. */
361 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 362 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
8339a7ed 363 pch_can_set_rxtx(priv, i + 1, set, PCH_TX_IFREG);
b21d18b5
MO		 364 }
365}
366
8339a7ed
T		 367static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
368 enum pch_ifreg dir)
b21d18b5
MO		 369{
370 unsigned long flags;
8339a7ed 371 u32 ie, enable;
b21d18b5 372
8339a7ed
T		 373 if (dir)
374 ie = PCH_IF_MCONT_RXIE;
b21d18b5 375 else
8339a7ed 376 ie = PCH_IF_MCONT_TXIE;
b21d18b5
MO		 377
378 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
8339a7ed
T		 379 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
380 pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
b21d18b5 381
8339a7ed
T		 382 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
383 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
384 enable = PCH_ENABLE;
b21d18b5 385 } else {
8339a7ed 386 enable = PCH_DISABLE;
b21d18b5
MO		 387 }
388 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
8339a7ed 389 return enable;
b21d18b5
MO		 390}
391
392static int pch_can_int_pending(struct pch_can_priv *priv)
393{
394 return ioread32(&priv->regs->intr) & 0xffff;
395}
396
397static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
398 u32 buffer_num, u32 set)
399{
400 unsigned long flags;
401
402 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
8339a7ed
T		 403 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
404 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
405 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
406 &priv->regs->ifregs[0].cmask);
086b5650 407 if (set == PCH_ENABLE)
8339a7ed
T		 408 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
409 PCH_IF_MCONT_EOB);
b21d18b5 410 else
8339a7ed 411 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
b21d18b5 412
8339a7ed 413 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
b21d18b5
MO		 414 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
415}
416
417static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
418 u32 buffer_num, u32 *link)
419{
420 unsigned long flags;
421
422 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
8339a7ed
T		 423 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
424 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
b21d18b5 425
8339a7ed 426 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
086b5650 427 *link = PCH_DISABLE;
b21d18b5 428 else
086b5650 429 *link = PCH_ENABLE;
b21d18b5
MO		 430 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
431}
432
433static void pch_can_clear_buffers(struct pch_can_priv *priv)
434{
435 int i;
436
437 for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
8339a7ed
T		 438 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
439 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
440 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
441 iowrite32(0x0, &priv->regs->ifregs[0].id1);
442 iowrite32(0x0, &priv->regs->ifregs[0].id2);
443 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
444 iowrite32(0x0, &priv->regs->ifregs[0].dataa1);
445 iowrite32(0x0, &priv->regs->ifregs[0].dataa2);
446 iowrite32(0x0, &priv->regs->ifregs[0].datab1);
447 iowrite32(0x0, &priv->regs->ifregs[0].datab2);
086b5650
T		 448 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
449 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed
T		 450 &priv->regs->ifregs[0].cmask);
451 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i+1);
b21d18b5
MO		 452 }
453
454 for (i = i; i < PCH_OBJ_NUM; i++) {
8339a7ed
T		 455 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask);
456 iowrite32(0xffff, &priv->regs->ifregs[1].mask1);
457 iowrite32(0xffff, &priv->regs->ifregs[1].mask2);
458 iowrite32(0x0, &priv->regs->ifregs[1].id1);
459 iowrite32(0x0, &priv->regs->ifregs[1].id2);
460 iowrite32(0x0, &priv->regs->ifregs[1].mcont);
461 iowrite32(0x0, &priv->regs->ifregs[1].dataa1);
462 iowrite32(0x0, &priv->regs->ifregs[1].dataa2);
463 iowrite32(0x0, &priv->regs->ifregs[1].datab1);
464 iowrite32(0x0, &priv->regs->ifregs[1].datab2);
086b5650
T		 465 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
466 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed
T		 467 &priv->regs->ifregs[1].cmask);
468 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i+1);
b21d18b5
MO		 469 }
470}
471
472static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
473{
474 int i;
475 unsigned long flags;
476
477 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
478
479 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650
T		 480 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
481 iowrite32(PCH_CMASK_RX_TX_GET,
8339a7ed
T		 482 &priv->regs->ifregs[0].cmask);
483 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i+1);
b21d18b5 484
8339a7ed
T		 485 iowrite32(0x0, &priv->regs->ifregs[0].id1);
486 iowrite32(0x0, &priv->regs->ifregs[0].id2);
b21d18b5 487
8339a7ed 488 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
086b5650 489 PCH_IF_MCONT_UMASK);
b21d18b5
MO		 490
491 /* Set FIFO mode set to 0 except last Rx Obj*/
8339a7ed 492 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 493 PCH_IF_MCONT_EOB);
b21d18b5
MO		 494 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
495 if (i == (PCH_RX_OBJ_NUM - 1))
8339a7ed 496 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
086b5650 497 PCH_IF_MCONT_EOB);
b21d18b5 498
8339a7ed
T		 499 iowrite32(0, &priv->regs->ifregs[0].mask1);
500 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
086b5650 501 0x1fff | PCH_MASK2_MDIR_MXTD);
b21d18b5
MO		 502
503 /* Setting CMASK for writing */
086b5650
T		 504 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
505 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 506 &priv->regs->ifregs[0].cmask);
b21d18b5 507
8339a7ed 508 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i+1);
086b5650
T		 509 } else if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
510 iowrite32(PCH_CMASK_RX_TX_GET,
8339a7ed
T		 511 &priv->regs->ifregs[1].cmask);
512 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i+1);
b21d18b5
MO		 513
514 /* Resetting DIR bit for reception */
8339a7ed
T		 515 iowrite32(0x0, &priv->regs->ifregs[1].id1);
516 iowrite32(0x0, &priv->regs->ifregs[1].id2);
517 pch_can_bit_set(&priv->regs->ifregs[1].id2,
518 PCH_ID2_DIR);
b21d18b5
MO		 519
520 /* Setting EOB bit for transmitter */
8339a7ed
T		 521 iowrite32(PCH_IF_MCONT_EOB,
522 &priv->regs->ifregs[1].mcont);
b21d18b5 523
8339a7ed 524 pch_can_bit_set(&priv->regs->ifregs[1].mcont,
086b5650 525 PCH_IF_MCONT_UMASK);
b21d18b5 526
8339a7ed
T		 527 iowrite32(0, &priv->regs->ifregs[1].mask1);
528 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
b21d18b5
MO		 529
530 /* Setting CMASK for writing */
086b5650
T		 531 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
532 PCH_CMASK_ARB | PCH_CMASK_CTRL,
8339a7ed 533 &priv->regs->ifregs[1].cmask);
b21d18b5 534
8339a7ed 535 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i+1);
b21d18b5
MO		 536 }
537 }
538 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
539}
540
541static void pch_can_init(struct pch_can_priv *priv)
542{
543 /* Stopping the Can device. */
544 pch_can_set_run_mode(priv, PCH_CAN_STOP);
545
546 /* Clearing all the message object buffers. */
547 pch_can_clear_buffers(priv);
548
549 /* Configuring the respective message object as either rx/tx object. */
550 pch_can_config_rx_tx_buffers(priv);
551
552 /* Enabling the interrupts. */
553 pch_can_set_int_enables(priv, PCH_CAN_ALL);
554}
555
556static void pch_can_release(struct pch_can_priv *priv)
557{
558 /* Stooping the CAN device. */
559 pch_can_set_run_mode(priv, PCH_CAN_STOP);
560
561 /* Disabling the interrupts. */
562 pch_can_set_int_enables(priv, PCH_CAN_NONE);
563
564 /* Disabling all the receive object. */
8339a7ed 565 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 566
567 /* Disabling all the transmit object. */
8339a7ed 568 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 569}
570
571/* This function clears interrupt(s) from the CAN device. */
572static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
573{
086b5650 574 if (mask == PCH_STATUS_INT) {
b21d18b5
MO		 575 ioread32(&priv->regs->stat);
576 return;
577 }
578
579 /* Clear interrupt for transmit object */
086b5650 580 if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_TX) {
b21d18b5
MO		 581 /* Setting CMASK for clearing interrupts for
582 frame transmission. */
086b5650 583 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 584 &priv->regs->ifregs[1].cmask);
b21d18b5
MO		 585
586 /* Resetting the ID registers. */
8339a7ed 587 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 588 PCH_ID2_DIR | (0x7ff << 2));
8339a7ed 589 iowrite32(0x0, &priv->regs->ifregs[1].id1);
b21d18b5
MO		 590
591 /* Claring NewDat, TxRqst & IntPnd */
8339a7ed 592 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 593 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
594 PCH_IF_MCONT_TXRQXT);
8339a7ed 595 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask);
086b5650 596 } else if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_RX) {
b21d18b5 597 /* Setting CMASK for clearing the reception interrupts. */
086b5650 598 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
8339a7ed 599 &priv->regs->ifregs[0].cmask);
b21d18b5
MO		 600
601 /* Clearing the Dir bit. */
8339a7ed 602 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
b21d18b5
MO		 603
604 /* Clearing NewDat & IntPnd */
8339a7ed 605 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 606 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
b21d18b5 607
8339a7ed 608 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask);
b21d18b5
MO		 609 }
610}
611
612static int pch_can_get_buffer_status(struct pch_can_priv *priv)
613{
614 return (ioread32(&priv->regs->treq1) & 0xffff) |
615 ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
616}
617
618static void pch_can_reset(struct pch_can_priv *priv)
619{
620 /* write to sw reset register */
621 iowrite32(1, &priv->regs->srst);
622 iowrite32(0, &priv->regs->srst);
623}
624
625static void pch_can_error(struct net_device *ndev, u32 status)
626{
627 struct sk_buff *skb;
628 struct pch_can_priv *priv = netdev_priv(ndev);
629 struct can_frame *cf;
630 u32 errc;
631 struct net_device_stats *stats = &(priv->ndev->stats);
632 enum can_state state = priv->can.state;
633
634 skb = alloc_can_err_skb(ndev, &cf);
635 if (!skb)
636 return;
637
638 if (status & PCH_BUS_OFF) {
8339a7ed
T		 639 pch_can_set_tx_all(priv, 0);
640 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 641 state = CAN_STATE_BUS_OFF;
642 cf->can_id |= CAN_ERR_BUSOFF;
643 can_bus_off(ndev);
644 pch_can_set_run_mode(priv, PCH_CAN_RUN);
645 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
646 }
647
648 /* Warning interrupt. */
649 if (status & PCH_EWARN) {
650 state = CAN_STATE_ERROR_WARNING;
651 priv->can.can_stats.error_warning++;
652 cf->can_id |= CAN_ERR_CRTL;
653 errc = ioread32(&priv->regs->errc);
086b5650 654 if (((errc & PCH_REC) >> 8) > 96)
b21d18b5 655 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
086b5650 656 if ((errc & PCH_TEC) > 96)
b21d18b5
MO		 657 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
658 dev_warn(&ndev->dev,
659 "%s -> Error Counter is more than 96.\n", __func__);
660 }
661 /* Error passive interrupt. */
662 if (status & PCH_EPASSIV) {
663 priv->can.can_stats.error_passive++;
664 state = CAN_STATE_ERROR_PASSIVE;
665 cf->can_id |= CAN_ERR_CRTL;
666 errc = ioread32(&priv->regs->errc);
086b5650 667 if (((errc & PCH_REC) >> 8) > 127)
b21d18b5 668 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
086b5650 669 if ((errc & PCH_TEC) > 127)
b21d18b5
MO		 670 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
671 dev_err(&ndev->dev,
672 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
673 }
674
675 if (status & PCH_LEC_ALL) {
676 priv->can.can_stats.bus_error++;
677 stats->rx_errors++;
678 switch (status & PCH_LEC_ALL) {
679 case PCH_STUF_ERR:
680 cf->data[2] |= CAN_ERR_PROT_STUFF;
681 break;
682 case PCH_FORM_ERR:
683 cf->data[2] |= CAN_ERR_PROT_FORM;
684 break;
685 case PCH_ACK_ERR:
686 cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
687 CAN_ERR_PROT_LOC_ACK_DEL;
688 break;
689 case PCH_BIT1_ERR:
690 case PCH_BIT0_ERR:
691 cf->data[2] |= CAN_ERR_PROT_BIT;
692 break;
693 case PCH_CRC_ERR:
694 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
695 CAN_ERR_PROT_LOC_CRC_DEL;
696 break;
697 default:
698 iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
699 break;
700 }
701
702 }
703
704 priv->can.state = state;
705 netif_rx(skb);
706
707 stats->rx_packets++;
708 stats->rx_bytes += cf->can_dlc;
709}
710
711static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
712{
713 struct net_device *ndev = (struct net_device *)dev_id;
714 struct pch_can_priv *priv = netdev_priv(ndev);
715
716 pch_can_set_int_enables(priv, PCH_CAN_NONE);
717
718 napi_schedule(&priv->napi);
719
720 return IRQ_HANDLED;
721}
722
723static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
724{
725 u32 reg;
726 canid_t id;
727 u32 ide;
728 u32 rtr;
729 int i, j, k;
730 int rcv_pkts = 0;
731 struct sk_buff *skb;
732 struct can_frame *cf;
733 struct pch_can_priv *priv = netdev_priv(ndev);
734 struct net_device_stats *stats = &(priv->ndev->stats);
735
736 /* Reading the messsage object from the Message RAM */
8339a7ed
T		 737 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
738 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat);
b21d18b5
MO		 739
740 /* Reading the MCONT register. */
8339a7ed 741 reg = ioread32(&priv->regs->ifregs[0].mcont);
b21d18b5
MO		 742 reg &= 0xffff;
743
086b5650 744 for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
b21d18b5 745 /* If MsgLost bit set. */
086b5650 746 if (reg & PCH_IF_MCONT_MSGLOST) {
b21d18b5 747 dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
8339a7ed 748 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650
T		 749 PCH_IF_MCONT_MSGLOST);
750 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
8339a7ed
T		 751 &priv->regs->ifregs[0].cmask);
752 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
b21d18b5
MO		 753
754 skb = alloc_can_err_skb(ndev, &cf);
755 if (!skb)
756 return -ENOMEM;
757
758 priv->can.can_stats.error_passive++;
759 priv->can.state = CAN_STATE_ERROR_PASSIVE;
760 cf->can_id |= CAN_ERR_CRTL;
761 cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
762 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
763 stats->rx_packets++;
764 stats->rx_bytes += cf->can_dlc;
765
766 netif_receive_skb(skb);
767 rcv_pkts++;
768 goto RX_NEXT;
769 }
086b5650 770 if (!(reg & PCH_IF_MCONT_NEWDAT))
b21d18b5
MO		 771 goto RX_NEXT;
772
773 skb = alloc_can_skb(priv->ndev, &cf);
774 if (!skb)
775 return -ENOMEM;
776
777 /* Get Received data */
8339a7ed
T		 778 ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >>
779 14;
b21d18b5 780 if (ide) {
8339a7ed
T		 781 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
782 id |= (((ioread32(&priv->regs->ifregs[0].id2)) &
b21d18b5
MO		 783 0x1fff) << 16);
784 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
785 } else {
8339a7ed
T		 786 id = (((ioread32(&priv->regs->ifregs[0].id2)) &
787 (CAN_SFF_MASK << 2)) >> 2);
b21d18b5
MO		 788 cf->can_id = (id & CAN_SFF_MASK);
789 }
790
8339a7ed 791 rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR);
b21d18b5
MO		 792 if (rtr) {
793 cf->can_dlc = 0;
794 cf->can_id |= CAN_RTR_FLAG;
795 } else {
8339a7ed
T		 796 cf->can_dlc = ((ioread32(&priv->regs->ifregs[0].mcont))
797 & 0x0f);
b21d18b5
MO		 798 }
799
800 for (i = 0, j = 0; i < cf->can_dlc; j++) {
8339a7ed 801 reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4);
b21d18b5
MO		 802 cf->data[i++] = cpu_to_le32(reg & 0xff);
803 if (i == cf->can_dlc)
804 break;
805 cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
806 }
807
808 netif_receive_skb(skb);
809 rcv_pkts++;
810 stats->rx_packets++;
811 stats->rx_bytes += cf->can_dlc;
812
813 if (k < PCH_FIFO_THRESH) {
086b5650 814 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
8339a7ed 815 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
b21d18b5
MO		 816
817 /* Clearing the Dir bit. */
8339a7ed
T		 818 pch_can_bit_clear(&priv->regs->ifregs[0].id2,
819 PCH_ID2_DIR);
b21d18b5
MO		 820
821 /* Clearing NewDat & IntPnd */
8339a7ed 822 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
086b5650 823 PCH_IF_MCONT_INTPND);
8339a7ed 824 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
b21d18b5
MO		 825 } else if (k > PCH_FIFO_THRESH) {
826 pch_can_int_clr(priv, k);
827 } else if (k == PCH_FIFO_THRESH) {
828 int cnt;
829 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
830 pch_can_int_clr(priv, cnt+1);
831 }
832RX_NEXT:
833 /* Reading the messsage object from the Message RAM */
8339a7ed
T		 834 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
835 pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k + 1);
836 reg = ioread32(&priv->regs->ifregs[0].mcont);
b21d18b5
MO		 837 }
838
839 return rcv_pkts;
840}
841static int pch_can_rx_poll(struct napi_struct *napi, int quota)
842{
843 struct net_device *ndev = napi->dev;
844 struct pch_can_priv *priv = netdev_priv(ndev);
845 struct net_device_stats *stats = &(priv->ndev->stats);
846 u32 dlc;
847 u32 int_stat;
848 int rcv_pkts = 0;
849 u32 reg_stat;
850 unsigned long flags;
851
852 int_stat = pch_can_int_pending(priv);
853 if (!int_stat)
854 return 0;
855
856INT_STAT:
086b5650 857 if (int_stat == PCH_STATUS_INT) {
b21d18b5
MO		 858 reg_stat = ioread32(&priv->regs->stat);
859 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
860 if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
861 pch_can_error(ndev, reg_stat);
862 }
863
864 if (reg_stat & PCH_TX_OK) {
865 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
8339a7ed
T		 866 iowrite32(PCH_CMASK_RX_TX_GET,
867 &priv->regs->ifregs[1].cmask);
868 pch_can_check_if_busy(&priv->regs->ifregs[1].creq,
b21d18b5
MO		 869 ioread32(&priv->regs->intr));
870 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
871 pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
872 }
873
874 if (reg_stat & PCH_RX_OK)
875 pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
876
877 int_stat = pch_can_int_pending(priv);
086b5650 878 if (int_stat == PCH_STATUS_INT)
b21d18b5
MO		 879 goto INT_STAT;
880 }
881
882MSG_OBJ:
883 if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
884 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
885 rcv_pkts = pch_can_rx_normal(ndev, int_stat);
886 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
887 if (rcv_pkts < 0)
888 return 0;
889 } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
086b5650 890 if (priv->msg_obj[int_stat - 1] == PCH_MSG_OBJ_TX) {
b21d18b5
MO		 891 /* Handle transmission interrupt */
892 can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
893 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
086b5650 894 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
8339a7ed
T		 895 &priv->regs->ifregs[1].cmask);
896 dlc = ioread32(&priv->regs->ifregs[1].mcont) &
086b5650 897 PCH_IF_MCONT_DLC;
8339a7ed
T		 898 pch_can_check_if_busy(&priv->regs->ifregs[1].creq,
899 int_stat);
b21d18b5
MO		 900 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
901 if (dlc > 8)
902 dlc = 8;
903 stats->tx_bytes += dlc;
904 stats->tx_packets++;
905 }
906 }
907
908 int_stat = pch_can_int_pending(priv);
086b5650 909 if (int_stat == PCH_STATUS_INT)
b21d18b5
MO		 910 goto INT_STAT;
911 else if (int_stat >= 1 && int_stat <= 32)
912 goto MSG_OBJ;
913
914 napi_complete(napi);
915 pch_can_set_int_enables(priv, PCH_CAN_ALL);
916
917 return rcv_pkts;
918}
919
920static int pch_set_bittiming(struct net_device *ndev)
921{
922 struct pch_can_priv *priv = netdev_priv(ndev);
923 const struct can_bittiming *bt = &priv->can.bittiming;
924 u32 canbit;
925 u32 bepe;
926 u32 brp;
927
928 /* Setting the CCE bit for accessing the Can Timing register. */
086b5650 929 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 930
931 brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
086b5650
T		 932 canbit = brp & PCH_MSK_BITT_BRP;
933 canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
934 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
935 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
936 bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
b21d18b5
MO		 937 iowrite32(canbit, &priv->regs->bitt);
938 iowrite32(bepe, &priv->regs->brpe);
086b5650 939 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
b21d18b5
MO		 940
941 return 0;
942}
943
944static void pch_can_start(struct net_device *ndev)
945{
946 struct pch_can_priv *priv = netdev_priv(ndev);
947
948 if (priv->can.state != CAN_STATE_STOPPED)
949 pch_can_reset(priv);
950
951 pch_set_bittiming(ndev);
952 pch_can_set_optmode(priv);
953
8339a7ed
T		 954 pch_can_set_tx_all(priv, 1);
955 pch_can_set_rx_all(priv, 1);
b21d18b5
MO		 956
957 /* Setting the CAN to run mode. */
958 pch_can_set_run_mode(priv, PCH_CAN_RUN);
959
960 priv->can.state = CAN_STATE_ERROR_ACTIVE;
961
962 return;
963}
964
965static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
966{
967 int ret = 0;
968
969 switch (mode) {
970 case CAN_MODE_START:
971 pch_can_start(ndev);
972 netif_wake_queue(ndev);
973 break;
974 default:
975 ret = -EOPNOTSUPP;
976 break;
977 }
978
979 return ret;
980}
981
982static int pch_can_open(struct net_device *ndev)
983{
984 struct pch_can_priv *priv = netdev_priv(ndev);
985 int retval;
986
987 retval = pci_enable_msi(priv->dev);
988 if (retval) {
989 dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
990 priv->use_msi = 0;
991 } else {
992 dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
993 priv->use_msi = 1;
994 }
995
996 /* Regsitering the interrupt. */
997 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
998 ndev->name, ndev);
999 if (retval) {
1000 dev_err(&ndev->dev, "request_irq failed.\n");
1001 goto req_irq_err;
1002 }
1003
1004 /* Open common can device */
1005 retval = open_candev(ndev);
1006 if (retval) {
1007 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
1008 goto err_open_candev;
1009 }
1010
1011 pch_can_init(priv);
1012 pch_can_start(ndev);
1013 napi_enable(&priv->napi);
1014 netif_start_queue(ndev);
1015
1016 return 0;
1017
1018err_open_candev:
1019 free_irq(priv->dev->irq, ndev);
1020req_irq_err:
1021 if (priv->use_msi)
1022 pci_disable_msi(priv->dev);
1023
1024 pch_can_release(priv);
1025
1026 return retval;
1027}
1028
1029static int pch_close(struct net_device *ndev)
1030{
1031 struct pch_can_priv *priv = netdev_priv(ndev);
1032
1033 netif_stop_queue(ndev);
1034 napi_disable(&priv->napi);
1035 pch_can_release(priv);
1036 free_irq(priv->dev->irq, ndev);
1037 if (priv->use_msi)
1038 pci_disable_msi(priv->dev);
1039 close_candev(ndev);
1040 priv->can.state = CAN_STATE_STOPPED;
1041 return 0;
1042}
1043
1044static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
1045{
1046 u32 buffer_status = 0;
1047 struct pch_can_priv *priv = netdev_priv(ndev);
1048
1049 /* Getting the message object status. */
1050 buffer_status = (u32) pch_can_get_buffer_status(priv);
1051
1052 return buffer_status & obj_id;
1053}
1054
1055
1056static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
1057{
1058 int i, j;
1059 unsigned long flags;
1060 struct pch_can_priv *priv = netdev_priv(ndev);
1061 struct can_frame *cf = (struct can_frame *)skb->data;
1062 int tx_buffer_avail = 0;
1063
1064 if (can_dropped_invalid_skb(ndev, skb))
1065 return NETDEV_TX_OK;
1066
1067 if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */
1068 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
1069 PCH_RX_OBJ_NUM)))
1070 udelay(500);
1071
1072 priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
1073 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
1074 } else {
1075 tx_buffer_avail = priv->tx_obj;
1076 }
1077 priv->tx_obj++;
1078
1079 /* Attaining the lock. */
1080 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
1081
1082 /* Reading the Msg Obj from the Msg RAM to the Interface register. */
8339a7ed
T		 1083 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
1084 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
b21d18b5
MO		 1085
1086 /* Setting the CMASK register. */
8339a7ed 1087 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
b21d18b5
MO		 1088
1089 /* If ID extended is set. */
8339a7ed
T		 1090 pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff);
1091 pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD);
b21d18b5 1092 if (cf->can_id & CAN_EFF_FLAG) {
8339a7ed
T		 1093 pch_can_bit_set(&priv->regs->ifregs[1].id1,
1094 cf->can_id & 0xffff);
1095 pch_can_bit_set(&priv->regs->ifregs[1].id2,
086b5650 1096 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
b21d18b5 1097 } else {
8339a7ed
T		 1098 pch_can_bit_set(&priv->regs->ifregs[1].id1, 0);
1099 pch_can_bit_set(&priv->regs->ifregs[1].id2,
b21d18b5
MO		 1100 (cf->can_id & CAN_SFF_MASK) << 2);
1101 }
1102
1103 /* If remote frame has to be transmitted.. */
1104 if (cf->can_id & CAN_RTR_FLAG)
8339a7ed 1105 pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
b21d18b5
MO		 1106
1107 for (i = 0, j = 0; i < cf->can_dlc; j++) {
1108 iowrite32(le32_to_cpu(cf->data[i++]),
8339a7ed 1109 (&priv->regs->ifregs[1].dataa1) + j*4);
b21d18b5
MO		 1110 if (i == cf->can_dlc)
1111 break;
1112 iowrite32(le32_to_cpu(cf->data[i++] << 8),
8339a7ed 1113 (&priv->regs->ifregs[1].dataa1) + j*4);
b21d18b5
MO		 1114 }
1115
1116 can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
1117
1118 /* Updating the size of the data. */
8339a7ed
T		 1119 pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f);
1120 pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc);
b21d18b5
MO		 1121
1122 /* Clearing IntPend, NewDat & TxRqst */
8339a7ed 1123 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
086b5650
T		 1124 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
1125 PCH_IF_MCONT_TXRQXT);
b21d18b5
MO		 1126
1127 /* Setting NewDat, TxRqst bits */
8339a7ed 1128 pch_can_bit_set(&priv->regs->ifregs[1].mcont,
086b5650 1129 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
b21d18b5 1130
8339a7ed 1131 pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
b21d18b5
MO		 1132
1133 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
1134
1135 return NETDEV_TX_OK;
1136}
1137
1138static const struct net_device_ops pch_can_netdev_ops = {
1139 .ndo_open = pch_can_open,
1140 .ndo_stop = pch_close,
1141 .ndo_start_xmit = pch_xmit,
1142};
1143
1144static void __devexit pch_can_remove(struct pci_dev *pdev)
1145{
1146 struct net_device *ndev = pci_get_drvdata(pdev);
1147 struct pch_can_priv *priv = netdev_priv(ndev);
1148
1149 unregister_candev(priv->ndev);
1150 free_candev(priv->ndev);
1151 pci_iounmap(pdev, priv->regs);
1152 pci_release_regions(pdev);
1153 pci_disable_device(pdev);
1154 pci_set_drvdata(pdev, NULL);
1155 pch_can_reset(priv);
1156}
1157
1158#ifdef CONFIG_PM
1159static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1160{
1161 int i; /* Counter variable. */
1162 int retval; /* Return value. */
1163 u32 buf_stat; /* Variable for reading the transmit buffer status. */
1164 u32 counter = 0xFFFFFF;
1165
1166 struct net_device *dev = pci_get_drvdata(pdev);
1167 struct pch_can_priv *priv = netdev_priv(dev);
1168
1169 /* Stop the CAN controller */
1170 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1171
1172 /* Indicate that we are aboutto/in suspend */
1173 priv->can.state = CAN_STATE_SLEEPING;
1174
1175 /* Waiting for all transmission to complete. */
1176 while (counter) {
1177 buf_stat = pch_can_get_buffer_status(priv);
1178 if (!buf_stat)
1179 break;
1180 counter--;
1181 udelay(1);
1182 }
1183 if (!counter)
1184 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1185
1186 /* Save interrupt configuration and then disable them */
1187 pch_can_get_int_enables(priv, &(priv->int_enables));
1188 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1189
1190 /* Save Tx buffer enable state */
1191 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1192 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
8339a7ed
T		 1193 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i + 1,
1194 PCH_TX_IFREG);
b21d18b5
MO		 1195 }
1196
1197 /* Disable all Transmit buffers */
8339a7ed 1198 pch_can_set_tx_all(priv, 0);
b21d18b5
MO		 1199
1200 /* Save Rx buffer enable state */
1201 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1202 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
8339a7ed
T		 1203 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i + 1,
1204 PCH_RX_IFREG);
b21d18b5
MO		 1205 pch_can_get_rx_buffer_link(priv, i + 1,
1206 &(priv->rx_link[i]));
1207 }
1208 }
1209
1210 /* Disable all Receive buffers */
8339a7ed 1211 pch_can_set_rx_all(priv, 0);
b21d18b5
MO		 1212 retval = pci_save_state(pdev);
1213 if (retval) {
1214 dev_err(&pdev->dev, "pci_save_state failed.\n");
1215 } else {
1216 pci_enable_wake(pdev, PCI_D3hot, 0);
1217 pci_disable_device(pdev);
1218 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1219 }
1220
1221 return retval;
1222}
1223
1224static int pch_can_resume(struct pci_dev *pdev)
1225{
1226 int i; /* Counter variable. */
1227 int retval; /* Return variable. */
1228 struct net_device *dev = pci_get_drvdata(pdev);
1229 struct pch_can_priv *priv = netdev_priv(dev);
1230
1231 pci_set_power_state(pdev, PCI_D0);
1232 pci_restore_state(pdev);
1233 retval = pci_enable_device(pdev);
1234 if (retval) {
1235 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1236 return retval;
1237 }
1238
1239 pci_enable_wake(pdev, PCI_D3hot, 0);
1240
1241 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1242
1243 /* Disabling all interrupts. */
1244 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1245
1246 /* Setting the CAN device in Stop Mode. */
1247 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1248
1249 /* Configuring the transmit and receive buffers. */
1250 pch_can_config_rx_tx_buffers(priv);
1251
1252 /* Restore the CAN state */
1253 pch_set_bittiming(dev);
1254
1255 /* Listen/Active */
1256 pch_can_set_optmode(priv);
1257
1258 /* Enabling the transmit buffer. */
1259 for (i = 0; i < PCH_OBJ_NUM; i++) {
8339a7ed
T		 1260 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
1261 pch_can_set_rxtx(priv, i, priv->tx_enable[i],
1262 PCH_TX_IFREG);
b21d18b5
MO		 1263 }
1264
1265 /* Configuring the receive buffer and enabling them. */
1266 for (i = 0; i < PCH_OBJ_NUM; i++) {
086b5650 1267 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
b21d18b5
MO		 1268 /* Restore buffer link */
1269 pch_can_set_rx_buffer_link(priv, i + 1,
1270 priv->rx_link[i]);
1271
1272 /* Restore buffer enables */
8339a7ed
T		 1273 pch_can_set_rxtx(priv, i, priv->rx_enable[i],
1274 PCH_RX_IFREG);
1275
b21d18b5
MO		 1276 }
1277 }
1278
1279 /* Enable CAN Interrupts */
1280 pch_can_set_int_custom(priv);
1281
1282 /* Restore Run Mode */
1283 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1284
1285 return retval;
1286}
1287#else
1288#define pch_can_suspend NULL
1289#define pch_can_resume NULL
1290#endif
1291
1292static int pch_can_get_berr_counter(const struct net_device *dev,
1293 struct can_berr_counter *bec)
1294{
1295 struct pch_can_priv *priv = netdev_priv(dev);
1296
086b5650
T		 1297 bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
1298 bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
b21d18b5
MO		 1299
1300 return 0;
1301}
1302
1303static int __devinit pch_can_probe(struct pci_dev *pdev,
1304 const struct pci_device_id *id)
1305{
1306 struct net_device *ndev;
1307 struct pch_can_priv *priv;
1308 int rc;
1309 int index;
1310 void __iomem *addr;
1311
1312 rc = pci_enable_device(pdev);
1313 if (rc) {
1314 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1315 goto probe_exit_endev;
1316 }
1317
1318 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1319 if (rc) {
1320 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1321 goto probe_exit_pcireq;
1322 }
1323
1324 addr = pci_iomap(pdev, 1, 0);
1325 if (!addr) {
1326 rc = -EIO;
1327 dev_err(&pdev->dev, "Failed pci_iomap\n");
1328 goto probe_exit_ipmap;
1329 }
1330
1331 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
1332 if (!ndev) {
1333 rc = -ENOMEM;
1334 dev_err(&pdev->dev, "Failed alloc_candev\n");
1335 goto probe_exit_alloc_candev;
1336 }
1337
1338 priv = netdev_priv(ndev);
1339 priv->ndev = ndev;
1340 priv->regs = addr;
1341 priv->dev = pdev;
1342 priv->can.bittiming_const = &pch_can_bittiming_const;
1343 priv->can.do_set_mode = pch_can_do_set_mode;
1344 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1345 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1346 CAN_CTRLMODE_LOOPBACK;
1347 priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
1348
1349 ndev->irq = pdev->irq;
1350 ndev->flags |= IFF_ECHO;
1351
1352 pci_set_drvdata(pdev, ndev);
1353 SET_NETDEV_DEV(ndev, &pdev->dev);
1354 ndev->netdev_ops = &pch_can_netdev_ops;
1355
1356 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1357 for (index = 0; index < PCH_RX_OBJ_NUM;)
086b5650 1358 priv->msg_obj[index++] = PCH_MSG_OBJ_RX;
b21d18b5
MO		 1359
1360 for (index = index; index < PCH_OBJ_NUM;)
086b5650 1361 priv->msg_obj[index++] = PCH_MSG_OBJ_TX;
b21d18b5
MO		 1362
1363 netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
1364
1365 rc = register_candev(ndev);
1366 if (rc) {
1367 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1368 goto probe_exit_reg_candev;
1369 }
1370
1371 return 0;
1372
1373probe_exit_reg_candev:
1374 free_candev(ndev);
1375probe_exit_alloc_candev:
1376 pci_iounmap(pdev, addr);
1377probe_exit_ipmap:
1378 pci_release_regions(pdev);
1379probe_exit_pcireq:
1380 pci_disable_device(pdev);
1381probe_exit_endev:
1382 return rc;
1383}
1384
bdfa3d8f 1385static struct pci_driver pch_can_pci_driver = {
b21d18b5
MO		 1386 .name = "pch_can",
1387 .id_table = pch_pci_tbl,
1388 .probe = pch_can_probe,
1389 .remove = __devexit_p(pch_can_remove),
1390 .suspend = pch_can_suspend,
1391 .resume = pch_can_resume,
1392};
1393
1394static int __init pch_can_pci_init(void)
1395{
bdfa3d8f 1396 return pci_register_driver(&pch_can_pci_driver);
b21d18b5
MO		 1397}
1398module_init(pch_can_pci_init);
1399
1400static void __exit pch_can_pci_exit(void)
1401{
bdfa3d8f 1402 pci_unregister_driver(&pch_can_pci_driver);
b21d18b5
MO		 1403}
1404module_exit(pch_can_pci_exit);
1405
1406MODULE_DESCRIPTION("Controller Area Network Driver");
1407MODULE_LICENSE("GPL v2");
1408MODULE_VERSION("0.94");
Linux 6.x block layer and io_uring tree(s)