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can: Proper ctrlmode handling for CAN devices
[linux-2.6-block.git] / drivers / net / can / mscan / mscan.c
CommitLineData
afa17a50
WS		 1/*
2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
2d4b6faf 7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
afa17a50
WS		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/if_arp.h>
29#include <linux/if_ether.h>
30#include <linux/list.h>
31#include <linux/can.h>
32#include <linux/can/dev.h>
33#include <linux/can/error.h>
34#include <linux/io.h>
35
36#include "mscan.h"
37
afa17a50
WS		 38static struct can_bittiming_const mscan_bittiming_const = {
39 .name = "mscan",
40 .tseg1_min = 4,
41 .tseg1_max = 16,
42 .tseg2_min = 2,
43 .tseg2_max = 8,
44 .sjw_max = 4,
45 .brp_min = 1,
46 .brp_max = 64,
47 .brp_inc = 1,
48};
49
50struct mscan_state {
51 u8 mode;
52 u8 canrier;
53 u8 cantier;
54};
55
afa17a50
WS		 56static enum can_state state_map[] = {
57 CAN_STATE_ERROR_ACTIVE,
58 CAN_STATE_ERROR_WARNING,
59 CAN_STATE_ERROR_PASSIVE,
60 CAN_STATE_BUS_OFF
61};
62
63static int mscan_set_mode(struct net_device *dev, u8 mode)
64{
65 struct mscan_priv *priv = netdev_priv(dev);
66 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
67 int ret = 0;
68 int i;
69 u8 canctl1;
70
71 if (mode != MSCAN_NORMAL_MODE) {
afa17a50
WS		 72 if (priv->tx_active) {
73 /* Abort transfers before going to sleep */#
74 out_8(&regs->cantarq, priv->tx_active);
75 /* Suppress TX done interrupts */
76 out_8(&regs->cantier, 0);
77 }
78
79 canctl1 = in_8(&regs->canctl1);
0285e7ce 80 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
59179ea6 81 setbits8(&regs->canctl0, MSCAN_SLPRQ);
afa17a50
WS		 82 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
83 if (in_8(&regs->canctl1) & MSCAN_SLPAK)
84 break;
85 udelay(100);
86 }
87 /*
88 * The mscan controller will fail to enter sleep mode,
89 * while there are irregular activities on bus, like
90 * somebody keeps retransmitting. This behavior is
91 * undocumented and seems to differ between mscan built
92 * in mpc5200b and mpc5200. We proceed in that case,
93 * since otherwise the slprq will be kept set and the
94 * controller will get stuck. NOTE: INITRQ or CSWAI
95 * will abort all active transmit actions, if still
96 * any, at once.
97 */
98 if (i >= MSCAN_SET_MODE_RETRIES)
99 dev_dbg(dev->dev.parent,
100 "device failed to enter sleep mode. "
101 "We proceed anyhow.\n");
102 else
103 priv->can.state = CAN_STATE_SLEEPING;
104 }
105
0285e7ce 106 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
59179ea6 107 setbits8(&regs->canctl0, MSCAN_INITRQ);
afa17a50
WS		 108 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
109 if (in_8(&regs->canctl1) & MSCAN_INITAK)
110 break;
111 }
112 if (i >= MSCAN_SET_MODE_RETRIES)
113 ret = -ENODEV;
114 }
115 if (!ret)
116 priv->can.state = CAN_STATE_STOPPED;
117
118 if (mode & MSCAN_CSWAI)
59179ea6 119 setbits8(&regs->canctl0, MSCAN_CSWAI);
afa17a50
WS		 120
121 } else {
122 canctl1 = in_8(&regs->canctl1);
123 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
59179ea6 124 clrbits8(&regs->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
afa17a50
WS		 125 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
126 canctl1 = in_8(&regs->canctl1);
127 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
128 break;
129 }
130 if (i >= MSCAN_SET_MODE_RETRIES)
131 ret = -ENODEV;
132 else
133 priv->can.state = CAN_STATE_ERROR_ACTIVE;
134 }
135 }
136 return ret;
137}
138
139static int mscan_start(struct net_device *dev)
140{
141 struct mscan_priv *priv = netdev_priv(dev);
142 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
143 u8 canrflg;
144 int err;
145
146 out_8(&regs->canrier, 0);
147
148 INIT_LIST_HEAD(&priv->tx_head);
149 priv->prev_buf_id = 0;
150 priv->cur_pri = 0;
151 priv->tx_active = 0;
152 priv->shadow_canrier = 0;
153 priv->flags = 0;
154
bf3af547
WG		 155 if (priv->type == MSCAN_TYPE_MPC5121) {
156 /* Clear pending bus-off condition */
157 if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
158 out_8(&regs->canmisc, MSCAN_BOHOLD);
159 }
160
afa17a50
WS		 161 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
162 if (err)
163 return err;
164
165 canrflg = in_8(&regs->canrflg);
166 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
167 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
168 MSCAN_STATE_TX(canrflg))];
169 out_8(&regs->cantier, 0);
170
171 /* Enable receive interrupts. */
bf3af547
WG		 172 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
173
174 return 0;
175}
176
177static int mscan_restart(struct net_device *dev)
178{
179 struct mscan_priv *priv = netdev_priv(dev);
180
181 if (priv->type == MSCAN_TYPE_MPC5121) {
182 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
183
184 priv->can.state = CAN_STATE_ERROR_ACTIVE;
185 WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
186 "bus-off state expected");
187 out_8(&regs->canmisc, MSCAN_BOHOLD);
188 /* Re-enable receive interrupts. */
189 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
190 } else {
191 if (priv->can.state <= CAN_STATE_BUS_OFF)
192 mscan_set_mode(dev, MSCAN_INIT_MODE);
193 return mscan_start(dev);
194 }
afa17a50
WS		 195
196 return 0;
197}
198
199static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
200{
201 struct can_frame *frame = (struct can_frame *)skb->data;
202 struct mscan_priv *priv = netdev_priv(dev);
203 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
204 int i, rtr, buf_id;
205 u32 can_id;
206
3ccd4c61 207 if (can_dropped_invalid_skb(dev, skb))
2d4b6faf 208 return NETDEV_TX_OK;
afa17a50
WS		 209
210 out_8(&regs->cantier, 0);
211
212 i = ~priv->tx_active & MSCAN_TXE;
213 buf_id = ffs(i) - 1;
214 switch (hweight8(i)) {
215 case 0:
216 netif_stop_queue(dev);
217 dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n");
218 return NETDEV_TX_BUSY;
219 case 1:
220 /*
221 * if buf_id < 3, then current frame will be send out of order,
222 * since buffer with lower id have higher priority (hell..)
223 */
224 netif_stop_queue(dev);
225 case 2:
226 if (buf_id < priv->prev_buf_id) {
227 priv->cur_pri++;
228 if (priv->cur_pri == 0xff) {
229 set_bit(F_TX_WAIT_ALL, &priv->flags);
230 netif_stop_queue(dev);
231 }
232 }
233 set_bit(F_TX_PROGRESS, &priv->flags);
234 break;
235 }
236 priv->prev_buf_id = buf_id;
237 out_8(&regs->cantbsel, i);
238
239 rtr = frame->can_id & CAN_RTR_FLAG;
240
74ff60b2 241 /* RTR is always the lowest bit of interest, then IDs follow */
afa17a50 242 if (frame->can_id & CAN_EFF_FLAG) {
74ff60b2
WS		 243 can_id = (frame->can_id & CAN_EFF_MASK)
244 << (MSCAN_EFF_RTR_SHIFT + 1);
afa17a50 245 if (rtr)
74ff60b2 246 can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
afa17a50
WS		 247 out_be16(&regs->tx.idr3_2, can_id);
248
249 can_id >>= 16;
74ff60b2
WS		 250 /* EFF_FLAGS are inbetween the IDs :( */
251 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
252 | MSCAN_EFF_FLAGS;
afa17a50 253 } else {
74ff60b2
WS		 254 can_id = (frame->can_id & CAN_SFF_MASK)
255 << (MSCAN_SFF_RTR_SHIFT + 1);
afa17a50 256 if (rtr)
74ff60b2 257 can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
afa17a50
WS		 258 }
259 out_be16(&regs->tx.idr1_0, can_id);
260
261 if (!rtr) {
262 void __iomem *data = &regs->tx.dsr1_0;
0285e7ce
WS		 263 u16 *payload = (u16 *)frame->data;
264
afa17a50
WS		 265 /* It is safe to write into dsr[dlc+1] */
266 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
267 out_be16(data, *payload++);
268 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
269 }
270 }
271
272 out_8(&regs->tx.dlr, frame->can_dlc);
273 out_8(&regs->tx.tbpr, priv->cur_pri);
274
275 /* Start transmission. */
276 out_8(&regs->cantflg, 1 << buf_id);
277
278 if (!test_bit(F_TX_PROGRESS, &priv->flags))
279 dev->trans_start = jiffies;
280
281 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
282
283 can_put_echo_skb(skb, dev, buf_id);
284
285 /* Enable interrupt. */
286 priv->tx_active |= 1 << buf_id;
287 out_8(&regs->cantier, priv->tx_active);
288
289 return NETDEV_TX_OK;
290}
291
292/* This function returns the old state to see where we came from */
293static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
294{
295 struct mscan_priv *priv = netdev_priv(dev);
296 enum can_state state, old_state = priv->can.state;
297
298 if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
299 state = state_map[max(MSCAN_STATE_RX(canrflg),
300 MSCAN_STATE_TX(canrflg))];
301 priv->can.state = state;
302 }
303 return old_state;
304}
305
306static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
307{
308 struct mscan_priv *priv = netdev_priv(dev);
309 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
310 u32 can_id;
311 int i;
312
313 can_id = in_be16(&regs->rx.idr1_0);
314 if (can_id & (1 << 3)) {
315 frame->can_id = CAN_EFF_FLAG;
316 can_id = ((can_id << 16) | in_be16(&regs->rx.idr3_2));
317 can_id = ((can_id & 0xffe00000) |
318 ((can_id & 0x7ffff) << 2)) >> 2;
319 } else {
320 can_id >>= 4;
321 frame->can_id = 0;
322 }
323
324 frame->can_id |= can_id >> 1;
325 if (can_id & 1)
326 frame->can_id |= CAN_RTR_FLAG;
c7cd606f
OH		 327
328 frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);
afa17a50
WS		 329
330 if (!(frame->can_id & CAN_RTR_FLAG)) {
331 void __iomem *data = &regs->rx.dsr1_0;
0285e7ce
WS		 332 u16 *payload = (u16 *)frame->data;
333
afa17a50
WS		 334 for (i = 0; i < (frame->can_dlc + 1) / 2; i++) {
335 *payload++ = in_be16(data);
336 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
337 }
338 }
339
340 out_8(&regs->canrflg, MSCAN_RXF);
341}
342
343static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
344 u8 canrflg)
345{
346 struct mscan_priv *priv = netdev_priv(dev);
347 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
348 struct net_device_stats *stats = &dev->stats;
349 enum can_state old_state;
350
351 dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg);
352 frame->can_id = CAN_ERR_FLAG;
353
354 if (canrflg & MSCAN_OVRIF) {
355 frame->can_id |= CAN_ERR_CRTL;
356 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
357 stats->rx_over_errors++;
358 stats->rx_errors++;
0285e7ce 359 } else {
afa17a50 360 frame->data[1] = 0;
0285e7ce 361 }
afa17a50
WS		 362
363 old_state = check_set_state(dev, canrflg);
364 /* State changed */
365 if (old_state != priv->can.state) {
366 switch (priv->can.state) {
367 case CAN_STATE_ERROR_WARNING:
368 frame->can_id |= CAN_ERR_CRTL;
369 priv->can.can_stats.error_warning++;
370 if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
371 (canrflg & MSCAN_RSTAT_MSK))
372 frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
afa17a50
WS		 373 if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
374 (canrflg & MSCAN_TSTAT_MSK))
375 frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
376 break;
377 case CAN_STATE_ERROR_PASSIVE:
378 frame->can_id |= CAN_ERR_CRTL;
379 priv->can.can_stats.error_passive++;
380 frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
381 break;
382 case CAN_STATE_BUS_OFF:
383 frame->can_id |= CAN_ERR_BUSOFF;
384 /*
385 * The MSCAN on the MPC5200 does recover from bus-off
386 * automatically. To avoid that we stop the chip doing
387 * a light-weight stop (we are in irq-context).
388 */
bf3af547
WG		 389 if (priv->type != MSCAN_TYPE_MPC5121) {
390 out_8(&regs->cantier, 0);
391 out_8(&regs->canrier, 0);
392 setbits8(&regs->canctl0,
393 MSCAN_SLPRQ | MSCAN_INITRQ);
394 }
afa17a50
WS		 395 can_bus_off(dev);
396 break;
397 default:
398 break;
399 }
400 }
401 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
402 frame->can_dlc = CAN_ERR_DLC;
403 out_8(&regs->canrflg, MSCAN_ERR_IF);
404}
405
406static int mscan_rx_poll(struct napi_struct *napi, int quota)
407{
408 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
409 struct net_device *dev = napi->dev;
410 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
411 struct net_device_stats *stats = &dev->stats;
412 int npackets = 0;
413 int ret = 1;
414 struct sk_buff *skb;
415 struct can_frame *frame;
416 u8 canrflg;
417
68bd7422
WS		 418 while (npackets < quota) {
419 canrflg = in_8(&regs->canrflg);
420 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
421 break;
afa17a50
WS		 422
423 skb = alloc_can_skb(dev, &frame);
424 if (!skb) {
425 if (printk_ratelimit())
426 dev_notice(dev->dev.parent, "packet dropped\n");
427 stats->rx_dropped++;
428 out_8(&regs->canrflg, canrflg);
429 continue;
430 }
431
432 if (canrflg & MSCAN_RXF)
433 mscan_get_rx_frame(dev, frame);
0285e7ce 434 else if (canrflg & MSCAN_ERR_IF)
afa17a50
WS		 435 mscan_get_err_frame(dev, frame, canrflg);
436
437 stats->rx_packets++;
438 stats->rx_bytes += frame->can_dlc;
439 npackets++;
440 netif_receive_skb(skb);
441 }
442
443 if (!(in_8(&regs->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
444 napi_complete(&priv->napi);
445 clear_bit(F_RX_PROGRESS, &priv->flags);
446 if (priv->can.state < CAN_STATE_BUS_OFF)
447 out_8(&regs->canrier, priv->shadow_canrier);
448 ret = 0;
449 }
450 return ret;
451}
452
453static irqreturn_t mscan_isr(int irq, void *dev_id)
454{
455 struct net_device *dev = (struct net_device *)dev_id;
456 struct mscan_priv *priv = netdev_priv(dev);
457 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
458 struct net_device_stats *stats = &dev->stats;
459 u8 cantier, cantflg, canrflg;
460 irqreturn_t ret = IRQ_NONE;
461
462 cantier = in_8(&regs->cantier) & MSCAN_TXE;
463 cantflg = in_8(&regs->cantflg) & cantier;
464
465 if (cantier && cantflg) {
afa17a50
WS		 466 struct list_head *tmp, *pos;
467
468 list_for_each_safe(pos, tmp, &priv->tx_head) {
469 struct tx_queue_entry *entry =
470 list_entry(pos, struct tx_queue_entry, list);
471 u8 mask = entry->mask;
472
473 if (!(cantflg & mask))
474 continue;
475
476 out_8(&regs->cantbsel, mask);
477 stats->tx_bytes += in_8(&regs->tx.dlr);
478 stats->tx_packets++;
479 can_get_echo_skb(dev, entry->id);
480 priv->tx_active &= ~mask;
481 list_del(pos);
482 }
483
484 if (list_empty(&priv->tx_head)) {
485 clear_bit(F_TX_WAIT_ALL, &priv->flags);
486 clear_bit(F_TX_PROGRESS, &priv->flags);
487 priv->cur_pri = 0;
0285e7ce 488 } else {
afa17a50 489 dev->trans_start = jiffies;
0285e7ce 490 }
afa17a50
WS		 491
492 if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
493 netif_wake_queue(dev);
494
495 out_8(&regs->cantier, priv->tx_active);
496 ret = IRQ_HANDLED;
497 }
498
499 canrflg = in_8(&regs->canrflg);
500 if ((canrflg & ~MSCAN_STAT_MSK) &&
501 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
502 if (canrflg & ~MSCAN_STAT_MSK) {
503 priv->shadow_canrier = in_8(&regs->canrier);
504 out_8(&regs->canrier, 0);
505 napi_schedule(&priv->napi);
506 ret = IRQ_HANDLED;
0285e7ce 507 } else {
afa17a50 508 clear_bit(F_RX_PROGRESS, &priv->flags);
0285e7ce 509 }
afa17a50
WS		 510 }
511 return ret;
512}
513
514static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
515{
afa17a50
WS		 516 struct mscan_priv *priv = netdev_priv(dev);
517 int ret = 0;
518
519 if (!priv->open_time)
520 return -EINVAL;
521
522 switch (mode) {
afa17a50 523 case CAN_MODE_START:
bf3af547 524 ret = mscan_restart(dev);
afa17a50
WS		 525 if (ret)
526 break;
527 if (netif_queue_stopped(dev))
528 netif_wake_queue(dev);
529 break;
530
531 default:
532 ret = -EOPNOTSUPP;
533 break;
534 }
535 return ret;
536}
537
538static int mscan_do_set_bittiming(struct net_device *dev)
539{
540 struct mscan_priv *priv = netdev_priv(dev);
541 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
542 struct can_bittiming *bt = &priv->can.bittiming;
543 u8 btr0, btr1;
544
545 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
546 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
547 BTR1_SET_TSEG2(bt->phase_seg2) |
548 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
549
550 dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n",
551 btr0, btr1);
552
553 out_8(&regs->canbtr0, btr0);
554 out_8(&regs->canbtr1, btr1);
555
556 return 0;
557}
558
559static int mscan_open(struct net_device *dev)
560{
561 int ret;
562 struct mscan_priv *priv = netdev_priv(dev);
563 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
564
565 /* common open */
566 ret = open_candev(dev);
567 if (ret)
568 return ret;
569
570 napi_enable(&priv->napi);
571
572 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
573 if (ret < 0) {
323907ac
WS		 574 dev_err(dev->dev.parent, "failed to attach interrupt\n");
575 goto exit_napi_disable;
afa17a50
WS		 576 }
577
578 priv->open_time = jiffies;
579
59179ea6 580 clrbits8(&regs->canctl1, MSCAN_LISTEN);
afa17a50
WS		 581
582 ret = mscan_start(dev);
583 if (ret)
323907ac 584 goto exit_free_irq;
afa17a50
WS		 585
586 netif_start_queue(dev);
587
588 return 0;
323907ac
WS		 589
590exit_free_irq:
591 priv->open_time = 0;
592 free_irq(dev->irq, dev);
593exit_napi_disable:
594 napi_disable(&priv->napi);
595 close_candev(dev);
596 return ret;
afa17a50
WS		 597}
598
599static int mscan_close(struct net_device *dev)
600{
601 struct mscan_priv *priv = netdev_priv(dev);
602 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
603
604 netif_stop_queue(dev);
605 napi_disable(&priv->napi);
606
607 out_8(&regs->cantier, 0);
608 out_8(&regs->canrier, 0);
609 mscan_set_mode(dev, MSCAN_INIT_MODE);
610 close_candev(dev);
611 free_irq(dev->irq, dev);
612 priv->open_time = 0;
613
614 return 0;
615}
616
617static const struct net_device_ops mscan_netdev_ops = {
618 .ndo_open = mscan_open,
619 .ndo_stop = mscan_close,
620 .ndo_start_xmit = mscan_start_xmit,
621};
622
bf3af547 623int register_mscandev(struct net_device *dev, int mscan_clksrc)
afa17a50
WS		 624{
625 struct mscan_priv *priv = netdev_priv(dev);
626 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
627 u8 ctl1;
628
629 ctl1 = in_8(&regs->canctl1);
bf3af547 630 if (mscan_clksrc)
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WS		 631 ctl1 |= MSCAN_CLKSRC;
632 else
633 ctl1 &= ~MSCAN_CLKSRC;
634
bf3af547
WG		 635 if (priv->type == MSCAN_TYPE_MPC5121)
636 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
637
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WS		 638 ctl1 |= MSCAN_CANE;
639 out_8(&regs->canctl1, ctl1);
640 udelay(100);
641
642 /* acceptance mask/acceptance code (accept everything) */
643 out_be16(&regs->canidar1_0, 0);
644 out_be16(&regs->canidar3_2, 0);
645 out_be16(&regs->canidar5_4, 0);
646 out_be16(&regs->canidar7_6, 0);
647
648 out_be16(&regs->canidmr1_0, 0xffff);
649 out_be16(&regs->canidmr3_2, 0xffff);
650 out_be16(&regs->canidmr5_4, 0xffff);
651 out_be16(&regs->canidmr7_6, 0xffff);
652 /* Two 32 bit Acceptance Filters */
653 out_8(&regs->canidac, MSCAN_AF_32BIT);
654
655 mscan_set_mode(dev, MSCAN_INIT_MODE);
656
657 return register_candev(dev);
658}
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WS		 659
660void unregister_mscandev(struct net_device *dev)
661{
662 struct mscan_priv *priv = netdev_priv(dev);
663 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
664 mscan_set_mode(dev, MSCAN_INIT_MODE);
59179ea6 665 clrbits8(&regs->canctl1, MSCAN_CANE);
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WS		 666 unregister_candev(dev);
667}
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WS		 668
669struct net_device *alloc_mscandev(void)
670{
671 struct net_device *dev;
672 struct mscan_priv *priv;
673 int i;
674
675 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
676 if (!dev)
677 return NULL;
678 priv = netdev_priv(dev);
679
680 dev->netdev_ops = &mscan_netdev_ops;
681
682 dev->flags |= IFF_ECHO; /* we support local echo */
683
684 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
685
686 priv->can.bittiming_const = &mscan_bittiming_const;
687 priv->can.do_set_bittiming = mscan_do_set_bittiming;
688 priv->can.do_set_mode = mscan_do_set_mode;
ad72c347 689 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
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WS		 690
691 for (i = 0; i < TX_QUEUE_SIZE; i++) {
692 priv->tx_queue[i].id = i;
693 priv->tx_queue[i].mask = 1 << i;
694 }
695
696 return dev;
697}
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WS		 698
699MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
700MODULE_LICENSE("GPL v2");
701MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
Linux 6.x block layer and io_uring tree(s)