[linux-2.6-block.git] / drivers / net / can / mscan / mscan.c

/*
 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
 *
 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
 *                         Varma Electronics Oy
 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the version 2 of the GNU General Public License
 * as published by the Free Software Foundation
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/list.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>
#include <linux/io.h>

#include "mscan.h"

static struct can_bittiming_const mscan_bittiming_const = {
	.name = "mscan",
	.tseg1_min = 4,
	.tseg1_max = 16,
	.tseg2_min = 2,
	.tseg2_max = 8,
	.sjw_max = 4,
	.brp_min = 1,
	.brp_max = 64,
	.brp_inc = 1,
};

struct mscan_state {
	u8 mode;
	u8 canrier;
	u8 cantier;
};

static enum can_state state_map[] = {
	CAN_STATE_ERROR_ACTIVE,
	CAN_STATE_ERROR_WARNING,
	CAN_STATE_ERROR_PASSIVE,
	CAN_STATE_BUS_OFF
};

static int mscan_set_mode(struct net_device *dev, u8 mode)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	int ret = 0;
	int i;
	u8 canctl1;

	if (mode != MSCAN_NORMAL_MODE) {
		if (priv->tx_active) {
			/* Abort transfers before going to sleep */#
			out_8(&regs->cantarq, priv->tx_active);
			/* Suppress TX done interrupts */
			out_8(&regs->cantier, 0);
		}

		canctl1 = in_8(&regs->canctl1);
		if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
			setbits8(&regs->canctl0, MSCAN_SLPRQ);
			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
				if (in_8(&regs->canctl1) & MSCAN_SLPAK)
					break;
				udelay(100);
			}
			/*
			 * The mscan controller will fail to enter sleep mode,
			 * while there are irregular activities on bus, like
			 * somebody keeps retransmitting. This behavior is
			 * undocumented and seems to differ between mscan built
			 * in mpc5200b and mpc5200. We proceed in that case,
			 * since otherwise the slprq will be kept set and the
			 * controller will get stuck. NOTE: INITRQ or CSWAI
			 * will abort all active transmit actions, if still
			 * any, at once.
			 */
			if (i >= MSCAN_SET_MODE_RETRIES)
				dev_dbg(dev->dev.parent,
					"device failed to enter sleep mode. "
					"We proceed anyhow.\n");
			else
				priv->can.state = CAN_STATE_SLEEPING;
		}

		if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
			setbits8(&regs->canctl0, MSCAN_INITRQ);
			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
				if (in_8(&regs->canctl1) & MSCAN_INITAK)
					break;
			}
			if (i >= MSCAN_SET_MODE_RETRIES)
				ret = -ENODEV;
		}
		if (!ret)
			priv->can.state = CAN_STATE_STOPPED;

		if (mode & MSCAN_CSWAI)
			setbits8(&regs->canctl0, MSCAN_CSWAI);

	} else {
		canctl1 = in_8(&regs->canctl1);
		if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
			clrbits8(&regs->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
			for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
				canctl1 = in_8(&regs->canctl1);
				if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
					break;
			}
			if (i >= MSCAN_SET_MODE_RETRIES)
				ret = -ENODEV;
			else
				priv->can.state = CAN_STATE_ERROR_ACTIVE;
		}
	}
	return ret;
}

static int mscan_start(struct net_device *dev)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	u8 canrflg;
	int err;

	out_8(&regs->canrier, 0);

	INIT_LIST_HEAD(&priv->tx_head);
	priv->prev_buf_id = 0;
	priv->cur_pri = 0;
	priv->tx_active = 0;
	priv->shadow_canrier = 0;
	priv->flags = 0;

	if (priv->type == MSCAN_TYPE_MPC5121) {
		/* Clear pending bus-off condition */
		if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
			out_8(&regs->canmisc, MSCAN_BOHOLD);
	}

	err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
	if (err)
		return err;

	canrflg = in_8(&regs->canrflg);
	priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
	priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
				    MSCAN_STATE_TX(canrflg))];
	out_8(&regs->cantier, 0);

	/* Enable receive interrupts. */
	out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);

	return 0;
}

static int mscan_restart(struct net_device *dev)
{
	struct mscan_priv *priv = netdev_priv(dev);

	if (priv->type == MSCAN_TYPE_MPC5121) {
		struct mscan_regs __iomem *regs = priv->reg_base;

		priv->can.state = CAN_STATE_ERROR_ACTIVE;
		WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
		     "bus-off state expected\n");
		out_8(&regs->canmisc, MSCAN_BOHOLD);
		/* Re-enable receive interrupts. */
		out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
	} else {
		if (priv->can.state <= CAN_STATE_BUS_OFF)
			mscan_set_mode(dev, MSCAN_INIT_MODE);
		return mscan_start(dev);
	}

	return 0;
}

static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct can_frame *frame = (struct can_frame *)skb->data;
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	int i, rtr, buf_id;
	u32 can_id;

	if (can_dropped_invalid_skb(dev, skb))
		return NETDEV_TX_OK;

	out_8(&regs->cantier, 0);

	i = ~priv->tx_active & MSCAN_TXE;
	buf_id = ffs(i) - 1;
	switch (hweight8(i)) {
	case 0:
		netif_stop_queue(dev);
		dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n");
		return NETDEV_TX_BUSY;
	case 1:
		/*
		 * if buf_id < 3, then current frame will be send out of order,
		 * since buffer with lower id have higher priority (hell..)
		 */
		netif_stop_queue(dev);
	case 2:
		if (buf_id < priv->prev_buf_id) {
			priv->cur_pri++;
			if (priv->cur_pri == 0xff) {
				set_bit(F_TX_WAIT_ALL, &priv->flags);
				netif_stop_queue(dev);
			}
		}
		set_bit(F_TX_PROGRESS, &priv->flags);
		break;
	}
	priv->prev_buf_id = buf_id;
	out_8(&regs->cantbsel, i);

	rtr = frame->can_id & CAN_RTR_FLAG;

	/* RTR is always the lowest bit of interest, then IDs follow */
	if (frame->can_id & CAN_EFF_FLAG) {
		can_id = (frame->can_id & CAN_EFF_MASK)
			 << (MSCAN_EFF_RTR_SHIFT + 1);
		if (rtr)
			can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
		out_be16(&regs->tx.idr3_2, can_id);

		can_id >>= 16;
		/* EFF_FLAGS are between the IDs :( */
		can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
			 | MSCAN_EFF_FLAGS;
	} else {
		can_id = (frame->can_id & CAN_SFF_MASK)
			 << (MSCAN_SFF_RTR_SHIFT + 1);
		if (rtr)
			can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
	}
	out_be16(&regs->tx.idr1_0, can_id);

	if (!rtr) {
		void __iomem *data = &regs->tx.dsr1_0;
		u16 *payload = (u16 *)frame->data;

		for (i = 0; i < frame->can_dlc / 2; i++) {
			out_be16(data, *payload++);
			data += 2 + _MSCAN_RESERVED_DSR_SIZE;
		}
		/* write remaining byte if necessary */
		if (frame->can_dlc & 1)
			out_8(data, frame->data[frame->can_dlc - 1]);
	}

	out_8(&regs->tx.dlr, frame->can_dlc);
	out_8(&regs->tx.tbpr, priv->cur_pri);

	/* Start transmission. */
	out_8(&regs->cantflg, 1 << buf_id);

	if (!test_bit(F_TX_PROGRESS, &priv->flags))
		dev->trans_start = jiffies;

	list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);

	can_put_echo_skb(skb, dev, buf_id);

	/* Enable interrupt. */
	priv->tx_active |= 1 << buf_id;
	out_8(&regs->cantier, priv->tx_active);

	return NETDEV_TX_OK;
}

/* This function returns the old state to see where we came from */
static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
{
	struct mscan_priv *priv = netdev_priv(dev);
	enum can_state state, old_state = priv->can.state;

	if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
		state = state_map[max(MSCAN_STATE_RX(canrflg),
				      MSCAN_STATE_TX(canrflg))];
		priv->can.state = state;
	}
	return old_state;
}

static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	u32 can_id;
	int i;

	can_id = in_be16(&regs->rx.idr1_0);
	if (can_id & (1 << 3)) {
		frame->can_id = CAN_EFF_FLAG;
		can_id = ((can_id << 16) | in_be16(&regs->rx.idr3_2));
		can_id = ((can_id & 0xffe00000) |
			  ((can_id & 0x7ffff) << 2)) >> 2;
	} else {
		can_id >>= 4;
		frame->can_id = 0;
	}

	frame->can_id |= can_id >> 1;
	if (can_id & 1)
		frame->can_id |= CAN_RTR_FLAG;

	frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);

	if (!(frame->can_id & CAN_RTR_FLAG)) {
		void __iomem *data = &regs->rx.dsr1_0;
		u16 *payload = (u16 *)frame->data;

		for (i = 0; i < frame->can_dlc / 2; i++) {
			*payload++ = in_be16(data);
			data += 2 + _MSCAN_RESERVED_DSR_SIZE;
		}
		/* read remaining byte if necessary */
		if (frame->can_dlc & 1)
			frame->data[frame->can_dlc - 1] = in_8(data);
	}

	out_8(&regs->canrflg, MSCAN_RXF);
}

static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
				u8 canrflg)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	struct net_device_stats *stats = &dev->stats;
	enum can_state old_state;

	dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg);
	frame->can_id = CAN_ERR_FLAG;

	if (canrflg & MSCAN_OVRIF) {
		frame->can_id |= CAN_ERR_CRTL;
		frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
		stats->rx_over_errors++;
		stats->rx_errors++;
	} else {
		frame->data[1] = 0;
	}

	old_state = check_set_state(dev, canrflg);
	/* State changed */
	if (old_state != priv->can.state) {
		switch (priv->can.state) {
		case CAN_STATE_ERROR_WARNING:
			frame->can_id |= CAN_ERR_CRTL;
			priv->can.can_stats.error_warning++;
			if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
			    (canrflg & MSCAN_RSTAT_MSK))
				frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
			if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
			    (canrflg & MSCAN_TSTAT_MSK))
				frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
			break;
		case CAN_STATE_ERROR_PASSIVE:
			frame->can_id |= CAN_ERR_CRTL;
			priv->can.can_stats.error_passive++;
			frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
			break;
		case CAN_STATE_BUS_OFF:
			frame->can_id |= CAN_ERR_BUSOFF;
			/*
			 * The MSCAN on the MPC5200 does recover from bus-off
			 * automatically. To avoid that we stop the chip doing
			 * a light-weight stop (we are in irq-context).
			 */
			if (priv->type != MSCAN_TYPE_MPC5121) {
				out_8(&regs->cantier, 0);
				out_8(&regs->canrier, 0);
				setbits8(&regs->canctl0,
					 MSCAN_SLPRQ | MSCAN_INITRQ);
			}
			can_bus_off(dev);
			break;
		default:
			break;
		}
	}
	priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
	frame->can_dlc = CAN_ERR_DLC;
	out_8(&regs->canrflg, MSCAN_ERR_IF);
}

static int mscan_rx_poll(struct napi_struct *napi, int quota)
{
	struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
	struct net_device *dev = napi->dev;
	struct mscan_regs __iomem *regs = priv->reg_base;
	struct net_device_stats *stats = &dev->stats;
	int npackets = 0;
	int ret = 1;
	struct sk_buff *skb;
	struct can_frame *frame;
	u8 canrflg;

	while (npackets < quota) {
		canrflg = in_8(&regs->canrflg);
		if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
			break;

		skb = alloc_can_skb(dev, &frame);
		if (!skb) {
			if (printk_ratelimit())
				dev_notice(dev->dev.parent, "packet dropped\n");
			stats->rx_dropped++;
			out_8(&regs->canrflg, canrflg);
			continue;
		}

		if (canrflg & MSCAN_RXF)
			mscan_get_rx_frame(dev, frame);
		else if (canrflg & MSCAN_ERR_IF)
			mscan_get_err_frame(dev, frame, canrflg);

		stats->rx_packets++;
		stats->rx_bytes += frame->can_dlc;
		npackets++;
		netif_receive_skb(skb);
	}

	if (!(in_8(&regs->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
		napi_complete(&priv->napi);
		clear_bit(F_RX_PROGRESS, &priv->flags);
		if (priv->can.state < CAN_STATE_BUS_OFF)
			out_8(&regs->canrier, priv->shadow_canrier);
		ret = 0;
	}
	return ret;
}

static irqreturn_t mscan_isr(int irq, void *dev_id)
{
	struct net_device *dev = (struct net_device *)dev_id;
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	struct net_device_stats *stats = &dev->stats;
	u8 cantier, cantflg, canrflg;
	irqreturn_t ret = IRQ_NONE;

	cantier = in_8(&regs->cantier) & MSCAN_TXE;
	cantflg = in_8(&regs->cantflg) & cantier;

	if (cantier && cantflg) {
		struct list_head *tmp, *pos;

		list_for_each_safe(pos, tmp, &priv->tx_head) {
			struct tx_queue_entry *entry =
			    list_entry(pos, struct tx_queue_entry, list);
			u8 mask = entry->mask;

			if (!(cantflg & mask))
				continue;

			out_8(&regs->cantbsel, mask);
			stats->tx_bytes += in_8(&regs->tx.dlr);
			stats->tx_packets++;
			can_get_echo_skb(dev, entry->id);
			priv->tx_active &= ~mask;
			list_del(pos);
		}

		if (list_empty(&priv->tx_head)) {
			clear_bit(F_TX_WAIT_ALL, &priv->flags);
			clear_bit(F_TX_PROGRESS, &priv->flags);
			priv->cur_pri = 0;
		} else {
			dev->trans_start = jiffies;
		}

		if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
			netif_wake_queue(dev);

		out_8(&regs->cantier, priv->tx_active);
		ret = IRQ_HANDLED;
	}

	canrflg = in_8(&regs->canrflg);
	if ((canrflg & ~MSCAN_STAT_MSK) &&
	    !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
		if (canrflg & ~MSCAN_STAT_MSK) {
			priv->shadow_canrier = in_8(&regs->canrier);
			out_8(&regs->canrier, 0);
			napi_schedule(&priv->napi);
			ret = IRQ_HANDLED;
		} else {
			clear_bit(F_RX_PROGRESS, &priv->flags);
		}
	}
	return ret;
}

static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
{
	struct mscan_priv *priv = netdev_priv(dev);
	int ret = 0;

	if (!priv->open_time)
		return -EINVAL;

	switch (mode) {
	case CAN_MODE_START:
		ret = mscan_restart(dev);
		if (ret)
			break;
		if (netif_queue_stopped(dev))
			netif_wake_queue(dev);
		break;

	default:
		ret = -EOPNOTSUPP;
		break;
	}
	return ret;
}

static int mscan_do_set_bittiming(struct net_device *dev)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	struct can_bittiming *bt = &priv->can.bittiming;
	u8 btr0, btr1;

	btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
	btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
		BTR1_SET_TSEG2(bt->phase_seg2) |
		BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));

	dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n",
		btr0, btr1);

	out_8(&regs->canbtr0, btr0);
	out_8(&regs->canbtr1, btr1);

	return 0;
}

static int mscan_open(struct net_device *dev)
{
	int ret;
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;

	/* common open */
	ret = open_candev(dev);
	if (ret)
		return ret;

	napi_enable(&priv->napi);

	ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
	if (ret < 0) {
		dev_err(dev->dev.parent, "failed to attach interrupt\n");
		goto exit_napi_disable;
	}

	priv->open_time = jiffies;

	if (ctrlmode.flags & CAN_CTRLMODE_LISTENONLY)
		setbits8(&regs->canctl1, MSCAN_LISTEN);
	else
		clrbits8(&regs->canctl1, MSCAN_LISTEN);

	ret = mscan_start(dev);
	if (ret)
		goto exit_free_irq;

	netif_start_queue(dev);

	return 0;

exit_free_irq:
	priv->open_time = 0;
	free_irq(dev->irq, dev);
exit_napi_disable:
	napi_disable(&priv->napi);
	close_candev(dev);
	return ret;
}

static int mscan_close(struct net_device *dev)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;

	netif_stop_queue(dev);
	napi_disable(&priv->napi);

	out_8(&regs->cantier, 0);
	out_8(&regs->canrier, 0);
	mscan_set_mode(dev, MSCAN_INIT_MODE);
	close_candev(dev);
	free_irq(dev->irq, dev);
	priv->open_time = 0;

	return 0;
}

static const struct net_device_ops mscan_netdev_ops = {
       .ndo_open               = mscan_open,
       .ndo_stop               = mscan_close,
       .ndo_start_xmit         = mscan_start_xmit,
};

int register_mscandev(struct net_device *dev, int mscan_clksrc)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	u8 ctl1;

	ctl1 = in_8(&regs->canctl1);
	if (mscan_clksrc)
		ctl1 |= MSCAN_CLKSRC;
	else
		ctl1 &= ~MSCAN_CLKSRC;

	if (priv->type == MSCAN_TYPE_MPC5121)
		ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */

	ctl1 |= MSCAN_CANE;
	out_8(&regs->canctl1, ctl1);
	udelay(100);

	/* acceptance mask/acceptance code (accept everything) */
	out_be16(&regs->canidar1_0, 0);
	out_be16(&regs->canidar3_2, 0);
	out_be16(&regs->canidar5_4, 0);
	out_be16(&regs->canidar7_6, 0);

	out_be16(&regs->canidmr1_0, 0xffff);
	out_be16(&regs->canidmr3_2, 0xffff);
	out_be16(&regs->canidmr5_4, 0xffff);
	out_be16(&regs->canidmr7_6, 0xffff);
	/* Two 32 bit Acceptance Filters */
	out_8(&regs->canidac, MSCAN_AF_32BIT);

	mscan_set_mode(dev, MSCAN_INIT_MODE);

	return register_candev(dev);
}

void unregister_mscandev(struct net_device *dev)
{
	struct mscan_priv *priv = netdev_priv(dev);
	struct mscan_regs __iomem *regs = priv->reg_base;
	mscan_set_mode(dev, MSCAN_INIT_MODE);
	clrbits8(&regs->canctl1, MSCAN_CANE);
	unregister_candev(dev);
}

struct net_device *alloc_mscandev(void)
{
	struct net_device *dev;
	struct mscan_priv *priv;
	int i;

	dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
	if (!dev)
		return NULL;
	priv = netdev_priv(dev);

	dev->netdev_ops = &mscan_netdev_ops;

	dev->flags |= IFF_ECHO;	/* we support local echo */

	netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);

	priv->can.bittiming_const = &mscan_bittiming_const;
	priv->can.do_set_bittiming = mscan_do_set_bittiming;
	priv->can.do_set_mode = mscan_do_set_mode;
	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
		CAN_CTRLMODE_LISTENONLY;

	for (i = 0; i < TX_QUEUE_SIZE; i++) {
		priv->tx_queue[i].id = i;
		priv->tx_queue[i].mask = 1 << i;
	}

	return dev;
}

MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
Commit	Line	Data
afa17a50 WS	1	/*
	2	* CAN bus driver for the alone generic (as possible as) MSCAN controller.
	3	*
	4	* Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
	5	* Varma Electronics Oy
	6	* Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
2d4b6faf	7	* Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
afa17a50 WS	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the version 2 of the GNU General Public License
	11	* as published by the Free Software Foundation
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/delay.h>
	27	#include <linux/netdevice.h>
	28	#include <linux/if_arp.h>
	29	#include <linux/if_ether.h>
	30	#include <linux/list.h>
afa17a50 WS	31	#include <linux/can/dev.h>
	32	#include <linux/can/error.h>
	33	#include <linux/io.h>
	34
	35	#include "mscan.h"
	36
afa17a50 WS	37	static struct can_bittiming_const mscan_bittiming_const = {
	38	.name = "mscan",
	39	.tseg1_min = 4,
	40	.tseg1_max = 16,
	41	.tseg2_min = 2,
	42	.tseg2_max = 8,
	43	.sjw_max = 4,
	44	.brp_min = 1,
	45	.brp_max = 64,
	46	.brp_inc = 1,
	47	};
	48
	49	struct mscan_state {
	50	u8 mode;
	51	u8 canrier;
	52	u8 cantier;
	53	};
	54
afa17a50 WS	55	static enum can_state state_map[] = {
	56	CAN_STATE_ERROR_ACTIVE,
	57	CAN_STATE_ERROR_WARNING,
	58	CAN_STATE_ERROR_PASSIVE,
	59	CAN_STATE_BUS_OFF
	60	};
	61
	62	static int mscan_set_mode(struct net_device *dev, u8 mode)
	63	{
	64	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	65	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	66	int ret = 0;
	67	int i;
	68	u8 canctl1;
	69
	70	if (mode != MSCAN_NORMAL_MODE) {
afa17a50 WS	71	if (priv->tx_active) {
	72	/* Abort transfers before going to sleep */#
	73	out_8(&regs->cantarq, priv->tx_active);
	74	/* Suppress TX done interrupts */
	75	out_8(&regs->cantier, 0);
	76	}
	77
	78	canctl1 = in_8(&regs->canctl1);
0285e7ce	79	if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
59179ea6	80	setbits8(&regs->canctl0, MSCAN_SLPRQ);
afa17a50 WS	81	for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
	82	if (in_8(&regs->canctl1) & MSCAN_SLPAK)
	83	break;
	84	udelay(100);
	85	}
	86	/*
	87	* The mscan controller will fail to enter sleep mode,
	88	* while there are irregular activities on bus, like
	89	* somebody keeps retransmitting. This behavior is
	90	* undocumented and seems to differ between mscan built
	91	* in mpc5200b and mpc5200. We proceed in that case,
	92	* since otherwise the slprq will be kept set and the
	93	* controller will get stuck. NOTE: INITRQ or CSWAI
	94	* will abort all active transmit actions, if still
	95	* any, at once.
	96	*/
	97	if (i >= MSCAN_SET_MODE_RETRIES)
	98	dev_dbg(dev->dev.parent,
	99	"device failed to enter sleep mode. "
	100	"We proceed anyhow.\n");
	101	else
	102	priv->can.state = CAN_STATE_SLEEPING;
	103	}
	104
0285e7ce	105	if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
59179ea6	106	setbits8(&regs->canctl0, MSCAN_INITRQ);
afa17a50 WS	107	for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
	108	if (in_8(&regs->canctl1) & MSCAN_INITAK)
	109	break;
	110	}
	111	if (i >= MSCAN_SET_MODE_RETRIES)
	112	ret = -ENODEV;
	113	}
	114	if (!ret)
	115	priv->can.state = CAN_STATE_STOPPED;
	116
	117	if (mode & MSCAN_CSWAI)
59179ea6	118	setbits8(&regs->canctl0, MSCAN_CSWAI);
afa17a50 WS	119
	120	} else {
	121	canctl1 = in_8(&regs->canctl1);
	122	if (canctl1 & (MSCAN_SLPAK \| MSCAN_INITAK)) {
59179ea6	123	clrbits8(&regs->canctl0, MSCAN_SLPRQ \| MSCAN_INITRQ);
afa17a50 WS	124	for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
	125	canctl1 = in_8(&regs->canctl1);
	126	if (!(canctl1 & (MSCAN_INITAK \| MSCAN_SLPAK)))
	127	break;
	128	}
	129	if (i >= MSCAN_SET_MODE_RETRIES)
	130	ret = -ENODEV;
	131	else
	132	priv->can.state = CAN_STATE_ERROR_ACTIVE;
	133	}
	134	}
	135	return ret;
	136	}
	137
	138	static int mscan_start(struct net_device *dev)
	139	{
	140	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	141	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	142	u8 canrflg;
	143	int err;
	144
	145	out_8(&regs->canrier, 0);
	146
	147	INIT_LIST_HEAD(&priv->tx_head);
	148	priv->prev_buf_id = 0;
	149	priv->cur_pri = 0;
	150	priv->tx_active = 0;
	151	priv->shadow_canrier = 0;
	152	priv->flags = 0;
	153
bf3af547 WG	154	if (priv->type == MSCAN_TYPE_MPC5121) {
	155	/* Clear pending bus-off condition */
	156	if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
	157	out_8(&regs->canmisc, MSCAN_BOHOLD);
	158	}
	159
afa17a50 WS	160	err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
	161	if (err)
	162	return err;
	163
	164	canrflg = in_8(&regs->canrflg);
	165	priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
	166	priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
	167	MSCAN_STATE_TX(canrflg))];
	168	out_8(&regs->cantier, 0);
	169
	170	/* Enable receive interrupts. */
bf3af547 WG	171	out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
	172
	173	return 0;
	174	}
	175
	176	static int mscan_restart(struct net_device *dev)
	177	{
	178	struct mscan_priv *priv = netdev_priv(dev);
	179
	180	if (priv->type == MSCAN_TYPE_MPC5121) {
665d7eb8	181	struct mscan_regs __iomem *regs = priv->reg_base;
bf3af547 WG	182
	183	priv->can.state = CAN_STATE_ERROR_ACTIVE;
	184	WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
c389ff80	185	"bus-off state expected\n");
bf3af547 WG	186	out_8(&regs->canmisc, MSCAN_BOHOLD);
	187	/* Re-enable receive interrupts. */
	188	out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
	189	} else {
	190	if (priv->can.state <= CAN_STATE_BUS_OFF)
	191	mscan_set_mode(dev, MSCAN_INIT_MODE);
	192	return mscan_start(dev);
	193	}
afa17a50 WS	194
	195	return 0;
	196	}
	197
	198	static netdev_tx_t mscan_start_xmit(struct sk_buff skb, struct net_device dev)
	199	{
	200	struct can_frame frame = (struct can_frame )skb->data;
	201	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	202	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	203	int i, rtr, buf_id;
	204	u32 can_id;
	205
3ccd4c61	206	if (can_dropped_invalid_skb(dev, skb))
2d4b6faf	207	return NETDEV_TX_OK;
afa17a50 WS	208
	209	out_8(&regs->cantier, 0);
	210
	211	i = ~priv->tx_active & MSCAN_TXE;
	212	buf_id = ffs(i) - 1;
	213	switch (hweight8(i)) {
	214	case 0:
	215	netif_stop_queue(dev);
	216	dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n");
	217	return NETDEV_TX_BUSY;
	218	case 1:
	219	/*
	220	* if buf_id < 3, then current frame will be send out of order,
	221	* since buffer with lower id have higher priority (hell..)
	222	*/
	223	netif_stop_queue(dev);
	224	case 2:
	225	if (buf_id < priv->prev_buf_id) {
	226	priv->cur_pri++;
	227	if (priv->cur_pri == 0xff) {
	228	set_bit(F_TX_WAIT_ALL, &priv->flags);
	229	netif_stop_queue(dev);
	230	}
	231	}
	232	set_bit(F_TX_PROGRESS, &priv->flags);
	233	break;
	234	}
	235	priv->prev_buf_id = buf_id;
	236	out_8(&regs->cantbsel, i);
	237
	238	rtr = frame->can_id & CAN_RTR_FLAG;
	239
74ff60b2	240	/* RTR is always the lowest bit of interest, then IDs follow */
afa17a50	241	if (frame->can_id & CAN_EFF_FLAG) {
74ff60b2 WS	242	can_id = (frame->can_id & CAN_EFF_MASK)
74ff60b2 WS	243	<< (MSCAN_EFF_RTR_SHIFT + 1);
afa17a50	244	if (rtr)
74ff60b2	245	can_id \|= 1 << MSCAN_EFF_RTR_SHIFT;
afa17a50 WS	246	out_be16(&regs->tx.idr3_2, can_id);
	247
	248	can_id >>= 16;
25985edc	249	/* EFF_FLAGS are between the IDs :( */
74ff60b2 WS	250	can_id = (can_id & 0x7) \| ((can_id << 2) & 0xffe0)
74ff60b2 WS	251	\| MSCAN_EFF_FLAGS;
afa17a50	252	} else {
74ff60b2 WS	253	can_id = (frame->can_id & CAN_SFF_MASK)
74ff60b2 WS	254	<< (MSCAN_SFF_RTR_SHIFT + 1);
afa17a50	255	if (rtr)
74ff60b2	256	can_id \|= 1 << MSCAN_SFF_RTR_SHIFT;
afa17a50 WS	257	}
	258	out_be16(&regs->tx.idr1_0, can_id);
	259
	260	if (!rtr) {
	261	void __iomem *data = &regs->tx.dsr1_0;
0285e7ce WS	262	u16 payload = (u16 )frame->data;
0285e7ce WS	263
a3a4bfde	264	for (i = 0; i < frame->can_dlc / 2; i++) {
afa17a50 WS	265	out_be16(data, *payload++);
	266	data += 2 + _MSCAN_RESERVED_DSR_SIZE;
	267	}
a3a4bfde WG	268	/* write remaining byte if necessary */
	269	if (frame->can_dlc & 1)
	270	out_8(data, frame->data[frame->can_dlc - 1]);
afa17a50 WS	271	}
	272
	273	out_8(&regs->tx.dlr, frame->can_dlc);
	274	out_8(&regs->tx.tbpr, priv->cur_pri);
	275
	276	/* Start transmission. */
	277	out_8(&regs->cantflg, 1 << buf_id);
	278
	279	if (!test_bit(F_TX_PROGRESS, &priv->flags))
	280	dev->trans_start = jiffies;
	281
	282	list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
	283
	284	can_put_echo_skb(skb, dev, buf_id);
	285
	286	/* Enable interrupt. */
	287	priv->tx_active \|= 1 << buf_id;
	288	out_8(&regs->cantier, priv->tx_active);
	289
	290	return NETDEV_TX_OK;
	291	}
	292
	293	/* This function returns the old state to see where we came from */
	294	static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
	295	{
	296	struct mscan_priv *priv = netdev_priv(dev);
	297	enum can_state state, old_state = priv->can.state;
	298
	299	if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
	300	state = state_map[max(MSCAN_STATE_RX(canrflg),
	301	MSCAN_STATE_TX(canrflg))];
	302	priv->can.state = state;
	303	}
	304	return old_state;
	305	}
	306
	307	static void mscan_get_rx_frame(struct net_device dev, struct can_frame frame)
	308	{
	309	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	310	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	311	u32 can_id;
	312	int i;
	313
	314	can_id = in_be16(&regs->rx.idr1_0);
	315	if (can_id & (1 << 3)) {
	316	frame->can_id = CAN_EFF_FLAG;
	317	can_id = ((can_id << 16) \| in_be16(&regs->rx.idr3_2));
	318	can_id = ((can_id & 0xffe00000) \|
	319	((can_id & 0x7ffff) << 2)) >> 2;
	320	} else {
	321	can_id >>= 4;
	322	frame->can_id = 0;
	323	}
	324
	325	frame->can_id \|= can_id >> 1;
	326	if (can_id & 1)
	327	frame->can_id \|= CAN_RTR_FLAG;
c7cd606f OH	328
c7cd606f OH	329	frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);
afa17a50 WS	330
	331	if (!(frame->can_id & CAN_RTR_FLAG)) {
	332	void __iomem *data = &regs->rx.dsr1_0;
0285e7ce WS	333	u16 payload = (u16 )frame->data;
0285e7ce WS	334
a3a4bfde	335	for (i = 0; i < frame->can_dlc / 2; i++) {
afa17a50 WS	336	*payload++ = in_be16(data);
	337	data += 2 + _MSCAN_RESERVED_DSR_SIZE;
	338	}
a3a4bfde WG	339	/* read remaining byte if necessary */
	340	if (frame->can_dlc & 1)
	341	frame->data[frame->can_dlc - 1] = in_8(data);
afa17a50 WS	342	}
	343
	344	out_8(&regs->canrflg, MSCAN_RXF);
	345	}
	346
	347	static void mscan_get_err_frame(struct net_device dev, struct can_frame frame,
	348	u8 canrflg)
	349	{
	350	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	351	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	352	struct net_device_stats *stats = &dev->stats;
	353	enum can_state old_state;
	354
	355	dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg);
	356	frame->can_id = CAN_ERR_FLAG;
	357
	358	if (canrflg & MSCAN_OVRIF) {
	359	frame->can_id \|= CAN_ERR_CRTL;
	360	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
	361	stats->rx_over_errors++;
	362	stats->rx_errors++;
0285e7ce	363	} else {
afa17a50	364	frame->data[1] = 0;
0285e7ce	365	}
afa17a50 WS	366
	367	old_state = check_set_state(dev, canrflg);
	368	/* State changed */
	369	if (old_state != priv->can.state) {
	370	switch (priv->can.state) {
	371	case CAN_STATE_ERROR_WARNING:
	372	frame->can_id \|= CAN_ERR_CRTL;
	373	priv->can.can_stats.error_warning++;
	374	if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
	375	(canrflg & MSCAN_RSTAT_MSK))
	376	frame->data[1] \|= CAN_ERR_CRTL_RX_WARNING;
afa17a50 WS	377	if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
	378	(canrflg & MSCAN_TSTAT_MSK))
	379	frame->data[1] \|= CAN_ERR_CRTL_TX_WARNING;
	380	break;
	381	case CAN_STATE_ERROR_PASSIVE:
	382	frame->can_id \|= CAN_ERR_CRTL;
	383	priv->can.can_stats.error_passive++;
	384	frame->data[1] \|= CAN_ERR_CRTL_RX_PASSIVE;
	385	break;
	386	case CAN_STATE_BUS_OFF:
	387	frame->can_id \|= CAN_ERR_BUSOFF;
	388	/*
	389	* The MSCAN on the MPC5200 does recover from bus-off
	390	* automatically. To avoid that we stop the chip doing
	391	* a light-weight stop (we are in irq-context).
	392	*/
bf3af547 WG	393	if (priv->type != MSCAN_TYPE_MPC5121) {
	394	out_8(&regs->cantier, 0);
	395	out_8(&regs->canrier, 0);
	396	setbits8(&regs->canctl0,
	397	MSCAN_SLPRQ \| MSCAN_INITRQ);
	398	}
afa17a50 WS	399	can_bus_off(dev);
	400	break;
	401	default:
	402	break;
	403	}
	404	}
	405	priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
	406	frame->can_dlc = CAN_ERR_DLC;
	407	out_8(&regs->canrflg, MSCAN_ERR_IF);
	408	}
	409
	410	static int mscan_rx_poll(struct napi_struct *napi, int quota)
	411	{
	412	struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
	413	struct net_device *dev = napi->dev;
665d7eb8	414	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	415	struct net_device_stats *stats = &dev->stats;
	416	int npackets = 0;
	417	int ret = 1;
	418	struct sk_buff *skb;
	419	struct can_frame *frame;
	420	u8 canrflg;
	421
68bd7422 WS	422	while (npackets < quota) {
	423	canrflg = in_8(&regs->canrflg);
	424	if (!(canrflg & (MSCAN_RXF \| MSCAN_ERR_IF)))
	425	break;
afa17a50 WS	426
	427	skb = alloc_can_skb(dev, &frame);
	428	if (!skb) {
	429	if (printk_ratelimit())
	430	dev_notice(dev->dev.parent, "packet dropped\n");
	431	stats->rx_dropped++;
	432	out_8(&regs->canrflg, canrflg);
	433	continue;
	434	}
	435
	436	if (canrflg & MSCAN_RXF)
	437	mscan_get_rx_frame(dev, frame);
0285e7ce	438	else if (canrflg & MSCAN_ERR_IF)
afa17a50 WS	439	mscan_get_err_frame(dev, frame, canrflg);
	440
	441	stats->rx_packets++;
	442	stats->rx_bytes += frame->can_dlc;
	443	npackets++;
	444	netif_receive_skb(skb);
	445	}
	446
	447	if (!(in_8(&regs->canrflg) & (MSCAN_RXF \| MSCAN_ERR_IF))) {
	448	napi_complete(&priv->napi);
	449	clear_bit(F_RX_PROGRESS, &priv->flags);
	450	if (priv->can.state < CAN_STATE_BUS_OFF)
	451	out_8(&regs->canrier, priv->shadow_canrier);
	452	ret = 0;
	453	}
	454	return ret;
	455	}
	456
	457	static irqreturn_t mscan_isr(int irq, void *dev_id)
	458	{
	459	struct net_device dev = (struct net_device )dev_id;
	460	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	461	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	462	struct net_device_stats *stats = &dev->stats;
	463	u8 cantier, cantflg, canrflg;
	464	irqreturn_t ret = IRQ_NONE;
	465
	466	cantier = in_8(&regs->cantier) & MSCAN_TXE;
	467	cantflg = in_8(&regs->cantflg) & cantier;
	468
	469	if (cantier && cantflg) {
afa17a50 WS	470	struct list_head tmp, pos;
	471
	472	list_for_each_safe(pos, tmp, &priv->tx_head) {
	473	struct tx_queue_entry *entry =
	474	list_entry(pos, struct tx_queue_entry, list);
	475	u8 mask = entry->mask;
	476
	477	if (!(cantflg & mask))
	478	continue;
	479
	480	out_8(&regs->cantbsel, mask);
	481	stats->tx_bytes += in_8(&regs->tx.dlr);
	482	stats->tx_packets++;
	483	can_get_echo_skb(dev, entry->id);
	484	priv->tx_active &= ~mask;
	485	list_del(pos);
	486	}
	487
	488	if (list_empty(&priv->tx_head)) {
	489	clear_bit(F_TX_WAIT_ALL, &priv->flags);
	490	clear_bit(F_TX_PROGRESS, &priv->flags);
	491	priv->cur_pri = 0;
0285e7ce	492	} else {
afa17a50	493	dev->trans_start = jiffies;
0285e7ce	494	}
afa17a50 WS	495
	496	if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
	497	netif_wake_queue(dev);
	498
	499	out_8(&regs->cantier, priv->tx_active);
	500	ret = IRQ_HANDLED;
	501	}
	502
	503	canrflg = in_8(&regs->canrflg);
	504	if ((canrflg & ~MSCAN_STAT_MSK) &&
	505	!test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
	506	if (canrflg & ~MSCAN_STAT_MSK) {
	507	priv->shadow_canrier = in_8(&regs->canrier);
	508	out_8(&regs->canrier, 0);
	509	napi_schedule(&priv->napi);
	510	ret = IRQ_HANDLED;
0285e7ce	511	} else {
afa17a50	512	clear_bit(F_RX_PROGRESS, &priv->flags);
0285e7ce	513	}
afa17a50 WS	514	}
	515	return ret;
	516	}
	517
	518	static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
	519	{
afa17a50 WS	520	struct mscan_priv *priv = netdev_priv(dev);
	521	int ret = 0;
	522
	523	if (!priv->open_time)
	524	return -EINVAL;
	525
	526	switch (mode) {
afa17a50	527	case CAN_MODE_START:
bf3af547	528	ret = mscan_restart(dev);
afa17a50 WS	529	if (ret)
	530	break;
	531	if (netif_queue_stopped(dev))
	532	netif_wake_queue(dev);
	533	break;
	534
	535	default:
	536	ret = -EOPNOTSUPP;
	537	break;
	538	}
	539	return ret;
	540	}
	541
	542	static int mscan_do_set_bittiming(struct net_device *dev)
	543	{
	544	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	545	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	546	struct can_bittiming *bt = &priv->can.bittiming;
	547	u8 btr0, btr1;
	548
	549	btr0 = BTR0_SET_BRP(bt->brp) \| BTR0_SET_SJW(bt->sjw);
	550	btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) \|
	551	BTR1_SET_TSEG2(bt->phase_seg2) \|
	552	BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
	553
	554	dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n",
	555	btr0, btr1);
	556
	557	out_8(&regs->canbtr0, btr0);
	558	out_8(&regs->canbtr1, btr1);
	559
	560	return 0;
	561	}
	562
	563	static int mscan_open(struct net_device *dev)
	564	{
	565	int ret;
	566	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	567	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	568
	569	/* common open */
	570	ret = open_candev(dev);
	571	if (ret)
	572	return ret;
	573
	574	napi_enable(&priv->napi);
	575
	576	ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
	577	if (ret < 0) {
323907ac WS	578	dev_err(dev->dev.parent, "failed to attach interrupt\n");
323907ac WS	579	goto exit_napi_disable;
afa17a50 WS	580	}
	581
	582	priv->open_time = jiffies;
	583
452448f9 MKB	584	if (ctrlmode.flags & CAN_CTRLMODE_LISTENONLY)
	585	setbits8(&regs->canctl1, MSCAN_LISTEN);
	586	else
	587	clrbits8(&regs->canctl1, MSCAN_LISTEN);
afa17a50 WS	588
	589	ret = mscan_start(dev);
	590	if (ret)
323907ac	591	goto exit_free_irq;
afa17a50 WS	592
	593	netif_start_queue(dev);
	594
	595	return 0;
323907ac WS	596
	597	exit_free_irq:
	598	priv->open_time = 0;
	599	free_irq(dev->irq, dev);
	600	exit_napi_disable:
	601	napi_disable(&priv->napi);
	602	close_candev(dev);
	603	return ret;
afa17a50 WS	604	}
	605
	606	static int mscan_close(struct net_device *dev)
	607	{
	608	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	609	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	610
	611	netif_stop_queue(dev);
	612	napi_disable(&priv->napi);
	613
	614	out_8(&regs->cantier, 0);
	615	out_8(&regs->canrier, 0);
	616	mscan_set_mode(dev, MSCAN_INIT_MODE);
	617	close_candev(dev);
	618	free_irq(dev->irq, dev);
	619	priv->open_time = 0;
	620
	621	return 0;
	622	}
	623
	624	static const struct net_device_ops mscan_netdev_ops = {
	625	.ndo_open = mscan_open,
	626	.ndo_stop = mscan_close,
	627	.ndo_start_xmit = mscan_start_xmit,
	628	};
	629
bf3af547	630	int register_mscandev(struct net_device *dev, int mscan_clksrc)
afa17a50 WS	631	{
afa17a50 WS	632	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	633	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 WS	634	u8 ctl1;
	635
	636	ctl1 = in_8(&regs->canctl1);
bf3af547	637	if (mscan_clksrc)
afa17a50 WS	638	ctl1 \|= MSCAN_CLKSRC;
	639	else
	640	ctl1 &= ~MSCAN_CLKSRC;
	641
bf3af547 WG	642	if (priv->type == MSCAN_TYPE_MPC5121)
	643	ctl1 \|= MSCAN_BORM; /* bus-off recovery upon request */
	644
afa17a50 WS	645	ctl1 \|= MSCAN_CANE;
	646	out_8(&regs->canctl1, ctl1);
	647	udelay(100);
	648
	649	/* acceptance mask/acceptance code (accept everything) */
	650	out_be16(&regs->canidar1_0, 0);
	651	out_be16(&regs->canidar3_2, 0);
	652	out_be16(&regs->canidar5_4, 0);
	653	out_be16(&regs->canidar7_6, 0);
	654
	655	out_be16(&regs->canidmr1_0, 0xffff);
	656	out_be16(&regs->canidmr3_2, 0xffff);
	657	out_be16(&regs->canidmr5_4, 0xffff);
	658	out_be16(&regs->canidmr7_6, 0xffff);
	659	/* Two 32 bit Acceptance Filters */
	660	out_8(&regs->canidac, MSCAN_AF_32BIT);
	661
	662	mscan_set_mode(dev, MSCAN_INIT_MODE);
	663
	664	return register_candev(dev);
	665	}
afa17a50 WS	666
	667	void unregister_mscandev(struct net_device *dev)
	668	{
	669	struct mscan_priv *priv = netdev_priv(dev);
665d7eb8	670	struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50	671	mscan_set_mode(dev, MSCAN_INIT_MODE);
59179ea6	672	clrbits8(&regs->canctl1, MSCAN_CANE);
afa17a50 WS	673	unregister_candev(dev);
afa17a50 WS	674	}
afa17a50 WS	675
	676	struct net_device *alloc_mscandev(void)
	677	{
	678	struct net_device *dev;
	679	struct mscan_priv *priv;
	680	int i;
	681
	682	dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
	683	if (!dev)
	684	return NULL;
	685	priv = netdev_priv(dev);
	686
	687	dev->netdev_ops = &mscan_netdev_ops;
	688
	689	dev->flags \|= IFF_ECHO; /* we support local echo */
	690
	691	netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
	692
	693	priv->can.bittiming_const = &mscan_bittiming_const;
	694	priv->can.do_set_bittiming = mscan_do_set_bittiming;
	695	priv->can.do_set_mode = mscan_do_set_mode;
452448f9 MKB	696	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES \|
452448f9 MKB	697	CAN_CTRLMODE_LISTENONLY;
afa17a50 WS	698
	699	for (i = 0; i < TX_QUEUE_SIZE; i++) {
	700	priv->tx_queue[i].id = i;
	701	priv->tx_queue[i].mask = 1 << i;
	702	}
	703
	704	return dev;
	705	}
afa17a50 WS	706
	707	MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
	708	MODULE_LICENSE("GPL v2");
	709	MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");