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Merge tag 'gpio-v3.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[linux-2.6-block.git] / drivers / net / can / mscan / mscan.c
CommitLineData
afa17a50
WS		 1/*
2 * CAN bus driver for the alone generic (as possible as) MSCAN controller.
3 *
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
5 * Varma Electronics Oy
6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
2d4b6faf 7 * Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
afa17a50
WS		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
05780d98 19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
afa17a50
WS		 20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/if_arp.h>
28#include <linux/if_ether.h>
29#include <linux/list.h>
afa17a50
WS		 30#include <linux/can/dev.h>
31#include <linux/can/error.h>
32#include <linux/io.h>
33
34#include "mscan.h"
35
194b9a4c 36static const struct can_bittiming_const mscan_bittiming_const = {
afa17a50
WS		 37 .name = "mscan",
38 .tseg1_min = 4,
39 .tseg1_max = 16,
40 .tseg2_min = 2,
41 .tseg2_max = 8,
42 .sjw_max = 4,
43 .brp_min = 1,
44 .brp_max = 64,
45 .brp_inc = 1,
46};
47
48struct mscan_state {
49 u8 mode;
50 u8 canrier;
51 u8 cantier;
52};
53
afa17a50
WS		 54static enum can_state state_map[] = {
55 CAN_STATE_ERROR_ACTIVE,
56 CAN_STATE_ERROR_WARNING,
57 CAN_STATE_ERROR_PASSIVE,
58 CAN_STATE_BUS_OFF
59};
60
61static int mscan_set_mode(struct net_device *dev, u8 mode)
62{
63 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 64 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 65 int ret = 0;
66 int i;
67 u8 canctl1;
68
69 if (mode != MSCAN_NORMAL_MODE) {
afa17a50
WS		 70 if (priv->tx_active) {
71 /* Abort transfers before going to sleep */#
72 out_8(&regs->cantarq, priv->tx_active);
73 /* Suppress TX done interrupts */
74 out_8(&regs->cantier, 0);
75 }
76
77 canctl1 = in_8(&regs->canctl1);
0285e7ce 78 if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
59179ea6 79 setbits8(&regs->canctl0, MSCAN_SLPRQ);
afa17a50
WS		 80 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
81 if (in_8(&regs->canctl1) & MSCAN_SLPAK)
82 break;
83 udelay(100);
84 }
85 /*
86 * The mscan controller will fail to enter sleep mode,
87 * while there are irregular activities on bus, like
88 * somebody keeps retransmitting. This behavior is
89 * undocumented and seems to differ between mscan built
90 * in mpc5200b and mpc5200. We proceed in that case,
91 * since otherwise the slprq will be kept set and the
92 * controller will get stuck. NOTE: INITRQ or CSWAI
93 * will abort all active transmit actions, if still
94 * any, at once.
95 */
96 if (i >= MSCAN_SET_MODE_RETRIES)
aabdfd6a
WG		 97 netdev_dbg(dev,
98 "device failed to enter sleep mode. "
99 "We proceed anyhow.\n");
afa17a50
WS		 100 else
101 priv->can.state = CAN_STATE_SLEEPING;
102 }
103
0285e7ce 104 if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
59179ea6 105 setbits8(&regs->canctl0, MSCAN_INITRQ);
afa17a50
WS		 106 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
107 if (in_8(&regs->canctl1) & MSCAN_INITAK)
108 break;
109 }
110 if (i >= MSCAN_SET_MODE_RETRIES)
111 ret = -ENODEV;
112 }
113 if (!ret)
114 priv->can.state = CAN_STATE_STOPPED;
115
116 if (mode & MSCAN_CSWAI)
59179ea6 117 setbits8(&regs->canctl0, MSCAN_CSWAI);
afa17a50
WS		 118
119 } else {
120 canctl1 = in_8(&regs->canctl1);
121 if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
59179ea6 122 clrbits8(&regs->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
afa17a50
WS		 123 for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
124 canctl1 = in_8(&regs->canctl1);
125 if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
126 break;
127 }
128 if (i >= MSCAN_SET_MODE_RETRIES)
129 ret = -ENODEV;
130 else
131 priv->can.state = CAN_STATE_ERROR_ACTIVE;
132 }
133 }
134 return ret;
135}
136
137static int mscan_start(struct net_device *dev)
138{
139 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 140 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 141 u8 canrflg;
142 int err;
143
144 out_8(&regs->canrier, 0);
145
146 INIT_LIST_HEAD(&priv->tx_head);
147 priv->prev_buf_id = 0;
148 priv->cur_pri = 0;
149 priv->tx_active = 0;
150 priv->shadow_canrier = 0;
151 priv->flags = 0;
152
bf3af547
WG		 153 if (priv->type == MSCAN_TYPE_MPC5121) {
154 /* Clear pending bus-off condition */
155 if (in_8(&regs->canmisc) & MSCAN_BOHOLD)
156 out_8(&regs->canmisc, MSCAN_BOHOLD);
157 }
158
afa17a50
WS		 159 err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
160 if (err)
161 return err;
162
163 canrflg = in_8(&regs->canrflg);
164 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
165 priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
166 MSCAN_STATE_TX(canrflg))];
167 out_8(&regs->cantier, 0);
168
169 /* Enable receive interrupts. */
bf3af547
WG		 170 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
171
172 return 0;
173}
174
175static int mscan_restart(struct net_device *dev)
176{
177 struct mscan_priv *priv = netdev_priv(dev);
178
179 if (priv->type == MSCAN_TYPE_MPC5121) {
665d7eb8 180 struct mscan_regs __iomem *regs = priv->reg_base;
bf3af547
WG		 181
182 priv->can.state = CAN_STATE_ERROR_ACTIVE;
183 WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
c389ff80 184 "bus-off state expected\n");
bf3af547
WG		 185 out_8(&regs->canmisc, MSCAN_BOHOLD);
186 /* Re-enable receive interrupts. */
187 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
188 } else {
189 if (priv->can.state <= CAN_STATE_BUS_OFF)
190 mscan_set_mode(dev, MSCAN_INIT_MODE);
191 return mscan_start(dev);
192 }
afa17a50
WS		 193
194 return 0;
195}
196
197static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
198{
199 struct can_frame *frame = (struct can_frame *)skb->data;
200 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 201 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 202 int i, rtr, buf_id;
203 u32 can_id;
204
3ccd4c61 205 if (can_dropped_invalid_skb(dev, skb))
2d4b6faf 206 return NETDEV_TX_OK;
afa17a50
WS		 207
208 out_8(&regs->cantier, 0);
209
210 i = ~priv->tx_active & MSCAN_TXE;
211 buf_id = ffs(i) - 1;
212 switch (hweight8(i)) {
213 case 0:
214 netif_stop_queue(dev);
aabdfd6a 215 netdev_err(dev, "Tx Ring full when queue awake!\n");
afa17a50
WS		 216 return NETDEV_TX_BUSY;
217 case 1:
218 /*
219 * if buf_id < 3, then current frame will be send out of order,
220 * since buffer with lower id have higher priority (hell..)
221 */
222 netif_stop_queue(dev);
223 case 2:
224 if (buf_id < priv->prev_buf_id) {
225 priv->cur_pri++;
226 if (priv->cur_pri == 0xff) {
227 set_bit(F_TX_WAIT_ALL, &priv->flags);
228 netif_stop_queue(dev);
229 }
230 }
231 set_bit(F_TX_PROGRESS, &priv->flags);
232 break;
233 }
234 priv->prev_buf_id = buf_id;
235 out_8(&regs->cantbsel, i);
236
237 rtr = frame->can_id & CAN_RTR_FLAG;
238
74ff60b2 239 /* RTR is always the lowest bit of interest, then IDs follow */
afa17a50 240 if (frame->can_id & CAN_EFF_FLAG) {
74ff60b2
WS		 241 can_id = (frame->can_id & CAN_EFF_MASK)
242 << (MSCAN_EFF_RTR_SHIFT + 1);
afa17a50 243 if (rtr)
74ff60b2 244 can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
afa17a50
WS		 245 out_be16(&regs->tx.idr3_2, can_id);
246
247 can_id >>= 16;
25985edc 248 /* EFF_FLAGS are between the IDs :( */
74ff60b2
WS		 249 can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
250 | MSCAN_EFF_FLAGS;
afa17a50 251 } else {
74ff60b2
WS		 252 can_id = (frame->can_id & CAN_SFF_MASK)
253 << (MSCAN_SFF_RTR_SHIFT + 1);
afa17a50 254 if (rtr)
74ff60b2 255 can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
afa17a50
WS		 256 }
257 out_be16(&regs->tx.idr1_0, can_id);
258
259 if (!rtr) {
260 void __iomem *data = &regs->tx.dsr1_0;
0285e7ce
WS		 261 u16 *payload = (u16 *)frame->data;
262
a3a4bfde 263 for (i = 0; i < frame->can_dlc / 2; i++) {
afa17a50
WS		 264 out_be16(data, *payload++);
265 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
266 }
a3a4bfde
WG		 267 /* write remaining byte if necessary */
268 if (frame->can_dlc & 1)
269 out_8(data, frame->data[frame->can_dlc - 1]);
afa17a50
WS		 270 }
271
272 out_8(&regs->tx.dlr, frame->can_dlc);
273 out_8(&regs->tx.tbpr, priv->cur_pri);
274
275 /* Start transmission. */
276 out_8(&regs->cantflg, 1 << buf_id);
277
278 if (!test_bit(F_TX_PROGRESS, &priv->flags))
279 dev->trans_start = jiffies;
280
281 list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
282
283 can_put_echo_skb(skb, dev, buf_id);
284
285 /* Enable interrupt. */
286 priv->tx_active |= 1 << buf_id;
287 out_8(&regs->cantier, priv->tx_active);
288
289 return NETDEV_TX_OK;
290}
291
b12a43e6 292static enum can_state get_new_state(struct net_device *dev, u8 canrflg)
afa17a50
WS		 293{
294 struct mscan_priv *priv = netdev_priv(dev);
afa17a50 295
b12a43e6
AY		 296 if (unlikely(canrflg & MSCAN_CSCIF))
297 return state_map[max(MSCAN_STATE_RX(canrflg),
298 MSCAN_STATE_TX(canrflg))];
299
300 return priv->can.state;
afa17a50
WS		 301}
302
303static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
304{
305 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 306 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 307 u32 can_id;
308 int i;
309
310 can_id = in_be16(&regs->rx.idr1_0);
311 if (can_id & (1 << 3)) {
312 frame->can_id = CAN_EFF_FLAG;
313 can_id = ((can_id << 16) | in_be16(&regs->rx.idr3_2));
314 can_id = ((can_id & 0xffe00000) |
315 ((can_id & 0x7ffff) << 2)) >> 2;
316 } else {
317 can_id >>= 4;
318 frame->can_id = 0;
319 }
320
321 frame->can_id |= can_id >> 1;
322 if (can_id & 1)
323 frame->can_id |= CAN_RTR_FLAG;
c7cd606f
OH		 324
325 frame->can_dlc = get_can_dlc(in_8(&regs->rx.dlr) & 0xf);
afa17a50
WS		 326
327 if (!(frame->can_id & CAN_RTR_FLAG)) {
328 void __iomem *data = &regs->rx.dsr1_0;
0285e7ce
WS		 329 u16 *payload = (u16 *)frame->data;
330
a3a4bfde 331 for (i = 0; i < frame->can_dlc / 2; i++) {
afa17a50
WS		 332 *payload++ = in_be16(data);
333 data += 2 + _MSCAN_RESERVED_DSR_SIZE;
334 }
a3a4bfde
WG		 335 /* read remaining byte if necessary */
336 if (frame->can_dlc & 1)
337 frame->data[frame->can_dlc - 1] = in_8(data);
afa17a50
WS		 338 }
339
340 out_8(&regs->canrflg, MSCAN_RXF);
341}
342
343static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
344 u8 canrflg)
345{
346 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 347 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 348 struct net_device_stats *stats = &dev->stats;
b12a43e6 349 enum can_state new_state;
afa17a50 350
aabdfd6a 351 netdev_dbg(dev, "error interrupt (canrflg=%#x)\n", canrflg);
afa17a50
WS		 352 frame->can_id = CAN_ERR_FLAG;
353
354 if (canrflg & MSCAN_OVRIF) {
355 frame->can_id |= CAN_ERR_CRTL;
356 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
357 stats->rx_over_errors++;
358 stats->rx_errors++;
0285e7ce 359 } else {
afa17a50 360 frame->data[1] = 0;
0285e7ce 361 }
afa17a50 362
b12a43e6
AY		 363 new_state = get_new_state(dev, canrflg);
364 if (new_state != priv->can.state) {
365 can_change_state(dev, frame,
366 state_map[MSCAN_STATE_TX(canrflg)],
367 state_map[MSCAN_STATE_RX(canrflg)]);
368
369 if (priv->can.state == CAN_STATE_BUS_OFF) {
afa17a50
WS		 370 /*
371 * The MSCAN on the MPC5200 does recover from bus-off
372 * automatically. To avoid that we stop the chip doing
373 * a light-weight stop (we are in irq-context).
374 */
bf3af547
WG		 375 if (priv->type != MSCAN_TYPE_MPC5121) {
376 out_8(&regs->cantier, 0);
377 out_8(&regs->canrier, 0);
378 setbits8(&regs->canctl0,
379 MSCAN_SLPRQ | MSCAN_INITRQ);
380 }
afa17a50 381 can_bus_off(dev);
afa17a50
WS		 382 }
383 }
384 priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
385 frame->can_dlc = CAN_ERR_DLC;
386 out_8(&regs->canrflg, MSCAN_ERR_IF);
387}
388
389static int mscan_rx_poll(struct napi_struct *napi, int quota)
390{
391 struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
392 struct net_device *dev = napi->dev;
665d7eb8 393 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 394 struct net_device_stats *stats = &dev->stats;
395 int npackets = 0;
396 int ret = 1;
397 struct sk_buff *skb;
398 struct can_frame *frame;
399 u8 canrflg;
400
68bd7422
WS		 401 while (npackets < quota) {
402 canrflg = in_8(&regs->canrflg);
403 if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
404 break;
afa17a50
WS		 405
406 skb = alloc_can_skb(dev, &frame);
407 if (!skb) {
408 if (printk_ratelimit())
aabdfd6a 409 netdev_notice(dev, "packet dropped\n");
afa17a50
WS		 410 stats->rx_dropped++;
411 out_8(&regs->canrflg, canrflg);
412 continue;
413 }
414
415 if (canrflg & MSCAN_RXF)
416 mscan_get_rx_frame(dev, frame);
0285e7ce 417 else if (canrflg & MSCAN_ERR_IF)
afa17a50
WS		 418 mscan_get_err_frame(dev, frame, canrflg);
419
420 stats->rx_packets++;
421 stats->rx_bytes += frame->can_dlc;
422 npackets++;
423 netif_receive_skb(skb);
424 }
425
426 if (!(in_8(&regs->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
427 napi_complete(&priv->napi);
428 clear_bit(F_RX_PROGRESS, &priv->flags);
429 if (priv->can.state < CAN_STATE_BUS_OFF)
430 out_8(&regs->canrier, priv->shadow_canrier);
431 ret = 0;
432 }
433 return ret;
434}
435
436static irqreturn_t mscan_isr(int irq, void *dev_id)
437{
438 struct net_device *dev = (struct net_device *)dev_id;
439 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 440 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 441 struct net_device_stats *stats = &dev->stats;
442 u8 cantier, cantflg, canrflg;
443 irqreturn_t ret = IRQ_NONE;
444
445 cantier = in_8(&regs->cantier) & MSCAN_TXE;
446 cantflg = in_8(&regs->cantflg) & cantier;
447
448 if (cantier && cantflg) {
afa17a50
WS		 449 struct list_head *tmp, *pos;
450
451 list_for_each_safe(pos, tmp, &priv->tx_head) {
452 struct tx_queue_entry *entry =
453 list_entry(pos, struct tx_queue_entry, list);
454 u8 mask = entry->mask;
455
456 if (!(cantflg & mask))
457 continue;
458
459 out_8(&regs->cantbsel, mask);
460 stats->tx_bytes += in_8(&regs->tx.dlr);
461 stats->tx_packets++;
462 can_get_echo_skb(dev, entry->id);
463 priv->tx_active &= ~mask;
464 list_del(pos);
465 }
466
467 if (list_empty(&priv->tx_head)) {
468 clear_bit(F_TX_WAIT_ALL, &priv->flags);
469 clear_bit(F_TX_PROGRESS, &priv->flags);
470 priv->cur_pri = 0;
0285e7ce 471 } else {
afa17a50 472 dev->trans_start = jiffies;
0285e7ce 473 }
afa17a50
WS		 474
475 if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
476 netif_wake_queue(dev);
477
478 out_8(&regs->cantier, priv->tx_active);
479 ret = IRQ_HANDLED;
480 }
481
482 canrflg = in_8(&regs->canrflg);
483 if ((canrflg & ~MSCAN_STAT_MSK) &&
484 !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
485 if (canrflg & ~MSCAN_STAT_MSK) {
486 priv->shadow_canrier = in_8(&regs->canrier);
487 out_8(&regs->canrier, 0);
488 napi_schedule(&priv->napi);
489 ret = IRQ_HANDLED;
0285e7ce 490 } else {
afa17a50 491 clear_bit(F_RX_PROGRESS, &priv->flags);
0285e7ce 492 }
afa17a50
WS		 493 }
494 return ret;
495}
496
497static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
498{
afa17a50
WS		 499 int ret = 0;
500
afa17a50 501 switch (mode) {
afa17a50 502 case CAN_MODE_START:
bf3af547 503 ret = mscan_restart(dev);
afa17a50
WS		 504 if (ret)
505 break;
506 if (netif_queue_stopped(dev))
507 netif_wake_queue(dev);
508 break;
509
510 default:
511 ret = -EOPNOTSUPP;
512 break;
513 }
514 return ret;
515}
516
517static int mscan_do_set_bittiming(struct net_device *dev)
518{
519 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 520 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 521 struct can_bittiming *bt = &priv->can.bittiming;
522 u8 btr0, btr1;
523
524 btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
525 btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
526 BTR1_SET_TSEG2(bt->phase_seg2) |
527 BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
528
aabdfd6a 529 netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
afa17a50
WS		 530
531 out_8(&regs->canbtr0, btr0);
532 out_8(&regs->canbtr1, btr1);
533
534 return 0;
535}
536
79d0d8a7
WG		 537static int mscan_get_berr_counter(const struct net_device *dev,
538 struct can_berr_counter *bec)
539{
540 struct mscan_priv *priv = netdev_priv(dev);
541 struct mscan_regs __iomem *regs = priv->reg_base;
542
543 bec->txerr = in_8(&regs->cantxerr);
544 bec->rxerr = in_8(&regs->canrxerr);
545
546 return 0;
547}
548
afa17a50
WS		 549static int mscan_open(struct net_device *dev)
550{
551 int ret;
552 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 553 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 554
1149108e
GS		 555 if (priv->clk_ipg) {
556 ret = clk_prepare_enable(priv->clk_ipg);
557 if (ret)
558 goto exit_retcode;
559 }
560 if (priv->clk_can) {
561 ret = clk_prepare_enable(priv->clk_can);
562 if (ret)
563 goto exit_dis_ipg_clock;
564 }
565
afa17a50
WS		 566 /* common open */
567 ret = open_candev(dev);
568 if (ret)
1149108e 569 goto exit_dis_can_clock;
afa17a50
WS		 570
571 napi_enable(&priv->napi);
572
573 ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
574 if (ret < 0) {
aabdfd6a 575 netdev_err(dev, "failed to attach interrupt\n");
323907ac 576 goto exit_napi_disable;
afa17a50
WS		 577 }
578
abbd00b8 579 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
452448f9
MKB		 580 setbits8(&regs->canctl1, MSCAN_LISTEN);
581 else
582 clrbits8(&regs->canctl1, MSCAN_LISTEN);
afa17a50
WS		 583
584 ret = mscan_start(dev);
585 if (ret)
323907ac 586 goto exit_free_irq;
afa17a50
WS		 587
588 netif_start_queue(dev);
589
590 return 0;
323907ac
WS		 591
592exit_free_irq:
323907ac
WS		 593 free_irq(dev->irq, dev);
594exit_napi_disable:
595 napi_disable(&priv->napi);
596 close_candev(dev);
1149108e
GS		 597exit_dis_can_clock:
598 if (priv->clk_can)
599 clk_disable_unprepare(priv->clk_can);
600exit_dis_ipg_clock:
601 if (priv->clk_ipg)
602 clk_disable_unprepare(priv->clk_ipg);
603exit_retcode:
323907ac 604 return ret;
afa17a50
WS		 605}
606
607static int mscan_close(struct net_device *dev)
608{
609 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 610 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 611
612 netif_stop_queue(dev);
613 napi_disable(&priv->napi);
614
615 out_8(&regs->cantier, 0);
616 out_8(&regs->canrier, 0);
617 mscan_set_mode(dev, MSCAN_INIT_MODE);
618 close_candev(dev);
619 free_irq(dev->irq, dev);
afa17a50 620
1149108e
GS		 621 if (priv->clk_can)
622 clk_disable_unprepare(priv->clk_can);
623 if (priv->clk_ipg)
624 clk_disable_unprepare(priv->clk_ipg);
625
afa17a50
WS		 626 return 0;
627}
628
629static const struct net_device_ops mscan_netdev_ops = {
c971fa2a
OH		 630 .ndo_open = mscan_open,
631 .ndo_stop = mscan_close,
632 .ndo_start_xmit = mscan_start_xmit,
633 .ndo_change_mtu = can_change_mtu,
afa17a50
WS		 634};
635
bf3af547 636int register_mscandev(struct net_device *dev, int mscan_clksrc)
afa17a50
WS		 637{
638 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 639 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50
WS		 640 u8 ctl1;
641
642 ctl1 = in_8(&regs->canctl1);
bf3af547 643 if (mscan_clksrc)
afa17a50
WS		 644 ctl1 |= MSCAN_CLKSRC;
645 else
646 ctl1 &= ~MSCAN_CLKSRC;
647
79d0d8a7
WG		 648 if (priv->type == MSCAN_TYPE_MPC5121) {
649 priv->can.do_get_berr_counter = mscan_get_berr_counter;
bf3af547 650 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
79d0d8a7 651 }
bf3af547 652
afa17a50
WS		 653 ctl1 |= MSCAN_CANE;
654 out_8(&regs->canctl1, ctl1);
655 udelay(100);
656
657 /* acceptance mask/acceptance code (accept everything) */
658 out_be16(&regs->canidar1_0, 0);
659 out_be16(&regs->canidar3_2, 0);
660 out_be16(&regs->canidar5_4, 0);
661 out_be16(&regs->canidar7_6, 0);
662
663 out_be16(&regs->canidmr1_0, 0xffff);
664 out_be16(&regs->canidmr3_2, 0xffff);
665 out_be16(&regs->canidmr5_4, 0xffff);
666 out_be16(&regs->canidmr7_6, 0xffff);
667 /* Two 32 bit Acceptance Filters */
668 out_8(&regs->canidac, MSCAN_AF_32BIT);
669
670 mscan_set_mode(dev, MSCAN_INIT_MODE);
671
672 return register_candev(dev);
673}
afa17a50
WS		 674
675void unregister_mscandev(struct net_device *dev)
676{
677 struct mscan_priv *priv = netdev_priv(dev);
665d7eb8 678 struct mscan_regs __iomem *regs = priv->reg_base;
afa17a50 679 mscan_set_mode(dev, MSCAN_INIT_MODE);
59179ea6 680 clrbits8(&regs->canctl1, MSCAN_CANE);
afa17a50
WS		 681 unregister_candev(dev);
682}
afa17a50
WS		 683
684struct net_device *alloc_mscandev(void)
685{
686 struct net_device *dev;
687 struct mscan_priv *priv;
688 int i;
689
690 dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
691 if (!dev)
692 return NULL;
693 priv = netdev_priv(dev);
694
695 dev->netdev_ops = &mscan_netdev_ops;
696
697 dev->flags |= IFF_ECHO; /* we support local echo */
698
699 netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
700
701 priv->can.bittiming_const = &mscan_bittiming_const;
702 priv->can.do_set_bittiming = mscan_do_set_bittiming;
703 priv->can.do_set_mode = mscan_do_set_mode;
452448f9
MKB		 704 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
705 CAN_CTRLMODE_LISTENONLY;
afa17a50
WS		 706
707 for (i = 0; i < TX_QUEUE_SIZE; i++) {
708 priv->tx_queue[i].id = i;
709 priv->tx_queue[i].mask = 1 << i;
710 }
711
712 return dev;
713}
afa17a50
WS		 714
715MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
716MODULE_LICENSE("GPL v2");
717MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
Linux 6.x block layer and io_uring tree(s)