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f524f829 DM |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* CAN bus driver for Bosch M_CAN controller | |
3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ | |
4 | */ | |
5 | ||
6 | #ifndef _CAN_M_CAN_H_ | |
7 | #define _CAN_M_CAN_H_ | |
8 | ||
9 | #include <linux/can/core.h> | |
09451f24 | 10 | #include <linux/can/dev.h> |
1be37d3b | 11 | #include <linux/can/rx-offload.h> |
09451f24 | 12 | #include <linux/clk.h> |
f524f829 | 13 | #include <linux/completion.h> |
09451f24 | 14 | #include <linux/delay.h> |
f524f829 DM |
15 | #include <linux/device.h> |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/freezer.h> | |
b382380c | 18 | #include <linux/hrtimer.h> |
f524f829 DM |
19 | #include <linux/interrupt.h> |
20 | #include <linux/io.h> | |
09451f24 | 21 | #include <linux/iopoll.h> |
f524f829 DM |
22 | #include <linux/kernel.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/netdevice.h> | |
25 | #include <linux/of.h> | |
d836cb5f | 26 | #include <linux/phy/phy.h> |
09451f24 VY |
27 | #include <linux/pinctrl/consumer.h> |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/uaccess.h> | |
f524f829 DM |
31 | |
32 | /* m_can lec values */ | |
33 | enum m_can_lec_type { | |
34 | LEC_NO_ERROR = 0, | |
35 | LEC_STUFF_ERROR, | |
36 | LEC_FORM_ERROR, | |
37 | LEC_ACK_ERROR, | |
38 | LEC_BIT1_ERROR, | |
39 | LEC_BIT0_ERROR, | |
40 | LEC_CRC_ERROR, | |
6a8836e3 | 41 | LEC_NO_CHANGE, |
f524f829 DM |
42 | }; |
43 | ||
44 | enum m_can_mram_cfg { | |
45 | MRAM_SIDF = 0, | |
46 | MRAM_XIDF, | |
47 | MRAM_RXF0, | |
48 | MRAM_RXF1, | |
49 | MRAM_RXB, | |
50 | MRAM_TXE, | |
51 | MRAM_TXB, | |
52 | MRAM_CFG_NUM, | |
53 | }; | |
54 | ||
55 | /* address offset and element number for each FIFO/Buffer in the Message RAM */ | |
56 | struct mram_cfg { | |
57 | u16 off; | |
58 | u8 num; | |
59 | }; | |
60 | ||
441ac340 | 61 | struct m_can_classdev; |
f524f829 DM |
62 | struct m_can_ops { |
63 | /* Device specific call backs */ | |
441ac340 DM |
64 | int (*clear_interrupts)(struct m_can_classdev *cdev); |
65 | u32 (*read_reg)(struct m_can_classdev *cdev, int reg); | |
66 | int (*write_reg)(struct m_can_classdev *cdev, int reg, int val); | |
e3938177 | 67 | int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count); |
441ac340 | 68 | int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset, |
e3938177 | 69 | const void *val, size_t val_count); |
441ac340 | 70 | int (*init)(struct m_can_classdev *cdev); |
f524f829 DM |
71 | }; |
72 | ||
e668673e MSP |
73 | struct m_can_tx_op { |
74 | struct m_can_classdev *cdev; | |
75 | struct work_struct work; | |
76 | struct sk_buff *skb; | |
77 | }; | |
78 | ||
441ac340 | 79 | struct m_can_classdev { |
f524f829 | 80 | struct can_priv can; |
1be37d3b | 81 | struct can_rx_offload offload; |
f524f829 DM |
82 | struct napi_struct napi; |
83 | struct net_device *net; | |
84 | struct device *dev; | |
85 | struct clk *hclk; | |
86 | struct clk *cclk; | |
87 | ||
88 | struct workqueue_struct *tx_wq; | |
d836cb5f | 89 | struct phy *transceiver; |
f524f829 | 90 | |
ec390d08 MSP |
91 | ktime_t irq_timer_wait; |
92 | ||
f524f829 DM |
93 | struct m_can_ops *ops; |
94 | ||
f524f829 | 95 | int version; |
f524f829 DM |
96 | u32 irqstatus; |
97 | ||
98 | int pm_clock_support; | |
99 | int is_peripheral; | |
100 | ||
07f25091 MSP |
101 | // Cached M_CAN_IE register content |
102 | u32 active_interrupts; | |
103 | u32 rx_max_coalesced_frames_irq; | |
104 | u32 rx_coalesce_usecs_irq; | |
ec390d08 MSP |
105 | u32 tx_max_coalesced_frames_irq; |
106 | u32 tx_coalesce_usecs_irq; | |
07f25091 | 107 | |
80c5bac0 | 108 | // Store this internally to avoid fetch delays on peripheral chips |
e668673e MSP |
109 | u32 tx_fifo_putidx; |
110 | ||
1fa80e23 MSP |
111 | /* Protects shared state between start_xmit and m_can_isr */ |
112 | spinlock_t tx_handling_spinlock; | |
113 | int tx_fifo_in_flight; | |
114 | ||
e668673e MSP |
115 | struct m_can_tx_op *tx_ops; |
116 | int tx_fifo_size; | |
117 | int next_tx_op; | |
80c5bac0 | 118 | |
f524f829 | 119 | struct mram_cfg mcfg[MRAM_CFG_NUM]; |
b382380c JM |
120 | |
121 | struct hrtimer hrtimer; | |
f524f829 DM |
122 | }; |
123 | ||
ac33ffd3 | 124 | struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv); |
a8c22f5b | 125 | void m_can_class_free_dev(struct net_device *net); |
441ac340 DM |
126 | int m_can_class_register(struct m_can_classdev *cdev); |
127 | void m_can_class_unregister(struct m_can_classdev *cdev); | |
128 | int m_can_class_get_clocks(struct m_can_classdev *cdev); | |
e3938177 | 129 | int m_can_init_ram(struct m_can_classdev *priv); |
c1b17ea7 | 130 | int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size); |
f524f829 DM |
131 | |
132 | int m_can_class_suspend(struct device *dev); | |
133 | int m_can_class_resume(struct device *dev); | |
134 | #endif /* _CAN_M_H_ */ |