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e955cead MKB |
1 | /* |
2 | * flexcan.c - FLEXCAN CAN controller driver | |
3 | * | |
4 | * Copyright (c) 2005-2006 Varma Electronics Oy | |
5 | * Copyright (c) 2009 Sascha Hauer, Pengutronix | |
6 | * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix | |
7 | * | |
8 | * Based on code originally by Andrey Volkov <avolkov@varma-el.com> | |
9 | * | |
10 | * LICENCE: | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation version 2. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/netdevice.h> | |
23 | #include <linux/can.h> | |
24 | #include <linux/can/dev.h> | |
25 | #include <linux/can/error.h> | |
adccadb9 | 26 | #include <linux/can/led.h> |
e955cead MKB |
27 | #include <linux/clk.h> |
28 | #include <linux/delay.h> | |
29 | #include <linux/if_arp.h> | |
30 | #include <linux/if_ether.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/list.h> | |
35 | #include <linux/module.h> | |
97efe9ae | 36 | #include <linux/of.h> |
30c1e672 | 37 | #include <linux/of_device.h> |
e955cead | 38 | #include <linux/platform_device.h> |
b7c4114b | 39 | #include <linux/regulator/consumer.h> |
e955cead | 40 | |
e955cead MKB |
41 | #define DRV_NAME "flexcan" |
42 | ||
43 | /* 8 for RX fifo and 2 error handling */ | |
44 | #define FLEXCAN_NAPI_WEIGHT (8 + 2) | |
45 | ||
46 | /* FLEXCAN module configuration register (CANMCR) bits */ | |
47 | #define FLEXCAN_MCR_MDIS BIT(31) | |
48 | #define FLEXCAN_MCR_FRZ BIT(30) | |
49 | #define FLEXCAN_MCR_FEN BIT(29) | |
50 | #define FLEXCAN_MCR_HALT BIT(28) | |
51 | #define FLEXCAN_MCR_NOT_RDY BIT(27) | |
52 | #define FLEXCAN_MCR_WAK_MSK BIT(26) | |
53 | #define FLEXCAN_MCR_SOFTRST BIT(25) | |
54 | #define FLEXCAN_MCR_FRZ_ACK BIT(24) | |
55 | #define FLEXCAN_MCR_SUPV BIT(23) | |
56 | #define FLEXCAN_MCR_SLF_WAK BIT(22) | |
57 | #define FLEXCAN_MCR_WRN_EN BIT(21) | |
58 | #define FLEXCAN_MCR_LPM_ACK BIT(20) | |
59 | #define FLEXCAN_MCR_WAK_SRC BIT(19) | |
60 | #define FLEXCAN_MCR_DOZE BIT(18) | |
61 | #define FLEXCAN_MCR_SRX_DIS BIT(17) | |
62 | #define FLEXCAN_MCR_BCC BIT(16) | |
63 | #define FLEXCAN_MCR_LPRIO_EN BIT(13) | |
64 | #define FLEXCAN_MCR_AEN BIT(12) | |
d5a7b406 | 65 | #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) |
e955cead MKB |
66 | #define FLEXCAN_MCR_IDAM_A (0 << 8) |
67 | #define FLEXCAN_MCR_IDAM_B (1 << 8) | |
68 | #define FLEXCAN_MCR_IDAM_C (2 << 8) | |
69 | #define FLEXCAN_MCR_IDAM_D (3 << 8) | |
70 | ||
71 | /* FLEXCAN control register (CANCTRL) bits */ | |
72 | #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) | |
73 | #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) | |
74 | #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) | |
75 | #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) | |
76 | #define FLEXCAN_CTRL_BOFF_MSK BIT(15) | |
77 | #define FLEXCAN_CTRL_ERR_MSK BIT(14) | |
78 | #define FLEXCAN_CTRL_CLK_SRC BIT(13) | |
79 | #define FLEXCAN_CTRL_LPB BIT(12) | |
80 | #define FLEXCAN_CTRL_TWRN_MSK BIT(11) | |
81 | #define FLEXCAN_CTRL_RWRN_MSK BIT(10) | |
82 | #define FLEXCAN_CTRL_SMP BIT(7) | |
83 | #define FLEXCAN_CTRL_BOFF_REC BIT(6) | |
84 | #define FLEXCAN_CTRL_TSYN BIT(5) | |
85 | #define FLEXCAN_CTRL_LBUF BIT(4) | |
86 | #define FLEXCAN_CTRL_LOM BIT(3) | |
87 | #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) | |
88 | #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) | |
89 | #define FLEXCAN_CTRL_ERR_STATE \ | |
90 | (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ | |
91 | FLEXCAN_CTRL_BOFF_MSK) | |
92 | #define FLEXCAN_CTRL_ERR_ALL \ | |
93 | (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) | |
94 | ||
95 | /* FLEXCAN error and status register (ESR) bits */ | |
96 | #define FLEXCAN_ESR_TWRN_INT BIT(17) | |
97 | #define FLEXCAN_ESR_RWRN_INT BIT(16) | |
98 | #define FLEXCAN_ESR_BIT1_ERR BIT(15) | |
99 | #define FLEXCAN_ESR_BIT0_ERR BIT(14) | |
100 | #define FLEXCAN_ESR_ACK_ERR BIT(13) | |
101 | #define FLEXCAN_ESR_CRC_ERR BIT(12) | |
102 | #define FLEXCAN_ESR_FRM_ERR BIT(11) | |
103 | #define FLEXCAN_ESR_STF_ERR BIT(10) | |
104 | #define FLEXCAN_ESR_TX_WRN BIT(9) | |
105 | #define FLEXCAN_ESR_RX_WRN BIT(8) | |
106 | #define FLEXCAN_ESR_IDLE BIT(7) | |
107 | #define FLEXCAN_ESR_TXRX BIT(6) | |
108 | #define FLEXCAN_EST_FLT_CONF_SHIFT (4) | |
109 | #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
110 | #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
111 | #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) | |
112 | #define FLEXCAN_ESR_BOFF_INT BIT(2) | |
113 | #define FLEXCAN_ESR_ERR_INT BIT(1) | |
114 | #define FLEXCAN_ESR_WAK_INT BIT(0) | |
115 | #define FLEXCAN_ESR_ERR_BUS \ | |
116 | (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ | |
117 | FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ | |
118 | FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) | |
119 | #define FLEXCAN_ESR_ERR_STATE \ | |
120 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) | |
121 | #define FLEXCAN_ESR_ERR_ALL \ | |
122 | (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) | |
6e9d554f WG |
123 | #define FLEXCAN_ESR_ALL_INT \ |
124 | (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ | |
125 | FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) | |
e955cead MKB |
126 | |
127 | /* FLEXCAN interrupt flag register (IFLAG) bits */ | |
128 | #define FLEXCAN_TX_BUF_ID 8 | |
129 | #define FLEXCAN_IFLAG_BUF(x) BIT(x) | |
130 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) | |
131 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) | |
132 | #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) | |
133 | #define FLEXCAN_IFLAG_DEFAULT \ | |
134 | (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \ | |
135 | FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID)) | |
136 | ||
137 | /* FLEXCAN message buffers */ | |
138 | #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24) | |
139 | #define FLEXCAN_MB_CNT_SRR BIT(22) | |
140 | #define FLEXCAN_MB_CNT_IDE BIT(21) | |
141 | #define FLEXCAN_MB_CNT_RTR BIT(20) | |
142 | #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) | |
143 | #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) | |
144 | ||
145 | #define FLEXCAN_MB_CODE_MASK (0xf0ffffff) | |
146 | ||
9b00b300 MKB |
147 | #define FLEXCAN_TIMEOUT_US (50) |
148 | ||
bb698ca4 WG |
149 | /* |
150 | * FLEXCAN hardware feature flags | |
151 | * | |
152 | * Below is some version info we got: | |
153 | * SOC Version IP-Version Glitch- [TR]WRN_INT | |
154 | * Filter? connected? | |
155 | * MX25 FlexCAN2 03.00.00.00 no no | |
156 | * MX28 FlexCAN2 03.00.04.00 yes yes | |
157 | * MX35 FlexCAN2 03.00.00.00 no no | |
158 | * MX53 FlexCAN2 03.00.00.00 yes no | |
159 | * MX6s FlexCAN3 10.00.12.00 yes yes | |
160 | * | |
161 | * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected. | |
162 | */ | |
4f72e5f0 | 163 | #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */ |
bb698ca4 | 164 | #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */ |
4f72e5f0 | 165 | |
e955cead MKB |
166 | /* Structure of the message buffer */ |
167 | struct flexcan_mb { | |
168 | u32 can_ctrl; | |
169 | u32 can_id; | |
170 | u32 data[2]; | |
171 | }; | |
172 | ||
173 | /* Structure of the hardware registers */ | |
174 | struct flexcan_regs { | |
175 | u32 mcr; /* 0x00 */ | |
176 | u32 ctrl; /* 0x04 */ | |
177 | u32 timer; /* 0x08 */ | |
178 | u32 _reserved1; /* 0x0c */ | |
179 | u32 rxgmask; /* 0x10 */ | |
180 | u32 rx14mask; /* 0x14 */ | |
181 | u32 rx15mask; /* 0x18 */ | |
182 | u32 ecr; /* 0x1c */ | |
183 | u32 esr; /* 0x20 */ | |
184 | u32 imask2; /* 0x24 */ | |
185 | u32 imask1; /* 0x28 */ | |
186 | u32 iflag2; /* 0x2c */ | |
187 | u32 iflag1; /* 0x30 */ | |
30c1e672 HW |
188 | u32 crl2; /* 0x34 */ |
189 | u32 esr2; /* 0x38 */ | |
190 | u32 imeur; /* 0x3c */ | |
191 | u32 lrfr; /* 0x40 */ | |
192 | u32 crcr; /* 0x44 */ | |
193 | u32 rxfgmask; /* 0x48 */ | |
194 | u32 rxfir; /* 0x4c */ | |
195 | u32 _reserved3[12]; | |
e955cead MKB |
196 | struct flexcan_mb cantxfg[64]; |
197 | }; | |
198 | ||
30c1e672 | 199 | struct flexcan_devtype_data { |
4f72e5f0 | 200 | u32 features; /* hardware controller features */ |
30c1e672 HW |
201 | }; |
202 | ||
e955cead MKB |
203 | struct flexcan_priv { |
204 | struct can_priv can; | |
205 | struct net_device *dev; | |
206 | struct napi_struct napi; | |
207 | ||
208 | void __iomem *base; | |
209 | u32 reg_esr; | |
210 | u32 reg_ctrl_default; | |
211 | ||
3d42a379 ST |
212 | struct clk *clk_ipg; |
213 | struct clk *clk_per; | |
e955cead | 214 | struct flexcan_platform_data *pdata; |
dda0b3bd | 215 | const struct flexcan_devtype_data *devtype_data; |
b7c4114b | 216 | struct regulator *reg_xceiver; |
30c1e672 HW |
217 | }; |
218 | ||
219 | static struct flexcan_devtype_data fsl_p1010_devtype_data = { | |
4f72e5f0 | 220 | .features = FLEXCAN_HAS_BROKEN_ERR_STATE, |
30c1e672 | 221 | }; |
4f72e5f0 | 222 | static struct flexcan_devtype_data fsl_imx28_devtype_data; |
30c1e672 | 223 | static struct flexcan_devtype_data fsl_imx6q_devtype_data = { |
bb698ca4 | 224 | .features = FLEXCAN_HAS_V10_FEATURES, |
e955cead MKB |
225 | }; |
226 | ||
194b9a4c | 227 | static const struct can_bittiming_const flexcan_bittiming_const = { |
e955cead MKB |
228 | .name = DRV_NAME, |
229 | .tseg1_min = 4, | |
230 | .tseg1_max = 16, | |
231 | .tseg2_min = 2, | |
232 | .tseg2_max = 8, | |
233 | .sjw_max = 4, | |
234 | .brp_min = 1, | |
235 | .brp_max = 256, | |
236 | .brp_inc = 1, | |
237 | }; | |
238 | ||
61e271ee | 239 | /* |
0e4b949e AB |
240 | * Abstract off the read/write for arm versus ppc. This |
241 | * assumes that PPC uses big-endian registers and everything | |
242 | * else uses little-endian registers, independent of CPU | |
243 | * endianess. | |
61e271ee | 244 | */ |
0e4b949e | 245 | #if defined(CONFIG_PPC) |
61e271ee | 246 | static inline u32 flexcan_read(void __iomem *addr) |
247 | { | |
248 | return in_be32(addr); | |
249 | } | |
250 | ||
251 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
252 | { | |
253 | out_be32(addr, val); | |
254 | } | |
255 | #else | |
256 | static inline u32 flexcan_read(void __iomem *addr) | |
257 | { | |
258 | return readl(addr); | |
259 | } | |
260 | ||
261 | static inline void flexcan_write(u32 val, void __iomem *addr) | |
262 | { | |
263 | writel(val, addr); | |
264 | } | |
265 | #endif | |
266 | ||
e955cead MKB |
267 | static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv, |
268 | u32 reg_esr) | |
269 | { | |
270 | return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && | |
271 | (reg_esr & FLEXCAN_ESR_ERR_BUS); | |
272 | } | |
273 | ||
9b00b300 | 274 | static int flexcan_chip_enable(struct flexcan_priv *priv) |
e955cead MKB |
275 | { |
276 | struct flexcan_regs __iomem *regs = priv->base; | |
9b00b300 | 277 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
278 | u32 reg; |
279 | ||
61e271ee | 280 | reg = flexcan_read(®s->mcr); |
e955cead | 281 | reg &= ~FLEXCAN_MCR_MDIS; |
61e271ee | 282 | flexcan_write(reg, ®s->mcr); |
e955cead | 283 | |
9b00b300 MKB |
284 | while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) |
285 | usleep_range(10, 20); | |
286 | ||
287 | if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) | |
288 | return -ETIMEDOUT; | |
289 | ||
290 | return 0; | |
e955cead MKB |
291 | } |
292 | ||
9b00b300 | 293 | static int flexcan_chip_disable(struct flexcan_priv *priv) |
e955cead MKB |
294 | { |
295 | struct flexcan_regs __iomem *regs = priv->base; | |
9b00b300 | 296 | unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; |
e955cead MKB |
297 | u32 reg; |
298 | ||
61e271ee | 299 | reg = flexcan_read(®s->mcr); |
e955cead | 300 | reg |= FLEXCAN_MCR_MDIS; |
61e271ee | 301 | flexcan_write(reg, ®s->mcr); |
9b00b300 MKB |
302 | |
303 | while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) | |
304 | usleep_range(10, 20); | |
305 | ||
306 | if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) | |
307 | return -ETIMEDOUT; | |
308 | ||
309 | return 0; | |
e955cead MKB |
310 | } |
311 | ||
312 | static int flexcan_get_berr_counter(const struct net_device *dev, | |
313 | struct can_berr_counter *bec) | |
314 | { | |
315 | const struct flexcan_priv *priv = netdev_priv(dev); | |
316 | struct flexcan_regs __iomem *regs = priv->base; | |
61e271ee | 317 | u32 reg = flexcan_read(®s->ecr); |
e955cead MKB |
318 | |
319 | bec->txerr = (reg >> 0) & 0xff; | |
320 | bec->rxerr = (reg >> 8) & 0xff; | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
326 | { | |
327 | const struct flexcan_priv *priv = netdev_priv(dev); | |
e955cead MKB |
328 | struct flexcan_regs __iomem *regs = priv->base; |
329 | struct can_frame *cf = (struct can_frame *)skb->data; | |
330 | u32 can_id; | |
331 | u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16); | |
332 | ||
333 | if (can_dropped_invalid_skb(dev, skb)) | |
334 | return NETDEV_TX_OK; | |
335 | ||
336 | netif_stop_queue(dev); | |
337 | ||
338 | if (cf->can_id & CAN_EFF_FLAG) { | |
339 | can_id = cf->can_id & CAN_EFF_MASK; | |
340 | ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; | |
341 | } else { | |
342 | can_id = (cf->can_id & CAN_SFF_MASK) << 18; | |
343 | } | |
344 | ||
345 | if (cf->can_id & CAN_RTR_FLAG) | |
346 | ctrl |= FLEXCAN_MB_CNT_RTR; | |
347 | ||
348 | if (cf->can_dlc > 0) { | |
349 | u32 data = be32_to_cpup((__be32 *)&cf->data[0]); | |
61e271ee | 350 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]); |
e955cead MKB |
351 | } |
352 | if (cf->can_dlc > 3) { | |
353 | u32 data = be32_to_cpup((__be32 *)&cf->data[4]); | |
61e271ee | 354 | flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]); |
e955cead MKB |
355 | } |
356 | ||
9a123496 RD |
357 | can_put_echo_skb(skb, dev, 0); |
358 | ||
61e271ee | 359 | flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id); |
360 | flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); | |
e955cead | 361 | |
e955cead MKB |
362 | return NETDEV_TX_OK; |
363 | } | |
364 | ||
365 | static void do_bus_err(struct net_device *dev, | |
366 | struct can_frame *cf, u32 reg_esr) | |
367 | { | |
368 | struct flexcan_priv *priv = netdev_priv(dev); | |
369 | int rx_errors = 0, tx_errors = 0; | |
370 | ||
371 | cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; | |
372 | ||
373 | if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { | |
aabdfd6a | 374 | netdev_dbg(dev, "BIT1_ERR irq\n"); |
e955cead MKB |
375 | cf->data[2] |= CAN_ERR_PROT_BIT1; |
376 | tx_errors = 1; | |
377 | } | |
378 | if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { | |
aabdfd6a | 379 | netdev_dbg(dev, "BIT0_ERR irq\n"); |
e955cead MKB |
380 | cf->data[2] |= CAN_ERR_PROT_BIT0; |
381 | tx_errors = 1; | |
382 | } | |
383 | if (reg_esr & FLEXCAN_ESR_ACK_ERR) { | |
aabdfd6a | 384 | netdev_dbg(dev, "ACK_ERR irq\n"); |
e955cead MKB |
385 | cf->can_id |= CAN_ERR_ACK; |
386 | cf->data[3] |= CAN_ERR_PROT_LOC_ACK; | |
387 | tx_errors = 1; | |
388 | } | |
389 | if (reg_esr & FLEXCAN_ESR_CRC_ERR) { | |
aabdfd6a | 390 | netdev_dbg(dev, "CRC_ERR irq\n"); |
e955cead MKB |
391 | cf->data[2] |= CAN_ERR_PROT_BIT; |
392 | cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; | |
393 | rx_errors = 1; | |
394 | } | |
395 | if (reg_esr & FLEXCAN_ESR_FRM_ERR) { | |
aabdfd6a | 396 | netdev_dbg(dev, "FRM_ERR irq\n"); |
e955cead MKB |
397 | cf->data[2] |= CAN_ERR_PROT_FORM; |
398 | rx_errors = 1; | |
399 | } | |
400 | if (reg_esr & FLEXCAN_ESR_STF_ERR) { | |
aabdfd6a | 401 | netdev_dbg(dev, "STF_ERR irq\n"); |
e955cead MKB |
402 | cf->data[2] |= CAN_ERR_PROT_STUFF; |
403 | rx_errors = 1; | |
404 | } | |
405 | ||
406 | priv->can.can_stats.bus_error++; | |
407 | if (rx_errors) | |
408 | dev->stats.rx_errors++; | |
409 | if (tx_errors) | |
410 | dev->stats.tx_errors++; | |
411 | } | |
412 | ||
413 | static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr) | |
414 | { | |
415 | struct sk_buff *skb; | |
416 | struct can_frame *cf; | |
417 | ||
418 | skb = alloc_can_err_skb(dev, &cf); | |
419 | if (unlikely(!skb)) | |
420 | return 0; | |
421 | ||
422 | do_bus_err(dev, cf, reg_esr); | |
423 | netif_receive_skb(skb); | |
424 | ||
425 | dev->stats.rx_packets++; | |
426 | dev->stats.rx_bytes += cf->can_dlc; | |
427 | ||
428 | return 1; | |
429 | } | |
430 | ||
431 | static void do_state(struct net_device *dev, | |
432 | struct can_frame *cf, enum can_state new_state) | |
433 | { | |
434 | struct flexcan_priv *priv = netdev_priv(dev); | |
435 | struct can_berr_counter bec; | |
436 | ||
437 | flexcan_get_berr_counter(dev, &bec); | |
438 | ||
439 | switch (priv->can.state) { | |
440 | case CAN_STATE_ERROR_ACTIVE: | |
441 | /* | |
442 | * from: ERROR_ACTIVE | |
443 | * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF | |
444 | * => : there was a warning int | |
445 | */ | |
446 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
447 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 448 | netdev_dbg(dev, "Error Warning IRQ\n"); |
e955cead MKB |
449 | priv->can.can_stats.error_warning++; |
450 | ||
451 | cf->can_id |= CAN_ERR_CRTL; | |
452 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
453 | CAN_ERR_CRTL_TX_WARNING : | |
454 | CAN_ERR_CRTL_RX_WARNING; | |
455 | } | |
456 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
457 | /* | |
458 | * from: ERROR_ACTIVE, ERROR_WARNING | |
459 | * to : ERROR_PASSIVE, BUS_OFF | |
460 | * => : error passive int | |
461 | */ | |
462 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
463 | new_state <= CAN_STATE_BUS_OFF) { | |
aabdfd6a | 464 | netdev_dbg(dev, "Error Passive IRQ\n"); |
e955cead MKB |
465 | priv->can.can_stats.error_passive++; |
466 | ||
467 | cf->can_id |= CAN_ERR_CRTL; | |
468 | cf->data[1] = (bec.txerr > bec.rxerr) ? | |
469 | CAN_ERR_CRTL_TX_PASSIVE : | |
470 | CAN_ERR_CRTL_RX_PASSIVE; | |
471 | } | |
472 | break; | |
473 | case CAN_STATE_BUS_OFF: | |
aabdfd6a WG |
474 | netdev_err(dev, "BUG! " |
475 | "hardware recovered automatically from BUS_OFF\n"); | |
e955cead MKB |
476 | break; |
477 | default: | |
478 | break; | |
479 | } | |
480 | ||
481 | /* process state changes depending on the new state */ | |
482 | switch (new_state) { | |
483 | case CAN_STATE_ERROR_ACTIVE: | |
aabdfd6a | 484 | netdev_dbg(dev, "Error Active\n"); |
e955cead MKB |
485 | cf->can_id |= CAN_ERR_PROT; |
486 | cf->data[2] = CAN_ERR_PROT_ACTIVE; | |
487 | break; | |
488 | case CAN_STATE_BUS_OFF: | |
489 | cf->can_id |= CAN_ERR_BUSOFF; | |
490 | can_bus_off(dev); | |
491 | break; | |
492 | default: | |
493 | break; | |
494 | } | |
495 | } | |
496 | ||
497 | static int flexcan_poll_state(struct net_device *dev, u32 reg_esr) | |
498 | { | |
499 | struct flexcan_priv *priv = netdev_priv(dev); | |
500 | struct sk_buff *skb; | |
501 | struct can_frame *cf; | |
502 | enum can_state new_state; | |
503 | int flt; | |
504 | ||
505 | flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; | |
506 | if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { | |
507 | if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN | | |
508 | FLEXCAN_ESR_RX_WRN)))) | |
509 | new_state = CAN_STATE_ERROR_ACTIVE; | |
510 | else | |
511 | new_state = CAN_STATE_ERROR_WARNING; | |
512 | } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE)) | |
513 | new_state = CAN_STATE_ERROR_PASSIVE; | |
514 | else | |
515 | new_state = CAN_STATE_BUS_OFF; | |
516 | ||
517 | /* state hasn't changed */ | |
518 | if (likely(new_state == priv->can.state)) | |
519 | return 0; | |
520 | ||
521 | skb = alloc_can_err_skb(dev, &cf); | |
522 | if (unlikely(!skb)) | |
523 | return 0; | |
524 | ||
525 | do_state(dev, cf, new_state); | |
526 | priv->can.state = new_state; | |
527 | netif_receive_skb(skb); | |
528 | ||
529 | dev->stats.rx_packets++; | |
530 | dev->stats.rx_bytes += cf->can_dlc; | |
531 | ||
532 | return 1; | |
533 | } | |
534 | ||
535 | static void flexcan_read_fifo(const struct net_device *dev, | |
536 | struct can_frame *cf) | |
537 | { | |
538 | const struct flexcan_priv *priv = netdev_priv(dev); | |
539 | struct flexcan_regs __iomem *regs = priv->base; | |
540 | struct flexcan_mb __iomem *mb = ®s->cantxfg[0]; | |
541 | u32 reg_ctrl, reg_id; | |
542 | ||
61e271ee | 543 | reg_ctrl = flexcan_read(&mb->can_ctrl); |
544 | reg_id = flexcan_read(&mb->can_id); | |
e955cead MKB |
545 | if (reg_ctrl & FLEXCAN_MB_CNT_IDE) |
546 | cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
547 | else | |
548 | cf->can_id = (reg_id >> 18) & CAN_SFF_MASK; | |
549 | ||
550 | if (reg_ctrl & FLEXCAN_MB_CNT_RTR) | |
551 | cf->can_id |= CAN_RTR_FLAG; | |
552 | cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf); | |
553 | ||
61e271ee | 554 | *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0])); |
555 | *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1])); | |
e955cead MKB |
556 | |
557 | /* mark as read */ | |
61e271ee | 558 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); |
559 | flexcan_read(®s->timer); | |
e955cead MKB |
560 | } |
561 | ||
562 | static int flexcan_read_frame(struct net_device *dev) | |
563 | { | |
564 | struct net_device_stats *stats = &dev->stats; | |
565 | struct can_frame *cf; | |
566 | struct sk_buff *skb; | |
567 | ||
568 | skb = alloc_can_skb(dev, &cf); | |
569 | if (unlikely(!skb)) { | |
570 | stats->rx_dropped++; | |
571 | return 0; | |
572 | } | |
573 | ||
574 | flexcan_read_fifo(dev, cf); | |
575 | netif_receive_skb(skb); | |
576 | ||
577 | stats->rx_packets++; | |
578 | stats->rx_bytes += cf->can_dlc; | |
579 | ||
adccadb9 FB |
580 | can_led_event(dev, CAN_LED_EVENT_RX); |
581 | ||
e955cead MKB |
582 | return 1; |
583 | } | |
584 | ||
585 | static int flexcan_poll(struct napi_struct *napi, int quota) | |
586 | { | |
587 | struct net_device *dev = napi->dev; | |
588 | const struct flexcan_priv *priv = netdev_priv(dev); | |
589 | struct flexcan_regs __iomem *regs = priv->base; | |
590 | u32 reg_iflag1, reg_esr; | |
591 | int work_done = 0; | |
592 | ||
593 | /* | |
594 | * The error bits are cleared on read, | |
595 | * use saved value from irq handler. | |
596 | */ | |
61e271ee | 597 | reg_esr = flexcan_read(®s->esr) | priv->reg_esr; |
e955cead MKB |
598 | |
599 | /* handle state changes */ | |
600 | work_done += flexcan_poll_state(dev, reg_esr); | |
601 | ||
602 | /* handle RX-FIFO */ | |
61e271ee | 603 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
604 | while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE && |
605 | work_done < quota) { | |
606 | work_done += flexcan_read_frame(dev); | |
61e271ee | 607 | reg_iflag1 = flexcan_read(®s->iflag1); |
e955cead MKB |
608 | } |
609 | ||
610 | /* report bus errors */ | |
611 | if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota) | |
612 | work_done += flexcan_poll_bus_err(dev, reg_esr); | |
613 | ||
614 | if (work_done < quota) { | |
615 | napi_complete(napi); | |
616 | /* enable IRQs */ | |
61e271ee | 617 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
618 | flexcan_write(priv->reg_ctrl_default, ®s->ctrl); | |
e955cead MKB |
619 | } |
620 | ||
621 | return work_done; | |
622 | } | |
623 | ||
624 | static irqreturn_t flexcan_irq(int irq, void *dev_id) | |
625 | { | |
626 | struct net_device *dev = dev_id; | |
627 | struct net_device_stats *stats = &dev->stats; | |
628 | struct flexcan_priv *priv = netdev_priv(dev); | |
629 | struct flexcan_regs __iomem *regs = priv->base; | |
630 | u32 reg_iflag1, reg_esr; | |
631 | ||
61e271ee | 632 | reg_iflag1 = flexcan_read(®s->iflag1); |
633 | reg_esr = flexcan_read(®s->esr); | |
6e9d554f WG |
634 | /* ACK all bus error and state change IRQ sources */ |
635 | if (reg_esr & FLEXCAN_ESR_ALL_INT) | |
636 | flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); | |
e955cead MKB |
637 | |
638 | /* | |
639 | * schedule NAPI in case of: | |
640 | * - rx IRQ | |
641 | * - state change IRQ | |
642 | * - bus error IRQ and bus error reporting is activated | |
643 | */ | |
644 | if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) || | |
645 | (reg_esr & FLEXCAN_ESR_ERR_STATE) || | |
646 | flexcan_has_and_handle_berr(priv, reg_esr)) { | |
647 | /* | |
648 | * The error bits are cleared on read, | |
649 | * save them for later use. | |
650 | */ | |
651 | priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS; | |
61e271ee | 652 | flexcan_write(FLEXCAN_IFLAG_DEFAULT & |
653 | ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1); | |
654 | flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
e955cead MKB |
655 | ®s->ctrl); |
656 | napi_schedule(&priv->napi); | |
657 | } | |
658 | ||
659 | /* FIFO overflow */ | |
660 | if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { | |
61e271ee | 661 | flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1); |
e955cead MKB |
662 | dev->stats.rx_over_errors++; |
663 | dev->stats.rx_errors++; | |
664 | } | |
665 | ||
666 | /* transmission complete interrupt */ | |
667 | if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) { | |
9a123496 | 668 | stats->tx_bytes += can_get_echo_skb(dev, 0); |
e955cead | 669 | stats->tx_packets++; |
adccadb9 | 670 | can_led_event(dev, CAN_LED_EVENT_TX); |
61e271ee | 671 | flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1); |
e955cead MKB |
672 | netif_wake_queue(dev); |
673 | } | |
674 | ||
675 | return IRQ_HANDLED; | |
676 | } | |
677 | ||
678 | static void flexcan_set_bittiming(struct net_device *dev) | |
679 | { | |
680 | const struct flexcan_priv *priv = netdev_priv(dev); | |
681 | const struct can_bittiming *bt = &priv->can.bittiming; | |
682 | struct flexcan_regs __iomem *regs = priv->base; | |
683 | u32 reg; | |
684 | ||
61e271ee | 685 | reg = flexcan_read(®s->ctrl); |
e955cead MKB |
686 | reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | |
687 | FLEXCAN_CTRL_RJW(0x3) | | |
688 | FLEXCAN_CTRL_PSEG1(0x7) | | |
689 | FLEXCAN_CTRL_PSEG2(0x7) | | |
690 | FLEXCAN_CTRL_PROPSEG(0x7) | | |
691 | FLEXCAN_CTRL_LPB | | |
692 | FLEXCAN_CTRL_SMP | | |
693 | FLEXCAN_CTRL_LOM); | |
694 | ||
695 | reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | | |
696 | FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | | |
697 | FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | | |
698 | FLEXCAN_CTRL_RJW(bt->sjw - 1) | | |
699 | FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); | |
700 | ||
701 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
702 | reg |= FLEXCAN_CTRL_LPB; | |
703 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
704 | reg |= FLEXCAN_CTRL_LOM; | |
705 | if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) | |
706 | reg |= FLEXCAN_CTRL_SMP; | |
707 | ||
aabdfd6a | 708 | netdev_info(dev, "writing ctrl=0x%08x\n", reg); |
61e271ee | 709 | flexcan_write(reg, ®s->ctrl); |
e955cead MKB |
710 | |
711 | /* print chip status */ | |
aabdfd6a WG |
712 | netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, |
713 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
714 | } |
715 | ||
716 | /* | |
717 | * flexcan_chip_start | |
718 | * | |
719 | * this functions is entered with clocks enabled | |
720 | * | |
721 | */ | |
722 | static int flexcan_chip_start(struct net_device *dev) | |
723 | { | |
724 | struct flexcan_priv *priv = netdev_priv(dev); | |
725 | struct flexcan_regs __iomem *regs = priv->base; | |
e955cead MKB |
726 | int err; |
727 | u32 reg_mcr, reg_ctrl; | |
728 | ||
729 | /* enable module */ | |
9b00b300 MKB |
730 | err = flexcan_chip_enable(priv); |
731 | if (err) | |
732 | return err; | |
e955cead MKB |
733 | |
734 | /* soft reset */ | |
61e271ee | 735 | flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr); |
e955cead MKB |
736 | udelay(10); |
737 | ||
61e271ee | 738 | reg_mcr = flexcan_read(®s->mcr); |
e955cead | 739 | if (reg_mcr & FLEXCAN_MCR_SOFTRST) { |
aabdfd6a WG |
740 | netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n", |
741 | reg_mcr); | |
e955cead MKB |
742 | err = -ENODEV; |
743 | goto out; | |
744 | } | |
745 | ||
746 | flexcan_set_bittiming(dev); | |
747 | ||
748 | /* | |
749 | * MCR | |
750 | * | |
751 | * enable freeze | |
752 | * enable fifo | |
753 | * halt now | |
754 | * only supervisor access | |
755 | * enable warning int | |
756 | * choose format C | |
9a123496 | 757 | * disable local echo |
e955cead MKB |
758 | * |
759 | */ | |
61e271ee | 760 | reg_mcr = flexcan_read(®s->mcr); |
d5a7b406 | 761 | reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); |
e955cead MKB |
762 | reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT | |
763 | FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | | |
d5a7b406 MKB |
764 | FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS | |
765 | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID); | |
aabdfd6a | 766 | netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); |
61e271ee | 767 | flexcan_write(reg_mcr, ®s->mcr); |
e955cead MKB |
768 | |
769 | /* | |
770 | * CTRL | |
771 | * | |
772 | * disable timer sync feature | |
773 | * | |
774 | * disable auto busoff recovery | |
775 | * transmit lowest buffer first | |
776 | * | |
777 | * enable tx and rx warning interrupt | |
778 | * enable bus off interrupt | |
779 | * (== FLEXCAN_CTRL_ERR_STATE) | |
e955cead | 780 | */ |
61e271ee | 781 | reg_ctrl = flexcan_read(®s->ctrl); |
e955cead MKB |
782 | reg_ctrl &= ~FLEXCAN_CTRL_TSYN; |
783 | reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | | |
4f72e5f0 WG |
784 | FLEXCAN_CTRL_ERR_STATE; |
785 | /* | |
786 | * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), | |
787 | * on most Flexcan cores, too. Otherwise we don't get | |
788 | * any error warning or passive interrupts. | |
789 | */ | |
790 | if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE || | |
791 | priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) | |
792 | reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; | |
e955cead MKB |
793 | |
794 | /* save for later use */ | |
795 | priv->reg_ctrl_default = reg_ctrl; | |
aabdfd6a | 796 | netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); |
61e271ee | 797 | flexcan_write(reg_ctrl, ®s->ctrl); |
e955cead | 798 | |
d5a7b406 MKB |
799 | /* Abort any pending TX, mark Mailbox as INACTIVE */ |
800 | flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), | |
801 | ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); | |
802 | ||
e955cead | 803 | /* acceptance mask/acceptance code (accept everything) */ |
61e271ee | 804 | flexcan_write(0x0, ®s->rxgmask); |
805 | flexcan_write(0x0, ®s->rx14mask); | |
806 | flexcan_write(0x0, ®s->rx15mask); | |
e955cead | 807 | |
4f72e5f0 | 808 | if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) |
30c1e672 HW |
809 | flexcan_write(0x0, ®s->rxfgmask); |
810 | ||
b7c4114b FE |
811 | if (priv->reg_xceiver) { |
812 | err = regulator_enable(priv->reg_xceiver); | |
813 | if (err) | |
814 | goto out; | |
815 | } | |
e955cead MKB |
816 | |
817 | /* synchronize with the can bus */ | |
61e271ee | 818 | reg_mcr = flexcan_read(®s->mcr); |
e955cead | 819 | reg_mcr &= ~FLEXCAN_MCR_HALT; |
61e271ee | 820 | flexcan_write(reg_mcr, ®s->mcr); |
e955cead MKB |
821 | |
822 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
823 | ||
824 | /* enable FIFO interrupts */ | |
61e271ee | 825 | flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1); |
e955cead MKB |
826 | |
827 | /* print chip status */ | |
aabdfd6a WG |
828 | netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, |
829 | flexcan_read(®s->mcr), flexcan_read(®s->ctrl)); | |
e955cead MKB |
830 | |
831 | return 0; | |
832 | ||
833 | out: | |
834 | flexcan_chip_disable(priv); | |
835 | return err; | |
836 | } | |
837 | ||
838 | /* | |
839 | * flexcan_chip_stop | |
840 | * | |
841 | * this functions is entered with clocks enabled | |
842 | * | |
843 | */ | |
844 | static void flexcan_chip_stop(struct net_device *dev) | |
845 | { | |
846 | struct flexcan_priv *priv = netdev_priv(dev); | |
847 | struct flexcan_regs __iomem *regs = priv->base; | |
848 | u32 reg; | |
849 | ||
e955cead | 850 | /* Disable + halt module */ |
61e271ee | 851 | reg = flexcan_read(®s->mcr); |
e955cead | 852 | reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT; |
61e271ee | 853 | flexcan_write(reg, ®s->mcr); |
e955cead | 854 | |
5be93bdd MKB |
855 | /* Disable all interrupts */ |
856 | flexcan_write(0, ®s->imask1); | |
857 | flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, | |
858 | ®s->ctrl); | |
859 | ||
b7c4114b FE |
860 | if (priv->reg_xceiver) |
861 | regulator_disable(priv->reg_xceiver); | |
e955cead MKB |
862 | priv->can.state = CAN_STATE_STOPPED; |
863 | ||
864 | return; | |
865 | } | |
866 | ||
867 | static int flexcan_open(struct net_device *dev) | |
868 | { | |
869 | struct flexcan_priv *priv = netdev_priv(dev); | |
870 | int err; | |
871 | ||
aa10181b FE |
872 | err = clk_prepare_enable(priv->clk_ipg); |
873 | if (err) | |
874 | return err; | |
875 | ||
876 | err = clk_prepare_enable(priv->clk_per); | |
877 | if (err) | |
878 | goto out_disable_ipg; | |
e955cead MKB |
879 | |
880 | err = open_candev(dev); | |
881 | if (err) | |
aa10181b | 882 | goto out_disable_per; |
e955cead MKB |
883 | |
884 | err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); | |
885 | if (err) | |
886 | goto out_close; | |
887 | ||
888 | /* start chip and queuing */ | |
889 | err = flexcan_chip_start(dev); | |
890 | if (err) | |
7e9e148a | 891 | goto out_free_irq; |
adccadb9 FB |
892 | |
893 | can_led_event(dev, CAN_LED_EVENT_OPEN); | |
894 | ||
e955cead MKB |
895 | napi_enable(&priv->napi); |
896 | netif_start_queue(dev); | |
897 | ||
898 | return 0; | |
899 | ||
7e9e148a MKB |
900 | out_free_irq: |
901 | free_irq(dev->irq, dev); | |
e955cead MKB |
902 | out_close: |
903 | close_candev(dev); | |
aa10181b | 904 | out_disable_per: |
3d42a379 | 905 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 906 | out_disable_ipg: |
3d42a379 | 907 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
908 | |
909 | return err; | |
910 | } | |
911 | ||
912 | static int flexcan_close(struct net_device *dev) | |
913 | { | |
914 | struct flexcan_priv *priv = netdev_priv(dev); | |
915 | ||
916 | netif_stop_queue(dev); | |
917 | napi_disable(&priv->napi); | |
918 | flexcan_chip_stop(dev); | |
919 | ||
920 | free_irq(dev->irq, dev); | |
3d42a379 ST |
921 | clk_disable_unprepare(priv->clk_per); |
922 | clk_disable_unprepare(priv->clk_ipg); | |
e955cead MKB |
923 | |
924 | close_candev(dev); | |
925 | ||
adccadb9 FB |
926 | can_led_event(dev, CAN_LED_EVENT_STOP); |
927 | ||
e955cead MKB |
928 | return 0; |
929 | } | |
930 | ||
931 | static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) | |
932 | { | |
933 | int err; | |
934 | ||
935 | switch (mode) { | |
936 | case CAN_MODE_START: | |
937 | err = flexcan_chip_start(dev); | |
938 | if (err) | |
939 | return err; | |
940 | ||
941 | netif_wake_queue(dev); | |
942 | break; | |
943 | ||
944 | default: | |
945 | return -EOPNOTSUPP; | |
946 | } | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | static const struct net_device_ops flexcan_netdev_ops = { | |
952 | .ndo_open = flexcan_open, | |
953 | .ndo_stop = flexcan_close, | |
954 | .ndo_start_xmit = flexcan_start_xmit, | |
955 | }; | |
956 | ||
3c8ac0f2 | 957 | static int register_flexcandev(struct net_device *dev) |
e955cead MKB |
958 | { |
959 | struct flexcan_priv *priv = netdev_priv(dev); | |
960 | struct flexcan_regs __iomem *regs = priv->base; | |
961 | u32 reg, err; | |
962 | ||
aa10181b FE |
963 | err = clk_prepare_enable(priv->clk_ipg); |
964 | if (err) | |
965 | return err; | |
966 | ||
967 | err = clk_prepare_enable(priv->clk_per); | |
968 | if (err) | |
969 | goto out_disable_ipg; | |
e955cead MKB |
970 | |
971 | /* select "bus clock", chip must be disabled */ | |
9b00b300 MKB |
972 | err = flexcan_chip_disable(priv); |
973 | if (err) | |
974 | goto out_disable_per; | |
61e271ee | 975 | reg = flexcan_read(®s->ctrl); |
e955cead | 976 | reg |= FLEXCAN_CTRL_CLK_SRC; |
61e271ee | 977 | flexcan_write(reg, ®s->ctrl); |
e955cead | 978 | |
9b00b300 MKB |
979 | err = flexcan_chip_enable(priv); |
980 | if (err) | |
981 | goto out_chip_disable; | |
e955cead MKB |
982 | |
983 | /* set freeze, halt and activate FIFO, restrict register access */ | |
61e271ee | 984 | reg = flexcan_read(®s->mcr); |
e955cead MKB |
985 | reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | |
986 | FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; | |
61e271ee | 987 | flexcan_write(reg, ®s->mcr); |
e955cead MKB |
988 | |
989 | /* | |
990 | * Currently we only support newer versions of this core | |
991 | * featuring a RX FIFO. Older cores found on some Coldfire | |
992 | * derivates are not yet supported. | |
993 | */ | |
61e271ee | 994 | reg = flexcan_read(®s->mcr); |
e955cead | 995 | if (!(reg & FLEXCAN_MCR_FEN)) { |
aabdfd6a | 996 | netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); |
e955cead | 997 | err = -ENODEV; |
9b00b300 | 998 | goto out_chip_disable; |
e955cead MKB |
999 | } |
1000 | ||
1001 | err = register_candev(dev); | |
1002 | ||
e955cead | 1003 | /* disable core and turn off clocks */ |
9b00b300 | 1004 | out_chip_disable: |
e955cead | 1005 | flexcan_chip_disable(priv); |
9b00b300 | 1006 | out_disable_per: |
3d42a379 | 1007 | clk_disable_unprepare(priv->clk_per); |
aa10181b | 1008 | out_disable_ipg: |
3d42a379 | 1009 | clk_disable_unprepare(priv->clk_ipg); |
e955cead MKB |
1010 | |
1011 | return err; | |
1012 | } | |
1013 | ||
3c8ac0f2 | 1014 | static void unregister_flexcandev(struct net_device *dev) |
e955cead MKB |
1015 | { |
1016 | unregister_candev(dev); | |
1017 | } | |
1018 | ||
30c1e672 | 1019 | static const struct of_device_id flexcan_of_match[] = { |
30c1e672 | 1020 | { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, |
e3587842 MKB |
1021 | { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, |
1022 | { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, | |
30c1e672 HW |
1023 | { /* sentinel */ }, |
1024 | }; | |
4358a9dc | 1025 | MODULE_DEVICE_TABLE(of, flexcan_of_match); |
30c1e672 HW |
1026 | |
1027 | static const struct platform_device_id flexcan_id_table[] = { | |
1028 | { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, }, | |
1029 | { /* sentinel */ }, | |
1030 | }; | |
4358a9dc | 1031 | MODULE_DEVICE_TABLE(platform, flexcan_id_table); |
30c1e672 | 1032 | |
3c8ac0f2 | 1033 | static int flexcan_probe(struct platform_device *pdev) |
e955cead | 1034 | { |
30c1e672 | 1035 | const struct of_device_id *of_id; |
dda0b3bd | 1036 | const struct flexcan_devtype_data *devtype_data; |
e955cead MKB |
1037 | struct net_device *dev; |
1038 | struct flexcan_priv *priv; | |
1039 | struct resource *mem; | |
3d42a379 | 1040 | struct clk *clk_ipg = NULL, *clk_per = NULL; |
e955cead | 1041 | void __iomem *base; |
e955cead | 1042 | int err, irq; |
97efe9ae | 1043 | u32 clock_freq = 0; |
1044 | ||
afc016d8 HW |
1045 | if (pdev->dev.of_node) |
1046 | of_property_read_u32(pdev->dev.of_node, | |
1047 | "clock-frequency", &clock_freq); | |
97efe9ae | 1048 | |
1049 | if (!clock_freq) { | |
3d42a379 ST |
1050 | clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1051 | if (IS_ERR(clk_ipg)) { | |
1052 | dev_err(&pdev->dev, "no ipg clock defined\n"); | |
933e4af4 | 1053 | return PTR_ERR(clk_ipg); |
3d42a379 | 1054 | } |
3d42a379 ST |
1055 | |
1056 | clk_per = devm_clk_get(&pdev->dev, "per"); | |
1057 | if (IS_ERR(clk_per)) { | |
1058 | dev_err(&pdev->dev, "no per clock defined\n"); | |
933e4af4 | 1059 | return PTR_ERR(clk_per); |
97efe9ae | 1060 | } |
1a3e5173 | 1061 | clock_freq = clk_get_rate(clk_per); |
e955cead MKB |
1062 | } |
1063 | ||
1064 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1065 | irq = platform_get_irq(pdev, 0); | |
933e4af4 FE |
1066 | if (irq <= 0) |
1067 | return -ENODEV; | |
e955cead | 1068 | |
933e4af4 FE |
1069 | base = devm_ioremap_resource(&pdev->dev, mem); |
1070 | if (IS_ERR(base)) | |
1071 | return PTR_ERR(base); | |
e955cead | 1072 | |
30c1e672 HW |
1073 | of_id = of_match_device(flexcan_of_match, &pdev->dev); |
1074 | if (of_id) { | |
1075 | devtype_data = of_id->data; | |
1076 | } else if (pdev->id_entry->driver_data) { | |
1077 | devtype_data = (struct flexcan_devtype_data *) | |
1078 | pdev->id_entry->driver_data; | |
1079 | } else { | |
933e4af4 | 1080 | return -ENODEV; |
30c1e672 HW |
1081 | } |
1082 | ||
933e4af4 FE |
1083 | dev = alloc_candev(sizeof(struct flexcan_priv), 1); |
1084 | if (!dev) | |
1085 | return -ENOMEM; | |
1086 | ||
e955cead MKB |
1087 | dev->netdev_ops = &flexcan_netdev_ops; |
1088 | dev->irq = irq; | |
9a123496 | 1089 | dev->flags |= IFF_ECHO; |
e955cead MKB |
1090 | |
1091 | priv = netdev_priv(dev); | |
97efe9ae | 1092 | priv->can.clock.freq = clock_freq; |
e955cead MKB |
1093 | priv->can.bittiming_const = &flexcan_bittiming_const; |
1094 | priv->can.do_set_mode = flexcan_set_mode; | |
1095 | priv->can.do_get_berr_counter = flexcan_get_berr_counter; | |
1096 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | | |
1097 | CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | | |
1098 | CAN_CTRLMODE_BERR_REPORTING; | |
1099 | priv->base = base; | |
1100 | priv->dev = dev; | |
3d42a379 ST |
1101 | priv->clk_ipg = clk_ipg; |
1102 | priv->clk_per = clk_per; | |
84ae6643 | 1103 | priv->pdata = dev_get_platdata(&pdev->dev); |
30c1e672 | 1104 | priv->devtype_data = devtype_data; |
e955cead | 1105 | |
b7c4114b FE |
1106 | priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver"); |
1107 | if (IS_ERR(priv->reg_xceiver)) | |
1108 | priv->reg_xceiver = NULL; | |
1109 | ||
e955cead MKB |
1110 | netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT); |
1111 | ||
d75ea942 | 1112 | platform_set_drvdata(pdev, dev); |
e955cead MKB |
1113 | SET_NETDEV_DEV(dev, &pdev->dev); |
1114 | ||
1115 | err = register_flexcandev(dev); | |
1116 | if (err) { | |
1117 | dev_err(&pdev->dev, "registering netdev failed\n"); | |
1118 | goto failed_register; | |
1119 | } | |
1120 | ||
adccadb9 FB |
1121 | devm_can_led_init(dev); |
1122 | ||
e955cead MKB |
1123 | dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", |
1124 | priv->base, dev->irq); | |
1125 | ||
1126 | return 0; | |
1127 | ||
1128 | failed_register: | |
1129 | free_candev(dev); | |
e955cead MKB |
1130 | return err; |
1131 | } | |
1132 | ||
3c8ac0f2 | 1133 | static int flexcan_remove(struct platform_device *pdev) |
e955cead MKB |
1134 | { |
1135 | struct net_device *dev = platform_get_drvdata(pdev); | |
e955cead MKB |
1136 | |
1137 | unregister_flexcandev(dev); | |
e955cead | 1138 | |
9a27586d MKB |
1139 | free_candev(dev); |
1140 | ||
e955cead MKB |
1141 | return 0; |
1142 | } | |
1143 | ||
588e7a8e FE |
1144 | #ifdef CONFIG_PM_SLEEP |
1145 | static int flexcan_suspend(struct device *device) | |
8b5e218d | 1146 | { |
588e7a8e | 1147 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d | 1148 | struct flexcan_priv *priv = netdev_priv(dev); |
9b00b300 | 1149 | int err; |
8b5e218d | 1150 | |
9b00b300 MKB |
1151 | err = flexcan_chip_disable(priv); |
1152 | if (err) | |
1153 | return err; | |
8b5e218d EB |
1154 | |
1155 | if (netif_running(dev)) { | |
1156 | netif_stop_queue(dev); | |
1157 | netif_device_detach(dev); | |
1158 | } | |
1159 | priv->can.state = CAN_STATE_SLEEPING; | |
1160 | ||
1161 | return 0; | |
1162 | } | |
1163 | ||
588e7a8e | 1164 | static int flexcan_resume(struct device *device) |
8b5e218d | 1165 | { |
588e7a8e | 1166 | struct net_device *dev = dev_get_drvdata(device); |
8b5e218d EB |
1167 | struct flexcan_priv *priv = netdev_priv(dev); |
1168 | ||
1169 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1170 | if (netif_running(dev)) { | |
1171 | netif_device_attach(dev); | |
1172 | netif_start_queue(dev); | |
1173 | } | |
9b00b300 | 1174 | return flexcan_chip_enable(priv); |
8b5e218d | 1175 | } |
588e7a8e FE |
1176 | #endif /* CONFIG_PM_SLEEP */ |
1177 | ||
1178 | static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume); | |
8b5e218d | 1179 | |
e955cead | 1180 | static struct platform_driver flexcan_driver = { |
c8aef4cb | 1181 | .driver = { |
1182 | .name = DRV_NAME, | |
1183 | .owner = THIS_MODULE, | |
588e7a8e | 1184 | .pm = &flexcan_pm_ops, |
c8aef4cb | 1185 | .of_match_table = flexcan_of_match, |
1186 | }, | |
e955cead | 1187 | .probe = flexcan_probe, |
3c8ac0f2 | 1188 | .remove = flexcan_remove, |
30c1e672 | 1189 | .id_table = flexcan_id_table, |
e955cead MKB |
1190 | }; |
1191 | ||
871d3372 | 1192 | module_platform_driver(flexcan_driver); |
e955cead MKB |
1193 | |
1194 | MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " | |
1195 | "Marc Kleine-Budde <kernel@pengutronix.de>"); | |
1196 | MODULE_LICENSE("GPL v2"); | |
1197 | MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); |