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can: flexcan: handle state passive -> warning transition
[linux-2.6-block.git] / drivers / net / can / flexcan.c
CommitLineData
e955cead
MKB		 1/*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22#include <linux/netdevice.h>
23#include <linux/can.h>
24#include <linux/can/dev.h>
25#include <linux/can/error.h>
adccadb9 26#include <linux/can/led.h>
e955cead
MKB		 27#include <linux/clk.h>
28#include <linux/delay.h>
29#include <linux/if_arp.h>
30#include <linux/if_ether.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kernel.h>
34#include <linux/list.h>
35#include <linux/module.h>
97efe9ae 36#include <linux/of.h>
30c1e672 37#include <linux/of_device.h>
e955cead 38#include <linux/platform_device.h>
b7c4114b 39#include <linux/regulator/consumer.h>
e955cead 40
e955cead
MKB		 41#define DRV_NAME "flexcan"
42
43/* 8 for RX fifo and 2 error handling */
44#define FLEXCAN_NAPI_WEIGHT (8 + 2)
45
46/* FLEXCAN module configuration register (CANMCR) bits */
47#define FLEXCAN_MCR_MDIS BIT(31)
48#define FLEXCAN_MCR_FRZ BIT(30)
49#define FLEXCAN_MCR_FEN BIT(29)
50#define FLEXCAN_MCR_HALT BIT(28)
51#define FLEXCAN_MCR_NOT_RDY BIT(27)
52#define FLEXCAN_MCR_WAK_MSK BIT(26)
53#define FLEXCAN_MCR_SOFTRST BIT(25)
54#define FLEXCAN_MCR_FRZ_ACK BIT(24)
55#define FLEXCAN_MCR_SUPV BIT(23)
56#define FLEXCAN_MCR_SLF_WAK BIT(22)
57#define FLEXCAN_MCR_WRN_EN BIT(21)
58#define FLEXCAN_MCR_LPM_ACK BIT(20)
59#define FLEXCAN_MCR_WAK_SRC BIT(19)
60#define FLEXCAN_MCR_DOZE BIT(18)
61#define FLEXCAN_MCR_SRX_DIS BIT(17)
62#define FLEXCAN_MCR_BCC BIT(16)
63#define FLEXCAN_MCR_LPRIO_EN BIT(13)
64#define FLEXCAN_MCR_AEN BIT(12)
d5a7b406 65#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
e955cead
MKB		 66#define FLEXCAN_MCR_IDAM_A (0 << 8)
67#define FLEXCAN_MCR_IDAM_B (1 << 8)
68#define FLEXCAN_MCR_IDAM_C (2 << 8)
69#define FLEXCAN_MCR_IDAM_D (3 << 8)
70
71/* FLEXCAN control register (CANCTRL) bits */
72#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
73#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
74#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
75#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
76#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
77#define FLEXCAN_CTRL_ERR_MSK BIT(14)
78#define FLEXCAN_CTRL_CLK_SRC BIT(13)
79#define FLEXCAN_CTRL_LPB BIT(12)
80#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
81#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
82#define FLEXCAN_CTRL_SMP BIT(7)
83#define FLEXCAN_CTRL_BOFF_REC BIT(6)
84#define FLEXCAN_CTRL_TSYN BIT(5)
85#define FLEXCAN_CTRL_LBUF BIT(4)
86#define FLEXCAN_CTRL_LOM BIT(3)
87#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
88#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
89#define FLEXCAN_CTRL_ERR_STATE \
90 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
91 FLEXCAN_CTRL_BOFF_MSK)
92#define FLEXCAN_CTRL_ERR_ALL \
93 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
94
95/* FLEXCAN error and status register (ESR) bits */
96#define FLEXCAN_ESR_TWRN_INT BIT(17)
97#define FLEXCAN_ESR_RWRN_INT BIT(16)
98#define FLEXCAN_ESR_BIT1_ERR BIT(15)
99#define FLEXCAN_ESR_BIT0_ERR BIT(14)
100#define FLEXCAN_ESR_ACK_ERR BIT(13)
101#define FLEXCAN_ESR_CRC_ERR BIT(12)
102#define FLEXCAN_ESR_FRM_ERR BIT(11)
103#define FLEXCAN_ESR_STF_ERR BIT(10)
104#define FLEXCAN_ESR_TX_WRN BIT(9)
105#define FLEXCAN_ESR_RX_WRN BIT(8)
106#define FLEXCAN_ESR_IDLE BIT(7)
107#define FLEXCAN_ESR_TXRX BIT(6)
108#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
109#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
110#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
111#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
112#define FLEXCAN_ESR_BOFF_INT BIT(2)
113#define FLEXCAN_ESR_ERR_INT BIT(1)
114#define FLEXCAN_ESR_WAK_INT BIT(0)
115#define FLEXCAN_ESR_ERR_BUS \
116 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
117 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
118 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
119#define FLEXCAN_ESR_ERR_STATE \
120 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
121#define FLEXCAN_ESR_ERR_ALL \
122 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
6e9d554f
WG		 123#define FLEXCAN_ESR_ALL_INT \
124 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
125 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
e955cead
MKB		 126
127/* FLEXCAN interrupt flag register (IFLAG) bits */
128#define FLEXCAN_TX_BUF_ID 8
129#define FLEXCAN_IFLAG_BUF(x) BIT(x)
130#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
131#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
132#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
133#define FLEXCAN_IFLAG_DEFAULT \
134 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
135 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
136
137/* FLEXCAN message buffers */
138#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
139#define FLEXCAN_MB_CNT_SRR BIT(22)
140#define FLEXCAN_MB_CNT_IDE BIT(21)
141#define FLEXCAN_MB_CNT_RTR BIT(20)
142#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
143#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
144
145#define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
146
9b00b300
MKB		 147#define FLEXCAN_TIMEOUT_US (50)
148
bb698ca4
WG		 149/*
150 * FLEXCAN hardware feature flags
151 *
152 * Below is some version info we got:
153 * SOC Version IP-Version Glitch- [TR]WRN_INT
154 * Filter? connected?
155 * MX25 FlexCAN2 03.00.00.00 no no
156 * MX28 FlexCAN2 03.00.04.00 yes yes
157 * MX35 FlexCAN2 03.00.00.00 no no
158 * MX53 FlexCAN2 03.00.00.00 yes no
159 * MX6s FlexCAN3 10.00.12.00 yes yes
160 *
161 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
162 */
4f72e5f0 163#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
bb698ca4 164#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
4f72e5f0 165
e955cead
MKB		 166/* Structure of the message buffer */
167struct flexcan_mb {
168 u32 can_ctrl;
169 u32 can_id;
170 u32 data[2];
171};
172
173/* Structure of the hardware registers */
174struct flexcan_regs {
175 u32 mcr; /* 0x00 */
176 u32 ctrl; /* 0x04 */
177 u32 timer; /* 0x08 */
178 u32 _reserved1; /* 0x0c */
179 u32 rxgmask; /* 0x10 */
180 u32 rx14mask; /* 0x14 */
181 u32 rx15mask; /* 0x18 */
182 u32 ecr; /* 0x1c */
183 u32 esr; /* 0x20 */
184 u32 imask2; /* 0x24 */
185 u32 imask1; /* 0x28 */
186 u32 iflag2; /* 0x2c */
187 u32 iflag1; /* 0x30 */
30c1e672
HW		 188 u32 crl2; /* 0x34 */
189 u32 esr2; /* 0x38 */
190 u32 imeur; /* 0x3c */
191 u32 lrfr; /* 0x40 */
192 u32 crcr; /* 0x44 */
193 u32 rxfgmask; /* 0x48 */
194 u32 rxfir; /* 0x4c */
195 u32 _reserved3[12];
e955cead
MKB		 196 struct flexcan_mb cantxfg[64];
197};
198
30c1e672 199struct flexcan_devtype_data {
4f72e5f0 200 u32 features; /* hardware controller features */
30c1e672
HW		 201};
202
e955cead
MKB		 203struct flexcan_priv {
204 struct can_priv can;
205 struct net_device *dev;
206 struct napi_struct napi;
207
208 void __iomem *base;
209 u32 reg_esr;
210 u32 reg_ctrl_default;
211
3d42a379
ST		 212 struct clk *clk_ipg;
213 struct clk *clk_per;
e955cead 214 struct flexcan_platform_data *pdata;
dda0b3bd 215 const struct flexcan_devtype_data *devtype_data;
b7c4114b 216 struct regulator *reg_xceiver;
30c1e672
HW		 217};
218
219static struct flexcan_devtype_data fsl_p1010_devtype_data = {
4f72e5f0 220 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
30c1e672 221};
4f72e5f0 222static struct flexcan_devtype_data fsl_imx28_devtype_data;
30c1e672 223static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
bb698ca4 224 .features = FLEXCAN_HAS_V10_FEATURES,
e955cead
MKB		 225};
226
194b9a4c 227static const struct can_bittiming_const flexcan_bittiming_const = {
e955cead
MKB		 228 .name = DRV_NAME,
229 .tseg1_min = 4,
230 .tseg1_max = 16,
231 .tseg2_min = 2,
232 .tseg2_max = 8,
233 .sjw_max = 4,
234 .brp_min = 1,
235 .brp_max = 256,
236 .brp_inc = 1,
237};
238
61e271ee 239/*
0e4b949e
AB		 240 * Abstract off the read/write for arm versus ppc. This
241 * assumes that PPC uses big-endian registers and everything
242 * else uses little-endian registers, independent of CPU
243 * endianess.
61e271ee 244 */
0e4b949e 245#if defined(CONFIG_PPC)
61e271ee 246static inline u32 flexcan_read(void __iomem *addr)
247{
248 return in_be32(addr);
249}
250
251static inline void flexcan_write(u32 val, void __iomem *addr)
252{
253 out_be32(addr, val);
254}
255#else
256static inline u32 flexcan_read(void __iomem *addr)
257{
258 return readl(addr);
259}
260
261static inline void flexcan_write(u32 val, void __iomem *addr)
262{
263 writel(val, addr);
264}
265#endif
266
f003698e
MKB		 267static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
268{
269 if (!priv->reg_xceiver)
270 return 0;
271
272 return regulator_enable(priv->reg_xceiver);
273}
274
275static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
276{
277 if (!priv->reg_xceiver)
278 return 0;
279
280 return regulator_disable(priv->reg_xceiver);
281}
282
e955cead
MKB		 283static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
284 u32 reg_esr)
285{
286 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
287 (reg_esr & FLEXCAN_ESR_ERR_BUS);
288}
289
9b00b300 290static int flexcan_chip_enable(struct flexcan_priv *priv)
e955cead
MKB		 291{
292 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 293 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 294 u32 reg;
295
61e271ee 296 reg = flexcan_read(&regs->mcr);
e955cead 297 reg &= ~FLEXCAN_MCR_MDIS;
61e271ee 298 flexcan_write(reg, &regs->mcr);
e955cead 299
9b00b300
MKB		 300 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
301 usleep_range(10, 20);
302
303 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
304 return -ETIMEDOUT;
305
306 return 0;
e955cead
MKB		 307}
308
9b00b300 309static int flexcan_chip_disable(struct flexcan_priv *priv)
e955cead
MKB		 310{
311 struct flexcan_regs __iomem *regs = priv->base;
9b00b300 312 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
e955cead
MKB		 313 u32 reg;
314
61e271ee 315 reg = flexcan_read(&regs->mcr);
e955cead 316 reg |= FLEXCAN_MCR_MDIS;
61e271ee 317 flexcan_write(reg, &regs->mcr);
9b00b300
MKB		 318
319 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
320 usleep_range(10, 20);
321
322 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
323 return -ETIMEDOUT;
324
325 return 0;
e955cead
MKB		 326}
327
b1aa1c7a
MKB		 328static int flexcan_chip_freeze(struct flexcan_priv *priv)
329{
330 struct flexcan_regs __iomem *regs = priv->base;
331 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
332 u32 reg;
333
334 reg = flexcan_read(&regs->mcr);
335 reg |= FLEXCAN_MCR_HALT;
336 flexcan_write(reg, &regs->mcr);
337
338 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
339 usleep_range(100, 200);
340
341 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
342 return -ETIMEDOUT;
343
344 return 0;
345}
346
347static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
348{
349 struct flexcan_regs __iomem *regs = priv->base;
350 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
351 u32 reg;
352
353 reg = flexcan_read(&regs->mcr);
354 reg &= ~FLEXCAN_MCR_HALT;
355 flexcan_write(reg, &regs->mcr);
356
357 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
358 usleep_range(10, 20);
359
360 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
361 return -ETIMEDOUT;
362
363 return 0;
364}
365
4b5b8227
MKB		 366static int flexcan_chip_softreset(struct flexcan_priv *priv)
367{
368 struct flexcan_regs __iomem *regs = priv->base;
369 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
370
371 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
372 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
373 usleep_range(10, 20);
374
375 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
376 return -ETIMEDOUT;
377
378 return 0;
379}
380
e955cead
MKB		 381static int flexcan_get_berr_counter(const struct net_device *dev,
382 struct can_berr_counter *bec)
383{
384 const struct flexcan_priv *priv = netdev_priv(dev);
385 struct flexcan_regs __iomem *regs = priv->base;
61e271ee 386 u32 reg = flexcan_read(&regs->ecr);
e955cead
MKB		 387
388 bec->txerr = (reg >> 0) & 0xff;
389 bec->rxerr = (reg >> 8) & 0xff;
390
391 return 0;
392}
393
394static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
395{
396 const struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 397 struct flexcan_regs __iomem *regs = priv->base;
398 struct can_frame *cf = (struct can_frame *)skb->data;
399 u32 can_id;
400 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
401
402 if (can_dropped_invalid_skb(dev, skb))
403 return NETDEV_TX_OK;
404
405 netif_stop_queue(dev);
406
407 if (cf->can_id & CAN_EFF_FLAG) {
408 can_id = cf->can_id & CAN_EFF_MASK;
409 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
410 } else {
411 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
412 }
413
414 if (cf->can_id & CAN_RTR_FLAG)
415 ctrl |= FLEXCAN_MB_CNT_RTR;
416
417 if (cf->can_dlc > 0) {
418 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
61e271ee 419 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
e955cead
MKB		 420 }
421 if (cf->can_dlc > 3) {
422 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
61e271ee 423 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
e955cead
MKB		 424 }
425
9a123496
RD		 426 can_put_echo_skb(skb, dev, 0);
427
61e271ee 428 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
429 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
e955cead 430
e955cead
MKB		 431 return NETDEV_TX_OK;
432}
433
434static void do_bus_err(struct net_device *dev,
435 struct can_frame *cf, u32 reg_esr)
436{
437 struct flexcan_priv *priv = netdev_priv(dev);
438 int rx_errors = 0, tx_errors = 0;
439
440 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
441
442 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
aabdfd6a 443 netdev_dbg(dev, "BIT1_ERR irq\n");
e955cead
MKB		 444 cf->data[2] |= CAN_ERR_PROT_BIT1;
445 tx_errors = 1;
446 }
447 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
aabdfd6a 448 netdev_dbg(dev, "BIT0_ERR irq\n");
e955cead
MKB		 449 cf->data[2] |= CAN_ERR_PROT_BIT0;
450 tx_errors = 1;
451 }
452 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
aabdfd6a 453 netdev_dbg(dev, "ACK_ERR irq\n");
e955cead
MKB		 454 cf->can_id |= CAN_ERR_ACK;
455 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
456 tx_errors = 1;
457 }
458 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
aabdfd6a 459 netdev_dbg(dev, "CRC_ERR irq\n");
e955cead
MKB		 460 cf->data[2] |= CAN_ERR_PROT_BIT;
461 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
462 rx_errors = 1;
463 }
464 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
aabdfd6a 465 netdev_dbg(dev, "FRM_ERR irq\n");
e955cead
MKB		 466 cf->data[2] |= CAN_ERR_PROT_FORM;
467 rx_errors = 1;
468 }
469 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
aabdfd6a 470 netdev_dbg(dev, "STF_ERR irq\n");
e955cead
MKB		 471 cf->data[2] |= CAN_ERR_PROT_STUFF;
472 rx_errors = 1;
473 }
474
475 priv->can.can_stats.bus_error++;
476 if (rx_errors)
477 dev->stats.rx_errors++;
478 if (tx_errors)
479 dev->stats.tx_errors++;
480}
481
482static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
483{
484 struct sk_buff *skb;
485 struct can_frame *cf;
486
487 skb = alloc_can_err_skb(dev, &cf);
488 if (unlikely(!skb))
489 return 0;
490
491 do_bus_err(dev, cf, reg_esr);
492 netif_receive_skb(skb);
493
494 dev->stats.rx_packets++;
495 dev->stats.rx_bytes += cf->can_dlc;
496
497 return 1;
498}
499
500static void do_state(struct net_device *dev,
501 struct can_frame *cf, enum can_state new_state)
502{
503 struct flexcan_priv *priv = netdev_priv(dev);
504 struct can_berr_counter bec;
505
506 flexcan_get_berr_counter(dev, &bec);
507
508 switch (priv->can.state) {
509 case CAN_STATE_ERROR_ACTIVE:
510 /*
511 * from: ERROR_ACTIVE
512 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
513 * => : there was a warning int
514 */
515 if (new_state >= CAN_STATE_ERROR_WARNING &&
516 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 517 netdev_dbg(dev, "Error Warning IRQ\n");
e955cead
MKB		 518 priv->can.can_stats.error_warning++;
519
520 cf->can_id |= CAN_ERR_CRTL;
521 cf->data[1] = (bec.txerr > bec.rxerr) ?
522 CAN_ERR_CRTL_TX_WARNING :
523 CAN_ERR_CRTL_RX_WARNING;
524 }
525 case CAN_STATE_ERROR_WARNING: /* fallthrough */
526 /*
527 * from: ERROR_ACTIVE, ERROR_WARNING
528 * to : ERROR_PASSIVE, BUS_OFF
529 * => : error passive int
530 */
531 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
532 new_state <= CAN_STATE_BUS_OFF) {
aabdfd6a 533 netdev_dbg(dev, "Error Passive IRQ\n");
e955cead
MKB		 534 priv->can.can_stats.error_passive++;
535
536 cf->can_id |= CAN_ERR_CRTL;
537 cf->data[1] = (bec.txerr > bec.rxerr) ?
538 CAN_ERR_CRTL_TX_PASSIVE :
539 CAN_ERR_CRTL_RX_PASSIVE;
540 }
541 break;
542 case CAN_STATE_BUS_OFF:
aabdfd6a
WG		 543 netdev_err(dev, "BUG! "
544 "hardware recovered automatically from BUS_OFF\n");
e955cead
MKB		 545 break;
546 default:
547 break;
548 }
549
550 /* process state changes depending on the new state */
551 switch (new_state) {
8ce261d0
SAS		 552 case CAN_STATE_ERROR_WARNING:
553 netdev_dbg(dev, "Error Warning\n");
554 cf->can_id |= CAN_ERR_CRTL;
555 cf->data[1] = (bec.txerr > bec.rxerr) ?
556 CAN_ERR_CRTL_TX_WARNING :
557 CAN_ERR_CRTL_RX_WARNING;
558 break;
e955cead 559 case CAN_STATE_ERROR_ACTIVE:
aabdfd6a 560 netdev_dbg(dev, "Error Active\n");
e955cead
MKB		 561 cf->can_id |= CAN_ERR_PROT;
562 cf->data[2] = CAN_ERR_PROT_ACTIVE;
563 break;
564 case CAN_STATE_BUS_OFF:
565 cf->can_id |= CAN_ERR_BUSOFF;
566 can_bus_off(dev);
567 break;
568 default:
569 break;
570 }
571}
572
573static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
574{
575 struct flexcan_priv *priv = netdev_priv(dev);
576 struct sk_buff *skb;
577 struct can_frame *cf;
578 enum can_state new_state;
579 int flt;
580
581 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
582 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
583 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
584 FLEXCAN_ESR_RX_WRN))))
585 new_state = CAN_STATE_ERROR_ACTIVE;
586 else
587 new_state = CAN_STATE_ERROR_WARNING;
588 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
589 new_state = CAN_STATE_ERROR_PASSIVE;
590 else
591 new_state = CAN_STATE_BUS_OFF;
592
593 /* state hasn't changed */
594 if (likely(new_state == priv->can.state))
595 return 0;
596
597 skb = alloc_can_err_skb(dev, &cf);
598 if (unlikely(!skb))
599 return 0;
600
601 do_state(dev, cf, new_state);
602 priv->can.state = new_state;
603 netif_receive_skb(skb);
604
605 dev->stats.rx_packets++;
606 dev->stats.rx_bytes += cf->can_dlc;
607
608 return 1;
609}
610
611static void flexcan_read_fifo(const struct net_device *dev,
612 struct can_frame *cf)
613{
614 const struct flexcan_priv *priv = netdev_priv(dev);
615 struct flexcan_regs __iomem *regs = priv->base;
616 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
617 u32 reg_ctrl, reg_id;
618
61e271ee 619 reg_ctrl = flexcan_read(&mb->can_ctrl);
620 reg_id = flexcan_read(&mb->can_id);
e955cead
MKB		 621 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
622 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
623 else
624 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
625
626 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
627 cf->can_id |= CAN_RTR_FLAG;
628 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
629
61e271ee 630 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
631 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
e955cead
MKB		 632
633 /* mark as read */
61e271ee 634 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
635 flexcan_read(&regs->timer);
e955cead
MKB		 636}
637
638static int flexcan_read_frame(struct net_device *dev)
639{
640 struct net_device_stats *stats = &dev->stats;
641 struct can_frame *cf;
642 struct sk_buff *skb;
643
644 skb = alloc_can_skb(dev, &cf);
645 if (unlikely(!skb)) {
646 stats->rx_dropped++;
647 return 0;
648 }
649
650 flexcan_read_fifo(dev, cf);
651 netif_receive_skb(skb);
652
653 stats->rx_packets++;
654 stats->rx_bytes += cf->can_dlc;
655
adccadb9
FB		 656 can_led_event(dev, CAN_LED_EVENT_RX);
657
e955cead
MKB		 658 return 1;
659}
660
661static int flexcan_poll(struct napi_struct *napi, int quota)
662{
663 struct net_device *dev = napi->dev;
664 const struct flexcan_priv *priv = netdev_priv(dev);
665 struct flexcan_regs __iomem *regs = priv->base;
666 u32 reg_iflag1, reg_esr;
667 int work_done = 0;
668
669 /*
670 * The error bits are cleared on read,
671 * use saved value from irq handler.
672 */
61e271ee 673 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
e955cead
MKB		 674
675 /* handle state changes */
676 work_done += flexcan_poll_state(dev, reg_esr);
677
678 /* handle RX-FIFO */
61e271ee 679 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 680 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
681 work_done < quota) {
682 work_done += flexcan_read_frame(dev);
61e271ee 683 reg_iflag1 = flexcan_read(&regs->iflag1);
e955cead
MKB		 684 }
685
686 /* report bus errors */
687 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
688 work_done += flexcan_poll_bus_err(dev, reg_esr);
689
690 if (work_done < quota) {
691 napi_complete(napi);
692 /* enable IRQs */
61e271ee 693 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
694 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
e955cead
MKB		 695 }
696
697 return work_done;
698}
699
700static irqreturn_t flexcan_irq(int irq, void *dev_id)
701{
702 struct net_device *dev = dev_id;
703 struct net_device_stats *stats = &dev->stats;
704 struct flexcan_priv *priv = netdev_priv(dev);
705 struct flexcan_regs __iomem *regs = priv->base;
706 u32 reg_iflag1, reg_esr;
707
61e271ee 708 reg_iflag1 = flexcan_read(&regs->iflag1);
709 reg_esr = flexcan_read(&regs->esr);
6e9d554f
WG		 710 /* ACK all bus error and state change IRQ sources */
711 if (reg_esr & FLEXCAN_ESR_ALL_INT)
712 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
e955cead
MKB		 713
714 /*
715 * schedule NAPI in case of:
716 * - rx IRQ
717 * - state change IRQ
718 * - bus error IRQ and bus error reporting is activated
719 */
720 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
721 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
722 flexcan_has_and_handle_berr(priv, reg_esr)) {
723 /*
724 * The error bits are cleared on read,
725 * save them for later use.
726 */
727 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
61e271ee 728 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
729 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
730 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
e955cead
MKB		 731 &regs->ctrl);
732 napi_schedule(&priv->napi);
733 }
734
735 /* FIFO overflow */
736 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
61e271ee 737 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
e955cead
MKB		 738 dev->stats.rx_over_errors++;
739 dev->stats.rx_errors++;
740 }
741
742 /* transmission complete interrupt */
743 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
9a123496 744 stats->tx_bytes += can_get_echo_skb(dev, 0);
e955cead 745 stats->tx_packets++;
adccadb9 746 can_led_event(dev, CAN_LED_EVENT_TX);
61e271ee 747 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
e955cead
MKB		 748 netif_wake_queue(dev);
749 }
750
751 return IRQ_HANDLED;
752}
753
754static void flexcan_set_bittiming(struct net_device *dev)
755{
756 const struct flexcan_priv *priv = netdev_priv(dev);
757 const struct can_bittiming *bt = &priv->can.bittiming;
758 struct flexcan_regs __iomem *regs = priv->base;
759 u32 reg;
760
61e271ee 761 reg = flexcan_read(&regs->ctrl);
e955cead
MKB		 762 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
763 FLEXCAN_CTRL_RJW(0x3) |
764 FLEXCAN_CTRL_PSEG1(0x7) |
765 FLEXCAN_CTRL_PSEG2(0x7) |
766 FLEXCAN_CTRL_PROPSEG(0x7) |
767 FLEXCAN_CTRL_LPB |
768 FLEXCAN_CTRL_SMP |
769 FLEXCAN_CTRL_LOM);
770
771 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
772 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
773 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
774 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
775 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
776
777 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
778 reg |= FLEXCAN_CTRL_LPB;
779 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
780 reg |= FLEXCAN_CTRL_LOM;
781 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
782 reg |= FLEXCAN_CTRL_SMP;
783
aabdfd6a 784 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
61e271ee 785 flexcan_write(reg, &regs->ctrl);
e955cead
MKB		 786
787 /* print chip status */
aabdfd6a
WG		 788 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
789 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 790}
791
792/*
793 * flexcan_chip_start
794 *
795 * this functions is entered with clocks enabled
796 *
797 */
798static int flexcan_chip_start(struct net_device *dev)
799{
800 struct flexcan_priv *priv = netdev_priv(dev);
801 struct flexcan_regs __iomem *regs = priv->base;
e955cead
MKB		 802 int err;
803 u32 reg_mcr, reg_ctrl;
804
805 /* enable module */
9b00b300
MKB		 806 err = flexcan_chip_enable(priv);
807 if (err)
808 return err;
e955cead
MKB		 809
810 /* soft reset */
4b5b8227
MKB		 811 err = flexcan_chip_softreset(priv);
812 if (err)
b1aa1c7a 813 goto out_chip_disable;
e955cead
MKB		 814
815 flexcan_set_bittiming(dev);
816
817 /*
818 * MCR
819 *
820 * enable freeze
821 * enable fifo
822 * halt now
823 * only supervisor access
824 * enable warning int
825 * choose format C
9a123496 826 * disable local echo
e955cead
MKB		 827 *
828 */
61e271ee 829 reg_mcr = flexcan_read(&regs->mcr);
d5a7b406 830 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
e955cead
MKB		 831 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
832 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
d5a7b406
MKB		 833 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
834 FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
aabdfd6a 835 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
61e271ee 836 flexcan_write(reg_mcr, &regs->mcr);
e955cead
MKB		 837
838 /*
839 * CTRL
840 *
841 * disable timer sync feature
842 *
843 * disable auto busoff recovery
844 * transmit lowest buffer first
845 *
846 * enable tx and rx warning interrupt
847 * enable bus off interrupt
848 * (== FLEXCAN_CTRL_ERR_STATE)
e955cead 849 */
61e271ee 850 reg_ctrl = flexcan_read(&regs->ctrl);
e955cead
MKB		 851 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
852 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
4f72e5f0
WG		 853 FLEXCAN_CTRL_ERR_STATE;
854 /*
855 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
856 * on most Flexcan cores, too. Otherwise we don't get
857 * any error warning or passive interrupts.
858 */
859 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
860 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
861 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
bc03a541
AS		 862 else
863 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
e955cead
MKB		 864
865 /* save for later use */
866 priv->reg_ctrl_default = reg_ctrl;
aabdfd6a 867 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
61e271ee 868 flexcan_write(reg_ctrl, &regs->ctrl);
e955cead 869
d5a7b406
MKB		 870 /* Abort any pending TX, mark Mailbox as INACTIVE */
871 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
872 &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
873
e955cead 874 /* acceptance mask/acceptance code (accept everything) */
61e271ee 875 flexcan_write(0x0, &regs->rxgmask);
876 flexcan_write(0x0, &regs->rx14mask);
877 flexcan_write(0x0, &regs->rx15mask);
e955cead 878
4f72e5f0 879 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
30c1e672
HW		 880 flexcan_write(0x0, &regs->rxfgmask);
881
f003698e
MKB		 882 err = flexcan_transceiver_enable(priv);
883 if (err)
b1aa1c7a 884 goto out_chip_disable;
e955cead
MKB		 885
886 /* synchronize with the can bus */
b1aa1c7a
MKB		 887 err = flexcan_chip_unfreeze(priv);
888 if (err)
889 goto out_transceiver_disable;
e955cead
MKB		 890
891 priv->can.state = CAN_STATE_ERROR_ACTIVE;
892
893 /* enable FIFO interrupts */
61e271ee 894 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
e955cead
MKB		 895
896 /* print chip status */
aabdfd6a
WG		 897 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
898 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
e955cead
MKB		 899
900 return 0;
901
b1aa1c7a
MKB		 902 out_transceiver_disable:
903 flexcan_transceiver_disable(priv);
904 out_chip_disable:
e955cead
MKB		 905 flexcan_chip_disable(priv);
906 return err;
907}
908
909/*
910 * flexcan_chip_stop
911 *
912 * this functions is entered with clocks enabled
913 *
914 */
915static void flexcan_chip_stop(struct net_device *dev)
916{
917 struct flexcan_priv *priv = netdev_priv(dev);
918 struct flexcan_regs __iomem *regs = priv->base;
e955cead 919
b1aa1c7a
MKB		 920 /* freeze + disable module */
921 flexcan_chip_freeze(priv);
922 flexcan_chip_disable(priv);
e955cead 923
5be93bdd
MKB		 924 /* Disable all interrupts */
925 flexcan_write(0, &regs->imask1);
926 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
927 &regs->ctrl);
928
f003698e 929 flexcan_transceiver_disable(priv);
e955cead
MKB		 930 priv->can.state = CAN_STATE_STOPPED;
931
932 return;
933}
934
935static int flexcan_open(struct net_device *dev)
936{
937 struct flexcan_priv *priv = netdev_priv(dev);
938 int err;
939
aa10181b
FE		 940 err = clk_prepare_enable(priv->clk_ipg);
941 if (err)
942 return err;
943
944 err = clk_prepare_enable(priv->clk_per);
945 if (err)
946 goto out_disable_ipg;
e955cead
MKB		 947
948 err = open_candev(dev);
949 if (err)
aa10181b 950 goto out_disable_per;
e955cead
MKB		 951
952 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
953 if (err)
954 goto out_close;
955
956 /* start chip and queuing */
957 err = flexcan_chip_start(dev);
958 if (err)
7e9e148a 959 goto out_free_irq;
adccadb9
FB		 960
961 can_led_event(dev, CAN_LED_EVENT_OPEN);
962
e955cead
MKB		 963 napi_enable(&priv->napi);
964 netif_start_queue(dev);
965
966 return 0;
967
7e9e148a
MKB		 968 out_free_irq:
969 free_irq(dev->irq, dev);
e955cead
MKB		 970 out_close:
971 close_candev(dev);
aa10181b 972 out_disable_per:
3d42a379 973 clk_disable_unprepare(priv->clk_per);
aa10181b 974 out_disable_ipg:
3d42a379 975 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 976
977 return err;
978}
979
980static int flexcan_close(struct net_device *dev)
981{
982 struct flexcan_priv *priv = netdev_priv(dev);
983
984 netif_stop_queue(dev);
985 napi_disable(&priv->napi);
986 flexcan_chip_stop(dev);
987
988 free_irq(dev->irq, dev);
3d42a379
ST		 989 clk_disable_unprepare(priv->clk_per);
990 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 991
992 close_candev(dev);
993
adccadb9
FB		 994 can_led_event(dev, CAN_LED_EVENT_STOP);
995
e955cead
MKB		 996 return 0;
997}
998
999static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1000{
1001 int err;
1002
1003 switch (mode) {
1004 case CAN_MODE_START:
1005 err = flexcan_chip_start(dev);
1006 if (err)
1007 return err;
1008
1009 netif_wake_queue(dev);
1010 break;
1011
1012 default:
1013 return -EOPNOTSUPP;
1014 }
1015
1016 return 0;
1017}
1018
1019static const struct net_device_ops flexcan_netdev_ops = {
1020 .ndo_open = flexcan_open,
1021 .ndo_stop = flexcan_close,
1022 .ndo_start_xmit = flexcan_start_xmit,
c971fa2a 1023 .ndo_change_mtu = can_change_mtu,
e955cead
MKB		 1024};
1025
3c8ac0f2 1026static int register_flexcandev(struct net_device *dev)
e955cead
MKB		 1027{
1028 struct flexcan_priv *priv = netdev_priv(dev);
1029 struct flexcan_regs __iomem *regs = priv->base;
1030 u32 reg, err;
1031
aa10181b
FE		 1032 err = clk_prepare_enable(priv->clk_ipg);
1033 if (err)
1034 return err;
1035
1036 err = clk_prepare_enable(priv->clk_per);
1037 if (err)
1038 goto out_disable_ipg;
e955cead
MKB		 1039
1040 /* select "bus clock", chip must be disabled */
9b00b300
MKB		 1041 err = flexcan_chip_disable(priv);
1042 if (err)
1043 goto out_disable_per;
61e271ee 1044 reg = flexcan_read(&regs->ctrl);
e955cead 1045 reg |= FLEXCAN_CTRL_CLK_SRC;
61e271ee 1046 flexcan_write(reg, &regs->ctrl);
e955cead 1047
9b00b300
MKB		 1048 err = flexcan_chip_enable(priv);
1049 if (err)
1050 goto out_chip_disable;
e955cead
MKB		 1051
1052 /* set freeze, halt and activate FIFO, restrict register access */
61e271ee 1053 reg = flexcan_read(&regs->mcr);
e955cead
MKB		 1054 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1055 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
61e271ee 1056 flexcan_write(reg, &regs->mcr);
e955cead
MKB		 1057
1058 /*
1059 * Currently we only support newer versions of this core
1060 * featuring a RX FIFO. Older cores found on some Coldfire
1061 * derivates are not yet supported.
1062 */
61e271ee 1063 reg = flexcan_read(&regs->mcr);
e955cead 1064 if (!(reg & FLEXCAN_MCR_FEN)) {
aabdfd6a 1065 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
e955cead 1066 err = -ENODEV;
9b00b300 1067 goto out_chip_disable;
e955cead
MKB		 1068 }
1069
1070 err = register_candev(dev);
1071
e955cead 1072 /* disable core and turn off clocks */
9b00b300 1073 out_chip_disable:
e955cead 1074 flexcan_chip_disable(priv);
9b00b300 1075 out_disable_per:
3d42a379 1076 clk_disable_unprepare(priv->clk_per);
aa10181b 1077 out_disable_ipg:
3d42a379 1078 clk_disable_unprepare(priv->clk_ipg);
e955cead
MKB		 1079
1080 return err;
1081}
1082
3c8ac0f2 1083static void unregister_flexcandev(struct net_device *dev)
e955cead
MKB		 1084{
1085 unregister_candev(dev);
1086}
1087
30c1e672 1088static const struct of_device_id flexcan_of_match[] = {
30c1e672 1089 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
e3587842
MKB		 1090 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1091 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
30c1e672
HW		 1092 { /* sentinel */ },
1093};
4358a9dc 1094MODULE_DEVICE_TABLE(of, flexcan_of_match);
30c1e672
HW		 1095
1096static const struct platform_device_id flexcan_id_table[] = {
1097 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1098 { /* sentinel */ },
1099};
4358a9dc 1100MODULE_DEVICE_TABLE(platform, flexcan_id_table);
30c1e672 1101
3c8ac0f2 1102static int flexcan_probe(struct platform_device *pdev)
e955cead 1103{
30c1e672 1104 const struct of_device_id *of_id;
dda0b3bd 1105 const struct flexcan_devtype_data *devtype_data;
e955cead
MKB		 1106 struct net_device *dev;
1107 struct flexcan_priv *priv;
1108 struct resource *mem;
3d42a379 1109 struct clk *clk_ipg = NULL, *clk_per = NULL;
e955cead 1110 void __iomem *base;
e955cead 1111 int err, irq;
97efe9ae 1112 u32 clock_freq = 0;
1113
afc016d8
HW		 1114 if (pdev->dev.of_node)
1115 of_property_read_u32(pdev->dev.of_node,
1116 "clock-frequency", &clock_freq);
97efe9ae 1117
1118 if (!clock_freq) {
3d42a379
ST		 1119 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1120 if (IS_ERR(clk_ipg)) {
1121 dev_err(&pdev->dev, "no ipg clock defined\n");
933e4af4 1122 return PTR_ERR(clk_ipg);
3d42a379 1123 }
3d42a379
ST		 1124
1125 clk_per = devm_clk_get(&pdev->dev, "per");
1126 if (IS_ERR(clk_per)) {
1127 dev_err(&pdev->dev, "no per clock defined\n");
933e4af4 1128 return PTR_ERR(clk_per);
97efe9ae 1129 }
1a3e5173 1130 clock_freq = clk_get_rate(clk_per);
e955cead
MKB		 1131 }
1132
1133 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134 irq = platform_get_irq(pdev, 0);
933e4af4
FE		 1135 if (irq <= 0)
1136 return -ENODEV;
e955cead 1137
933e4af4
FE		 1138 base = devm_ioremap_resource(&pdev->dev, mem);
1139 if (IS_ERR(base))
1140 return PTR_ERR(base);
e955cead 1141
30c1e672
HW		 1142 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1143 if (of_id) {
1144 devtype_data = of_id->data;
d0873e6f 1145 } else if (platform_get_device_id(pdev)->driver_data) {
30c1e672 1146 devtype_data = (struct flexcan_devtype_data *)
d0873e6f 1147 platform_get_device_id(pdev)->driver_data;
30c1e672 1148 } else {
933e4af4 1149 return -ENODEV;
30c1e672
HW		 1150 }
1151
933e4af4
FE		 1152 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1153 if (!dev)
1154 return -ENOMEM;
1155
e955cead
MKB		 1156 dev->netdev_ops = &flexcan_netdev_ops;
1157 dev->irq = irq;
9a123496 1158 dev->flags |= IFF_ECHO;
e955cead
MKB		 1159
1160 priv = netdev_priv(dev);
97efe9ae 1161 priv->can.clock.freq = clock_freq;
e955cead
MKB		 1162 priv->can.bittiming_const = &flexcan_bittiming_const;
1163 priv->can.do_set_mode = flexcan_set_mode;
1164 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1165 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1166 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1167 CAN_CTRLMODE_BERR_REPORTING;
1168 priv->base = base;
1169 priv->dev = dev;
3d42a379
ST		 1170 priv->clk_ipg = clk_ipg;
1171 priv->clk_per = clk_per;
84ae6643 1172 priv->pdata = dev_get_platdata(&pdev->dev);
30c1e672 1173 priv->devtype_data = devtype_data;
e955cead 1174
b7c4114b
FE		 1175 priv->reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1176 if (IS_ERR(priv->reg_xceiver))
1177 priv->reg_xceiver = NULL;
1178
e955cead
MKB		 1179 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1180
d75ea942 1181 platform_set_drvdata(pdev, dev);
e955cead
MKB		 1182 SET_NETDEV_DEV(dev, &pdev->dev);
1183
1184 err = register_flexcandev(dev);
1185 if (err) {
1186 dev_err(&pdev->dev, "registering netdev failed\n");
1187 goto failed_register;
1188 }
1189
adccadb9
FB		 1190 devm_can_led_init(dev);
1191
e955cead
MKB		 1192 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1193 priv->base, dev->irq);
1194
1195 return 0;
1196
1197 failed_register:
1198 free_candev(dev);
e955cead
MKB		 1199 return err;
1200}
1201
3c8ac0f2 1202static int flexcan_remove(struct platform_device *pdev)
e955cead
MKB		 1203{
1204 struct net_device *dev = platform_get_drvdata(pdev);
d96e43e8 1205 struct flexcan_priv *priv = netdev_priv(dev);
e955cead
MKB		 1206
1207 unregister_flexcandev(dev);
d96e43e8 1208 netif_napi_del(&priv->napi);
9a27586d
MKB		 1209 free_candev(dev);
1210
e955cead
MKB		 1211 return 0;
1212}
1213
08c6d351 1214static int __maybe_unused flexcan_suspend(struct device *device)
8b5e218d 1215{
588e7a8e 1216 struct net_device *dev = dev_get_drvdata(device);
8b5e218d 1217 struct flexcan_priv *priv = netdev_priv(dev);
9b00b300 1218 int err;
8b5e218d 1219
9b00b300
MKB		 1220 err = flexcan_chip_disable(priv);
1221 if (err)
1222 return err;
8b5e218d
EB		 1223
1224 if (netif_running(dev)) {
1225 netif_stop_queue(dev);
1226 netif_device_detach(dev);
1227 }
1228 priv->can.state = CAN_STATE_SLEEPING;
1229
1230 return 0;
1231}
1232
08c6d351 1233static int __maybe_unused flexcan_resume(struct device *device)
8b5e218d 1234{
588e7a8e 1235 struct net_device *dev = dev_get_drvdata(device);
8b5e218d
EB		 1236 struct flexcan_priv *priv = netdev_priv(dev);
1237
1238 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1239 if (netif_running(dev)) {
1240 netif_device_attach(dev);
1241 netif_start_queue(dev);
1242 }
9b00b300 1243 return flexcan_chip_enable(priv);
8b5e218d 1244}
588e7a8e
FE		 1245
1246static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
8b5e218d 1247
e955cead 1248static struct platform_driver flexcan_driver = {
c8aef4cb 1249 .driver = {
1250 .name = DRV_NAME,
1251 .owner = THIS_MODULE,
588e7a8e 1252 .pm = &flexcan_pm_ops,
c8aef4cb 1253 .of_match_table = flexcan_of_match,
1254 },
e955cead 1255 .probe = flexcan_probe,
3c8ac0f2 1256 .remove = flexcan_remove,
30c1e672 1257 .id_table = flexcan_id_table,
e955cead
MKB		 1258};
1259
871d3372 1260module_platform_driver(flexcan_driver);
e955cead
MKB		 1261
1262MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1263 "Marc Kleine-Budde <kernel@pengutronix.de>");
1264MODULE_LICENSE("GPL v2");
1265MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux 6.x block layer and io_uring tree(s)