[linux-2.6-block.git] / drivers / net / can / c_can / c_can_platform.c

/*
 * Platform CAN bus driver for Bosch C_CAN controller
 *
 * Copyright (C) 2010 ST Microelectronics
 * Bhupesh Sharma <bhupesh.sharma@st.com>
 *
 * Borrowed heavily from the C_CAN driver originally written by:
 * Copyright (C) 2007
 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
 *
 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
 * Bosch C_CAN user manual can be obtained from:
 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
 * users_manual_c_can.pdf
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include <linux/can/dev.h>

#include "c_can.h"

#define DCAN_RAM_INIT_BIT		(1 << 3)
static DEFINE_SPINLOCK(raminit_lock);
/*
 * 16-bit c_can registers can be arranged differently in the memory
 * architecture of different implementations. For example: 16-bit
 * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
 * Handle the same by providing a common read/write interface.
 */
static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
						enum reg index)
{
	return readw(priv->base + priv->regs[index]);
}

static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
						enum reg index, u16 val)
{
	writew(val, priv->base + priv->regs[index]);
}

static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
						enum reg index)
{
	return readw(priv->base + 2 * priv->regs[index]);
}

static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
						enum reg index, u16 val)
{
	writew(val, priv->base + 2 * priv->regs[index]);
}

static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
					 u32 mask, u32 val)
{
	const struct c_can_raminit *raminit = &priv->raminit_sys;
	int timeout = 0;
	u32 ctrl = 0;

	/* We look only at the bits of our instance. */
	val &= mask;
	do {
		udelay(1);
		timeout++;

		regmap_read(raminit->syscon, raminit->reg, &ctrl);
		if (timeout == 1000) {
			dev_err(&priv->dev->dev, "%s: time out\n", __func__);
			break;
		}
	} while ((ctrl & mask) != val);
}

static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
{
	const struct c_can_raminit *raminit = &priv->raminit_sys;
	u32 ctrl = 0;
	u32 mask;

	spin_lock(&raminit_lock);

	mask = 1 << raminit->bits.start | 1 << raminit->bits.done;
	regmap_read(raminit->syscon, raminit->reg, &ctrl);

	/* We clear the start bit first. The start bit is
	 * looking at the 0 -> transition, but is not self clearing;
	 * NOTE: DONE must be written with 1 to clear it.
	 * We can't clear the DONE bit here using regmap_update_bits()
	 * as it will bypass the write if initial condition is START:0 DONE:1
	 * e.g. on DRA7 which needs START pulse.
	 */
	ctrl &= ~mask;	/* START = 0, DONE = 0 */
	regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);

	/* check if START bit is 0. Ignore DONE bit for now
	 * as it can be either 0 or 1.
	 */
	c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl);

	if (enable) {
		/* Clear DONE bit & set START bit. */
		ctrl |= 1 << raminit->bits.start;
		/* DONE must be written with 1 to clear it */
		ctrl |= 1 << raminit->bits.done;
		regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
		/* prevent further clearing of DONE bit */
		ctrl &= ~(1 << raminit->bits.done);
		/* clear START bit if start pulse is needed */
		if (raminit->needs_pulse) {
			ctrl &= ~(1 << raminit->bits.start);
			regmap_update_bits(raminit->syscon, raminit->reg,
					   mask, ctrl);
		}

		ctrl |= 1 << raminit->bits.done;
		c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
	}
	spin_unlock(&raminit_lock);
}

static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
{
	u32 val;

	val = priv->read_reg(priv, index);
	val |= ((u32) priv->read_reg(priv, index + 1)) << 16;

	return val;
}

static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
		u32 val)
{
	priv->write_reg(priv, index + 1, val >> 16);
	priv->write_reg(priv, index, val);
}

static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
{
	return readl(priv->base + priv->regs[index]);
}

static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
		u32 val)
{
	writel(val, priv->base + priv->regs[index]);
}

static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
{
	while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
		udelay(1);
}

static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
{
	u32 ctrl;

	ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
	ctrl &= ~DCAN_RAM_INIT_BIT;
	priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
	c_can_hw_raminit_wait(priv, ctrl);

	if (enable) {
		ctrl |= DCAN_RAM_INIT_BIT;
		priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
		c_can_hw_raminit_wait(priv, ctrl);
	}
}

static const struct c_can_driver_data c_can_drvdata = {
	.id = BOSCH_C_CAN,
};

static const struct c_can_driver_data d_can_drvdata = {
	.id = BOSCH_D_CAN,
};

static const struct raminit_bits dra7_raminit_bits[] = {
	[0] = { .start = 3, .done = 1, },
	[1] = { .start = 5, .done = 2, },
};

static const struct c_can_driver_data dra7_dcan_drvdata = {
	.id = BOSCH_D_CAN,
	.raminit_num = ARRAY_SIZE(dra7_raminit_bits),
	.raminit_bits = dra7_raminit_bits,
	.raminit_pulse = true,
};

static const struct raminit_bits am3352_raminit_bits[] = {
	[0] = { .start = 0, .done = 8, },
	[1] = { .start = 1, .done = 9, },
};

static const struct c_can_driver_data am3352_dcan_drvdata = {
	.id = BOSCH_D_CAN,
	.raminit_num = ARRAY_SIZE(am3352_raminit_bits),
	.raminit_bits = am3352_raminit_bits,
};

static struct platform_device_id c_can_id_table[] = {
	{
		.name = KBUILD_MODNAME,
		.driver_data = (kernel_ulong_t)&c_can_drvdata,
	},
	{
		.name = "c_can",
		.driver_data = (kernel_ulong_t)&c_can_drvdata,
	},
	{
		.name = "d_can",
		.driver_data = (kernel_ulong_t)&d_can_drvdata,
	},
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(platform, c_can_id_table);

static const struct of_device_id c_can_of_table[] = {
	{ .compatible = "bosch,c_can", .data = &c_can_drvdata },
	{ .compatible = "bosch,d_can", .data = &d_can_drvdata },
	{ .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
	{ .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
	{ .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
	{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, c_can_of_table);

static int c_can_plat_probe(struct platform_device *pdev)
{
	int ret;
	void __iomem *addr;
	struct net_device *dev;
	struct c_can_priv *priv;
	const struct of_device_id *match;
	struct resource *mem;
	int irq;
	struct clk *clk;
	const struct c_can_driver_data *drvdata;
	struct device_node *np = pdev->dev.of_node;

	match = of_match_device(c_can_of_table, &pdev->dev);
	if (match) {
		drvdata = match->data;
	} else if (pdev->id_entry->driver_data) {
		drvdata = (struct c_can_driver_data *)
			platform_get_device_id(pdev)->driver_data;
	} else {
		return -ENODEV;
	}

	/* get the appropriate clk */
	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		ret = PTR_ERR(clk);
		goto exit;
	}

	/* get the platform data */
	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		ret = -ENODEV;
		goto exit;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	addr = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(addr)) {
		ret =  PTR_ERR(addr);
		goto exit;
	}

	/* allocate the c_can device */
	dev = alloc_c_can_dev();
	if (!dev) {
		ret = -ENOMEM;
		goto exit;
	}

	priv = netdev_priv(dev);
	switch (drvdata->id) {
	case BOSCH_C_CAN:
		priv->regs = reg_map_c_can;
		switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
		case IORESOURCE_MEM_32BIT:
			priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
			priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
			priv->read_reg32 = c_can_plat_read_reg32;
			priv->write_reg32 = c_can_plat_write_reg32;
			break;
		case IORESOURCE_MEM_16BIT:
		default:
			priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
			priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
			priv->read_reg32 = c_can_plat_read_reg32;
			priv->write_reg32 = c_can_plat_write_reg32;
			break;
		}
		break;
	case BOSCH_D_CAN:
		priv->regs = reg_map_d_can;
		priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
		priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
		priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
		priv->read_reg32 = d_can_plat_read_reg32;
		priv->write_reg32 = d_can_plat_write_reg32;

		/* Check if we need custom RAMINIT via syscon. Mostly for TI
		 * platforms. Only supported with DT boot.
		 */
		if (np && of_property_read_bool(np, "syscon-raminit")) {
			u32 id;
			struct c_can_raminit *raminit = &priv->raminit_sys;

			ret = -EINVAL;
			raminit->syscon = syscon_regmap_lookup_by_phandle(np,
									  "syscon-raminit");
			if (IS_ERR(raminit->syscon)) {
				/* can fail with -EPROBE_DEFER */
				ret = PTR_ERR(raminit->syscon);
				free_c_can_dev(dev);
				return ret;
			}

			if (of_property_read_u32_index(np, "syscon-raminit", 1,
						       &raminit->reg)) {
				dev_err(&pdev->dev,
					"couldn't get the RAMINIT reg. offset!\n");
				goto exit_free_device;
			}

			if (of_property_read_u32_index(np, "syscon-raminit", 2,
						       &id)) {
				dev_err(&pdev->dev,
					"couldn't get the CAN instance ID\n");
				goto exit_free_device;
			}

			if (id >= drvdata->raminit_num) {
				dev_err(&pdev->dev,
					"Invalid CAN instance ID\n");
				goto exit_free_device;
			}

			raminit->bits = drvdata->raminit_bits[id];
			raminit->needs_pulse = drvdata->raminit_pulse;

			priv->raminit = c_can_hw_raminit_syscon;
		} else {
			priv->raminit = c_can_hw_raminit;
		}
		break;
	default:
		ret = -EINVAL;
		goto exit_free_device;
	}

	dev->irq = irq;
	priv->base = addr;
	priv->device = &pdev->dev;
	priv->can.clock.freq = clk_get_rate(clk);
	priv->priv = clk;
	priv->type = drvdata->id;

	platform_set_drvdata(pdev, dev);
	SET_NETDEV_DEV(dev, &pdev->dev);

	ret = register_c_can_dev(dev);
	if (ret) {
		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
			KBUILD_MODNAME, ret);
		goto exit_free_device;
	}

	dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
		 KBUILD_MODNAME, priv->base, dev->irq);
	return 0;

exit_free_device:
	free_c_can_dev(dev);
exit:
	dev_err(&pdev->dev, "probe failed\n");

	return ret;
}

static int c_can_plat_remove(struct platform_device *pdev)
{
	struct net_device *dev = platform_get_drvdata(pdev);

	unregister_c_can_dev(dev);

	free_c_can_dev(dev);

	return 0;
}

#ifdef CONFIG_PM
static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
{
	int ret;
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct c_can_priv *priv = netdev_priv(ndev);

	if (priv->type != BOSCH_D_CAN) {
		dev_warn(&pdev->dev, "Not supported\n");
		return 0;
	}

	if (netif_running(ndev)) {
		netif_stop_queue(ndev);
		netif_device_detach(ndev);
	}

	ret = c_can_power_down(ndev);
	if (ret) {
		netdev_err(ndev, "failed to enter power down mode\n");
		return ret;
	}

	priv->can.state = CAN_STATE_SLEEPING;

	return 0;
}

static int c_can_resume(struct platform_device *pdev)
{
	int ret;
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct c_can_priv *priv = netdev_priv(ndev);

	if (priv->type != BOSCH_D_CAN) {
		dev_warn(&pdev->dev, "Not supported\n");
		return 0;
	}

	ret = c_can_power_up(ndev);
	if (ret) {
		netdev_err(ndev, "Still in power down mode\n");
		return ret;
	}

	priv->can.state = CAN_STATE_ERROR_ACTIVE;

	if (netif_running(ndev)) {
		netif_device_attach(ndev);
		netif_start_queue(ndev);
	}

	return 0;
}
#else
#define c_can_suspend NULL
#define c_can_resume NULL
#endif

static struct platform_driver c_can_plat_driver = {
	.driver = {
		.name = KBUILD_MODNAME,
		.of_match_table = c_can_of_table,
	},
	.probe = c_can_plat_probe,
	.remove = c_can_plat_remove,
	.suspend = c_can_suspend,
	.resume = c_can_resume,
	.id_table = c_can_id_table,
};

module_platform_driver(c_can_plat_driver);

MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
Commit	Line	Data
881ff67a BS	1	/*
	2	* Platform CAN bus driver for Bosch C_CAN controller
	3	*
	4	* Copyright (C) 2010 ST Microelectronics
	5	* Bhupesh Sharma <bhupesh.sharma@st.com>
	6	*
	7	* Borrowed heavily from the C_CAN driver originally written by:
	8	* Copyright (C) 2007
	9	* - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
	10	* - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
	11	*
	12	* Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
	13	* Bosch C_CAN user manual can be obtained from:
	14	* http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
	15	* users_manual_c_can.pdf
	16	*
	17	* This file is licensed under the terms of the GNU General Public
	18	* License version 2. This program is licensed "as is" without any
	19	* warranty of any kind, whether express or implied.
	20	*/
	21
	22	#include <linux/kernel.h>
881ff67a BS	23	#include <linux/module.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/delay.h>
	26	#include <linux/netdevice.h>
	27	#include <linux/if_arp.h>
	28	#include <linux/if_ether.h>
	29	#include <linux/list.h>
881ff67a BS	30	#include <linux/io.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/clk.h>
2469627d AC	33	#include <linux/of.h>
2469627d AC	34	#include <linux/of_device.h>
3ff9027c RQ	35	#include <linux/mfd/syscon.h>
3ff9027c RQ	36	#include <linux/regmap.h>
881ff67a BS	37
	38	#include <linux/can/dev.h>
	39
	40	#include "c_can.h"
	41
a9c69209	42	#define DCAN_RAM_INIT_BIT (1 << 3)
5bb9cbaa	43	static DEFINE_SPINLOCK(raminit_lock);
881ff67a BS	44	/*
	45	* 16-bit c_can registers can be arranged differently in the memory
	46	* architecture of different implementations. For example: 16-bit
	47	* registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
	48	* Handle the same by providing a common read/write interface.
	49	*/
e07e83ae	50	static u16 c_can_plat_read_reg_aligned_to_16bit(const struct c_can_priv *priv,
33f81009	51	enum reg index)
881ff67a	52	{
33f81009	53	return readw(priv->base + priv->regs[index]);
881ff67a BS	54	}
881ff67a BS	55
e07e83ae	56	static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
33f81009	57	enum reg index, u16 val)
881ff67a	58	{
33f81009	59	writew(val, priv->base + priv->regs[index]);
881ff67a BS	60	}
881ff67a BS	61
e07e83ae	62	static u16 c_can_plat_read_reg_aligned_to_32bit(const struct c_can_priv *priv,
33f81009	63	enum reg index)
881ff67a	64	{
33f81009	65	return readw(priv->base + 2 * priv->regs[index]);
881ff67a BS	66	}
881ff67a BS	67
e07e83ae	68	static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
33f81009	69	enum reg index, u16 val)
881ff67a	70	{
33f81009	71	writew(val, priv->base + 2 * priv->regs[index]);
881ff67a BS	72	}
881ff67a BS	73
3ff9027c RQ	74	static void c_can_hw_raminit_wait_syscon(const struct c_can_priv *priv,
3ff9027c RQ	75	u32 mask, u32 val)
5bb9cbaa	76	{
3ff9027c	77	const struct c_can_raminit *raminit = &priv->raminit_sys;
e7e26bc7	78	int timeout = 0;
3ff9027c	79	u32 ctrl = 0;
e7e26bc7	80
5bb9cbaa TG	81	/* We look only at the bits of our instance. */
5bb9cbaa TG	82	val &= mask;
3ff9027c	83	do {
5bb9cbaa	84	udelay(1);
e7e26bc7 RQ	85	timeout++;
e7e26bc7 RQ	86
3ff9027c	87	regmap_read(raminit->syscon, raminit->reg, &ctrl);
e7e26bc7 RQ	88	if (timeout == 1000) {
	89	dev_err(&priv->dev->dev, "%s: time out\n", __func__);
	90	break;
	91	}
3ff9027c	92	} while ((ctrl & mask) != val);
5bb9cbaa TG	93	}
5bb9cbaa TG	94
3ff9027c	95	static void c_can_hw_raminit_syscon(const struct c_can_priv *priv, bool enable)
52cde85a	96	{
3ff9027c RQ	97	const struct c_can_raminit *raminit = &priv->raminit_sys;
	98	u32 ctrl = 0;
	99	u32 mask;
52cde85a	100
5bb9cbaa TG	101	spin_lock(&raminit_lock);
5bb9cbaa TG	102
3ff9027c RQ	103	mask = 1 << raminit->bits.start \| 1 << raminit->bits.done;
	104	regmap_read(raminit->syscon, raminit->reg, &ctrl);
	105
47e3485a	106	/* We clear the start bit first. The start bit is
5bb9cbaa	107	* looking at the 0 -> transition, but is not self clearing;
3ff9027c	108	* NOTE: DONE must be written with 1 to clear it.
47e3485a RQ	109	* We can't clear the DONE bit here using regmap_update_bits()
	110	* as it will bypass the write if initial condition is START:0 DONE:1
	111	* e.g. on DRA7 which needs START pulse.
5bb9cbaa	112	*/
47e3485a RQ	113	ctrl &= ~mask; /* START = 0, DONE = 0 */
47e3485a RQ	114	regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
3ff9027c	115
47e3485a RQ	116	/* check if START bit is 0. Ignore DONE bit for now
	117	* as it can be either 0 or 1.
	118	*/
	119	c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl);
5bb9cbaa TG	120
5bb9cbaa TG	121	if (enable) {
47e3485a	122	/* Clear DONE bit & set START bit. */
3ff9027c	123	ctrl \|= 1 << raminit->bits.start;
47e3485a RQ	124	/* DONE must be written with 1 to clear it */
	125	ctrl \|= 1 << raminit->bits.done;
	126	regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl);
	127	/* prevent further clearing of DONE bit */
	128	ctrl &= ~(1 << raminit->bits.done);
0741bfb9 RQ	129	/* clear START bit if start pulse is needed */
	130	if (raminit->needs_pulse) {
	131	ctrl &= ~(1 << raminit->bits.start);
47e3485a RQ	132	regmap_update_bits(raminit->syscon, raminit->reg,
47e3485a RQ	133	mask, ctrl);
0741bfb9 RQ	134	}
0741bfb9 RQ	135
3ff9027c RQ	136	ctrl \|= 1 << raminit->bits.done;
3ff9027c RQ	137	c_can_hw_raminit_wait_syscon(priv, mask, ctrl);
5bb9cbaa TG	138	}
5bb9cbaa TG	139	spin_unlock(&raminit_lock);
52cde85a AC	140	}
52cde85a AC	141
ccbc5357 PM	142	static u32 c_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
	143	{
	144	u32 val;
	145
	146	val = priv->read_reg(priv, index);
	147	val \|= ((u32) priv->read_reg(priv, index + 1)) << 16;
	148
	149	return val;
	150	}
	151
	152	static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
	153	u32 val)
	154	{
	155	priv->write_reg(priv, index + 1, val >> 16);
	156	priv->write_reg(priv, index, val);
	157	}
	158
	159	static u32 d_can_plat_read_reg32(const struct c_can_priv *priv, enum reg index)
	160	{
	161	return readl(priv->base + priv->regs[index]);
	162	}
	163
	164	static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
	165	u32 val)
	166	{
	167	writel(val, priv->base + priv->regs[index]);
	168	}
	169
a9c69209 PM	170	static void c_can_hw_raminit_wait(const struct c_can_priv *priv, u32 mask)
	171	{
	172	while (priv->read_reg32(priv, C_CAN_FUNCTION_REG) & mask)
	173	udelay(1);
	174	}
	175
	176	static void c_can_hw_raminit(const struct c_can_priv *priv, bool enable)
	177	{
	178	u32 ctrl;
	179
	180	ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG);
	181	ctrl &= ~DCAN_RAM_INIT_BIT;
	182	priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
	183	c_can_hw_raminit_wait(priv, ctrl);
	184
	185	if (enable) {
	186	ctrl \|= DCAN_RAM_INIT_BIT;
	187	priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl);
	188	c_can_hw_raminit_wait(priv, ctrl);
	189	}
	190	}
	191
15151090 RQ	192	static const struct c_can_driver_data c_can_drvdata = {
	193	.id = BOSCH_C_CAN,
	194	};
	195
	196	static const struct c_can_driver_data d_can_drvdata = {
	197	.id = BOSCH_D_CAN,
	198	};
	199
0f4da3a8 RQ	200	static const struct raminit_bits dra7_raminit_bits[] = {
	201	[0] = { .start = 3, .done = 1, },
	202	[1] = { .start = 5, .done = 2, },
	203	};
	204
	205	static const struct c_can_driver_data dra7_dcan_drvdata = {
	206	.id = BOSCH_D_CAN,
	207	.raminit_num = ARRAY_SIZE(dra7_raminit_bits),
	208	.raminit_bits = dra7_raminit_bits,
	209	.raminit_pulse = true,
	210	};
	211
c71d0b31 RQ	212	static const struct raminit_bits am3352_raminit_bits[] = {
	213	[0] = { .start = 0, .done = 8, },
	214	[1] = { .start = 1, .done = 9, },
	215	};
	216
	217	static const struct c_can_driver_data am3352_dcan_drvdata = {
	218	.id = BOSCH_D_CAN,
	219	.raminit_num = ARRAY_SIZE(am3352_raminit_bits),
	220	.raminit_bits = am3352_raminit_bits,
	221	};
	222
2469627d	223	static struct platform_device_id c_can_id_table[] = {
15151090	224	{
2469627d	225	.name = KBUILD_MODNAME,
15151090	226	.driver_data = (kernel_ulong_t)&c_can_drvdata,
2469627d	227	},
15151090	228	{
2469627d	229	.name = "c_can",
15151090	230	.driver_data = (kernel_ulong_t)&c_can_drvdata,
2469627d	231	},
15151090	232	{
2469627d	233	.name = "d_can",
15151090 RQ	234	.driver_data = (kernel_ulong_t)&d_can_drvdata,
	235	},
	236	{ /* sentinel */ },
2469627d	237	};
69c0c5b1	238	MODULE_DEVICE_TABLE(platform, c_can_id_table);
2469627d AC	239
2469627d AC	240	static const struct of_device_id c_can_of_table[] = {
15151090 RQ	241	{ .compatible = "bosch,c_can", .data = &c_can_drvdata },
15151090 RQ	242	{ .compatible = "bosch,d_can", .data = &d_can_drvdata },
0f4da3a8	243	{ .compatible = "ti,dra7-d_can", .data = &dra7_dcan_drvdata },
c71d0b31	244	{ .compatible = "ti,am3352-d_can", .data = &am3352_dcan_drvdata },
f2bf2589	245	{ .compatible = "ti,am4372-d_can", .data = &am3352_dcan_drvdata },
2469627d AC	246	{ /* sentinel */ },
2469627d AC	247	};
69c0c5b1	248	MODULE_DEVICE_TABLE(of, c_can_of_table);
2469627d	249
3c8ac0f2	250	static int c_can_plat_probe(struct platform_device *pdev)
881ff67a BS	251	{
	252	int ret;
	253	void __iomem *addr;
	254	struct net_device *dev;
	255	struct c_can_priv *priv;
2469627d	256	const struct of_device_id *match;
3ff9027c	257	struct resource *mem;
b0052b08	258	int irq;
881ff67a	259	struct clk *clk;
15151090	260	const struct c_can_driver_data *drvdata;
3ff9027c	261	struct device_node *np = pdev->dev.of_node;
15151090 RQ	262
	263	match = of_match_device(c_can_of_table, &pdev->dev);
	264	if (match) {
	265	drvdata = match->data;
	266	} else if (pdev->id_entry->driver_data) {
	267	drvdata = (struct c_can_driver_data *)
	268	platform_get_device_id(pdev)->driver_data;
2469627d	269	} else {
15151090	270	return -ENODEV;
2469627d AC	271	}
2469627d AC	272
881ff67a	273	/* get the appropriate clk */
c6bf7e5f	274	clk = devm_clk_get(&pdev->dev, NULL);
881ff67a	275	if (IS_ERR(clk)) {
c6bf7e5f	276	ret = PTR_ERR(clk);
881ff67a BS	277	goto exit;
881ff67a BS	278	}
881ff67a BS	279
881ff67a BS	280	/* get the platform data */
b0052b08	281	irq = platform_get_irq(pdev, 0);
c6bf7e5f	282	if (irq <= 0) {
881ff67a	283	ret = -ENODEV;
c6bf7e5f	284	goto exit;
881ff67a BS	285	}
881ff67a BS	286
c6bf7e5f LP	287	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	288	addr = devm_ioremap_resource(&pdev->dev, mem);
	289	if (IS_ERR(addr)) {
	290	ret = PTR_ERR(addr);
	291	goto exit;
881ff67a BS	292	}
	293
	294	/* allocate the c_can device */
	295	dev = alloc_c_can_dev();
	296	if (!dev) {
	297	ret = -ENOMEM;
c6bf7e5f	298	goto exit;
881ff67a BS	299	}
	300
	301	priv = netdev_priv(dev);
15151090	302	switch (drvdata->id) {
f27b1db9	303	case BOSCH_C_CAN:
69927fcc AC	304	priv->regs = reg_map_c_can;
	305	switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
	306	case IORESOURCE_MEM_32BIT:
	307	priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
	308	priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
ccbc5357 PM	309	priv->read_reg32 = c_can_plat_read_reg32;
ccbc5357 PM	310	priv->write_reg32 = c_can_plat_write_reg32;
69927fcc AC	311	break;
	312	case IORESOURCE_MEM_16BIT:
	313	default:
	314	priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
	315	priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
ccbc5357 PM	316	priv->read_reg32 = c_can_plat_read_reg32;
ccbc5357 PM	317	priv->write_reg32 = c_can_plat_write_reg32;
69927fcc AC	318	break;
	319	}
	320	break;
f27b1db9	321	case BOSCH_D_CAN:
69927fcc AC	322	priv->regs = reg_map_d_can;
	323	priv->can.ctrlmode_supported \|= CAN_CTRLMODE_3_SAMPLES;
	324	priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
	325	priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
ccbc5357 PM	326	priv->read_reg32 = d_can_plat_read_reg32;
ccbc5357 PM	327	priv->write_reg32 = d_can_plat_write_reg32;
52cde85a	328
3ff9027c RQ	329	/* Check if we need custom RAMINIT via syscon. Mostly for TI
3ff9027c RQ	330	* platforms. Only supported with DT boot.
a9c69209	331	*/
3ff9027c RQ	332	if (np && of_property_read_bool(np, "syscon-raminit")) {
	333	u32 id;
	334	struct c_can_raminit *raminit = &priv->raminit_sys;
	335
	336	ret = -EINVAL;
	337	raminit->syscon = syscon_regmap_lookup_by_phandle(np,
	338	"syscon-raminit");
	339	if (IS_ERR(raminit->syscon)) {
	340	/* can fail with -EPROBE_DEFER */
	341	ret = PTR_ERR(raminit->syscon);
	342	free_c_can_dev(dev);
	343	return ret;
	344	}
	345
	346	if (of_property_read_u32_index(np, "syscon-raminit", 1,
	347	&raminit->reg)) {
	348	dev_err(&pdev->dev,
	349	"couldn't get the RAMINIT reg. offset!\n");
	350	goto exit_free_device;
	351	}
	352
	353	if (of_property_read_u32_index(np, "syscon-raminit", 2,
	354	&id)) {
	355	dev_err(&pdev->dev,
	356	"couldn't get the CAN instance ID\n");
	357	goto exit_free_device;
	358	}
	359
	360	if (id >= drvdata->raminit_num) {
	361	dev_err(&pdev->dev,
	362	"Invalid CAN instance ID\n");
	363	goto exit_free_device;
	364	}
	365
	366	raminit->bits = drvdata->raminit_bits[id];
0741bfb9	367	raminit->needs_pulse = drvdata->raminit_pulse;
3ff9027c RQ	368
	369	priv->raminit = c_can_hw_raminit_syscon;
	370	} else {
a9c69209	371	priv->raminit = c_can_hw_raminit;
a9c69209	372	}
69927fcc AC	373	break;
	374	default:
	375	ret = -EINVAL;
	376	goto exit_free_device;
	377	}
881ff67a	378
b0052b08	379	dev->irq = irq;
33f81009	380	priv->base = addr;
4cdd34b2	381	priv->device = &pdev->dev;
881ff67a BS	382	priv->can.clock.freq = clk_get_rate(clk);
881ff67a BS	383	priv->priv = clk;
15151090	384	priv->type = drvdata->id;
881ff67a	385
881ff67a BS	386	platform_set_drvdata(pdev, dev);
	387	SET_NETDEV_DEV(dev, &pdev->dev);
	388
	389	ret = register_c_can_dev(dev);
	390	if (ret) {
	391	dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
	392	KBUILD_MODNAME, ret);
	393	goto exit_free_device;
	394	}
	395
	396	dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
33f81009	397	KBUILD_MODNAME, priv->base, dev->irq);
881ff67a BS	398	return 0;
	399
	400	exit_free_device:
881ff67a	401	free_c_can_dev(dev);
881ff67a	402	exit:
881ff67a BS	403	dev_err(&pdev->dev, "probe failed\n");
	404
	405	return ret;
	406	}
	407
3c8ac0f2	408	static int c_can_plat_remove(struct platform_device *pdev)
881ff67a BS	409	{
881ff67a BS	410	struct net_device *dev = platform_get_drvdata(pdev);
881ff67a BS	411
881ff67a BS	412	unregister_c_can_dev(dev);
881ff67a BS	413
881ff67a BS	414	free_c_can_dev(dev);
881ff67a BS	415
	416	return 0;
	417	}
	418
82120032 AC	419	#ifdef CONFIG_PM
	420	static int c_can_suspend(struct platform_device *pdev, pm_message_t state)
	421	{
	422	int ret;
	423	struct net_device *ndev = platform_get_drvdata(pdev);
	424	struct c_can_priv *priv = netdev_priv(ndev);
	425
	426	if (priv->type != BOSCH_D_CAN) {
	427	dev_warn(&pdev->dev, "Not supported\n");
	428	return 0;
	429	}
	430
	431	if (netif_running(ndev)) {
	432	netif_stop_queue(ndev);
	433	netif_device_detach(ndev);
	434	}
	435
	436	ret = c_can_power_down(ndev);
	437	if (ret) {
	438	netdev_err(ndev, "failed to enter power down mode\n");
	439	return ret;
	440	}
	441
	442	priv->can.state = CAN_STATE_SLEEPING;
	443
	444	return 0;
	445	}
	446
	447	static int c_can_resume(struct platform_device *pdev)
	448	{
	449	int ret;
	450	struct net_device *ndev = platform_get_drvdata(pdev);
	451	struct c_can_priv *priv = netdev_priv(ndev);
	452
	453	if (priv->type != BOSCH_D_CAN) {
	454	dev_warn(&pdev->dev, "Not supported\n");
	455	return 0;
	456	}
	457
	458	ret = c_can_power_up(ndev);
	459	if (ret) {
	460	netdev_err(ndev, "Still in power down mode\n");
	461	return ret;
	462	}
	463
	464	priv->can.state = CAN_STATE_ERROR_ACTIVE;
	465
	466	if (netif_running(ndev)) {
	467	netif_device_attach(ndev);
	468	netif_start_queue(ndev);
	469	}
	470
	471	return 0;
	472	}
	473	#else
	474	#define c_can_suspend NULL
	475	#define c_can_resume NULL
	476	#endif
	477
881ff67a BS	478	static struct platform_driver c_can_plat_driver = {
	479	.driver = {
	480	.name = KBUILD_MODNAME,
b85f75ea	481	.of_match_table = c_can_of_table,
881ff67a BS	482	},
881ff67a BS	483	.probe = c_can_plat_probe,
3c8ac0f2	484	.remove = c_can_plat_remove,
82120032 AC	485	.suspend = c_can_suspend,
82120032 AC	486	.resume = c_can_resume,
69927fcc	487	.id_table = c_can_id_table,
881ff67a BS	488	};
881ff67a BS	489
871d3372	490	module_platform_driver(c_can_plat_driver);
881ff67a BS	491
	492	MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
	493	MODULE_LICENSE("GPL v2");
	494	MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");