bnx2x: Re-arrange the link structures for better alignment
[linux-2.6-block.git] / drivers / net / bnx2x_link.h
CommitLineData
2b144023 1/* Copyright 2008-2009 Broadcom Corporation
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2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#ifndef BNX2X_LINK_H
18#define BNX2X_LINK_H
19
20
21
22/***********************************************************/
23/* Defines */
24/***********************************************************/
25#define DEFAULT_PHY_DEV_ADDR 3
26
27
28
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29#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
30#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
31#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
32#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
33#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
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34
35#define SPEED_AUTO_NEG 0
36#define SPEED_12000 12000
37#define SPEED_12500 12500
38#define SPEED_13000 13000
39#define SPEED_15000 15000
40#define SPEED_16000 16000
41
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42#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
43#define SFP_EEPROM_VENDOR_NAME_SIZE 16
44#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
45#define SFP_EEPROM_VENDOR_OUI_SIZE 3
46#define SFP_EEPROM_PART_NO_ADDR 0x28
47#define SFP_EEPROM_PART_NO_SIZE 16
48#define PWR_FLT_ERR_MSG_LEN 250
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49/***********************************************************/
50/* Structs */
51/***********************************************************/
52/* Inputs parameters to the CLC */
53struct link_params {
54
55 u8 port;
56
57 /* Default / User Configuration */
58 u8 loopback_mode;
59#define LOOPBACK_NONE 0
60#define LOOPBACK_EMAC 1
61#define LOOPBACK_BMAC 2
62#define LOOPBACK_XGXS_10 3
63#define LOOPBACK_EXT_PHY 4
6bbca910 64#define LOOPBACK_EXT 5
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65
66 u16 req_duplex;
67 u16 req_flow_ctrl;
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68 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
69 req_flow_ctrl is set to AUTO */
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70 u16 req_line_speed; /* Also determine AutoNeg */
71
72 /* Device parameters */
73 u8 mac_addr[6];
8c99e7b0 74
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75 /* shmem parameters */
76 u32 shmem_base;
77 u32 speed_cap_mask;
78 u32 switch_cfg;
79#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
80#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
81#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
82
83 u16 hw_led_mode; /* part of the hw_config read from the shmem */
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84
85 /* phy_addr populated by the phy_init function */
86 u8 phy_addr;
87 /*u8 reserved1;*/
88
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89 u32 lane_config;
90 u32 ext_phy_config;
91#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
92 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
93#define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
94 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
95 /* Phy register parameter */
96 u32 chip_id;
97
c2c8b03e 98 u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
c2c8b03e 99 u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
1ef70b9c 100
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101 u32 feature_config_flags;
102#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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103#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
104#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
1ef70b9c 105
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106 /* Device pointer passed to all callback functions */
107 struct bnx2x *bp;
108};
109
110/* Output parameters */
111struct link_vars {
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112 u8 phy_flags;
113
114 u8 mac_type;
115#define MAC_TYPE_NONE 0
116#define MAC_TYPE_EMAC 1
117#define MAC_TYPE_BMAC 2
118
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119 u8 phy_link_up; /* internal phy link indication */
120 u8 link_up;
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121
122 u16 line_speed;
ea4e040a 123 u16 duplex;
1ef70b9c 124
ea4e040a 125 u16 flow_ctrl;
1ef70b9c 126 u16 ieee_fc;
ea4e040a 127
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128 u32 autoneg;
129#define AUTO_NEG_DISABLED 0x0
130#define AUTO_NEG_ENABLED 0x1
131#define AUTO_NEG_COMPLETE 0x2
1ef70b9c 132#define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
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133
134 /* The same definitions as the shmem parameter */
135 u32 link_status;
136};
137
138/***********************************************************/
139/* Functions */
140/***********************************************************/
141
142/* Initialize the phy */
143u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
144
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145/* Reset the link. Should be called when driver or interface goes down
146 Before calling phy firmware upgrade, the reset_ext_phy should be set
147 to 0 */
148u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
149 u8 reset_ext_phy);
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150
151/* bnx2x_link_update should be called upon link interrupt */
152u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
153
154/* use the following cl45 functions to read/write from external_phy
155 In order to use it to read/write internal phy registers, use
156 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
157 Use ext_phy_type of 0 in case of cl22 over cl45
158 the register */
159u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
160 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val);
161
162u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
163 u8 phy_addr, u8 devad, u16 reg, u16 val);
164
165/* Reads the link_status from the shmem,
33471629 166 and update the link vars accordingly */
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167void bnx2x_link_status_update(struct link_params *input,
168 struct link_vars *output);
169/* returns string representing the fw_version of the external phy */
170u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
171 u8 *version, u16 len);
172
173/* Set/Unset the led
174 Basically, the CLC takes care of the led for the link, but in case one needs
33471629 175 to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
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176 blink the led, and LED_MODE_OFF to set the led off.*/
177u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
178 u16 hw_led_mode, u32 chip_id);
179#define LED_MODE_OFF 0
180#define LED_MODE_OPER 2
181
182u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
183
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184/* bnx2x_handle_module_detect_int should be called upon module detection
185 interrupt */
186void bnx2x_handle_module_detect_int(struct link_params *params);
187
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188/* Get the actual link status. In case it returns 0, link is up,
189 otherwise link is down*/
190u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
191
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192/* One-time initialization for external phy after power up */
193u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base);
ea4e040a 194
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195/* Reset the external PHY using GPIO */
196void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
197
198void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr);
356e2385 199
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200u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
201 u8 byte_cnt, u8 *o_buf);
202
ea4e040a 203#endif /* BNX2X_LINK_H */