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2b144023 | 1 | /* Copyright 2008-2009 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef BNX2X_LINK_H | |
18 | #define BNX2X_LINK_H | |
19 | ||
20 | ||
21 | ||
22 | /***********************************************************/ | |
23 | /* Defines */ | |
24 | /***********************************************************/ | |
25 | #define DEFAULT_PHY_DEV_ADDR 3 | |
26 | ||
27 | ||
28 | ||
c0700f90 DM |
29 | #define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO |
30 | #define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX | |
31 | #define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX | |
32 | #define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH | |
33 | #define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE | |
ea4e040a YR |
34 | |
35 | #define SPEED_AUTO_NEG 0 | |
36 | #define SPEED_12000 12000 | |
37 | #define SPEED_12500 12500 | |
38 | #define SPEED_13000 13000 | |
39 | #define SPEED_15000 15000 | |
40 | #define SPEED_16000 16000 | |
41 | ||
42 | ||
43 | /***********************************************************/ | |
44 | /* Structs */ | |
45 | /***********************************************************/ | |
46 | /* Inputs parameters to the CLC */ | |
47 | struct link_params { | |
48 | ||
49 | u8 port; | |
50 | ||
51 | /* Default / User Configuration */ | |
52 | u8 loopback_mode; | |
53 | #define LOOPBACK_NONE 0 | |
54 | #define LOOPBACK_EMAC 1 | |
55 | #define LOOPBACK_BMAC 2 | |
56 | #define LOOPBACK_XGXS_10 3 | |
57 | #define LOOPBACK_EXT_PHY 4 | |
6bbca910 | 58 | #define LOOPBACK_EXT 5 |
ea4e040a YR |
59 | |
60 | u16 req_duplex; | |
61 | u16 req_flow_ctrl; | |
8c99e7b0 YR |
62 | u16 req_fc_auto_adv; /* Should be set to TX / BOTH when |
63 | req_flow_ctrl is set to AUTO */ | |
ea4e040a YR |
64 | u16 req_line_speed; /* Also determine AutoNeg */ |
65 | ||
66 | /* Device parameters */ | |
67 | u8 mac_addr[6]; | |
8c99e7b0 | 68 | |
ea4e040a YR |
69 | /* shmem parameters */ |
70 | u32 shmem_base; | |
71 | u32 speed_cap_mask; | |
72 | u32 switch_cfg; | |
73 | #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH | |
74 | #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH | |
75 | #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT | |
76 | ||
77 | u16 hw_led_mode; /* part of the hw_config read from the shmem */ | |
ea4e040a YR |
78 | u32 lane_config; |
79 | u32 ext_phy_config; | |
80 | #define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \ | |
81 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) | |
82 | #define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \ | |
83 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) | |
84 | /* Phy register parameter */ | |
85 | u32 chip_id; | |
86 | ||
87 | /* phy_addr populated by the CLC */ | |
88 | u8 phy_addr; | |
c2c8b03e EG |
89 | u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */ |
90 | ||
91 | u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */ | |
589abe3a EG |
92 | u32 feature_config_flags; |
93 | #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) | |
94 | #define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0) | |
ea4e040a YR |
95 | /* Device pointer passed to all callback functions */ |
96 | struct bnx2x *bp; | |
97 | }; | |
98 | ||
99 | /* Output parameters */ | |
100 | struct link_vars { | |
101 | u8 phy_link_up; /* internal phy link indication */ | |
102 | u8 link_up; | |
103 | u16 duplex; | |
104 | u16 flow_ctrl; | |
105 | u32 ieee_fc; | |
106 | u8 mac_type; | |
107 | ||
108 | #define MAC_TYPE_NONE 0 | |
109 | #define MAC_TYPE_EMAC 1 | |
110 | #define MAC_TYPE_BMAC 2 | |
111 | u16 line_speed; | |
112 | u32 autoneg; | |
113 | #define AUTO_NEG_DISABLED 0x0 | |
114 | #define AUTO_NEG_ENABLED 0x1 | |
115 | #define AUTO_NEG_COMPLETE 0x2 | |
116 | #define AUTO_NEG_PARALLEL_DETECTION_USED 0x3 | |
117 | ||
118 | u8 phy_flags; | |
119 | ||
120 | /* The same definitions as the shmem parameter */ | |
121 | u32 link_status; | |
122 | }; | |
123 | ||
124 | /***********************************************************/ | |
125 | /* Functions */ | |
126 | /***********************************************************/ | |
127 | ||
128 | /* Initialize the phy */ | |
129 | u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output); | |
130 | ||
589abe3a EG |
131 | /* Reset the link. Should be called when driver or interface goes down |
132 | Before calling phy firmware upgrade, the reset_ext_phy should be set | |
133 | to 0 */ | |
134 | u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, | |
135 | u8 reset_ext_phy); | |
ea4e040a YR |
136 | |
137 | /* bnx2x_link_update should be called upon link interrupt */ | |
138 | u8 bnx2x_link_update(struct link_params *input, struct link_vars *output); | |
139 | ||
140 | /* use the following cl45 functions to read/write from external_phy | |
141 | In order to use it to read/write internal phy registers, use | |
142 | DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as | |
143 | Use ext_phy_type of 0 in case of cl22 over cl45 | |
144 | the register */ | |
145 | u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type, | |
146 | u8 phy_addr, u8 devad, u16 reg, u16 *ret_val); | |
147 | ||
148 | u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type, | |
149 | u8 phy_addr, u8 devad, u16 reg, u16 val); | |
150 | ||
151 | /* Reads the link_status from the shmem, | |
33471629 | 152 | and update the link vars accordingly */ |
ea4e040a YR |
153 | void bnx2x_link_status_update(struct link_params *input, |
154 | struct link_vars *output); | |
155 | /* returns string representing the fw_version of the external phy */ | |
156 | u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, | |
157 | u8 *version, u16 len); | |
158 | ||
159 | /* Set/Unset the led | |
160 | Basically, the CLC takes care of the led for the link, but in case one needs | |
33471629 | 161 | to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to |
ea4e040a YR |
162 | blink the led, and LED_MODE_OFF to set the led off.*/ |
163 | u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed, | |
164 | u16 hw_led_mode, u32 chip_id); | |
165 | #define LED_MODE_OFF 0 | |
166 | #define LED_MODE_OPER 2 | |
167 | ||
168 | u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value); | |
169 | ||
170 | u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config, | |
171 | u8 driver_loaded, char data[], u32 size); | |
589abe3a EG |
172 | /* bnx2x_handle_module_detect_int should be called upon module detection |
173 | interrupt */ | |
174 | void bnx2x_handle_module_detect_int(struct link_params *params); | |
175 | ||
ea4e040a YR |
176 | /* Get the actual link status. In case it returns 0, link is up, |
177 | otherwise link is down*/ | |
178 | u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars); | |
179 | ||
6bbca910 YR |
180 | /* One-time initialization for external phy after power up */ |
181 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base); | |
ea4e040a | 182 | |
356e2385 | 183 | |
ea4e040a | 184 | #endif /* BNX2X_LINK_H */ |