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bnx2x: get_ext_phy_fw_version returns NULL if not applicable
[linux-block.git] / drivers / net / bnx2x_link.c
CommitLineData
d05c26ce 1/* Copyright 2008-2009 Broadcom Corporation
ea4e040a
YR		 2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/pci.h>
20#include <linux/netdevice.h>
21#include <linux/delay.h>
22#include <linux/ethtool.h>
23#include <linux/mutex.h>
ea4e040a 24
ea4e040a
YR		 25#include "bnx2x.h"
26
27/********************************************************/
3196a88a 28#define ETH_HLEN 14
ea4e040a
YR		 29#define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30#define ETH_MIN_PACKET_SIZE 60
31#define ETH_MAX_PACKET_SIZE 1500
32#define ETH_MAX_JUMBO_PACKET_SIZE 9600
33#define MDIO_ACCESS_TIMEOUT 1000
34#define BMAC_CONTROL_RX_ENABLE 2
ea4e040a
YR		 35
36/***********************************************************/
3196a88a 37/* Shortcut definitions */
ea4e040a
YR		 38/***********************************************************/
39
2f904460
EG		 40#define NIG_LATCH_BC_ENABLE_MI_INT 0
41
42#define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
ea4e040a
YR		 44#define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46#define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50#define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52#define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54#define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56#define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58#define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
60
61#define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
64
65#define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
71
72#define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
77
78#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
3196a88a
EG		 80#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81#define AUTONEG_PARALLEL \
ea4e040a 82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
3196a88a 83#define AUTONEG_SGMII_FIBER_AUTODET \
ea4e040a 84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
3196a88a 85#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
ea4e040a
YR		 86
87#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91#define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99#define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101#define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103#define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110#define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
112
113#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
136
137#define PHY_XGXS_FLAG 0x1
138#define PHY_SGMII_FLAG 0x2
139#define PHY_SERDES_FLAG 0x4
140
589abe3a
EG		 141/* */
142#define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
145
4d295db0
EG		 146
147#define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
151
589abe3a
EG		 152#define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
4d295db0 155
589abe3a
EG		 156#define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158#define SFP_EEPROM_OPTIONS_SIZE 2
159
4d295db0
EG		 160#define EDC_MODE_LINEAR 0x0022
161#define EDC_MODE_LIMITING 0x0044
162#define EDC_MODE_PASSIVE_DAC 0x0055
163
164
589abe3a 165
ea4e040a
YR		 166/**********************************************************/
167/* INTERFACE */
168/**********************************************************/
169#define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
173 _val)
174
175#define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
179 _val)
180
c1b73990 181static void bnx2x_set_serdes_access(struct link_params *params)
ea4e040a
YR		 182{
183 struct bnx2x *bp = params->bp;
c1b73990
EG		 184 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
185 /* Set Clause 22 */
186 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
187 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
188 udelay(500);
189 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
190 udelay(500);
191 /* Set Clause 45 */
192 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
193}
194static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
195{
196 struct bnx2x *bp = params->bp;
197 if (phy_flags & PHY_XGXS_FLAG) {
198 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
199 params->port*0x18, 0);
200 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
201 DEFAULT_PHY_DEV_ADDR);
202 } else {
203 bnx2x_set_serdes_access(params);
204
205 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
206 params->port*0x10,
207 DEFAULT_PHY_DEV_ADDR);
208 }
ea4e040a
YR		 209}
210
211static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
212{
213 u32 val = REG_RD(bp, reg);
214
215 val |= bits;
216 REG_WR(bp, reg, val);
217 return val;
218}
219
220static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
221{
222 u32 val = REG_RD(bp, reg);
223
224 val &= ~bits;
225 REG_WR(bp, reg, val);
226 return val;
227}
228
229static void bnx2x_emac_init(struct link_params *params,
230 struct link_vars *vars)
231{
232 /* reset and unreset the emac core */
233 struct bnx2x *bp = params->bp;
234 u8 port = params->port;
235 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
236 u32 val;
237 u16 timeout;
238
239 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
241 udelay(5);
242 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
243 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
244
245 /* init emac - use read-modify-write */
246 /* self clear reset */
247 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 248 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
ea4e040a
YR		 249
250 timeout = 200;
3196a88a 251 do {
ea4e040a
YR		 252 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
253 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
254 if (!timeout) {
255 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
256 return;
257 }
258 timeout--;
3196a88a 259 } while (val & EMAC_MODE_RESET);
ea4e040a
YR		 260
261 /* Set mac address */
262 val = ((params->mac_addr[0] << 8) |
263 params->mac_addr[1]);
3196a88a 264 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
ea4e040a
YR		 265
266 val = ((params->mac_addr[2] << 24) |
267 (params->mac_addr[3] << 16) |
268 (params->mac_addr[4] << 8) |
269 params->mac_addr[5]);
3196a88a 270 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
ea4e040a
YR		 271}
272
273static u8 bnx2x_emac_enable(struct link_params *params,
274 struct link_vars *vars, u8 lb)
275{
276 struct bnx2x *bp = params->bp;
277 u8 port = params->port;
278 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
279 u32 val;
280
281 DP(NETIF_MSG_LINK, "enabling EMAC\n");
282
283 /* enable emac and not bmac */
284 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
285
286 /* for paladium */
287 if (CHIP_REV_IS_EMUL(bp)) {
288 /* Use lane 1 (of lanes 0-3) */
289 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
290 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
291 port*4, 1);
292 }
293 /* for fpga */
294 else
295
296 if (CHIP_REV_IS_FPGA(bp)) {
297 /* Use lane 1 (of lanes 0-3) */
298 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
299
300 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
301 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
302 0);
303 } else
304 /* ASIC */
305 if (vars->phy_flags & PHY_XGXS_FLAG) {
306 u32 ser_lane = ((params->lane_config &
307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
309
310 DP(NETIF_MSG_LINK, "XGXS\n");
311 /* select the master lanes (out of 0-3) */
312 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
313 port*4, ser_lane);
314 /* select XGXS */
315 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
316 port*4, 1);
317
318 } else { /* SerDes */
319 DP(NETIF_MSG_LINK, "SerDes\n");
320 /* select SerDes */
321 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
322 port*4, 0);
323 }
324
811a2f2d
EG		 325 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
326 EMAC_RX_MODE_RESET);
327 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
328 EMAC_TX_MODE_RESET);
ea4e040a
YR		 329
330 if (CHIP_REV_IS_SLOW(bp)) {
331 /* config GMII mode */
332 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
3196a88a 333 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
ea4e040a
YR		 334 (val | EMAC_MODE_PORT_GMII));
335 } else { /* ASIC */
336 /* pause enable/disable */
337 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
338 EMAC_RX_MODE_FLOW_EN);
c0700f90 339 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 340 bnx2x_bits_en(bp, emac_base +
341 EMAC_REG_EMAC_RX_MODE,
342 EMAC_RX_MODE_FLOW_EN);
343
344 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 345 (EMAC_TX_MODE_EXT_PAUSE_EN |
346 EMAC_TX_MODE_FLOW_EN));
c0700f90 347 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 348 bnx2x_bits_en(bp, emac_base +
349 EMAC_REG_EMAC_TX_MODE,
8c99e7b0
YR		 350 (EMAC_TX_MODE_EXT_PAUSE_EN |
351 EMAC_TX_MODE_FLOW_EN));
ea4e040a
YR		 352 }
353
354 /* KEEP_VLAN_TAG, promiscuous */
355 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
356 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
3196a88a 357 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
ea4e040a
YR		 358
359 /* Set Loopback */
360 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
361 if (lb)
362 val |= 0x810;
363 else
364 val &= ~0x810;
3196a88a 365 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
ea4e040a 366
6c55c3cd
EG		 367 /* enable emac */
368 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
369
ea4e040a 370 /* enable emac for jumbo packets */
3196a88a 371 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
ea4e040a
YR		 372 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
373 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
374
375 /* strip CRC */
376 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
377
378 /* disable the NIG in/out to the bmac */
379 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
380 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
381 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
382
383 /* enable the NIG in/out to the emac */
384 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
385 val = 0;
c0700f90 386 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 387 val = 1;
388
389 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
390 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
391
392 if (CHIP_REV_IS_EMUL(bp)) {
393 /* take the BigMac out of reset */
394 REG_WR(bp,
395 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
397
398 /* enable access for bmac registers */
399 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
400 }
401
402 vars->mac_type = MAC_TYPE_EMAC;
403 return 0;
404}
405
406
407
408static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
409 u8 is_lb)
410{
411 struct bnx2x *bp = params->bp;
412 u8 port = params->port;
413 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
414 NIG_REG_INGRESS_BMAC0_MEM;
415 u32 wb_data[2];
416 u32 val;
417
418 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
419 /* reset and unreset the BigMac */
420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
421 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
422 msleep(1);
423
424 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
425 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
426
427 /* enable access for bmac registers */
428 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
429
430 /* XGXS control */
431 wb_data[0] = 0x3c;
432 wb_data[1] = 0;
433 REG_WR_DMAE(bp, bmac_addr +
434 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
435 wb_data, 2);
436
437 /* tx MAC SA */
438 wb_data[0] = ((params->mac_addr[2] << 24) |
439 (params->mac_addr[3] << 16) |
440 (params->mac_addr[4] << 8) |
441 params->mac_addr[5]);
442 wb_data[1] = ((params->mac_addr[0] << 8) |
443 params->mac_addr[1]);
444 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
445 wb_data, 2);
446
447 /* tx control */
448 val = 0xc0;
c0700f90 449 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 450 val |= 0x800000;
451 wb_data[0] = val;
452 wb_data[1] = 0;
453 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
454 wb_data, 2);
455
456 /* mac control */
457 val = 0x3;
458 if (is_lb) {
459 val |= 0x4;
460 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
461 }
462 wb_data[0] = val;
463 wb_data[1] = 0;
464 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
465 wb_data, 2);
466
467
468 /* set rx mtu */
469 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
470 wb_data[1] = 0;
471 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
472 wb_data, 2);
473
474 /* rx control set to don't strip crc */
475 val = 0x14;
c0700f90 476 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
ea4e040a
YR		 477 val |= 0x20;
478 wb_data[0] = val;
479 wb_data[1] = 0;
480 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
481 wb_data, 2);
482
483 /* set tx mtu */
484 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
485 wb_data[1] = 0;
486 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
487 wb_data, 2);
488
489 /* set cnt max size */
490 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
491 wb_data[1] = 0;
492 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
493 wb_data, 2);
494
495 /* configure safc */
496 wb_data[0] = 0x1000200;
497 wb_data[1] = 0;
498 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
499 wb_data, 2);
500 /* fix for emulation */
501 if (CHIP_REV_IS_EMUL(bp)) {
502 wb_data[0] = 0xf000;
503 wb_data[1] = 0;
504 REG_WR_DMAE(bp,
505 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
506 wb_data, 2);
507 }
508
509 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
510 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
511 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
512 val = 0;
c0700f90 513 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
ea4e040a
YR		 514 val = 1;
515 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
516 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
517 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
518 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
519 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
520 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
521
522 vars->mac_type = MAC_TYPE_BMAC;
523 return 0;
524}
525
526static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
527{
528 struct bnx2x *bp = params->bp;
529 u32 val;
530
531 if (phy_flags & PHY_XGXS_FLAG) {
532 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
533 val = XGXS_RESET_BITS;
534
535 } else { /* SerDes */
536 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
537 val = SERDES_RESET_BITS;
538 }
539
540 val = val << (params->port*16);
541
542 /* reset and unreset the SerDes/XGXS */
543 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
544 val);
545 udelay(500);
546 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
547 val);
c1b73990 548 bnx2x_set_phy_mdio(params, phy_flags);
ea4e040a
YR		 549}
550
551void bnx2x_link_status_update(struct link_params *params,
552 struct link_vars *vars)
553{
554 struct bnx2x *bp = params->bp;
555 u8 link_10g;
556 u8 port = params->port;
557
558 if (params->switch_cfg == SWITCH_CFG_1G)
559 vars->phy_flags = PHY_SERDES_FLAG;
560 else
561 vars->phy_flags = PHY_XGXS_FLAG;
562 vars->link_status = REG_RD(bp, params->shmem_base +
563 offsetof(struct shmem_region,
564 port_mb[port].link_status));
565
566 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
567
568 if (vars->link_up) {
569 DP(NETIF_MSG_LINK, "phy link up\n");
570
571 vars->phy_link_up = 1;
572 vars->duplex = DUPLEX_FULL;
573 switch (vars->link_status &
574 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
575 case LINK_10THD:
576 vars->duplex = DUPLEX_HALF;
577 /* fall thru */
578 case LINK_10TFD:
579 vars->line_speed = SPEED_10;
580 break;
581
582 case LINK_100TXHD:
583 vars->duplex = DUPLEX_HALF;
584 /* fall thru */
585 case LINK_100T4:
586 case LINK_100TXFD:
587 vars->line_speed = SPEED_100;
588 break;
589
590 case LINK_1000THD:
591 vars->duplex = DUPLEX_HALF;
592 /* fall thru */
593 case LINK_1000TFD:
594 vars->line_speed = SPEED_1000;
595 break;
596
597 case LINK_2500THD:
598 vars->duplex = DUPLEX_HALF;
599 /* fall thru */
600 case LINK_2500TFD:
601 vars->line_speed = SPEED_2500;
602 break;
603
604 case LINK_10GTFD:
605 vars->line_speed = SPEED_10000;
606 break;
607
608 case LINK_12GTFD:
609 vars->line_speed = SPEED_12000;
610 break;
611
612 case LINK_12_5GTFD:
613 vars->line_speed = SPEED_12500;
614 break;
615
616 case LINK_13GTFD:
617 vars->line_speed = SPEED_13000;
618 break;
619
620 case LINK_15GTFD:
621 vars->line_speed = SPEED_15000;
622 break;
623
624 case LINK_16GTFD:
625 vars->line_speed = SPEED_16000;
626 break;
627
628 default:
629 break;
630 }
631
632 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
c0700f90 633 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
ea4e040a 634 else
c0700f90 635 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 636
637 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
c0700f90 638 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
ea4e040a 639 else
c0700f90 640 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 641
642 if (vars->phy_flags & PHY_XGXS_FLAG) {
8c99e7b0
YR		 643 if (vars->line_speed &&
644 ((vars->line_speed == SPEED_10) ||
645 (vars->line_speed == SPEED_100))) {
ea4e040a
YR		 646 vars->phy_flags |= PHY_SGMII_FLAG;
647 } else {
648 vars->phy_flags &= ~PHY_SGMII_FLAG;
649 }
650 }
651
652 /* anything 10 and over uses the bmac */
653 link_10g = ((vars->line_speed == SPEED_10000) ||
654 (vars->line_speed == SPEED_12000) ||
655 (vars->line_speed == SPEED_12500) ||
656 (vars->line_speed == SPEED_13000) ||
657 (vars->line_speed == SPEED_15000) ||
658 (vars->line_speed == SPEED_16000));
659 if (link_10g)
660 vars->mac_type = MAC_TYPE_BMAC;
661 else
662 vars->mac_type = MAC_TYPE_EMAC;
663
664 } else { /* link down */
665 DP(NETIF_MSG_LINK, "phy link down\n");
666
667 vars->phy_link_up = 0;
668
669 vars->line_speed = 0;
670 vars->duplex = DUPLEX_FULL;
c0700f90 671 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 672
673 /* indicate no mac active */
674 vars->mac_type = MAC_TYPE_NONE;
675 }
676
677 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
678 vars->link_status, vars->phy_link_up);
679 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
680 vars->line_speed, vars->duplex, vars->flow_ctrl);
681}
682
683static void bnx2x_update_mng(struct link_params *params, u32 link_status)
684{
685 struct bnx2x *bp = params->bp;
686 REG_WR(bp, params->shmem_base +
687 offsetof(struct shmem_region,
688 port_mb[params->port].link_status),
689 link_status);
690}
691
692static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
693{
694 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
695 NIG_REG_INGRESS_BMAC0_MEM;
696 u32 wb_data[2];
3196a88a 697 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
ea4e040a
YR		 698
699 /* Only if the bmac is out of reset */
700 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
701 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
702 nig_bmac_enable) {
703
704 /* Clear Rx Enable bit in BMAC_CONTROL register */
705 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
706 wb_data, 2);
707 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
708 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
709 wb_data, 2);
710
711 msleep(1);
712 }
713}
714
715static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
716 u32 line_speed)
717{
718 struct bnx2x *bp = params->bp;
719 u8 port = params->port;
720 u32 init_crd, crd;
721 u32 count = 1000;
ea4e040a
YR		 722
723 /* disable port */
724 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
725
726 /* wait for init credit */
727 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
728 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
729 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
730
731 while ((init_crd != crd) && count) {
732 msleep(5);
733
734 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
735 count--;
736 }
737 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
738 if (init_crd != crd) {
739 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
740 init_crd, crd);
741 return -EINVAL;
742 }
743
c0700f90 744 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
8c99e7b0
YR		 745 line_speed == SPEED_10 ||
746 line_speed == SPEED_100 ||
747 line_speed == SPEED_1000 ||
748 line_speed == SPEED_2500) {
749 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
ea4e040a
YR		 750 /* update threshold */
751 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
752 /* update init credit */
8c99e7b0 753 init_crd = 778; /* (800-18-4) */
ea4e040a
YR		 754
755 } else {
756 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
757 ETH_OVREHEAD)/16;
8c99e7b0 758 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
ea4e040a
YR		 759 /* update threshold */
760 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
761 /* update init credit */
762 switch (line_speed) {
ea4e040a
YR		 763 case SPEED_10000:
764 init_crd = thresh + 553 - 22;
765 break;
766
767 case SPEED_12000:
768 init_crd = thresh + 664 - 22;
769 break;
770
771 case SPEED_13000:
772 init_crd = thresh + 742 - 22;
773 break;
774
775 case SPEED_16000:
776 init_crd = thresh + 778 - 22;
777 break;
778 default:
779 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
780 line_speed);
781 return -EINVAL;
782 break;
783 }
784 }
785 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
786 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
787 line_speed, init_crd);
788
789 /* probe the credit changes */
790 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
791 msleep(5);
792 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
793
794 /* enable port */
795 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
796 return 0;
797}
798
589abe3a 799static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
ea4e040a
YR		 800{
801 u32 emac_base;
802 switch (ext_phy_type) {
803 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
589abe3a 804 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4d295db0 805 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
589abe3a
EG		 806 /* All MDC/MDIO is directed through single EMAC */
807 if (REG_RD(bp, NIG_REG_PORT_SWAP))
808 emac_base = GRCBASE_EMAC0;
809 else
810 emac_base = GRCBASE_EMAC1;
ea4e040a
YR		 811 break;
812 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6378c025 813 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
ea4e040a
YR		 814 break;
815 default:
6378c025 816 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a
YR		 817 break;
818 }
819 return emac_base;
820
821}
822
823u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
824 u8 phy_addr, u8 devad, u16 reg, u16 val)
825{
826 u32 tmp, saved_mode;
827 u8 i, rc = 0;
589abe3a 828 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 829
830 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
831 * (a value of 49==0x31) and make sure that the AUTO poll is off
832 */
589abe3a 833
ea4e040a
YR		 834 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
835 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
836 EMAC_MDIO_MODE_CLOCK_CNT);
837 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
838 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
839 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
840 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
841 udelay(40);
842
843 /* address */
844
845 tmp = ((phy_addr << 21) | (devad << 16) | reg |
846 EMAC_MDIO_COMM_COMMAND_ADDRESS |
847 EMAC_MDIO_COMM_START_BUSY);
848 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
849
850 for (i = 0; i < 50; i++) {
851 udelay(10);
852
853 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
854 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
855 udelay(5);
856 break;
857 }
858 }
859 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
860 DP(NETIF_MSG_LINK, "write phy register failed\n");
861 rc = -EFAULT;
862 } else {
863 /* data */
864 tmp = ((phy_addr << 21) | (devad << 16) | val |
865 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
866 EMAC_MDIO_COMM_START_BUSY);
867 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
868
869 for (i = 0; i < 50; i++) {
870 udelay(10);
871
872 tmp = REG_RD(bp, mdio_ctrl +
873 EMAC_REG_EMAC_MDIO_COMM);
874 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
875 udelay(5);
876 break;
877 }
878 }
879 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
880 DP(NETIF_MSG_LINK, "write phy register failed\n");
881 rc = -EFAULT;
882 }
883 }
884
885 /* Restore the saved mode */
886 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
887
888 return rc;
889}
890
891u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
892 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
893{
894 u32 val, saved_mode;
895 u16 i;
896 u8 rc = 0;
897
589abe3a 898 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
ea4e040a
YR		 899 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
900 * (a value of 49==0x31) and make sure that the AUTO poll is off
901 */
589abe3a 902
ea4e040a
YR		 903 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
904 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
905 EMAC_MDIO_MODE_CLOCK_CNT));
906 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
907 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
908 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
909 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
910 udelay(40);
911
912 /* address */
913 val = ((phy_addr << 21) | (devad << 16) | reg |
914 EMAC_MDIO_COMM_COMMAND_ADDRESS |
915 EMAC_MDIO_COMM_START_BUSY);
916 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
917
918 for (i = 0; i < 50; i++) {
919 udelay(10);
920
921 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
922 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
923 udelay(5);
924 break;
925 }
926 }
927 if (val & EMAC_MDIO_COMM_START_BUSY) {
928 DP(NETIF_MSG_LINK, "read phy register failed\n");
929
930 *ret_val = 0;
931 rc = -EFAULT;
932
933 } else {
934 /* data */
935 val = ((phy_addr << 21) | (devad << 16) |
936 EMAC_MDIO_COMM_COMMAND_READ_45 |
937 EMAC_MDIO_COMM_START_BUSY);
938 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
939
940 for (i = 0; i < 50; i++) {
941 udelay(10);
942
943 val = REG_RD(bp, mdio_ctrl +
944 EMAC_REG_EMAC_MDIO_COMM);
945 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
946 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
947 break;
948 }
949 }
950 if (val & EMAC_MDIO_COMM_START_BUSY) {
951 DP(NETIF_MSG_LINK, "read phy register failed\n");
952
953 *ret_val = 0;
954 rc = -EFAULT;
955 }
956 }
957
958 /* Restore the saved mode */
959 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
960
961 return rc;
962}
963
964static void bnx2x_set_aer_mmd(struct link_params *params,
965 struct link_vars *vars)
966{
967 struct bnx2x *bp = params->bp;
968 u32 ser_lane;
969 u16 offset;
970
971 ser_lane = ((params->lane_config &
972 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
973 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
974
975 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
976 (params->phy_addr + ser_lane) : 0;
977
978 CL45_WR_OVER_CL22(bp, params->port,
979 params->phy_addr,
980 MDIO_REG_BANK_AER_BLOCK,
981 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
982}
983
984static void bnx2x_set_master_ln(struct link_params *params)
985{
986 struct bnx2x *bp = params->bp;
987 u16 new_master_ln, ser_lane;
988 ser_lane = ((params->lane_config &
989 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
990 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
991
992 /* set the master_ln for AN */
993 CL45_RD_OVER_CL22(bp, params->port,
994 params->phy_addr,
995 MDIO_REG_BANK_XGXS_BLOCK2,
996 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
997 &new_master_ln);
998
999 CL45_WR_OVER_CL22(bp, params->port,
1000 params->phy_addr,
1001 MDIO_REG_BANK_XGXS_BLOCK2 ,
1002 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1003 (new_master_ln | ser_lane));
1004}
1005
1006static u8 bnx2x_reset_unicore(struct link_params *params)
1007{
1008 struct bnx2x *bp = params->bp;
1009 u16 mii_control;
1010 u16 i;
1011
1012 CL45_RD_OVER_CL22(bp, params->port,
1013 params->phy_addr,
1014 MDIO_REG_BANK_COMBO_IEEE0,
1015 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1016
1017 /* reset the unicore */
1018 CL45_WR_OVER_CL22(bp, params->port,
1019 params->phy_addr,
1020 MDIO_REG_BANK_COMBO_IEEE0,
1021 MDIO_COMBO_IEEE0_MII_CONTROL,
1022 (mii_control |
1023 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1024
c1b73990
EG		 1025 bnx2x_set_serdes_access(params);
1026
ea4e040a
YR		 1027 /* wait for the reset to self clear */
1028 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1029 udelay(5);
1030
1031 /* the reset erased the previous bank value */
1032 CL45_RD_OVER_CL22(bp, params->port,
1033 params->phy_addr,
1034 MDIO_REG_BANK_COMBO_IEEE0,
1035 MDIO_COMBO_IEEE0_MII_CONTROL,
1036 &mii_control);
1037
1038 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1039 udelay(5);
1040 return 0;
1041 }
1042 }
1043
1044 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1045 return -EINVAL;
1046
1047}
1048
1049static void bnx2x_set_swap_lanes(struct link_params *params)
1050{
1051 struct bnx2x *bp = params->bp;
1052 /* Each two bits represents a lane number:
1053 No swap is 0123 => 0x1b no need to enable the swap */
1054 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1055
1056 ser_lane = ((params->lane_config &
1057 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1059 rx_lane_swap = ((params->lane_config &
1060 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1061 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1062 tx_lane_swap = ((params->lane_config &
1063 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1064 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1065
1066 if (rx_lane_swap != 0x1b) {
1067 CL45_WR_OVER_CL22(bp, params->port,
1068 params->phy_addr,
1069 MDIO_REG_BANK_XGXS_BLOCK2,
1070 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1071 (rx_lane_swap |
1072 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1074 } else {
1075 CL45_WR_OVER_CL22(bp, params->port,
1076 params->phy_addr,
1077 MDIO_REG_BANK_XGXS_BLOCK2,
1078 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1079 }
1080
1081 if (tx_lane_swap != 0x1b) {
1082 CL45_WR_OVER_CL22(bp, params->port,
1083 params->phy_addr,
1084 MDIO_REG_BANK_XGXS_BLOCK2,
1085 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1086 (tx_lane_swap |
1087 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1088 } else {
1089 CL45_WR_OVER_CL22(bp, params->port,
1090 params->phy_addr,
1091 MDIO_REG_BANK_XGXS_BLOCK2,
1092 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1093 }
1094}
1095
1096static void bnx2x_set_parallel_detection(struct link_params *params,
3196a88a 1097 u8 phy_flags)
ea4e040a
YR		 1098{
1099 struct bnx2x *bp = params->bp;
1100 u16 control2;
1101
1102 CL45_RD_OVER_CL22(bp, params->port,
1103 params->phy_addr,
1104 MDIO_REG_BANK_SERDES_DIGITAL,
1105 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1106 &control2);
1107
1108
1109 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1110
1111
1112 CL45_WR_OVER_CL22(bp, params->port,
1113 params->phy_addr,
1114 MDIO_REG_BANK_SERDES_DIGITAL,
1115 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1116 control2);
1117
1118 if (phy_flags & PHY_XGXS_FLAG) {
1119 DP(NETIF_MSG_LINK, "XGXS\n");
1120
1121 CL45_WR_OVER_CL22(bp, params->port,
1122 params->phy_addr,
1123 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1124 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1125 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1126
1127 CL45_RD_OVER_CL22(bp, params->port,
1128 params->phy_addr,
1129 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1130 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1131 &control2);
1132
1133
1134 control2 |=
1135 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1136
1137 CL45_WR_OVER_CL22(bp, params->port,
1138 params->phy_addr,
1139 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1140 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1141 control2);
1142
1143 /* Disable parallel detection of HiG */
1144 CL45_WR_OVER_CL22(bp, params->port,
1145 params->phy_addr,
1146 MDIO_REG_BANK_XGXS_BLOCK2,
1147 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1148 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1149 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1150 }
1151}
1152
1153static void bnx2x_set_autoneg(struct link_params *params,
1154 struct link_vars *vars)
1155{
1156 struct bnx2x *bp = params->bp;
1157 u16 reg_val;
1158
1159 /* CL37 Autoneg */
1160
1161 CL45_RD_OVER_CL22(bp, params->port,
1162 params->phy_addr,
1163 MDIO_REG_BANK_COMBO_IEEE0,
1164 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1165
1166 /* CL37 Autoneg Enabled */
8c99e7b0 1167 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1168 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1169 else /* CL37 Autoneg Disabled */
1170 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1171 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1172
1173 CL45_WR_OVER_CL22(bp, params->port,
1174 params->phy_addr,
1175 MDIO_REG_BANK_COMBO_IEEE0,
1176 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1177
1178 /* Enable/Disable Autodetection */
1179
1180 CL45_RD_OVER_CL22(bp, params->port,
1181 params->phy_addr,
1182 MDIO_REG_BANK_SERDES_DIGITAL,
1183 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1184 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
8c99e7b0 1185 if (vars->line_speed == SPEED_AUTO_NEG)
ea4e040a
YR		 1186 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1187 else
1188 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1189
1190 CL45_WR_OVER_CL22(bp, params->port,
1191 params->phy_addr,
1192 MDIO_REG_BANK_SERDES_DIGITAL,
1193 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1194
1195 /* Enable TetonII and BAM autoneg */
1196 CL45_RD_OVER_CL22(bp, params->port,
1197 params->phy_addr,
1198 MDIO_REG_BANK_BAM_NEXT_PAGE,
1199 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1200 &reg_val);
8c99e7b0 1201 if (vars->line_speed == SPEED_AUTO_NEG) {
ea4e040a
YR		 1202 /* Enable BAM aneg Mode and TetonII aneg Mode */
1203 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1204 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1205 } else {
1206 /* TetonII and BAM Autoneg Disabled */
1207 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1209 }
1210 CL45_WR_OVER_CL22(bp, params->port,
1211 params->phy_addr,
1212 MDIO_REG_BANK_BAM_NEXT_PAGE,
1213 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1214 reg_val);
1215
3a36f2ef
EG		 1216 /* CL73 Autoneg Disabled */
1217 reg_val = 0;
ea4e040a 1218
ea4e040a
YR		 1219 CL45_WR_OVER_CL22(bp, params->port,
1220 params->phy_addr,
1221 MDIO_REG_BANK_CL73_IEEEB0,
1222 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1223}
1224
1225/* program SerDes, forced speed */
8c99e7b0
YR		 1226static void bnx2x_program_serdes(struct link_params *params,
1227 struct link_vars *vars)
ea4e040a
YR		 1228{
1229 struct bnx2x *bp = params->bp;
1230 u16 reg_val;
1231
1232 /* program duplex, disable autoneg */
1233
1234 CL45_RD_OVER_CL22(bp, params->port,
1235 params->phy_addr,
1236 MDIO_REG_BANK_COMBO_IEEE0,
1237 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1238 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1239 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
1240 if (params->req_duplex == DUPLEX_FULL)
1241 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1242 CL45_WR_OVER_CL22(bp, params->port,
1243 params->phy_addr,
1244 MDIO_REG_BANK_COMBO_IEEE0,
1245 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1246
1247 /* program speed
1248 - needed only if the speed is greater than 1G (2.5G or 10G) */
8c99e7b0 1249 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a
YR		 1250 params->phy_addr,
1251 MDIO_REG_BANK_SERDES_DIGITAL,
1252 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
8c99e7b0
YR		 1253 /* clearing the speed value before setting the right speed */
1254 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1255
1256 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1257 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1258
1259 if (!((vars->line_speed == SPEED_1000) ||
1260 (vars->line_speed == SPEED_100) ||
1261 (vars->line_speed == SPEED_10))) {
1262
ea4e040a
YR		 1263 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1264 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
8c99e7b0 1265 if (vars->line_speed == SPEED_10000)
ea4e040a
YR		 1266 reg_val |=
1267 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
8c99e7b0 1268 if (vars->line_speed == SPEED_13000)
ea4e040a
YR		 1269 reg_val |=
1270 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
8c99e7b0
YR		 1271 }
1272
1273 CL45_WR_OVER_CL22(bp, params->port,
ea4e040a
YR		 1274 params->phy_addr,
1275 MDIO_REG_BANK_SERDES_DIGITAL,
1276 MDIO_SERDES_DIGITAL_MISC1, reg_val);
8c99e7b0 1277
ea4e040a
YR		 1278}
1279
1280static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1281{
1282 struct bnx2x *bp = params->bp;
1283 u16 val = 0;
1284
1285 /* configure the 48 bits for BAM AN */
1286
1287 /* set extended capabilities */
1288 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1289 val |= MDIO_OVER_1G_UP1_2_5G;
1290 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1291 val |= MDIO_OVER_1G_UP1_10G;
1292 CL45_WR_OVER_CL22(bp, params->port,
1293 params->phy_addr,
1294 MDIO_REG_BANK_OVER_1G,
1295 MDIO_OVER_1G_UP1, val);
1296
1297 CL45_WR_OVER_CL22(bp, params->port,
1298 params->phy_addr,
1299 MDIO_REG_BANK_OVER_1G,
1300 MDIO_OVER_1G_UP3, 0);
1301}
1302
8c99e7b0 1303static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
ea4e040a 1304{
8c99e7b0 1305 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
ea4e040a
YR		 1306 /* resolve pause mode and advertisement
1307 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1308
1309 switch (params->req_flow_ctrl) {
c0700f90
DM		 1310 case BNX2X_FLOW_CTRL_AUTO:
1311 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
8c99e7b0 1312 *ieee_fc |=
ea4e040a
YR		 1313 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1314 } else {
8c99e7b0 1315 *ieee_fc |=
ea4e040a
YR		 1316 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1317 }
1318 break;
c0700f90 1319 case BNX2X_FLOW_CTRL_TX:
8c99e7b0 1320 *ieee_fc |=
ea4e040a
YR		 1321 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1322 break;
1323
c0700f90
DM		 1324 case BNX2X_FLOW_CTRL_RX:
1325 case BNX2X_FLOW_CTRL_BOTH:
8c99e7b0 1326 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
ea4e040a
YR		 1327 break;
1328
c0700f90 1329 case BNX2X_FLOW_CTRL_NONE:
ea4e040a 1330 default:
8c99e7b0 1331 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
ea4e040a
YR		 1332 break;
1333 }
8c99e7b0 1334}
ea4e040a 1335
8c99e7b0
YR		 1336static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1337 u32 ieee_fc)
1338{
1339 struct bnx2x *bp = params->bp;
1340 /* for AN, we are always publishing full duplex */
ea4e040a
YR		 1341
1342 CL45_WR_OVER_CL22(bp, params->port,
1343 params->phy_addr,
1344 MDIO_REG_BANK_COMBO_IEEE0,
8c99e7b0 1345 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
ea4e040a
YR		 1346}
1347
1348static void bnx2x_restart_autoneg(struct link_params *params)
1349{
1350 struct bnx2x *bp = params->bp;
3a36f2ef 1351 u16 mii_control;
ea4e040a 1352 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
3a36f2ef 1353 /* Enable and restart BAM/CL37 aneg */
ea4e040a 1354
3a36f2ef
EG		 1355 CL45_RD_OVER_CL22(bp, params->port,
1356 params->phy_addr,
1357 MDIO_REG_BANK_COMBO_IEEE0,
1358 MDIO_COMBO_IEEE0_MII_CONTROL,
1359 &mii_control);
1360 DP(NETIF_MSG_LINK,
1361 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1362 mii_control);
1363 CL45_WR_OVER_CL22(bp, params->port,
1364 params->phy_addr,
1365 MDIO_REG_BANK_COMBO_IEEE0,
1366 MDIO_COMBO_IEEE0_MII_CONTROL,
1367 (mii_control |
1368 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1369 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
ea4e040a
YR		 1370}
1371
8c99e7b0
YR		 1372static void bnx2x_initialize_sgmii_process(struct link_params *params,
1373 struct link_vars *vars)
ea4e040a
YR		 1374{
1375 struct bnx2x *bp = params->bp;
1376 u16 control1;
1377
1378 /* in SGMII mode, the unicore is always slave */
1379
1380 CL45_RD_OVER_CL22(bp, params->port,
1381 params->phy_addr,
1382 MDIO_REG_BANK_SERDES_DIGITAL,
1383 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1384 &control1);
1385 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1386 /* set sgmii mode (and not fiber) */
1387 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1388 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1389 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1390 CL45_WR_OVER_CL22(bp, params->port,
1391 params->phy_addr,
1392 MDIO_REG_BANK_SERDES_DIGITAL,
1393 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1394 control1);
1395
1396 /* if forced speed */
8c99e7b0 1397 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
ea4e040a
YR		 1398 /* set speed, disable autoneg */
1399 u16 mii_control;
1400
1401 CL45_RD_OVER_CL22(bp, params->port,
1402 params->phy_addr,
1403 MDIO_REG_BANK_COMBO_IEEE0,
1404 MDIO_COMBO_IEEE0_MII_CONTROL,
1405 &mii_control);
1406 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1407 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1408 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1409
8c99e7b0 1410 switch (vars->line_speed) {
ea4e040a
YR		 1411 case SPEED_100:
1412 mii_control |=
1413 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1414 break;
1415 case SPEED_1000:
1416 mii_control |=
1417 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1418 break;
1419 case SPEED_10:
1420 /* there is nothing to set for 10M */
1421 break;
1422 default:
1423 /* invalid speed for SGMII */
8c99e7b0
YR		 1424 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1425 vars->line_speed);
ea4e040a
YR		 1426 break;
1427 }
1428
1429 /* setting the full duplex */
1430 if (params->req_duplex == DUPLEX_FULL)
1431 mii_control |=
1432 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1433 CL45_WR_OVER_CL22(bp, params->port,
1434 params->phy_addr,
1435 MDIO_REG_BANK_COMBO_IEEE0,
1436 MDIO_COMBO_IEEE0_MII_CONTROL,
1437 mii_control);
1438
1439 } else { /* AN mode */
1440 /* enable and restart AN */
1441 bnx2x_restart_autoneg(params);
1442 }
1443}
1444
1445
1446/*
1447 * link management
1448 */
1449
1450static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
8c99e7b0
YR		 1451{ /* LD LP */
1452 switch (pause_result) { /* ASYM P ASYM P */
1453 case 0xb: /* 1 0 1 1 */
c0700f90 1454 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
ea4e040a
YR		 1455 break;
1456
8c99e7b0 1457 case 0xe: /* 1 1 1 0 */
c0700f90 1458 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
ea4e040a
YR		 1459 break;
1460
8c99e7b0
YR		 1461 case 0x5: /* 0 1 0 1 */
1462 case 0x7: /* 0 1 1 1 */
1463 case 0xd: /* 1 1 0 1 */
1464 case 0xf: /* 1 1 1 1 */
c0700f90 1465 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
ea4e040a
YR		 1466 break;
1467
1468 default:
1469 break;
1470 }
1471}
1472
1473static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1474 struct link_vars *vars)
1475{
1476 struct bnx2x *bp = params->bp;
1477 u8 ext_phy_addr;
3196a88a
EG		 1478 u16 ld_pause; /* local */
1479 u16 lp_pause; /* link partner */
ea4e040a
YR		 1480 u16 an_complete; /* AN complete */
1481 u16 pause_result;
1482 u8 ret = 0;
1483 u32 ext_phy_type;
1484 u8 port = params->port;
1485 ext_phy_addr = ((params->ext_phy_config &
1486 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1487 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1488
1489 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1490 /* read twice */
1491
1492 bnx2x_cl45_read(bp, port,
1493 ext_phy_type,
1494 ext_phy_addr,
1495 MDIO_AN_DEVAD,
1496 MDIO_AN_REG_STATUS, &an_complete);
1497 bnx2x_cl45_read(bp, port,
1498 ext_phy_type,
1499 ext_phy_addr,
1500 MDIO_AN_DEVAD,
1501 MDIO_AN_REG_STATUS, &an_complete);
1502
1503 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1504 ret = 1;
1505 bnx2x_cl45_read(bp, port,
1506 ext_phy_type,
1507 ext_phy_addr,
1508 MDIO_AN_DEVAD,
1509 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1510 bnx2x_cl45_read(bp, port,
1511 ext_phy_type,
1512 ext_phy_addr,
1513 MDIO_AN_DEVAD,
1514 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1515 pause_result = (ld_pause &
1516 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1517 pause_result |= (lp_pause &
1518 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1519 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1520 pause_result);
1521 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1522 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
8c99e7b0
YR		 1523 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1524 bnx2x_cl45_read(bp, port,
1525 ext_phy_type,
1526 ext_phy_addr,
1527 MDIO_AN_DEVAD,
1528 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1529
1530 bnx2x_cl45_read(bp, port,
1531 ext_phy_type,
1532 ext_phy_addr,
1533 MDIO_AN_DEVAD,
1534 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1535 pause_result = (ld_pause &
1536 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1537 pause_result |= (lp_pause &
1538 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1539
1540 bnx2x_pause_resolve(vars, pause_result);
1541 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1542 pause_result);
1543 }
ea4e040a
YR		 1544 }
1545 return ret;
1546}
1547
1548
1549static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1550 struct link_vars *vars,
1551 u32 gp_status)
1552{
1553 struct bnx2x *bp = params->bp;
3196a88a
EG		 1554 u16 ld_pause; /* local driver */
1555 u16 lp_pause; /* link partner */
ea4e040a
YR		 1556 u16 pause_result;
1557
c0700f90 1558 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1559
1560 /* resolve from gp_status in case of AN complete and not sgmii */
c0700f90 1561 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ea4e040a
YR		 1562 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1563 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1564 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1565 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1566 CL45_RD_OVER_CL22(bp, params->port,
1567 params->phy_addr,
1568 MDIO_REG_BANK_COMBO_IEEE0,
1569 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1570 &ld_pause);
1571 CL45_RD_OVER_CL22(bp, params->port,
1572 params->phy_addr,
1573 MDIO_REG_BANK_COMBO_IEEE0,
1574 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1575 &lp_pause);
1576 pause_result = (ld_pause &
1577 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1578 pause_result |= (lp_pause &
1579 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1580 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1581 bnx2x_pause_resolve(vars, pause_result);
c0700f90 1582 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
ea4e040a
YR		 1583 (bnx2x_ext_phy_resove_fc(params, vars))) {
1584 return;
1585 } else {
c0700f90 1586 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
8c99e7b0
YR		 1587 vars->flow_ctrl = params->req_fc_auto_adv;
1588 else
1589 vars->flow_ctrl = params->req_flow_ctrl;
ea4e040a
YR		 1590 }
1591 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1592}
1593
1594
1595static u8 bnx2x_link_settings_status(struct link_params *params,
2f904460
EG		 1596 struct link_vars *vars,
1597 u32 gp_status,
1598 u8 ext_phy_link_up)
ea4e040a
YR		 1599{
1600 struct bnx2x *bp = params->bp;
6c55c3cd 1601 u16 new_line_speed;
ea4e040a
YR		 1602 u8 rc = 0;
1603 vars->link_status = 0;
1604
1605 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1606 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1607 gp_status);
1608
1609 vars->phy_link_up = 1;
1610 vars->link_status |= LINK_STATUS_LINK_UP;
1611
1612 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1613 vars->duplex = DUPLEX_FULL;
1614 else
1615 vars->duplex = DUPLEX_HALF;
1616
1617 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1618
1619 switch (gp_status & GP_STATUS_SPEED_MASK) {
1620 case GP_STATUS_10M:
6c55c3cd 1621 new_line_speed = SPEED_10;
ea4e040a
YR		 1622 if (vars->duplex == DUPLEX_FULL)
1623 vars->link_status |= LINK_10TFD;
1624 else
1625 vars->link_status |= LINK_10THD;
1626 break;
1627
1628 case GP_STATUS_100M:
6c55c3cd 1629 new_line_speed = SPEED_100;
ea4e040a
YR		 1630 if (vars->duplex == DUPLEX_FULL)
1631 vars->link_status |= LINK_100TXFD;
1632 else
1633 vars->link_status |= LINK_100TXHD;
1634 break;
1635
1636 case GP_STATUS_1G:
1637 case GP_STATUS_1G_KX:
6c55c3cd 1638 new_line_speed = SPEED_1000;
ea4e040a
YR		 1639 if (vars->duplex == DUPLEX_FULL)
1640 vars->link_status |= LINK_1000TFD;
1641 else
1642 vars->link_status |= LINK_1000THD;
1643 break;
1644
1645 case GP_STATUS_2_5G:
6c55c3cd 1646 new_line_speed = SPEED_2500;
ea4e040a
YR		 1647 if (vars->duplex == DUPLEX_FULL)
1648 vars->link_status |= LINK_2500TFD;
1649 else
1650 vars->link_status |= LINK_2500THD;
1651 break;
1652
1653 case GP_STATUS_5G:
1654 case GP_STATUS_6G:
1655 DP(NETIF_MSG_LINK,
1656 "link speed unsupported gp_status 0x%x\n",
1657 gp_status);
1658 return -EINVAL;
1659 break;
1660 case GP_STATUS_10G_KX4:
1661 case GP_STATUS_10G_HIG:
1662 case GP_STATUS_10G_CX4:
6c55c3cd 1663 new_line_speed = SPEED_10000;
ea4e040a
YR		 1664 vars->link_status |= LINK_10GTFD;
1665 break;
1666
1667 case GP_STATUS_12G_HIG:
6c55c3cd 1668 new_line_speed = SPEED_12000;
ea4e040a
YR		 1669 vars->link_status |= LINK_12GTFD;
1670 break;
1671
1672 case GP_STATUS_12_5G:
6c55c3cd 1673 new_line_speed = SPEED_12500;
ea4e040a
YR		 1674 vars->link_status |= LINK_12_5GTFD;
1675 break;
1676
1677 case GP_STATUS_13G:
6c55c3cd 1678 new_line_speed = SPEED_13000;
ea4e040a
YR		 1679 vars->link_status |= LINK_13GTFD;
1680 break;
1681
1682 case GP_STATUS_15G:
6c55c3cd 1683 new_line_speed = SPEED_15000;
ea4e040a
YR		 1684 vars->link_status |= LINK_15GTFD;
1685 break;
1686
1687 case GP_STATUS_16G:
6c55c3cd 1688 new_line_speed = SPEED_16000;
ea4e040a
YR		 1689 vars->link_status |= LINK_16GTFD;
1690 break;
1691
1692 default:
1693 DP(NETIF_MSG_LINK,
1694 "link speed unsupported gp_status 0x%x\n",
1695 gp_status);
1696 return -EINVAL;
1697 break;
1698 }
1699
6c55c3cd
EG		 1700 /* Upon link speed change set the NIG into drain mode.
1701 Comes to deals with possible FIFO glitch due to clk change
1702 when speed is decreased without link down indicator */
1703 if (new_line_speed != vars->line_speed) {
2f904460
EG		 1704 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1705 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1706 ext_phy_link_up) {
1707 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1708 " different than the external"
1709 " link speed %d\n", new_line_speed,
1710 vars->line_speed);
1711 vars->phy_link_up = 0;
1712 return 0;
1713 }
6c55c3cd
EG		 1714 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1715 + params->port*4, 0);
1716 msleep(1);
1717 }
1718 vars->line_speed = new_line_speed;
ea4e040a
YR		 1719 vars->link_status |= LINK_STATUS_SERDES_LINK;
1720
57963ed9
YR		 1721 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1722 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1723 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1724 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
589abe3a
EG		 1725 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1726 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
2f904460 1727 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
ea4e040a
YR		 1728 vars->autoneg = AUTO_NEG_ENABLED;
1729
1730 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1731 vars->autoneg |= AUTO_NEG_COMPLETE;
1732 vars->link_status |=
1733 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1734 }
1735
1736 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1737 vars->link_status |=
1738 LINK_STATUS_PARALLEL_DETECTION_USED;
1739
1740 }
c0700f90 1741 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
8c99e7b0
YR		 1742 vars->link_status |=
1743 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
ea4e040a 1744
c0700f90 1745 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
8c99e7b0
YR		 1746 vars->link_status |=
1747 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
ea4e040a
YR		 1748
1749 } else { /* link_down */
1750 DP(NETIF_MSG_LINK, "phy link down\n");
1751
1752 vars->phy_link_up = 0;
57963ed9 1753
ea4e040a 1754 vars->duplex = DUPLEX_FULL;
c0700f90 1755 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 1756 vars->autoneg = AUTO_NEG_DISABLED;
1757 vars->mac_type = MAC_TYPE_NONE;
1758 }
1759
1760 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1761 gp_status, vars->phy_link_up, vars->line_speed);
1762 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1763 " autoneg 0x%x\n",
1764 vars->duplex,
1765 vars->flow_ctrl, vars->autoneg);
1766 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1767
1768 return rc;
1769}
1770
ed8680a7 1771static void bnx2x_set_gmii_tx_driver(struct link_params *params)
ea4e040a
YR		 1772{
1773 struct bnx2x *bp = params->bp;
1774 u16 lp_up2;
1775 u16 tx_driver;
c2c8b03e 1776 u16 bank;
ea4e040a
YR		 1777
1778 /* read precomp */
ea4e040a
YR		 1779 CL45_RD_OVER_CL22(bp, params->port,
1780 params->phy_addr,
1781 MDIO_REG_BANK_OVER_1G,
1782 MDIO_OVER_1G_LP_UP2, &lp_up2);
1783
ea4e040a
YR		 1784 /* bits [10:7] at lp_up2, positioned at [15:12] */
1785 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1786 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1787 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1788
c2c8b03e
EG		 1789 if (lp_up2 == 0)
1790 return;
1791
1792 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1793 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
1794 CL45_RD_OVER_CL22(bp, params->port,
ea4e040a 1795 params->phy_addr,
c2c8b03e
EG		 1796 bank,
1797 MDIO_TX0_TX_DRIVER, &tx_driver);
1798
1799 /* replace tx_driver bits [15:12] */
1800 if (lp_up2 !=
1801 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1802 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1803 tx_driver |= lp_up2;
1804 CL45_WR_OVER_CL22(bp, params->port,
1805 params->phy_addr,
1806 bank,
1807 MDIO_TX0_TX_DRIVER, tx_driver);
1808 }
ea4e040a
YR		 1809 }
1810}
1811
1812static u8 bnx2x_emac_program(struct link_params *params,
1813 u32 line_speed, u32 duplex)
1814{
1815 struct bnx2x *bp = params->bp;
1816 u8 port = params->port;
1817 u16 mode = 0;
1818
1819 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1820 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1821 EMAC_REG_EMAC_MODE,
1822 (EMAC_MODE_25G_MODE |
1823 EMAC_MODE_PORT_MII_10M |
1824 EMAC_MODE_HALF_DUPLEX));
1825 switch (line_speed) {
1826 case SPEED_10:
1827 mode |= EMAC_MODE_PORT_MII_10M;
1828 break;
1829
1830 case SPEED_100:
1831 mode |= EMAC_MODE_PORT_MII;
1832 break;
1833
1834 case SPEED_1000:
1835 mode |= EMAC_MODE_PORT_GMII;
1836 break;
1837
1838 case SPEED_2500:
1839 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1840 break;
1841
1842 default:
1843 /* 10G not valid for EMAC */
1844 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1845 return -EINVAL;
1846 }
1847
1848 if (duplex == DUPLEX_HALF)
1849 mode |= EMAC_MODE_HALF_DUPLEX;
1850 bnx2x_bits_en(bp,
1851 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1852 mode);
1853
1854 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1855 line_speed, params->hw_led_mode, params->chip_id);
1856 return 0;
1857}
1858
1859/*****************************************************************************/
17de50b7 1860/* External Phy section */
ea4e040a 1861/*****************************************************************************/
17de50b7 1862static void bnx2x_hw_reset(struct bnx2x *bp, u8 port)
ea4e040a
YR		 1863{
1864 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 1865 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
ea4e040a
YR		 1866 msleep(1);
1867 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7 1868 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
ea4e040a
YR		 1869}
1870
1871static void bnx2x_ext_phy_reset(struct link_params *params,
1872 struct link_vars *vars)
1873{
1874 struct bnx2x *bp = params->bp;
1875 u32 ext_phy_type;
1876 u8 ext_phy_addr = ((params->ext_phy_config &
1877 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1878 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1879 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
1880 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1881 /* The PHY reset is controled by GPIO 1
1882 * Give it 1ms of reset pulse
1883 */
1884 if (vars->phy_flags & PHY_XGXS_FLAG) {
1885
1886 switch (ext_phy_type) {
1887 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1888 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1889 break;
1890
1891 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1892 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1893 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
1894
1895 /* Restore normal power mode*/
1896 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 1897 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1898 params->port);
ea4e040a
YR		 1899
1900 /* HW reset */
17de50b7 1901 bnx2x_hw_reset(bp, params->port);
ea4e040a
YR		 1902
1903 bnx2x_cl45_write(bp, params->port,
1904 ext_phy_type,
1905 ext_phy_addr,
1906 MDIO_PMA_DEVAD,
1907 MDIO_PMA_REG_CTRL, 0xa040);
1908 break;
4d295db0
EG		 1909
1910 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
1911 break;
1912
589abe3a
EG		 1913 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
1914
1915 /* Restore normal power mode*/
1916 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1917 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1918 params->port);
1919
1920 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1921 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1922 params->port);
1923
1924 bnx2x_cl45_write(bp, params->port,
1925 ext_phy_type,
1926 ext_phy_addr,
1927 MDIO_PMA_DEVAD,
1928 MDIO_PMA_REG_CTRL,
1929 1<<15);
1930
1931 break;
ea4e040a
YR		 1932 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
1933 /* Unset Low Power Mode and SW reset */
1934 /* Restore normal power mode*/
1935 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 1936 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1937 params->port);
ea4e040a
YR		 1938
1939 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1940 bnx2x_cl45_write(bp, params->port,
1941 ext_phy_type,
1942 ext_phy_addr,
1943 MDIO_PMA_DEVAD,
1944 MDIO_PMA_REG_CTRL,
1945 1<<15);
1946 break;
1947 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
1948 {
ea4e040a
YR		 1949
1950 /* Restore normal power mode*/
1951 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 1952 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1953 params->port);
ea4e040a
YR		 1954
1955 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 1956 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1957 params->port);
ea4e040a
YR		 1958
1959 DP(NETIF_MSG_LINK, "XGXS 8073\n");
ea4e040a
YR		 1960 }
1961 break;
1962
1963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1964 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
1965
1966 /* Restore normal power mode*/
1967 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 1968 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1969 params->port);
ea4e040a
YR		 1970
1971 /* HW reset */
17de50b7 1972 bnx2x_hw_reset(bp, params->port);
ea4e040a
YR		 1973
1974 break;
1975
28577185
EG		 1976 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
1977
1978 /* Restore normal power mode*/
1979 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1980 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
1981 params->port);
1982
1983 /* HW reset */
1984 bnx2x_hw_reset(bp, params->port);
1985
1986 bnx2x_cl45_write(bp, params->port,
1987 ext_phy_type,
1988 ext_phy_addr,
1989 MDIO_PMA_DEVAD,
1990 MDIO_PMA_REG_CTRL,
1991 1<<15);
1992 break;
ea4e040a
YR		 1993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
1994 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
1995 break;
1996
1997 default:
1998 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
1999 params->ext_phy_config);
2000 break;
2001 }
2002
2003 } else { /* SerDes */
2004 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2005 switch (ext_phy_type) {
2006 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2007 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2008 break;
2009
2010 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2011 DP(NETIF_MSG_LINK, "SerDes 5482\n");
17de50b7 2012 bnx2x_hw_reset(bp, params->port);
ea4e040a
YR		 2013 break;
2014
2015 default:
2016 DP(NETIF_MSG_LINK,
2017 "BAD SerDes ext_phy_config 0x%x\n",
2018 params->ext_phy_config);
2019 break;
2020 }
2021 }
2022}
2023
a35da8db
EG		 2024
2025static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2026 u32 shmem_base, u32 spirom_ver)
2027{
2028 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
2029 (u16)(spirom_ver>>16), (u16)spirom_ver);
2030 REG_WR(bp, shmem_base +
2031 offsetof(struct shmem_region,
2032 port_mb[port].ext_phy_fw_version),
2033 spirom_ver);
2034}
2035
2036static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2037 u32 ext_phy_type, u8 ext_phy_addr,
2038 u32 shmem_base)
2039{
2040 u16 fw_ver1, fw_ver2;
2041 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2042 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2043 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2044 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2045 bnx2x_save_spirom_version(bp, port, shmem_base,
2046 (u32)(fw_ver1<<16 | fw_ver2));
2047}
2048
b1607af5
EG		 2049
2050static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2051 u8 ext_phy_addr, u32 shmem_base)
2052{
2053 u16 val, fw_ver1, fw_ver2, cnt;
2054 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2055 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2056 bnx2x_cl45_write(bp, port,
2057 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2058 ext_phy_addr, MDIO_PMA_DEVAD,
2059 0xA819, 0x0014);
2060 bnx2x_cl45_write(bp, port,
2061 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2062 ext_phy_addr,
2063 MDIO_PMA_DEVAD,
2064 0xA81A,
2065 0xc200);
2066 bnx2x_cl45_write(bp, port,
2067 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2068 ext_phy_addr,
2069 MDIO_PMA_DEVAD,
2070 0xA81B,
2071 0x0000);
2072 bnx2x_cl45_write(bp, port,
2073 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2074 ext_phy_addr,
2075 MDIO_PMA_DEVAD,
2076 0xA81C,
2077 0x0300);
2078 bnx2x_cl45_write(bp, port,
2079 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2080 ext_phy_addr,
2081 MDIO_PMA_DEVAD,
2082 0xA817,
2083 0x0009);
2084
2085 for (cnt = 0; cnt < 100; cnt++) {
2086 bnx2x_cl45_read(bp, port,
2087 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2088 ext_phy_addr,
2089 MDIO_PMA_DEVAD,
2090 0xA818,
2091 &val);
2092 if (val & 1)
2093 break;
2094 udelay(5);
2095 }
2096 if (cnt == 100) {
2097 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2098 bnx2x_save_spirom_version(bp, port,
2099 shmem_base, 0);
2100 return;
2101 }
2102
2103
2104 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2105 bnx2x_cl45_write(bp, port,
2106 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2107 ext_phy_addr, MDIO_PMA_DEVAD,
2108 0xA819, 0x0000);
2109 bnx2x_cl45_write(bp, port,
2110 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2111 ext_phy_addr, MDIO_PMA_DEVAD,
2112 0xA81A, 0xc200);
2113 bnx2x_cl45_write(bp, port,
2114 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2115 ext_phy_addr, MDIO_PMA_DEVAD,
2116 0xA817, 0x000A);
2117 for (cnt = 0; cnt < 100; cnt++) {
2118 bnx2x_cl45_read(bp, port,
2119 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2120 ext_phy_addr,
2121 MDIO_PMA_DEVAD,
2122 0xA818,
2123 &val);
2124 if (val & 1)
2125 break;
2126 udelay(5);
2127 }
2128 if (cnt == 100) {
2129 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2130 bnx2x_save_spirom_version(bp, port,
2131 shmem_base, 0);
2132 return;
2133 }
2134
2135 /* lower 16 bits of the register SPI_FW_STATUS */
2136 bnx2x_cl45_read(bp, port,
2137 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2138 ext_phy_addr,
2139 MDIO_PMA_DEVAD,
2140 0xA81B,
2141 &fw_ver1);
2142 /* upper 16 bits of register SPI_FW_STATUS */
2143 bnx2x_cl45_read(bp, port,
2144 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2145 ext_phy_addr,
2146 MDIO_PMA_DEVAD,
2147 0xA81C,
2148 &fw_ver2);
2149
2150 bnx2x_save_spirom_version(bp, port,
2151 shmem_base, (fw_ver2<<16) | fw_ver1);
2152}
2153
ea4e040a
YR		 2154static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2155{
2156 struct bnx2x *bp = params->bp;
2157 u8 port = params->port;
2158 u8 ext_phy_addr = ((params->ext_phy_config &
2159 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2160 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2161 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 2162
2163 /* Need to wait 200ms after reset */
2164 msleep(200);
2165 /* Boot port from external ROM
2166 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2167 */
2168 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2169 MDIO_PMA_DEVAD,
2170 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2171
2172 /* Reset internal microprocessor */
2173 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2174 MDIO_PMA_DEVAD,
2175 MDIO_PMA_REG_GEN_CTRL,
2176 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2177 /* set micro reset = 0 */
2178 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2179 MDIO_PMA_DEVAD,
2180 MDIO_PMA_REG_GEN_CTRL,
2181 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2182 /* Reset internal microprocessor */
2183 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2184 MDIO_PMA_DEVAD,
2185 MDIO_PMA_REG_GEN_CTRL,
2186 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2187 /* wait for 100ms for code download via SPI port */
2188 msleep(100);
2189
2190 /* Clear ser_boot_ctl bit */
2191 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2192 MDIO_PMA_DEVAD,
2193 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2194 /* Wait 100ms */
2195 msleep(100);
2196
a35da8db
EG		 2197 bnx2x_save_bcm_spirom_ver(bp, port,
2198 ext_phy_type,
2199 ext_phy_addr,
2200 params->shmem_base);
ea4e040a
YR		 2201}
2202
2203static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2204{
2205 /* This is only required for 8073A1, version 102 only */
2206
2207 struct bnx2x *bp = params->bp;
2208 u8 ext_phy_addr = ((params->ext_phy_config &
2209 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2210 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2211 u16 val;
2212
2213 /* Read 8073 HW revision*/
2214 bnx2x_cl45_read(bp, params->port,
2215 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2216 ext_phy_addr,
2217 MDIO_PMA_DEVAD,
052a38e0 2218 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2219
2220 if (val != 1) {
2221 /* No need to workaround in 8073 A1 */
2222 return 0;
2223 }
2224
2225 bnx2x_cl45_read(bp, params->port,
2226 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2227 ext_phy_addr,
2228 MDIO_PMA_DEVAD,
2229 MDIO_PMA_REG_ROM_VER2, &val);
2230
2231 /* SNR should be applied only for version 0x102 */
2232 if (val != 0x102)
2233 return 0;
2234
2235 return 1;
2236}
2237
2238static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2239{
2240 struct bnx2x *bp = params->bp;
2241 u8 ext_phy_addr = ((params->ext_phy_config &
2242 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2243 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2244 u16 val, cnt, cnt1 ;
2245
2246 bnx2x_cl45_read(bp, params->port,
2247 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2248 ext_phy_addr,
2249 MDIO_PMA_DEVAD,
052a38e0 2250 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 2251
2252 if (val > 0) {
2253 /* No need to workaround in 8073 A1 */
2254 return 0;
2255 }
2256 /* XAUI workaround in 8073 A0: */
2257
2258 /* After loading the boot ROM and restarting Autoneg,
2259 poll Dev1, Reg $C820: */
2260
2261 for (cnt = 0; cnt < 1000; cnt++) {
2262 bnx2x_cl45_read(bp, params->port,
2263 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2264 ext_phy_addr,
2265 MDIO_PMA_DEVAD,
052a38e0
EG		 2266 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2267 &val);
ea4e040a
YR		 2268 /* If bit [14] = 0 or bit [13] = 0, continue on with
2269 system initialization (XAUI work-around not required,
2270 as these bits indicate 2.5G or 1G link up). */
2271 if (!(val & (1<<14)) || !(val & (1<<13))) {
2272 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2273 return 0;
2274 } else if (!(val & (1<<15))) {
2275 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2276 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2277 it's MSB (bit 15) goes to 1 (indicating that the
2278 XAUI workaround has completed),
2279 then continue on with system initialization.*/
2280 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2281 bnx2x_cl45_read(bp, params->port,
2282 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2283 ext_phy_addr,
2284 MDIO_PMA_DEVAD,
052a38e0 2285 MDIO_PMA_REG_8073_XAUI_WA, &val);
ea4e040a
YR		 2286 if (val & (1<<15)) {
2287 DP(NETIF_MSG_LINK,
2288 "XAUI workaround has completed\n");
2289 return 0;
2290 }
2291 msleep(3);
2292 }
2293 break;
2294 }
2295 msleep(3);
2296 }
2297 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2298 return -EINVAL;
2299
2300}
2301
4d295db0
EG		 2302static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2303 u8 ext_phy_addr,
2304 u32 ext_phy_type,
2305 u32 shmem_base)
ea4e040a 2306{
6bbca910 2307 /* Boot port from external ROM */
ea4e040a 2308 /* EDC grst */
6bbca910 2309 bnx2x_cl45_write(bp, port,
4d295db0 2310 ext_phy_type,
6bbca910 2311 ext_phy_addr,
ea4e040a
YR		 2312 MDIO_PMA_DEVAD,
2313 MDIO_PMA_REG_GEN_CTRL,
2314 0x0001);
2315
2316 /* ucode reboot and rst */
6bbca910 2317 bnx2x_cl45_write(bp, port,
4d295db0 2318 ext_phy_type,
6bbca910 2319 ext_phy_addr,
ea4e040a
YR		 2320 MDIO_PMA_DEVAD,
2321 MDIO_PMA_REG_GEN_CTRL,
2322 0x008c);
2323
6bbca910 2324 bnx2x_cl45_write(bp, port,
4d295db0 2325 ext_phy_type,
6bbca910 2326 ext_phy_addr,
ea4e040a
YR		 2327 MDIO_PMA_DEVAD,
2328 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2329
2330 /* Reset internal microprocessor */
6bbca910 2331 bnx2x_cl45_write(bp, port,
4d295db0 2332 ext_phy_type,
6bbca910 2333 ext_phy_addr,
ea4e040a
YR		 2334 MDIO_PMA_DEVAD,
2335 MDIO_PMA_REG_GEN_CTRL,
2336 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2337
2338 /* Release srst bit */
6bbca910 2339 bnx2x_cl45_write(bp, port,
4d295db0 2340 ext_phy_type,
6bbca910 2341 ext_phy_addr,
ea4e040a
YR		 2342 MDIO_PMA_DEVAD,
2343 MDIO_PMA_REG_GEN_CTRL,
2344 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2345
2346 /* wait for 100ms for code download via SPI port */
2347 msleep(100);
2348
2349 /* Clear ser_boot_ctl bit */
6bbca910 2350 bnx2x_cl45_write(bp, port,
4d295db0 2351 ext_phy_type,
6bbca910 2352 ext_phy_addr,
ea4e040a
YR		 2353 MDIO_PMA_DEVAD,
2354 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2355
a35da8db 2356 bnx2x_save_bcm_spirom_ver(bp, port,
4d295db0 2357 ext_phy_type,
a35da8db
EG		 2358 ext_phy_addr,
2359 shmem_base);
6bbca910 2360}
ea4e040a 2361
4d295db0
EG		 2362static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2363 u8 ext_phy_addr,
2364 u32 shmem_base)
2365{
2366 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2367 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2368 shmem_base);
2369}
2370
2371static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2372 u8 ext_phy_addr,
2373 u32 shmem_base)
2374{
2375 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2376 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2377 shmem_base);
2378
2379}
2380
589abe3a
EG		 2381static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2382{
2383 struct bnx2x *bp = params->bp;
2384 u8 port = params->port;
2385 u8 ext_phy_addr = ((params->ext_phy_config &
2386 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2387 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2388 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2389
2390 /* Need to wait 100ms after reset */
2391 msleep(100);
2392
2393 /* Set serial boot control for external load */
2394 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2395 MDIO_PMA_DEVAD,
2396 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2397
2398 /* Micro controller re-boot */
2399 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2400 MDIO_PMA_DEVAD,
2401 MDIO_PMA_REG_GEN_CTRL,
2402 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2403
2404 /* Set soft reset */
2405 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2406 MDIO_PMA_DEVAD,
2407 MDIO_PMA_REG_GEN_CTRL,
2408 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2409
4d295db0 2410 /* Set PLL register value to be same like in P13 ver */
cc1cb004
EG		 2411 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2412 MDIO_PMA_DEVAD,
4d295db0 2413 MDIO_PMA_REG_PLL_CTRL,
cc1cb004
EG		 2414 0x73A0);
2415
589abe3a
EG		 2416 /* Clear soft reset.
2417 Will automatically reset micro-controller re-boot */
2418 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2419 MDIO_PMA_DEVAD,
2420 MDIO_PMA_REG_GEN_CTRL,
2421 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2422
cc1cb004
EG		 2423 /* wait for 150ms for microcode load */
2424 msleep(150);
589abe3a
EG		 2425
2426 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2427 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2428 MDIO_PMA_DEVAD,
2429 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2430
2431 msleep(200);
a35da8db
EG		 2432 bnx2x_save_bcm_spirom_ver(bp, port,
2433 ext_phy_type,
2434 ext_phy_addr,
2435 params->shmem_base);
589abe3a
EG		 2436}
2437
4d295db0
EG		 2438static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2439 u32 ext_phy_type, u8 ext_phy_addr,
2440 u8 tx_en)
589abe3a
EG		 2441{
2442 u16 val;
2443 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2444 tx_en, port);
2445 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2446 bnx2x_cl45_read(bp, port,
4d295db0 2447 ext_phy_type,
589abe3a
EG		 2448 ext_phy_addr,
2449 MDIO_PMA_DEVAD,
2450 MDIO_PMA_REG_PHY_IDENTIFIER,
2451 &val);
2452
2453 if (tx_en)
2454 val &= ~(1<<15);
2455 else
2456 val |= (1<<15);
2457
2458 bnx2x_cl45_write(bp, port,
4d295db0 2459 ext_phy_type,
589abe3a
EG		 2460 ext_phy_addr,
2461 MDIO_PMA_DEVAD,
2462 MDIO_PMA_REG_PHY_IDENTIFIER,
2463 val);
2464}
2465
4d295db0
EG		 2466static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2467 u16 addr, u8 byte_cnt, u8 *o_buf)
2468{
589abe3a 2469 struct bnx2x *bp = params->bp;
4d295db0
EG		 2470 u16 val = 0;
2471 u16 i;
589abe3a
EG		 2472 u8 port = params->port;
2473 u8 ext_phy_addr = ((params->ext_phy_config &
2474 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2475 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2476 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2477 if (byte_cnt > 16) {
2478 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2479 " is limited to 0xf\n");
2480 return -EINVAL;
2481 }
2482 /* Set the read command byte count */
2483 bnx2x_cl45_write(bp, port,
2484 ext_phy_type,
2485 ext_phy_addr,
2486 MDIO_PMA_DEVAD,
4d295db0 2487 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
589abe3a
EG		 2488 (byte_cnt | 0xa000));
2489
2490 /* Set the read command address */
2491 bnx2x_cl45_write(bp, port,
2492 ext_phy_type,
2493 ext_phy_addr,
2494 MDIO_PMA_DEVAD,
4d295db0 2495 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
589abe3a
EG		 2496 addr);
2497
2498 /* Activate read command */
2499 bnx2x_cl45_write(bp, port,
2500 ext_phy_type,
2501 ext_phy_addr,
2502 MDIO_PMA_DEVAD,
4d295db0 2503 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
589abe3a
EG		 2504 0x2c0f);
2505
2506 /* Wait up to 500us for command complete status */
2507 for (i = 0; i < 100; i++) {
2508 bnx2x_cl45_read(bp, port,
2509 ext_phy_type,
2510 ext_phy_addr,
2511 MDIO_PMA_DEVAD,
4d295db0
EG		 2512 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2513 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2514 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
589abe3a
EG		 2515 break;
2516 udelay(5);
2517 }
2518
4d295db0
EG		 2519 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2520 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
589abe3a
EG		 2521 DP(NETIF_MSG_LINK,
2522 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4d295db0 2523 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
589abe3a
EG		 2524 return -EINVAL;
2525 }
2526
2527 /* Read the buffer */
2528 for (i = 0; i < byte_cnt; i++) {
2529 bnx2x_cl45_read(bp, port,
2530 ext_phy_type,
2531 ext_phy_addr,
2532 MDIO_PMA_DEVAD,
2533 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2534 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2535 }
2536
2537 for (i = 0; i < 100; i++) {
2538 bnx2x_cl45_read(bp, port,
2539 ext_phy_type,
2540 ext_phy_addr,
2541 MDIO_PMA_DEVAD,
4d295db0
EG		 2542 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2543 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2544 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2545 return 0;;
2546 msleep(1);
2547 }
2548 return -EINVAL;
2549}
2550
2551static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2552 u16 addr, u8 byte_cnt, u8 *o_buf)
2553{
2554 struct bnx2x *bp = params->bp;
2555 u16 val, i;
2556 u8 port = params->port;
2557 u8 ext_phy_addr = ((params->ext_phy_config &
2558 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2559 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2560 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2561
2562 if (byte_cnt > 16) {
2563 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2564 " is limited to 0xf\n");
2565 return -EINVAL;
2566 }
2567
2568 /* Need to read from 1.8000 to clear it */
2569 bnx2x_cl45_read(bp, port,
2570 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2571 ext_phy_addr,
2572 MDIO_PMA_DEVAD,
2573 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2574 &val);
2575
2576 /* Set the read command byte count */
2577 bnx2x_cl45_write(bp, port,
2578 ext_phy_type,
2579 ext_phy_addr,
2580 MDIO_PMA_DEVAD,
2581 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2582 ((byte_cnt < 2) ? 2 : byte_cnt));
2583
2584 /* Set the read command address */
2585 bnx2x_cl45_write(bp, port,
2586 ext_phy_type,
2587 ext_phy_addr,
2588 MDIO_PMA_DEVAD,
2589 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2590 addr);
2591 /* Set the destination address */
2592 bnx2x_cl45_write(bp, port,
2593 ext_phy_type,
2594 ext_phy_addr,
2595 MDIO_PMA_DEVAD,
2596 0x8004,
2597 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2598
2599 /* Activate read command */
2600 bnx2x_cl45_write(bp, port,
2601 ext_phy_type,
2602 ext_phy_addr,
2603 MDIO_PMA_DEVAD,
2604 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2605 0x8002);
2606 /* Wait appropriate time for two-wire command to finish before
2607 polling the status register */
2608 msleep(1);
2609
2610 /* Wait up to 500us for command complete status */
2611 for (i = 0; i < 100; i++) {
2612 bnx2x_cl45_read(bp, port,
2613 ext_phy_type,
2614 ext_phy_addr,
2615 MDIO_PMA_DEVAD,
2616 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2617 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2618 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2619 break;
2620 udelay(5);
2621 }
2622
2623 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2624 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2625 DP(NETIF_MSG_LINK,
2626 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2627 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2628 return -EINVAL;
2629 }
2630
2631 /* Read the buffer */
2632 for (i = 0; i < byte_cnt; i++) {
2633 bnx2x_cl45_read(bp, port,
2634 ext_phy_type,
2635 ext_phy_addr,
2636 MDIO_PMA_DEVAD,
2637 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2638 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2639 }
2640
2641 for (i = 0; i < 100; i++) {
2642 bnx2x_cl45_read(bp, port,
2643 ext_phy_type,
2644 ext_phy_addr,
2645 MDIO_PMA_DEVAD,
2646 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2647 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2648 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
589abe3a
EG		 2649 return 0;;
2650 msleep(1);
2651 }
4d295db0 2652
589abe3a
EG		 2653 return -EINVAL;
2654}
2655
4d295db0
EG		 2656u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2657 u8 byte_cnt, u8 *o_buf)
2658{
2659 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2660
2661 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2662 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2663 byte_cnt, o_buf);
2664 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2665 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2666 byte_cnt, o_buf);
2667 return -EINVAL;
2668}
589abe3a 2669
4d295db0
EG		 2670static u8 bnx2x_get_edc_mode(struct link_params *params,
2671 u16 *edc_mode)
589abe3a
EG		 2672{
2673 struct bnx2x *bp = params->bp;
4d295db0
EG		 2674 u8 val, check_limiting_mode = 0;
2675 *edc_mode = EDC_MODE_LIMITING;
589abe3a
EG		 2676
2677 /* First check for copper cable */
2678 if (bnx2x_read_sfp_module_eeprom(params,
2679 SFP_EEPROM_CON_TYPE_ADDR,
2680 1,
2681 &val) != 0) {
4d295db0 2682 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
589abe3a
EG		 2683 return -EINVAL;
2684 }
2685
2686 switch (val) {
2687 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2688 {
2689 u8 copper_module_type;
2690 /* Check if its active cable( includes SFP+ module)
2691 of passive cable*/
2692 if (bnx2x_read_sfp_module_eeprom(params,
2693 SFP_EEPROM_FC_TX_TECH_ADDR,
2694 1,
2695 &copper_module_type) !=
2696 0) {
2697 DP(NETIF_MSG_LINK,
2698 "Failed to read copper-cable-type"
2699 " from SFP+ EEPROM\n");
2700 return -EINVAL;
2701 }
2702
2703 if (copper_module_type &
2704 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2705 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4d295db0 2706 check_limiting_mode = 1;
589abe3a
EG		 2707 } else if (copper_module_type &
2708 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2709 DP(NETIF_MSG_LINK, "Passive Copper"
2710 " cable detected\n");
4d295db0
EG		 2711 *edc_mode =
2712 EDC_MODE_PASSIVE_DAC;
589abe3a
EG		 2713 } else {
2714 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2715 "type 0x%x !!!\n", copper_module_type);
2716 return -EINVAL;
2717 }
2718 break;
2719 }
2720 case SFP_EEPROM_CON_TYPE_VAL_LC:
2721 DP(NETIF_MSG_LINK, "Optic module detected\n");
4d295db0 2722 check_limiting_mode = 1;
589abe3a
EG		 2723 break;
2724
2725 default:
2726 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2727 val);
2728 return -EINVAL;
2729 }
4d295db0
EG		 2730
2731 if (check_limiting_mode) {
2732 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2733 if (bnx2x_read_sfp_module_eeprom(params,
2734 SFP_EEPROM_OPTIONS_ADDR,
2735 SFP_EEPROM_OPTIONS_SIZE,
2736 options) != 0) {
2737 DP(NETIF_MSG_LINK, "Failed to read Option"
2738 " field from module EEPROM\n");
2739 return -EINVAL;
2740 }
2741 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2742 *edc_mode = EDC_MODE_LINEAR;
2743 else
2744 *edc_mode = EDC_MODE_LIMITING;
2745 }
2746 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
589abe3a
EG		 2747 return 0;
2748}
2749
589abe3a
EG		 2750/* This function read the relevant field from the module ( SFP+ ),
2751 and verify it is compliant with this board */
4d295db0 2752static u8 bnx2x_verify_sfp_module(struct link_params *params)
589abe3a
EG		 2753{
2754 struct bnx2x *bp = params->bp;
4d295db0
EG		 2755 u32 val;
2756 u32 fw_resp;
2757 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2758 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2759
2760 val = REG_RD(bp, params->shmem_base +
2761 offsetof(struct shmem_region, dev_info.
2762 port_feature_config[params->port].config));
2763 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2764 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
589abe3a
EG		 2765 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2766 return 0;
2767 }
2768
4d295db0
EG		 2769 /* Ask the FW to validate the module */
2770 if (!(params->feature_config_flags &
2771 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2772 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2773 "verification\n");
2774 return -EINVAL;
2775 }
2776
2777 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2778 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2779 DP(NETIF_MSG_LINK, "Approved module\n");
589abe3a
EG		 2780 return 0;
2781 }
2782
4d295db0 2783 /* format the warning message */
589abe3a
EG		 2784 if (bnx2x_read_sfp_module_eeprom(params,
2785 SFP_EEPROM_VENDOR_NAME_ADDR,
2786 SFP_EEPROM_VENDOR_NAME_SIZE,
4d295db0
EG		 2787 (u8 *)vendor_name))
2788 vendor_name[0] = '\0';
2789 else
2790 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2791 if (bnx2x_read_sfp_module_eeprom(params,
2792 SFP_EEPROM_PART_NO_ADDR,
2793 SFP_EEPROM_PART_NO_SIZE,
2794 (u8 *)vendor_pn))
2795 vendor_pn[0] = '\0';
2796 else
2797 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
589abe3a 2798
4d295db0
EG		 2799 printk(KERN_INFO PFX "Warning: "
2800 "Unqualified SFP+ module "
2801 "detected on %s, Port %d from %s part number %s\n"
2802 , bp->dev->name, params->port,
2803 vendor_name, vendor_pn);
589abe3a
EG		 2804 return -EINVAL;
2805}
2806
589abe3a 2807static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
4d295db0 2808 u16 edc_mode)
589abe3a
EG		 2809{
2810 struct bnx2x *bp = params->bp;
2811 u8 port = params->port;
589abe3a
EG		 2812 u8 ext_phy_addr = ((params->ext_phy_config &
2813 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2814 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
cc1cb004 2815 u16 cur_limiting_mode;
cc1cb004
EG		 2816
2817 bnx2x_cl45_read(bp, port,
2818 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2819 ext_phy_addr,
2820 MDIO_PMA_DEVAD,
2821 MDIO_PMA_REG_ROM_VER2,
2822 &cur_limiting_mode);
2823 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
2824 cur_limiting_mode);
2825
4d295db0 2826 if (edc_mode == EDC_MODE_LIMITING) {
589abe3a 2827 DP(NETIF_MSG_LINK,
4d295db0 2828 "Setting LIMITING MODE\n");
589abe3a
EG		 2829 bnx2x_cl45_write(bp, port,
2830 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2831 ext_phy_addr,
2832 MDIO_PMA_DEVAD,
2833 MDIO_PMA_REG_ROM_VER2,
4d295db0 2834 EDC_MODE_LIMITING);
589abe3a 2835 } else { /* LRM mode ( default )*/
cc1cb004 2836
4d295db0 2837 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
589abe3a 2838
589abe3a
EG		 2839 /* Changing to LRM mode takes quite few seconds.
2840 So do it only if current mode is limiting
2841 ( default is LRM )*/
4d295db0 2842 if (cur_limiting_mode != EDC_MODE_LIMITING)
589abe3a
EG		 2843 return 0;
2844
2845 bnx2x_cl45_write(bp, port,
2846 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2847 ext_phy_addr,
2848 MDIO_PMA_DEVAD,
2849 MDIO_PMA_REG_LRM_MODE,
2850 0);
2851 bnx2x_cl45_write(bp, port,
2852 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2853 ext_phy_addr,
2854 MDIO_PMA_DEVAD,
2855 MDIO_PMA_REG_ROM_VER2,
2856 0x128);
2857 bnx2x_cl45_write(bp, port,
2858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2859 ext_phy_addr,
2860 MDIO_PMA_DEVAD,
2861 MDIO_PMA_REG_MISC_CTRL0,
2862 0x4008);
2863 bnx2x_cl45_write(bp, port,
2864 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2865 ext_phy_addr,
2866 MDIO_PMA_DEVAD,
2867 MDIO_PMA_REG_LRM_MODE,
2868 0xaaaa);
2869 }
2870 return 0;
2871}
2872
4d295db0
EG		 2873static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
2874 u16 edc_mode)
2875{
2876 struct bnx2x *bp = params->bp;
2877 u8 port = params->port;
2878 u16 phy_identifier;
2879 u16 rom_ver2_val;
2880 u8 ext_phy_addr = ((params->ext_phy_config &
2881 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2882 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2883
2884 bnx2x_cl45_read(bp, port,
2885 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2886 ext_phy_addr,
2887 MDIO_PMA_DEVAD,
2888 MDIO_PMA_REG_PHY_IDENTIFIER,
2889 &phy_identifier);
2890
2891 bnx2x_cl45_write(bp, port,
2892 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2893 ext_phy_addr,
2894 MDIO_PMA_DEVAD,
2895 MDIO_PMA_REG_PHY_IDENTIFIER,
2896 (phy_identifier & ~(1<<9)));
2897
2898 bnx2x_cl45_read(bp, port,
2899 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2900 ext_phy_addr,
2901 MDIO_PMA_DEVAD,
2902 MDIO_PMA_REG_ROM_VER2,
2903 &rom_ver2_val);
2904 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
2905 bnx2x_cl45_write(bp, port,
2906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2907 ext_phy_addr,
2908 MDIO_PMA_DEVAD,
2909 MDIO_PMA_REG_ROM_VER2,
2910 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
2911
2912 bnx2x_cl45_write(bp, port,
2913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2914 ext_phy_addr,
2915 MDIO_PMA_DEVAD,
2916 MDIO_PMA_REG_PHY_IDENTIFIER,
2917 (phy_identifier | (1<<9)));
2918
2919 return 0;
2920}
2921
2922
589abe3a
EG		 2923static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
2924{
2925 u8 val;
2926 struct bnx2x *bp = params->bp;
2927 u16 timeout;
2928 /* Initialization time after hot-plug may take up to 300ms for some
2929 phys type ( e.g. JDSU ) */
2930 for (timeout = 0; timeout < 60; timeout++) {
2931 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
2932 == 0) {
2933 DP(NETIF_MSG_LINK, "SFP+ module initialization "
2934 "took %d ms\n", timeout * 5);
2935 return 0;
2936 }
2937 msleep(5);
2938 }
2939 return -EINVAL;
2940}
2941
4d295db0
EG		 2942static void bnx2x_8727_power_module(struct bnx2x *bp,
2943 struct link_params *params,
2944 u8 ext_phy_addr, u8 is_power_up) {
2945 /* Make sure GPIOs are not using for LED mode */
2946 u16 val;
2947 u8 port = params->port;
2948 /*
2949 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
2950 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
2951 * output
2952 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
2953 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
2954 * where the 1st bit is the over-current(only input), and 2nd bit is
2955 * for power( only output )
2956 */
2957
2958 /*
2959 * In case of NOC feature is disabled and power is up, set GPIO control
2960 * as input to enable listening of over-current indication
2961 */
2962
2963 if (!(params->feature_config_flags &
2964 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
2965 val = (1<<4);
2966 else
2967 /*
2968 * Set GPIO control to OUTPUT, and set the power bit
2969 * to according to the is_power_up
2970 */
2971 val = ((!(is_power_up)) << 1);
2972
2973 bnx2x_cl45_write(bp, port,
2974 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2975 ext_phy_addr,
2976 MDIO_PMA_DEVAD,
2977 MDIO_PMA_REG_8727_GPIO_CTRL,
2978 val);
2979}
2980
589abe3a
EG		 2981static u8 bnx2x_sfp_module_detection(struct link_params *params)
2982{
2983 struct bnx2x *bp = params->bp;
4d295db0
EG		 2984 u16 edc_mode;
2985 u8 rc = 0;
589abe3a
EG		 2986 u8 ext_phy_addr = ((params->ext_phy_config &
2987 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2988 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2989 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4d295db0
EG		 2990 u32 val = REG_RD(bp, params->shmem_base +
2991 offsetof(struct shmem_region, dev_info.
2992 port_feature_config[params->port].config));
589abe3a
EG		 2993
2994 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
2995 params->port);
2996
4d295db0 2997 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
589abe3a 2998 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4d295db0
EG		 2999 return -EINVAL;
3000 } else if (bnx2x_verify_sfp_module(params) !=
589abe3a
EG		 3001 0) {
3002 /* check SFP+ module compatibility */
3003 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4d295db0 3004 rc = -EINVAL;
589abe3a
EG		 3005 /* Turn on fault module-detected led */
3006 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3007 MISC_REGISTERS_GPIO_HIGH,
3008 params->port);
4d295db0
EG		 3009 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3010 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3011 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3012 /* Shutdown SFP+ module */
3013 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3014 bnx2x_8727_power_module(bp, params,
3015 ext_phy_addr, 0);
3016 return rc;
3017 }
3018 } else {
3019 /* Turn off fault module-detected led */
3020 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3021 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3022 MISC_REGISTERS_GPIO_LOW,
3023 params->port);
589abe3a
EG		 3024 }
3025
4d295db0
EG		 3026 /* power up the SFP module */
3027 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3028 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
589abe3a 3029
4d295db0
EG		 3030 /* Check and set limiting mode / LRM mode on 8726.
3031 On 8727 it is done automatically */
3032 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3033 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3034 else
3035 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3036 /*
3037 * Enable transmit for this module if the module is approved, or
3038 * if unapproved modules should also enable the Tx laser
3039 */
3040 if (rc == 0 ||
3041 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3042 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3043 bnx2x_sfp_set_transmitter(bp, params->port,
3044 ext_phy_type, ext_phy_addr, 1);
3045 else
3046 bnx2x_sfp_set_transmitter(bp, params->port,
3047 ext_phy_type, ext_phy_addr, 0);
589abe3a 3048
4d295db0 3049 return rc;
589abe3a
EG		 3050}
3051
3052void bnx2x_handle_module_detect_int(struct link_params *params)
3053{
3054 struct bnx2x *bp = params->bp;
3055 u32 gpio_val;
3056 u8 port = params->port;
3057 /* Set valid module led off */
3058 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3059 MISC_REGISTERS_GPIO_HIGH,
3060 params->port);
3061
3062 /* Get current gpio val refelecting module plugged in / out*/
3063 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3064
3065 /* Call the handling function in case module is detected */
3066 if (gpio_val == 0) {
3067
3068 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3069 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3070 port);
3071
4d295db0
EG		 3072 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3073 0)
589abe3a
EG		 3074 bnx2x_sfp_module_detection(params);
3075 else
3076 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3077 } else {
3078 u8 ext_phy_addr = ((params->ext_phy_config &
3079 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3080 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4d295db0
EG		 3081 u32 ext_phy_type =
3082 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3083 u32 val = REG_RD(bp, params->shmem_base +
3084 offsetof(struct shmem_region, dev_info.
3085 port_feature_config[params->port].
3086 config));
3087
589abe3a
EG		 3088 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3089 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3090 port);
3091 /* Module was plugged out. */
3092 /* Disable transmit for this module */
4d295db0
EG		 3093 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3094 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3095 bnx2x_sfp_set_transmitter(bp, params->port,
3096 ext_phy_type, ext_phy_addr, 0);
589abe3a
EG		 3097 }
3098}
3099
6bbca910
YR		 3100static void bnx2x_bcm807x_force_10G(struct link_params *params)
3101{
3102 struct bnx2x *bp = params->bp;
3103 u8 port = params->port;
3104 u8 ext_phy_addr = ((params->ext_phy_config &
3105 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3106 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3107 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3108
3109 /* Force KR or KX */
ea4e040a
YR		 3110 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3111 MDIO_PMA_DEVAD,
6bbca910
YR		 3112 MDIO_PMA_REG_CTRL,
3113 0x2040);
ea4e040a
YR		 3114 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3115 MDIO_PMA_DEVAD,
6bbca910
YR		 3116 MDIO_PMA_REG_10G_CTRL2,
3117 0x000b);
3118 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3119 MDIO_PMA_DEVAD,
3120 MDIO_PMA_REG_BCM_CTRL,
3121 0x0000);
3122 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3123 MDIO_AN_DEVAD,
3124 MDIO_AN_REG_CTRL,
3125 0x0000);
ea4e040a 3126}
ea4e040a
YR		 3127static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3128{
3129 struct bnx2x *bp = params->bp;
3130 u8 port = params->port;
3131 u16 val;
3132 u8 ext_phy_addr = ((params->ext_phy_config &
3133 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3134 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3135 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3136
3137 bnx2x_cl45_read(bp, params->port,
3138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3139 ext_phy_addr,
3140 MDIO_PMA_DEVAD,
052a38e0 3141 MDIO_PMA_REG_8073_CHIP_REV, &val);
ea4e040a
YR		 3142
3143 if (val == 0) {
3144 /* Mustn't set low power mode in 8073 A0 */
3145 return;
3146 }
3147
3148 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3149 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3150 MDIO_XS_DEVAD,
3151 MDIO_XS_PLL_SEQUENCER, &val);
3152 val &= ~(1<<13);
3153 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3154 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3155
3156 /* PLL controls */
3157 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3158 MDIO_XS_DEVAD, 0x805E, 0x1077);
3159 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3160 MDIO_XS_DEVAD, 0x805D, 0x0000);
3161 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3162 MDIO_XS_DEVAD, 0x805C, 0x030B);
3163 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3164 MDIO_XS_DEVAD, 0x805B, 0x1240);
3165 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3166 MDIO_XS_DEVAD, 0x805A, 0x2490);
3167
3168 /* Tx Controls */
3169 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3170 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3171 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3172 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3173 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3174 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3175
3176 /* Rx Controls */
3177 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3178 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3179 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3180 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3181 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3182 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3183
3184 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3185 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3186 MDIO_XS_DEVAD,
3187 MDIO_XS_PLL_SEQUENCER, &val);
3188 val |= (1<<13);
3189 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3190 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3191}
6bbca910
YR		 3192
3193static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3194 struct link_vars *vars)
ea4e040a 3195{
6bbca910 3196
ea4e040a 3197 struct bnx2x *bp = params->bp;
6bbca910 3198 u16 cl37_val;
ea4e040a
YR		 3199 u8 ext_phy_addr = ((params->ext_phy_config &
3200 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3201 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3202 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3203
6bbca910
YR		 3204 bnx2x_cl45_read(bp, params->port,
3205 ext_phy_type,
3206 ext_phy_addr,
3207 MDIO_AN_DEVAD,
3208 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3209
3210 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3211 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3212
3213 if ((vars->ieee_fc &
3214 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3215 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3216 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3217 }
3218 if ((vars->ieee_fc &
3219 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3220 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3221 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3222 }
3223 if ((vars->ieee_fc &
3224 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3225 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3226 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3227 }
3228 DP(NETIF_MSG_LINK,
3229 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3230
3231 bnx2x_cl45_write(bp, params->port,
3232 ext_phy_type,
3233 ext_phy_addr,
ea4e040a 3234 MDIO_AN_DEVAD,
6bbca910
YR		 3235 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3236 msleep(500);
ea4e040a
YR		 3237}
3238
3239static void bnx2x_ext_phy_set_pause(struct link_params *params,
3240 struct link_vars *vars)
3241{
3242 struct bnx2x *bp = params->bp;
3243 u16 val;
3244 u8 ext_phy_addr = ((params->ext_phy_config &
3245 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3246 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3247 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3248
3249 /* read modify write pause advertizing */
3250 bnx2x_cl45_read(bp, params->port,
3251 ext_phy_type,
3252 ext_phy_addr,
3253 MDIO_AN_DEVAD,
3254 MDIO_AN_REG_ADV_PAUSE, &val);
3255
3256 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
8c99e7b0 3257
ea4e040a
YR		 3258 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3259
8c99e7b0
YR		 3260 if ((vars->ieee_fc &
3261 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
ea4e040a
YR		 3262 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3263 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3264 }
8c99e7b0
YR		 3265 if ((vars->ieee_fc &
3266 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
ea4e040a
YR		 3267 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3268 val |=
3269 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3270 }
3271 DP(NETIF_MSG_LINK,
3272 "Ext phy AN advertize 0x%x\n", val);
3273 bnx2x_cl45_write(bp, params->port,
3274 ext_phy_type,
3275 ext_phy_addr,
3276 MDIO_AN_DEVAD,
3277 MDIO_AN_REG_ADV_PAUSE, val);
3278}
c2c8b03e
EG		 3279static void bnx2x_set_preemphasis(struct link_params *params)
3280{
3281 u16 bank, i = 0;
3282 struct bnx2x *bp = params->bp;
ea4e040a 3283
c2c8b03e
EG		 3284 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3285 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3286 CL45_WR_OVER_CL22(bp, params->port,
3287 params->phy_addr,
3288 bank,
3289 MDIO_RX0_RX_EQ_BOOST,
3290 params->xgxs_config_rx[i]);
3291 }
3292
3293 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3294 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3295 CL45_WR_OVER_CL22(bp, params->port,
3296 params->phy_addr,
3297 bank,
3298 MDIO_TX0_TX_DRIVER,
3299 params->xgxs_config_tx[i]);
3300 }
3301}
57963ed9 3302
2f904460
EG		 3303
3304static void bnx2x_8481_set_led4(struct link_params *params,
3305 u32 ext_phy_type, u8 ext_phy_addr)
3306{
3307 struct bnx2x *bp = params->bp;
3308
3309 /* PHYC_CTL_LED_CTL */
3310 bnx2x_cl45_write(bp, params->port,
3311 ext_phy_type,
3312 ext_phy_addr,
3313 MDIO_PMA_DEVAD,
3314 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3315
3316 /* Unmask LED4 for 10G link */
3317 bnx2x_cl45_write(bp, params->port,
3318 ext_phy_type,
3319 ext_phy_addr,
3320 MDIO_PMA_DEVAD,
3321 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3322 /* 'Interrupt Mask' */
3323 bnx2x_cl45_write(bp, params->port,
3324 ext_phy_type,
3325 ext_phy_addr,
3326 MDIO_AN_DEVAD,
3327 0xFFFB, 0xFFFD);
3328}
3329static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3330 u32 ext_phy_type, u8 ext_phy_addr)
3331{
3332 struct bnx2x *bp = params->bp;
3333
3334 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3335 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3336 bnx2x_cl45_write(bp, params->port,
3337 ext_phy_type,
3338 ext_phy_addr,
3339 MDIO_AN_DEVAD,
3340 MDIO_AN_REG_8481_LEGACY_SHADOW,
3341 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3342}
3343
3344static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3345 u32 ext_phy_type, u8 ext_phy_addr)
3346{
3347 struct bnx2x *bp = params->bp;
3348 u16 val1;
3349
3350 /* LED1 (10G Link) */
3351 /* Enable continuse based on source 7(10G-link) */
3352 bnx2x_cl45_read(bp, params->port,
3353 ext_phy_type,
3354 ext_phy_addr,
3355 MDIO_PMA_DEVAD,
3356 MDIO_PMA_REG_8481_LINK_SIGNAL,
3357 &val1);
3358 /* Set bit 2 to 0, and bits [1:0] to 10 */
3359 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3360 val1 |= (1<<1); /* Set bit 1 */
3361
3362 bnx2x_cl45_write(bp, params->port,
3363 ext_phy_type,
3364 ext_phy_addr,
3365 MDIO_PMA_DEVAD,
3366 MDIO_PMA_REG_8481_LINK_SIGNAL,
3367 val1);
3368
3369 /* Unmask LED1 for 10G link */
3370 bnx2x_cl45_read(bp, params->port,
3371 ext_phy_type,
3372 ext_phy_addr,
3373 MDIO_PMA_DEVAD,
3374 MDIO_PMA_REG_8481_LED1_MASK,
3375 &val1);
3376 /* Set bit 2 to 0, and bits [1:0] to 10 */
3377 val1 |= (1<<7);
3378 bnx2x_cl45_write(bp, params->port,
3379 ext_phy_type,
3380 ext_phy_addr,
3381 MDIO_PMA_DEVAD,
3382 MDIO_PMA_REG_8481_LED1_MASK,
3383 val1);
3384
3385 /* LED2 (1G/100/10G Link) */
3386 /* Mask LED2 for 10G link */
3387 bnx2x_cl45_write(bp, params->port,
3388 ext_phy_type,
3389 ext_phy_addr,
3390 MDIO_PMA_DEVAD,
3391 MDIO_PMA_REG_8481_LED2_MASK,
3392 0);
3393
3394 /* LED3 (10G/1G/100/10G Activity) */
3395 bnx2x_cl45_read(bp, params->port,
3396 ext_phy_type,
3397 ext_phy_addr,
3398 MDIO_PMA_DEVAD,
3399 MDIO_PMA_REG_8481_LINK_SIGNAL,
3400 &val1);
3401 /* Enable blink based on source 4(Activity) */
3402 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3403 val1 |= (1<<6); /* Set only bit 6 */
3404 bnx2x_cl45_write(bp, params->port,
3405 ext_phy_type,
3406 ext_phy_addr,
3407 MDIO_PMA_DEVAD,
3408 MDIO_PMA_REG_8481_LINK_SIGNAL,
3409 val1);
3410
3411 bnx2x_cl45_read(bp, params->port,
3412 ext_phy_type,
3413 ext_phy_addr,
3414 MDIO_PMA_DEVAD,
3415 MDIO_PMA_REG_8481_LED3_MASK,
3416 &val1);
3417 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3418 bnx2x_cl45_write(bp, params->port,
3419 ext_phy_type,
3420 ext_phy_addr,
3421 MDIO_PMA_DEVAD,
3422 MDIO_PMA_REG_8481_LED3_MASK,
3423 val1);
3424}
3425
3426
57963ed9
YR		 3427static void bnx2x_init_internal_phy(struct link_params *params,
3428 struct link_vars *vars)
3429{
3430 struct bnx2x *bp = params->bp;
57963ed9 3431 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
c2c8b03e
EG		 3432 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3433 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3434 (params->feature_config_flags &
3435 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3436 bnx2x_set_preemphasis(params);
57963ed9
YR		 3437
3438 /* forced speed requested? */
3439 if (vars->line_speed != SPEED_AUTO_NEG) {
3440 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3441
3442 /* disable autoneg */
3443 bnx2x_set_autoneg(params, vars);
3444
3445 /* program speed and duplex */
8c99e7b0 3446 bnx2x_program_serdes(params, vars);
57963ed9
YR		 3447
3448 } else { /* AN_mode */
3449 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3450
3451 /* AN enabled */
3452 bnx2x_set_brcm_cl37_advertisment(params);
3453
3454 /* program duplex & pause advertisement (for aneg) */
3455 bnx2x_set_ieee_aneg_advertisment(params,
8c99e7b0 3456 vars->ieee_fc);
57963ed9
YR		 3457
3458 /* enable autoneg */
3459 bnx2x_set_autoneg(params, vars);
3460
3461 /* enable and restart AN */
3462 bnx2x_restart_autoneg(params);
3463 }
3464
3465 } else { /* SGMII mode */
3466 DP(NETIF_MSG_LINK, "SGMII\n");
3467
8c99e7b0 3468 bnx2x_initialize_sgmii_process(params, vars);
57963ed9
YR		 3469 }
3470}
3471
ea4e040a
YR		 3472static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3473{
3474 struct bnx2x *bp = params->bp;
3475 u32 ext_phy_type;
3476 u8 ext_phy_addr;
3477 u16 cnt;
3478 u16 ctrl = 0;
3479 u16 val = 0;
3480 u8 rc = 0;
3481 if (vars->phy_flags & PHY_XGXS_FLAG) {
3482 ext_phy_addr = ((params->ext_phy_config &
3483 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3484 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3485
3486 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3487 /* Make sure that the soft reset is off (expect for the 8072:
3488 * due to the lock, it will be done inside the specific
3489 * handling)
3490 */
3491 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3492 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3493 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3494 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3495 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3496 /* Wait for soft reset to get cleared upto 1 sec */
3497 for (cnt = 0; cnt < 1000; cnt++) {
3498 bnx2x_cl45_read(bp, params->port,
3499 ext_phy_type,
3500 ext_phy_addr,
3501 MDIO_PMA_DEVAD,
3502 MDIO_PMA_REG_CTRL, &ctrl);
3503 if (!(ctrl & (1<<15)))
3504 break;
3505 msleep(1);
3506 }
3507 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3508 ctrl, cnt);
3509 }
3510
3511 switch (ext_phy_type) {
3512 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
ea4e040a
YR		 3513 break;
3514
3515 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3516 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3517
3518 bnx2x_cl45_write(bp, params->port,
3519 ext_phy_type,
3520 ext_phy_addr,
3521 MDIO_PMA_DEVAD,
3522 MDIO_PMA_REG_MISC_CTRL,
3523 0x8288);
3524 bnx2x_cl45_write(bp, params->port,
3525 ext_phy_type,
3526 ext_phy_addr,
3527 MDIO_PMA_DEVAD,
3528 MDIO_PMA_REG_PHY_IDENTIFIER,
3529 0x7fbf);
3530 bnx2x_cl45_write(bp, params->port,
3531 ext_phy_type,
3532 ext_phy_addr,
3533 MDIO_PMA_DEVAD,
3534 MDIO_PMA_REG_CMU_PLL_BYPASS,
3535 0x0100);
3536 bnx2x_cl45_write(bp, params->port,
3537 ext_phy_type,
3538 ext_phy_addr,
3539 MDIO_WIS_DEVAD,
3540 MDIO_WIS_REG_LASI_CNTL, 0x1);
a35da8db 3541
3b313b61
EG		 3542 /* BCM8705 doesn't have microcode, hence the 0 */
3543 bnx2x_save_spirom_version(bp, params->port,
3544 params->shmem_base, 0);
ea4e040a
YR		 3545 break;
3546
3547 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
a35da8db
EG		 3548 /* Wait until fw is loaded */
3549 for (cnt = 0; cnt < 100; cnt++) {
3550 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3551 ext_phy_addr, MDIO_PMA_DEVAD,
3552 MDIO_PMA_REG_ROM_VER1, &val);
3553 if (val)
3554 break;
3555 msleep(10);
3556 }
3557 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3558 "after %d ms\n", cnt);
c2c8b03e
EG		 3559 if ((params->feature_config_flags &
3560 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3561 u8 i;
3562 u16 reg;
3563 for (i = 0; i < 4; i++) {
3564 reg = MDIO_XS_8706_REG_BANK_RX0 +
3565 i*(MDIO_XS_8706_REG_BANK_RX1 -
3566 MDIO_XS_8706_REG_BANK_RX0);
3567 bnx2x_cl45_read(bp, params->port,
3568 ext_phy_type,
3569 ext_phy_addr,
3570 MDIO_XS_DEVAD,
3571 reg, &val);
3572 /* Clear first 3 bits of the control */
3573 val &= ~0x7;
3574 /* Set control bits according to
3575 configuation */
3576 val |= (params->xgxs_config_rx[i] &
3577 0x7);
3578 DP(NETIF_MSG_LINK, "Setting RX"
3579 "Equalizer to BCM8706 reg 0x%x"
3580 " <-- val 0x%x\n", reg, val);
3581 bnx2x_cl45_write(bp, params->port,
3582 ext_phy_type,
3583 ext_phy_addr,
3584 MDIO_XS_DEVAD,
3585 reg, val);
3586 }
3587 }
ea4e040a
YR		 3588 /* Force speed */
3589 /* First enable LASI */
3590 bnx2x_cl45_write(bp, params->port,
3591 ext_phy_type,
3592 ext_phy_addr,
3593 MDIO_PMA_DEVAD,
3594 MDIO_PMA_REG_RX_ALARM_CTRL,
3595 0x0400);
3596 bnx2x_cl45_write(bp, params->port,
3597 ext_phy_type,
3598 ext_phy_addr,
3599 MDIO_PMA_DEVAD,
3600 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3601
3602 if (params->req_line_speed == SPEED_10000) {
3603 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3604
3605 bnx2x_cl45_write(bp, params->port,
3606 ext_phy_type,
3607 ext_phy_addr,
3608 MDIO_PMA_DEVAD,
3609 MDIO_PMA_REG_DIGITAL_CTRL,
3610 0x400);
3611 } else {
3612 /* Force 1Gbps using autoneg with 1G
3613 advertisment */
3614
3615 /* Allow CL37 through CL73 */
3616 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3617 bnx2x_cl45_write(bp, params->port,
3618 ext_phy_type,
3619 ext_phy_addr,
3620 MDIO_AN_DEVAD,
3621 MDIO_AN_REG_CL37_CL73,
3622 0x040c);
3623
3624 /* Enable Full-Duplex advertisment on CL37 */
3625 bnx2x_cl45_write(bp, params->port,
3626 ext_phy_type,
3627 ext_phy_addr,
3628 MDIO_AN_DEVAD,
8c99e7b0 3629 MDIO_AN_REG_CL37_FC_LP,
ea4e040a
YR		 3630 0x0020);
3631 /* Enable CL37 AN */
3632 bnx2x_cl45_write(bp, params->port,
3633 ext_phy_type,
3634 ext_phy_addr,
3635 MDIO_AN_DEVAD,
3636 MDIO_AN_REG_CL37_AN,
3637 0x1000);
3638 /* 1G support */
3639 bnx2x_cl45_write(bp, params->port,
3640 ext_phy_type,
3641 ext_phy_addr,
3642 MDIO_AN_DEVAD,
3643 MDIO_AN_REG_ADV, (1<<5));
3644
3645 /* Enable clause 73 AN */
3646 bnx2x_cl45_write(bp, params->port,
3647 ext_phy_type,
3648 ext_phy_addr,
3649 MDIO_AN_DEVAD,
3650 MDIO_AN_REG_CTRL,
3651 0x1200);
3652
3653 }
a35da8db
EG		 3654 bnx2x_save_bcm_spirom_ver(bp, params->port,
3655 ext_phy_type,
3656 ext_phy_addr,
3657 params->shmem_base);
ea4e040a 3658 break;
589abe3a
EG		 3659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3660 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3661 bnx2x_bcm8726_external_rom_boot(params);
3662
3663 /* Need to call module detected on initialization since
3664 the module detection triggered by actual module
3665 insertion might occur before driver is loaded, and when
3666 driver is loaded, it reset all registers, including the
3667 transmitter */
3668 bnx2x_sfp_module_detection(params);
4d295db0
EG		 3669
3670 /* Set Flow control */
3671 bnx2x_ext_phy_set_pause(params, vars);
589abe3a
EG		 3672 if (params->req_line_speed == SPEED_1000) {
3673 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3674 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3675 ext_phy_addr, MDIO_PMA_DEVAD,
3676 MDIO_PMA_REG_CTRL, 0x40);
3677 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3678 ext_phy_addr, MDIO_PMA_DEVAD,
3679 MDIO_PMA_REG_10G_CTRL2, 0xD);
3680 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3681 ext_phy_addr, MDIO_PMA_DEVAD,
3682 MDIO_PMA_REG_LASI_CTRL, 0x5);
3683 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3684 ext_phy_addr, MDIO_PMA_DEVAD,
3685 MDIO_PMA_REG_RX_ALARM_CTRL,
3686 0x400);
3687 } else if ((params->req_line_speed ==
3688 SPEED_AUTO_NEG) &&
3689 ((params->speed_cap_mask &
3690 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3691 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
3692 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3693 ext_phy_addr, MDIO_AN_DEVAD,
3694 MDIO_AN_REG_ADV, 0x20);
3695 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3696 ext_phy_addr, MDIO_AN_DEVAD,
3697 MDIO_AN_REG_CL37_CL73, 0x040c);
3698 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3699 ext_phy_addr, MDIO_AN_DEVAD,
3700 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3701 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3702 ext_phy_addr, MDIO_AN_DEVAD,
3703 MDIO_AN_REG_CL37_AN, 0x1000);
3704 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3705 ext_phy_addr, MDIO_AN_DEVAD,
3706 MDIO_AN_REG_CTRL, 0x1200);
3707
3708 /* Enable RX-ALARM control to receive
3709 interrupt for 1G speed change */
3710 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3711 ext_phy_addr, MDIO_PMA_DEVAD,
3712 MDIO_PMA_REG_LASI_CTRL, 0x4);
3713 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3714 ext_phy_addr, MDIO_PMA_DEVAD,
3715 MDIO_PMA_REG_RX_ALARM_CTRL,
3716 0x400);
ea4e040a 3717
589abe3a
EG		 3718 } else { /* Default 10G. Set only LASI control */
3719 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3720 ext_phy_addr, MDIO_PMA_DEVAD,
3721 MDIO_PMA_REG_LASI_CTRL, 1);
3722 }
c2c8b03e
EG		 3723
3724 /* Set TX PreEmphasis if needed */
3725 if ((params->feature_config_flags &
3726 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3727 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3728 "TX_CTRL2 0x%x\n",
3729 params->xgxs_config_tx[0],
3730 params->xgxs_config_tx[1]);
3731 bnx2x_cl45_write(bp, params->port,
3732 ext_phy_type,
3733 ext_phy_addr,
3734 MDIO_PMA_DEVAD,
3735 MDIO_PMA_REG_8726_TX_CTRL1,
3736 params->xgxs_config_tx[0]);
3737
3738 bnx2x_cl45_write(bp, params->port,
3739 ext_phy_type,
3740 ext_phy_addr,
3741 MDIO_PMA_DEVAD,
3742 MDIO_PMA_REG_8726_TX_CTRL2,
3743 params->xgxs_config_tx[1]);
3744 }
589abe3a 3745 break;
ea4e040a
YR		 3746 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3747 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3748 {
3749 u16 tmp1;
3750 u16 rx_alarm_ctrl_val;
3751 u16 lasi_ctrl_val;
3752 if (ext_phy_type ==
3753 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3754 rx_alarm_ctrl_val = 0x400;
3755 lasi_ctrl_val = 0x0004;
3756 } else {
ea4e040a 3757 rx_alarm_ctrl_val = (1<<2);
ea4e040a
YR		 3758 lasi_ctrl_val = 0x0004;
3759 }
3760
6bbca910
YR		 3761 /* enable LASI */
3762 bnx2x_cl45_write(bp, params->port,
3763 ext_phy_type,
3764 ext_phy_addr,
3765 MDIO_PMA_DEVAD,
3766 MDIO_PMA_REG_RX_ALARM_CTRL,
3767 rx_alarm_ctrl_val);
3768
3769 bnx2x_cl45_write(bp, params->port,
3770 ext_phy_type,
3771 ext_phy_addr,
3772 MDIO_PMA_DEVAD,
3773 MDIO_PMA_REG_LASI_CTRL,
3774 lasi_ctrl_val);
3775
3776 bnx2x_8073_set_pause_cl37(params, vars);
ea4e040a
YR		 3777
3778 if (ext_phy_type ==
3779 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
3780 bnx2x_bcm8072_external_rom_boot(params);
3781 } else {
6bbca910 3782
ea4e040a
YR		 3783 /* In case of 8073 with long xaui lines,
3784 don't set the 8073 xaui low power*/
3785 bnx2x_bcm8073_set_xaui_low_power_mode(params);
3786 }
3787
6bbca910
YR		 3788 bnx2x_cl45_read(bp, params->port,
3789 ext_phy_type,
3790 ext_phy_addr,
3791 MDIO_PMA_DEVAD,
052a38e0 3792 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910 3793 &tmp1);
ea4e040a
YR		 3794
3795 bnx2x_cl45_read(bp, params->port,
3796 ext_phy_type,
3797 ext_phy_addr,
3798 MDIO_PMA_DEVAD,
3799 MDIO_PMA_REG_RX_ALARM, &tmp1);
3800
3801 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3802 "0x%x\n", tmp1);
3803
3804 /* If this is forced speed, set to KR or KX
3805 * (all other are not supported)
3806 */
6bbca910
YR		 3807 if (params->loopback_mode == LOOPBACK_EXT) {
3808 bnx2x_bcm807x_force_10G(params);
3809 DP(NETIF_MSG_LINK,
3810 "Forced speed 10G on 807X\n");
3811 break;
3812 } else {
3813 bnx2x_cl45_write(bp, params->port,
3814 ext_phy_type, ext_phy_addr,
3815 MDIO_PMA_DEVAD,
3816 MDIO_PMA_REG_BCM_CTRL,
3817 0x0002);
3818 }
3819 if (params->req_line_speed != SPEED_AUTO_NEG) {
3820 if (params->req_line_speed == SPEED_10000) {
3821 val = (1<<7);
ea4e040a
YR		 3822 } else if (params->req_line_speed ==
3823 SPEED_2500) {
3824 val = (1<<5);
3825 /* Note that 2.5G works only
3826 when used with 1G advertisment */
3827 } else
3828 val = (1<<5);
3829 } else {
3830
3831 val = 0;
3832 if (params->speed_cap_mask &
3833 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3834 val |= (1<<7);
3835
6bbca910
YR		 3836 /* Note that 2.5G works only when
3837 used with 1G advertisment */
ea4e040a 3838 if (params->speed_cap_mask &
6bbca910
YR		 3839 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3840 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
ea4e040a 3841 val |= (1<<5);
6bbca910
YR		 3842 DP(NETIF_MSG_LINK,
3843 "807x autoneg val = 0x%x\n", val);
ea4e040a
YR		 3844 }
3845
3846 bnx2x_cl45_write(bp, params->port,
3847 ext_phy_type,
3848 ext_phy_addr,
3849 MDIO_AN_DEVAD,
3850 MDIO_AN_REG_ADV, val);
3851
3852 if (ext_phy_type ==
3853 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 3854
ea4e040a
YR		 3855 bnx2x_cl45_read(bp, params->port,
3856 ext_phy_type,
3857 ext_phy_addr,
3858 MDIO_AN_DEVAD,
052a38e0 3859 MDIO_AN_REG_8073_2_5G, &tmp1);
6bbca910
YR		 3860
3861 if (((params->speed_cap_mask &
3862 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3863 (params->req_line_speed ==
3864 SPEED_AUTO_NEG)) ||
3865 (params->req_line_speed ==
3866 SPEED_2500)) {
ea4e040a
YR		 3867 u16 phy_ver;
3868 /* Allow 2.5G for A1 and above */
3869 bnx2x_cl45_read(bp, params->port,
3870 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3871 ext_phy_addr,
3872 MDIO_PMA_DEVAD,
052a38e0 3873 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
6bbca910 3874 DP(NETIF_MSG_LINK, "Add 2.5G\n");
ea4e040a
YR		 3875 if (phy_ver > 0)
3876 tmp1 |= 1;
3877 else
3878 tmp1 &= 0xfffe;
6bbca910
YR		 3879 } else {
3880 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
ea4e040a 3881 tmp1 &= 0xfffe;
6bbca910 3882 }
ea4e040a 3883
6bbca910
YR		 3884 bnx2x_cl45_write(bp, params->port,
3885 ext_phy_type,
3886 ext_phy_addr,
3887 MDIO_AN_DEVAD,
052a38e0 3888 MDIO_AN_REG_8073_2_5G, tmp1);
ea4e040a 3889 }
6bbca910
YR		 3890
3891 /* Add support for CL37 (passive mode) II */
3892
3893 bnx2x_cl45_read(bp, params->port,
ea4e040a
YR		 3894 ext_phy_type,
3895 ext_phy_addr,
3896 MDIO_AN_DEVAD,
6bbca910
YR		 3897 MDIO_AN_REG_CL37_FC_LD,
3898 &tmp1);
3899
ea4e040a
YR		 3900 bnx2x_cl45_write(bp, params->port,
3901 ext_phy_type,
3902 ext_phy_addr,
3903 MDIO_AN_DEVAD,
6bbca910
YR		 3904 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
3905 ((params->req_duplex == DUPLEX_FULL) ?
3906 0x20 : 0x40)));
3907
ea4e040a
YR		 3908 /* Add support for CL37 (passive mode) III */
3909 bnx2x_cl45_write(bp, params->port,
3910 ext_phy_type,
3911 ext_phy_addr,
3912 MDIO_AN_DEVAD,
3913 MDIO_AN_REG_CL37_AN, 0x1000);
ea4e040a
YR		 3914
3915 if (ext_phy_type ==
3916 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 3917 /* The SNR will improve about 2db by changing
ea4e040a
YR		 3918 BW and FEE main tap. Rest commands are executed
3919 after link is up*/
6bbca910 3920 /*Change FFE main cursor to 5 in EDC register*/
ea4e040a
YR		 3921 if (bnx2x_8073_is_snr_needed(params))
3922 bnx2x_cl45_write(bp, params->port,
3923 ext_phy_type,
3924 ext_phy_addr,
3925 MDIO_PMA_DEVAD,
3926 MDIO_PMA_REG_EDC_FFE_MAIN,
3927 0xFB0C);
3928
6bbca910
YR		 3929 /* Enable FEC (Forware Error Correction)
3930 Request in the AN */
3931 bnx2x_cl45_read(bp, params->port,
3932 ext_phy_type,
3933 ext_phy_addr,
3934 MDIO_AN_DEVAD,
3935 MDIO_AN_REG_ADV2, &tmp1);
ea4e040a 3936
6bbca910
YR		 3937 tmp1 |= (1<<15);
3938
3939 bnx2x_cl45_write(bp, params->port,
3940 ext_phy_type,
3941 ext_phy_addr,
3942 MDIO_AN_DEVAD,
3943 MDIO_AN_REG_ADV2, tmp1);
ea4e040a 3944
ea4e040a
YR		 3945 }
3946
3947 bnx2x_ext_phy_set_pause(params, vars);
3948
6bbca910
YR		 3949 /* Restart autoneg */
3950 msleep(500);
ea4e040a
YR		 3951 bnx2x_cl45_write(bp, params->port,
3952 ext_phy_type,
3953 ext_phy_addr,
3954 MDIO_AN_DEVAD,
3955 MDIO_AN_REG_CTRL, 0x1200);
3956 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
3957 "Advertise 1G=%x, 10G=%x\n",
3958 ((val & (1<<5)) > 0),
3959 ((val & (1<<7)) > 0));
3960 break;
3961 }
4d295db0
EG		 3962
3963 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
a35da8db 3964 {
4d295db0
EG		 3965 u16 tmp1;
3966 u16 rx_alarm_ctrl_val;
3967 u16 lasi_ctrl_val;
ea4e040a 3968
4d295db0
EG		 3969 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
3970
3971 u16 mod_abs;
3972 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
3973 lasi_ctrl_val = 0x0004;
3974
3975 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
3976 /* enable LASI */
ea4e040a
YR		 3977 bnx2x_cl45_write(bp, params->port,
3978 ext_phy_type,
3979 ext_phy_addr,
3980 MDIO_PMA_DEVAD,
4d295db0
EG		 3981 MDIO_PMA_REG_RX_ALARM_CTRL,
3982 rx_alarm_ctrl_val);
3983
ea4e040a
YR		 3984 bnx2x_cl45_write(bp, params->port,
3985 ext_phy_type,
3986 ext_phy_addr,
3987 MDIO_PMA_DEVAD,
4d295db0
EG		 3988 MDIO_PMA_REG_LASI_CTRL,
3989 lasi_ctrl_val);
ea4e040a 3990
4d295db0
EG		 3991 /* Initially configure MOD_ABS to interrupt when
3992 module is presence( bit 8) */
ea4e040a
YR		 3993 bnx2x_cl45_read(bp, params->port,
3994 ext_phy_type,
3995 ext_phy_addr,
4d295db0
EG		 3996 MDIO_PMA_DEVAD,
3997 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
3998 /* Set EDC off by setting OPTXLOS signal input to low
3999 (bit 9).
4000 When the EDC is off it locks onto a reference clock and
4001 avoids becoming 'lost'.*/
4002 mod_abs &= ~((1<<8) | (1<<9));
ea4e040a
YR		 4003 bnx2x_cl45_write(bp, params->port,
4004 ext_phy_type,
4005 ext_phy_addr,
4d295db0
EG		 4006 MDIO_PMA_DEVAD,
4007 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
28577185 4008
4d295db0
EG		 4009 /* Make MOD_ABS give interrupt on change */
4010 bnx2x_cl45_read(bp, params->port,
4011 ext_phy_type,
4012 ext_phy_addr,
4013 MDIO_PMA_DEVAD,
4014 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4015 &val);
4016 val |= (1<<12);
4017 bnx2x_cl45_write(bp, params->port,
4018 ext_phy_type,
4019 ext_phy_addr,
4020 MDIO_PMA_DEVAD,
4021 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4022 val);
4023
4024 /* Set 8727 GPIOs to input to allow reading from the
4025 8727 GPIO0 status which reflect SFP+ module
4026 over-current */
4027
4028 bnx2x_cl45_read(bp, params->port,
4029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4030 ext_phy_addr,
4031 MDIO_PMA_DEVAD,
4032 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4033 &val);
4034 val &= 0xff8f; /* Reset bits 4-6 */
4035 bnx2x_cl45_write(bp, params->port,
4036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4037 ext_phy_addr,
4038 MDIO_PMA_DEVAD,
4039 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4040 val);
4041
4042 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4043 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4044
4045 bnx2x_cl45_read(bp, params->port,
4046 ext_phy_type,
4047 ext_phy_addr,
4048 MDIO_PMA_DEVAD,
4049 MDIO_PMA_REG_M8051_MSGOUT_REG,
4050 &tmp1);
4051
4052 bnx2x_cl45_read(bp, params->port,
4053 ext_phy_type,
4054 ext_phy_addr,
4055 MDIO_PMA_DEVAD,
4056 MDIO_PMA_REG_RX_ALARM, &tmp1);
4057
4058 /* Set option 1G speed */
4059 if (params->req_line_speed == SPEED_1000) {
4060
4061 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4062 bnx2x_cl45_write(bp, params->port,
4063 ext_phy_type,
4064 ext_phy_addr,
4065 MDIO_PMA_DEVAD,
4066 MDIO_PMA_REG_CTRL, 0x40);
4067 bnx2x_cl45_write(bp, params->port,
4068 ext_phy_type,
4069 ext_phy_addr,
4070 MDIO_PMA_DEVAD,
4071 MDIO_PMA_REG_10G_CTRL2, 0xD);
4072 bnx2x_cl45_read(bp, params->port,
4073 ext_phy_type,
4074 ext_phy_addr,
4075 MDIO_PMA_DEVAD,
4076 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4077 DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
4078
4079 } else if ((params->req_line_speed ==
4080 SPEED_AUTO_NEG) &&
4081 ((params->speed_cap_mask &
4082 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
4083
4084 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
4085 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4086 ext_phy_addr, MDIO_AN_DEVAD,
4087 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4088 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4089 ext_phy_addr, MDIO_AN_DEVAD,
4090 MDIO_AN_REG_CL37_AN, 0x1300);
4091 } else {
4092 /* Since the 8727 has only single reset pin,
4093 need to set the 10G registers although it is
4094 default */
4095 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4096 ext_phy_addr, MDIO_AN_DEVAD,
4097 MDIO_AN_REG_CTRL, 0x0020);
4098 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4099 ext_phy_addr, MDIO_AN_DEVAD,
4100 0x7, 0x0100);
4101 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4102 ext_phy_addr, MDIO_PMA_DEVAD,
4103 MDIO_PMA_REG_CTRL, 0x2040);
4104 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4105 ext_phy_addr, MDIO_PMA_DEVAD,
4106 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4107 }
4108
4109 /* Set 2-wire transfer rate to 400Khz since 100Khz
4110 is not operational */
4111 bnx2x_cl45_write(bp, params->port,
4112 ext_phy_type,
4113 ext_phy_addr,
4114 MDIO_PMA_DEVAD,
4115 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4116 0xa101);
4117
4118 /* Set TX PreEmphasis if needed */
4119 if ((params->feature_config_flags &
4120 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4121 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4122 "TX_CTRL2 0x%x\n",
4123 params->xgxs_config_tx[0],
4124 params->xgxs_config_tx[1]);
4125 bnx2x_cl45_write(bp, params->port,
4126 ext_phy_type,
4127 ext_phy_addr,
4128 MDIO_PMA_DEVAD,
4129 MDIO_PMA_REG_8727_TX_CTRL1,
4130 params->xgxs_config_tx[0]);
4131
4132 bnx2x_cl45_write(bp, params->port,
4133 ext_phy_type,
4134 ext_phy_addr,
4135 MDIO_PMA_DEVAD,
4136 MDIO_PMA_REG_8727_TX_CTRL2,
4137 params->xgxs_config_tx[1]);
4138 }
4139
4140 break;
4141 }
4142
4143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4144 {
4145 u16 fw_ver1, fw_ver2;
4146 DP(NETIF_MSG_LINK,
4147 "Setting the SFX7101 LASI indication\n");
4148
4149 bnx2x_cl45_write(bp, params->port,
4150 ext_phy_type,
4151 ext_phy_addr,
4152 MDIO_PMA_DEVAD,
4153 MDIO_PMA_REG_LASI_CTRL, 0x1);
4154 DP(NETIF_MSG_LINK,
4155 "Setting the SFX7101 LED to blink on traffic\n");
4156 bnx2x_cl45_write(bp, params->port,
4157 ext_phy_type,
4158 ext_phy_addr,
4159 MDIO_PMA_DEVAD,
4160 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4161
4162 bnx2x_ext_phy_set_pause(params, vars);
4163 /* Restart autoneg */
4164 bnx2x_cl45_read(bp, params->port,
4165 ext_phy_type,
4166 ext_phy_addr,
4167 MDIO_AN_DEVAD,
4168 MDIO_AN_REG_CTRL, &val);
4169 val |= 0x200;
4170 bnx2x_cl45_write(bp, params->port,
4171 ext_phy_type,
4172 ext_phy_addr,
4173 MDIO_AN_DEVAD,
4174 MDIO_AN_REG_CTRL, val);
4175
4176 /* Save spirom version */
4177 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4178 ext_phy_addr, MDIO_PMA_DEVAD,
4179 MDIO_PMA_REG_7101_VER1, &fw_ver1);
a35da8db
EG		 4180
4181 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4182 ext_phy_addr, MDIO_PMA_DEVAD,
4183 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4184
4185 bnx2x_save_spirom_version(params->bp, params->port,
4186 params->shmem_base,
4187 (u32)(fw_ver1<<16 | fw_ver2));
4188
28577185 4189 break;
a35da8db 4190 }
28577185 4191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2f904460
EG		 4192 /* This phy uses the NIG latch mechanism since link
4193 indication arrives through its LED4 and not via
4194 its LASI signal, so we get steady signal
4195 instead of clear on read */
4196 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4197 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4198
4199 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4200 if (params->req_line_speed == SPEED_AUTO_NEG) {
4201
4202 u16 autoneg_val, an_1000_val, an_10_100_val;
4203 /* set 1000 speed advertisement */
4204 bnx2x_cl45_read(bp, params->port,
4205 ext_phy_type,
4206 ext_phy_addr,
4207 MDIO_AN_DEVAD,
4208 MDIO_AN_REG_8481_1000T_CTRL,
4209 &an_1000_val);
28577185 4210
2f904460
EG		 4211 if (params->speed_cap_mask &
4212 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4213 an_1000_val |= (1<<8);
4214 if (params->req_duplex == DUPLEX_FULL)
4215 an_1000_val |= (1<<9);
4216 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4217 } else
4218 an_1000_val &= ~((1<<8) | (1<<9));
28577185 4219
2f904460
EG		 4220 bnx2x_cl45_write(bp, params->port,
4221 ext_phy_type,
4222 ext_phy_addr,
4223 MDIO_AN_DEVAD,
4224 MDIO_AN_REG_8481_1000T_CTRL,
4225 an_1000_val);
4226
4227 /* set 100 speed advertisement */
4228 bnx2x_cl45_read(bp, params->port,
4229 ext_phy_type,
4230 ext_phy_addr,
4231 MDIO_AN_DEVAD,
4232 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4233 &an_10_100_val);
4234
4235 if (params->speed_cap_mask &
4236 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4237 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4238 an_10_100_val |= (1<<7);
4239 if (params->req_duplex == DUPLEX_FULL)
4240 an_10_100_val |= (1<<8);
4241 DP(NETIF_MSG_LINK,
4242 "Advertising 100M\n");
4243 } else
4244 an_10_100_val &= ~((1<<7) | (1<<8));
4245
4246 /* set 10 speed advertisement */
4247 if (params->speed_cap_mask &
4248 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4250 an_10_100_val |= (1<<5);
4251 if (params->req_duplex == DUPLEX_FULL)
4252 an_10_100_val |= (1<<6);
4253 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4254 }
4255 else
4256 an_10_100_val &= ~((1<<5) | (1<<6));
4257
4258 bnx2x_cl45_write(bp, params->port,
4259 ext_phy_type,
4260 ext_phy_addr,
4261 MDIO_AN_DEVAD,
4262 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4263 an_10_100_val);
4264
4265 bnx2x_cl45_read(bp, params->port,
4266 ext_phy_type,
4267 ext_phy_addr,
4268 MDIO_AN_DEVAD,
4269 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4270 &autoneg_val);
4271
4272 /* Disable forced speed */
4273 autoneg_val &= ~(1<<6|1<<13);
4274
4275 /* Enable autoneg and restart autoneg
4276 for legacy speeds */
4277 autoneg_val |= (1<<9|1<<12);
4278
4279 if (params->req_duplex == DUPLEX_FULL)
4280 autoneg_val |= (1<<8);
4281 else
4282 autoneg_val &= ~(1<<8);
4283
4284 bnx2x_cl45_write(bp, params->port,
4285 ext_phy_type,
4286 ext_phy_addr,
4287 MDIO_AN_DEVAD,
4288 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4289 autoneg_val);
4290
4291 if (params->speed_cap_mask &
4292 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4293 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4294 /* Restart autoneg for 10G*/
28577185
EG		 4295 bnx2x_cl45_read(bp, params->port,
4296 ext_phy_type,
4297 ext_phy_addr,
4298 MDIO_AN_DEVAD,
4299 MDIO_AN_REG_CTRL, &val);
4300 val |= 0x200;
4301 bnx2x_cl45_write(bp, params->port,
4302 ext_phy_type,
4303 ext_phy_addr,
4304 MDIO_AN_DEVAD,
4305 MDIO_AN_REG_CTRL, val);
2f904460
EG		 4306 }
4307 } else {
4308 /* Force speed */
4309 u16 autoneg_ctrl, pma_ctrl;
4310 bnx2x_cl45_read(bp, params->port,
4311 ext_phy_type,
4312 ext_phy_addr,
4313 MDIO_AN_DEVAD,
4314 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4315 &autoneg_ctrl);
4316
4317 /* Disable autoneg */
4318 autoneg_ctrl &= ~(1<<12);
4319
4320 /* Set 1000 force */
4321 switch (params->req_line_speed) {
4322 case SPEED_10000:
4323 DP(NETIF_MSG_LINK,
4324 "Unable to set 10G force !\n");
4325 break;
4326 case SPEED_1000:
4327 bnx2x_cl45_read(bp, params->port,
4328 ext_phy_type,
4329 ext_phy_addr,
4330 MDIO_PMA_DEVAD,
4331 MDIO_PMA_REG_CTRL,
4332 &pma_ctrl);
4333 autoneg_ctrl &= ~(1<<13);
4334 autoneg_ctrl |= (1<<6);
4335 pma_ctrl &= ~(1<<13);
4336 pma_ctrl |= (1<<6);
4337 DP(NETIF_MSG_LINK,
4338 "Setting 1000M force\n");
4339 bnx2x_cl45_write(bp, params->port,
4340 ext_phy_type,
4341 ext_phy_addr,
4342 MDIO_PMA_DEVAD,
4343 MDIO_PMA_REG_CTRL,
4344 pma_ctrl);
4345 break;
4346 case SPEED_100:
4347 autoneg_ctrl |= (1<<13);
4348 autoneg_ctrl &= ~(1<<6);
4349 DP(NETIF_MSG_LINK,
4350 "Setting 100M force\n");
4351 break;
4352 case SPEED_10:
4353 autoneg_ctrl &= ~(1<<13);
4354 autoneg_ctrl &= ~(1<<6);
4355 DP(NETIF_MSG_LINK,
4356 "Setting 10M force\n");
4357 break;
4358 }
4359
4360 /* Duplex mode */
4361 if (params->req_duplex == DUPLEX_FULL) {
4362 autoneg_ctrl |= (1<<8);
4363 DP(NETIF_MSG_LINK,
4364 "Setting full duplex\n");
4365 } else
4366 autoneg_ctrl &= ~(1<<8);
4367
4368 /* Update autoneg ctrl and pma ctrl */
4369 bnx2x_cl45_write(bp, params->port,
4370 ext_phy_type,
4371 ext_phy_addr,
4372 MDIO_AN_DEVAD,
4373 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4374 autoneg_ctrl);
4375 }
28577185 4376
b1607af5
EG		 4377 /* Save spirom version */
4378 bnx2x_save_8481_spirom_version(bp, params->port,
4379 ext_phy_addr,
4380 params->shmem_base);
ea4e040a
YR		 4381 break;
4382 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4383 DP(NETIF_MSG_LINK,
4384 "XGXS PHY Failure detected 0x%x\n",
4385 params->ext_phy_config);
4386 rc = -EINVAL;
4387 break;
4388 default:
4389 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4390 params->ext_phy_config);
4391 rc = -EINVAL;
4392 break;
4393 }
4394
4395 } else { /* SerDes */
57963ed9 4396
ea4e040a
YR		 4397 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4398 switch (ext_phy_type) {
4399 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4400 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4401 break;
4402
4403 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4404 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4405 break;
4406
4407 default:
4408 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4409 params->ext_phy_config);
4410 break;
4411 }
4412 }
4413 return rc;
4414}
4415
4d295db0
EG		 4416static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4417{
4418 struct bnx2x *bp = params->bp;
4419 u16 mod_abs, rx_alarm_status;
4420 u8 ext_phy_addr = ((params->ext_phy_config &
4421 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4422 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4423 u32 val = REG_RD(bp, params->shmem_base +
4424 offsetof(struct shmem_region, dev_info.
4425 port_feature_config[params->port].
4426 config));
4427 bnx2x_cl45_read(bp, params->port,
4428 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4429 ext_phy_addr,
4430 MDIO_PMA_DEVAD,
4431 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4432 if (mod_abs & (1<<8)) {
4433
4434 /* Module is absent */
4435 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4436 "show module is absent\n");
4437
4438 /* 1. Set mod_abs to detect next module
4439 presence event
4440 2. Set EDC off by setting OPTXLOS signal input to low
4441 (bit 9).
4442 When the EDC is off it locks onto a reference clock and
4443 avoids becoming 'lost'.*/
4444 mod_abs &= ~((1<<8)|(1<<9));
4445 bnx2x_cl45_write(bp, params->port,
4446 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4447 ext_phy_addr,
4448 MDIO_PMA_DEVAD,
4449 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4450
4451 /* Clear RX alarm since it stays up as long as
4452 the mod_abs wasn't changed */
4453 bnx2x_cl45_read(bp, params->port,
4454 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4455 ext_phy_addr,
4456 MDIO_PMA_DEVAD,
4457 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4458
4459 } else {
4460 /* Module is present */
4461 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4462 "show module is present\n");
4463 /* First thing, disable transmitter,
4464 and if the module is ok, the
4465 module_detection will enable it*/
4466
4467 /* 1. Set mod_abs to detect next module
4468 absent event ( bit 8)
4469 2. Restore the default polarity of the OPRXLOS signal and
4470 this signal will then correctly indicate the presence or
4471 absence of the Rx signal. (bit 9) */
4472 mod_abs |= ((1<<8)|(1<<9));
4473 bnx2x_cl45_write(bp, params->port,
4474 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4475 ext_phy_addr,
4476 MDIO_PMA_DEVAD,
4477 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4478
4479 /* Clear RX alarm since it stays up as long as
4480 the mod_abs wasn't changed. This is need to be done
4481 before calling the module detection, otherwise it will clear
4482 the link update alarm */
4483 bnx2x_cl45_read(bp, params->port,
4484 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4485 ext_phy_addr,
4486 MDIO_PMA_DEVAD,
4487 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4488
4489
4490 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4491 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4492 bnx2x_sfp_set_transmitter(bp, params->port,
4493 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4494 ext_phy_addr, 0);
4495
4496 if (bnx2x_wait_for_sfp_module_initialized(params)
4497 == 0)
4498 bnx2x_sfp_module_detection(params);
4499 else
4500 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4501 }
4502
4503 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4504 rx_alarm_status);
4505 /* No need to check link status in case of
4506 module plugged in/out */
4507}
4508
ea4e040a
YR		 4509
4510static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2f904460
EG		 4511 struct link_vars *vars,
4512 u8 is_mi_int)
ea4e040a
YR		 4513{
4514 struct bnx2x *bp = params->bp;
4515 u32 ext_phy_type;
4516 u8 ext_phy_addr;
4517 u16 val1 = 0, val2;
4518 u16 rx_sd, pcs_status;
4519 u8 ext_phy_link_up = 0;
4520 u8 port = params->port;
4521 if (vars->phy_flags & PHY_XGXS_FLAG) {
4522 ext_phy_addr = ((params->ext_phy_config &
4523 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4524 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4525
4526 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4527 switch (ext_phy_type) {
4528 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4529 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4530 ext_phy_link_up = 1;
4531 break;
4532
4533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4534 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4535 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4536 ext_phy_addr,
4537 MDIO_WIS_DEVAD,
4538 MDIO_WIS_REG_LASI_STATUS, &val1);
4539 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4540
4541 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4542 ext_phy_addr,
4543 MDIO_WIS_DEVAD,
4544 MDIO_WIS_REG_LASI_STATUS, &val1);
4545 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4546
4547 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4548 ext_phy_addr,
4549 MDIO_PMA_DEVAD,
4550 MDIO_PMA_REG_RX_SD, &rx_sd);
4d295db0
EG		 4551
4552 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4553 ext_phy_addr,
4554 1,
4555 0xc809, &val1);
4556 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4557 ext_phy_addr,
4558 1,
4559 0xc809, &val1);
4560
4561 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4562 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
4563 && ((val1 & (1<<8)) == 0));
8c99e7b0
YR		 4564 if (ext_phy_link_up)
4565 vars->line_speed = SPEED_10000;
ea4e040a
YR		 4566 break;
4567
4568 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a
EG		 4569 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4570 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4571 /* Clear RX Alarm*/
ea4e040a
YR		 4572 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4573 ext_phy_addr,
589abe3a
EG		 4574 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4575 &val2);
4576 /* clear LASI indication*/
ea4e040a
YR		 4577 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4578 ext_phy_addr,
589abe3a
EG		 4579 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4580 &val1);
4581 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4582 ext_phy_addr,
4583 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4584 &val2);
4585 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4586 "0x%x\n", val1, val2);
ea4e040a
YR		 4587
4588 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4589 ext_phy_addr,
589abe3a
EG		 4590 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4591 &rx_sd);
ea4e040a
YR		 4592 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4593 ext_phy_addr,
589abe3a
EG		 4594 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4595 &pcs_status);
ea4e040a
YR		 4596 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4597 ext_phy_addr,
589abe3a
EG		 4598 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4599 &val2);
ea4e040a
YR		 4600 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4601 ext_phy_addr,
589abe3a
EG		 4602 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4603 &val2);
ea4e040a 4604
589abe3a 4605 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
ea4e040a
YR		 4606 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4607 rx_sd, pcs_status, val2);
4608 /* link is up if both bit 0 of pmd_rx_sd and
4609 * bit 0 of pcs_status are set, or if the autoneg bit
4610 1 is set
4611 */
4612 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4613 (val2 & (1<<1)));
57963ed9 4614 if (ext_phy_link_up) {
589abe3a
EG		 4615 if (ext_phy_type ==
4616 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4617 /* If transmitter is disabled,
4618 ignore false link up indication */
4619 bnx2x_cl45_read(bp, params->port,
4620 ext_phy_type,
4621 ext_phy_addr,
4622 MDIO_PMA_DEVAD,
4623 MDIO_PMA_REG_PHY_IDENTIFIER,
4624 &val1);
4625 if (val1 & (1<<15)) {
4626 DP(NETIF_MSG_LINK, "Tx is "
4627 "disabled\n");
4628 ext_phy_link_up = 0;
4629 break;
4630 }
4631 }
4632
57963ed9
YR		 4633 if (val2 & (1<<1))
4634 vars->line_speed = SPEED_1000;
4635 else
4636 vars->line_speed = SPEED_10000;
4637 }
4d295db0
EG		 4638 break;
4639
4640 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4641 {
4642 u16 link_status = 0;
4643 u16 rx_alarm_status;
4644 /* Check the LASI */
4645 bnx2x_cl45_read(bp, params->port,
4646 ext_phy_type,
4647 ext_phy_addr,
4648 MDIO_PMA_DEVAD,
4649 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4650
4651 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4652 rx_alarm_status);
4653
4654 bnx2x_cl45_read(bp, params->port,
4655 ext_phy_type,
4656 ext_phy_addr,
4657 MDIO_PMA_DEVAD,
4658 MDIO_PMA_REG_LASI_STATUS, &val1);
4659
4660 DP(NETIF_MSG_LINK,
4661 "8727 LASI status 0x%x\n",
4662 val1);
4663
4664 /* Clear MSG-OUT */
4665 bnx2x_cl45_read(bp, params->port,
4666 ext_phy_type,
4667 ext_phy_addr,
4668 MDIO_PMA_DEVAD,
4669 MDIO_PMA_REG_M8051_MSGOUT_REG,
4670 &val1);
4671
4672 /*
4673 * If a module is present and there is need to check
4674 * for over current
4675 */
4676 if (!(params->feature_config_flags &
4677 FEATURE_CONFIG_BCM8727_NOC) &&
4678 !(rx_alarm_status & (1<<5))) {
4679 /* Check over-current using 8727 GPIO0 input*/
4680 bnx2x_cl45_read(bp, params->port,
4681 ext_phy_type,
4682 ext_phy_addr,
4683 MDIO_PMA_DEVAD,
4684 MDIO_PMA_REG_8727_GPIO_CTRL,
4685 &val1);
4686
4687 if ((val1 & (1<<8)) == 0) {
4688 DP(NETIF_MSG_LINK, "8727 Power fault"
4689 " has been detected on port"
4690 " %d\n", params->port);
4691 printk(KERN_ERR PFX "Error: Power"
4692 " fault on %s Port %d has"
4693 " been detected and the"
4694 " power to that SFP+ module"
4695 " has been removed to prevent"
4696 " failure of the card. Please"
4697 " remove the SFP+ module and"
4698 " restart the system to clear"
4699 " this error.\n"
4700 , bp->dev->name, params->port);
4701 /*
4702 * Disable all RX_ALARMs except for
4703 * mod_abs
4704 */
4705 bnx2x_cl45_write(bp, params->port,
4706 ext_phy_type,
4707 ext_phy_addr,
4708 MDIO_PMA_DEVAD,
4709 MDIO_PMA_REG_RX_ALARM_CTRL,
4710 (1<<5));
4711
4712 bnx2x_cl45_read(bp, params->port,
4713 ext_phy_type,
4714 ext_phy_addr,
4715 MDIO_PMA_DEVAD,
4716 MDIO_PMA_REG_PHY_IDENTIFIER,
4717 &val1);
4718 /* Wait for module_absent_event */
4719 val1 |= (1<<8);
4720 bnx2x_cl45_write(bp, params->port,
4721 ext_phy_type,
4722 ext_phy_addr,
4723 MDIO_PMA_DEVAD,
4724 MDIO_PMA_REG_PHY_IDENTIFIER,
4725 val1);
4726 /* Clear RX alarm */
4727 bnx2x_cl45_read(bp, params->port,
4728 ext_phy_type,
4729 ext_phy_addr,
4730 MDIO_PMA_DEVAD,
4731 MDIO_PMA_REG_RX_ALARM,
4732 &rx_alarm_status);
4733 break;
4734 }
4735 } /* Over current check */
4736
4737 /* When module absent bit is set, check module */
4738 if (rx_alarm_status & (1<<5)) {
4739 bnx2x_8727_handle_mod_abs(params);
4740 /* Enable all mod_abs and link detection bits */
4741 bnx2x_cl45_write(bp, params->port,
4742 ext_phy_type,
4743 ext_phy_addr,
4744 MDIO_PMA_DEVAD,
4745 MDIO_PMA_REG_RX_ALARM_CTRL,
4746 ((1<<5) | (1<<2)));
4747 }
4748
4749 /* If transmitter is disabled,
4750 ignore false link up indication */
4751 bnx2x_cl45_read(bp, params->port,
4752 ext_phy_type,
4753 ext_phy_addr,
4754 MDIO_PMA_DEVAD,
4755 MDIO_PMA_REG_PHY_IDENTIFIER,
4756 &val1);
4757 if (val1 & (1<<15)) {
4758 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4759 ext_phy_link_up = 0;
4760 break;
4761 }
4762
4763 bnx2x_cl45_read(bp, params->port,
4764 ext_phy_type,
4765 ext_phy_addr,
4766 MDIO_PMA_DEVAD,
4767 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4768 &link_status);
57963ed9 4769
4d295db0
EG		 4770 /* Bits 0..2 --> speed detected,
4771 bits 13..15--> link is down */
4772 if ((link_status & (1<<2)) &&
4773 (!(link_status & (1<<15)))) {
4774 ext_phy_link_up = 1;
4775 vars->line_speed = SPEED_10000;
4776 } else if ((link_status & (1<<0)) &&
4777 (!(link_status & (1<<13)))) {
4778 ext_phy_link_up = 1;
4779 vars->line_speed = SPEED_1000;
4780 DP(NETIF_MSG_LINK,
4781 "port %x: External link"
4782 " up in 1G\n", params->port);
4783 } else {
4784 ext_phy_link_up = 0;
4785 DP(NETIF_MSG_LINK,
4786 "port %x: External link"
4787 " is down\n", params->port);
4788 }
ea4e040a 4789 break;
4d295db0
EG		 4790 }
4791
ea4e040a
YR		 4792 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4793 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4794 {
6bbca910
YR		 4795 u16 link_status = 0;
4796 u16 an1000_status = 0;
ea4e040a
YR		 4797 if (ext_phy_type ==
4798 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4799 bnx2x_cl45_read(bp, params->port,
4800 ext_phy_type,
4801 ext_phy_addr,
4802 MDIO_PCS_DEVAD,
4803 MDIO_PCS_REG_LASI_STATUS, &val1);
4804 bnx2x_cl45_read(bp, params->port,
4805 ext_phy_type,
4806 ext_phy_addr,
4807 MDIO_PCS_DEVAD,
4808 MDIO_PCS_REG_LASI_STATUS, &val2);
4809 DP(NETIF_MSG_LINK,
4810 "870x LASI status 0x%x->0x%x\n",
4811 val1, val2);
4812
4813 } else {
4814 /* In 8073, port1 is directed through emac0 and
4815 * port0 is directed through emac1
4816 */
4817 bnx2x_cl45_read(bp, params->port,
4818 ext_phy_type,
4819 ext_phy_addr,
4820 MDIO_PMA_DEVAD,
4821 MDIO_PMA_REG_LASI_STATUS, &val1);
4822
ea4e040a 4823 DP(NETIF_MSG_LINK,
6bbca910
YR		 4824 "8703 LASI status 0x%x\n",
4825 val1);
ea4e040a
YR		 4826 }
4827
4828 /* clear the interrupt LASI status register */
4829 bnx2x_cl45_read(bp, params->port,
4830 ext_phy_type,
4831 ext_phy_addr,
4832 MDIO_PCS_DEVAD,
4833 MDIO_PCS_REG_STATUS, &val2);
4834 bnx2x_cl45_read(bp, params->port,
4835 ext_phy_type,
4836 ext_phy_addr,
4837 MDIO_PCS_DEVAD,
4838 MDIO_PCS_REG_STATUS, &val1);
4839 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4840 val2, val1);
6bbca910 4841 /* Clear MSG-OUT */
ea4e040a
YR		 4842 bnx2x_cl45_read(bp, params->port,
4843 ext_phy_type,
4844 ext_phy_addr,
4845 MDIO_PMA_DEVAD,
052a38e0 4846 MDIO_PMA_REG_M8051_MSGOUT_REG,
6bbca910
YR		 4847 &val1);
4848
4849 /* Check the LASI */
ea4e040a
YR		 4850 bnx2x_cl45_read(bp, params->port,
4851 ext_phy_type,
4852 ext_phy_addr,
4853 MDIO_PMA_DEVAD,
6bbca910
YR		 4854 MDIO_PMA_REG_RX_ALARM, &val2);
4855
4856 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4857
ea4e040a
YR		 4858 /* Check the link status */
4859 bnx2x_cl45_read(bp, params->port,
4860 ext_phy_type,
4861 ext_phy_addr,
4862 MDIO_PCS_DEVAD,
4863 MDIO_PCS_REG_STATUS, &val2);
4864 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4865
4866 bnx2x_cl45_read(bp, params->port,
4867 ext_phy_type,
4868 ext_phy_addr,
4869 MDIO_PMA_DEVAD,
4870 MDIO_PMA_REG_STATUS, &val2);
4871 bnx2x_cl45_read(bp, params->port,
4872 ext_phy_type,
4873 ext_phy_addr,
4874 MDIO_PMA_DEVAD,
4875 MDIO_PMA_REG_STATUS, &val1);
4876 ext_phy_link_up = ((val1 & 4) == 4);
4877 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4878 if (ext_phy_type ==
4879 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
6bbca910 4880
ea4e040a 4881 if (ext_phy_link_up &&
6bbca910
YR		 4882 ((params->req_line_speed !=
4883 SPEED_10000))) {
ea4e040a
YR		 4884 if (bnx2x_bcm8073_xaui_wa(params)
4885 != 0) {
4886 ext_phy_link_up = 0;
4887 break;
4888 }
6bbca910
YR		 4889 }
4890 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 4891 ext_phy_type,
4892 ext_phy_addr,
4893 MDIO_AN_DEVAD,
4894 MDIO_AN_REG_LINK_STATUS,
4895 &an1000_status);
6bbca910 4896 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 4897 ext_phy_type,
4898 ext_phy_addr,
4899 MDIO_AN_DEVAD,
4900 MDIO_AN_REG_LINK_STATUS,
4901 &an1000_status);
6bbca910 4902
ea4e040a
YR		 4903 /* Check the link status on 1.1.2 */
4904 bnx2x_cl45_read(bp, params->port,
4905 ext_phy_type,
4906 ext_phy_addr,
4907 MDIO_PMA_DEVAD,
4908 MDIO_PMA_REG_STATUS, &val2);
4909 bnx2x_cl45_read(bp, params->port,
4910 ext_phy_type,
4911 ext_phy_addr,
4912 MDIO_PMA_DEVAD,
4913 MDIO_PMA_REG_STATUS, &val1);
4914 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4915 "an_link_status=0x%x\n",
4916 val2, val1, an1000_status);
4917
356e2385 4918 ext_phy_link_up = (((val1 & 4) == 4) ||
6bbca910 4919 (an1000_status & (1<<1)));
ea4e040a
YR		 4920 if (ext_phy_link_up &&
4921 bnx2x_8073_is_snr_needed(params)) {
4922 /* The SNR will improve about 2dbby
4923 changing the BW and FEE main tap.*/
4924
4925 /* The 1st write to change FFE main
4926 tap is set before restart AN */
4927 /* Change PLL Bandwidth in EDC
4928 register */
4929 bnx2x_cl45_write(bp, port, ext_phy_type,
4930 ext_phy_addr,
4931 MDIO_PMA_DEVAD,
4932 MDIO_PMA_REG_PLL_BANDWIDTH,
4933 0x26BC);
4934
4935 /* Change CDR Bandwidth in EDC
4936 register */
4937 bnx2x_cl45_write(bp, port, ext_phy_type,
4938 ext_phy_addr,
4939 MDIO_PMA_DEVAD,
4940 MDIO_PMA_REG_CDR_BANDWIDTH,
4941 0x0333);
4942
6bbca910
YR		 4943
4944 }
4945 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 4946 ext_phy_type,
4947 ext_phy_addr,
4948 MDIO_PMA_DEVAD,
4949 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4950 &link_status);
6bbca910
YR		 4951
4952 /* Bits 0..2 --> speed detected,
4953 bits 13..15--> link is down */
4954 if ((link_status & (1<<2)) &&
4955 (!(link_status & (1<<15)))) {
4956 ext_phy_link_up = 1;
4957 vars->line_speed = SPEED_10000;
4958 DP(NETIF_MSG_LINK,
4959 "port %x: External link"
4960 " up in 10G\n", params->port);
4961 } else if ((link_status & (1<<1)) &&
4962 (!(link_status & (1<<14)))) {
4963 ext_phy_link_up = 1;
4964 vars->line_speed = SPEED_2500;
4965 DP(NETIF_MSG_LINK,
4966 "port %x: External link"
4967 " up in 2.5G\n", params->port);
4968 } else if ((link_status & (1<<0)) &&
4969 (!(link_status & (1<<13)))) {
4970 ext_phy_link_up = 1;
4971 vars->line_speed = SPEED_1000;
4972 DP(NETIF_MSG_LINK,
4973 "port %x: External link"
4974 " up in 1G\n", params->port);
4975 } else {
4976 ext_phy_link_up = 0;
4977 DP(NETIF_MSG_LINK,
4978 "port %x: External link"
4979 " is down\n", params->port);
4980 }
4981 } else {
4982 /* See if 1G link is up for the 8072 */
4983 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 4984 ext_phy_type,
4985 ext_phy_addr,
4986 MDIO_AN_DEVAD,
4987 MDIO_AN_REG_LINK_STATUS,
4988 &an1000_status);
6bbca910 4989 bnx2x_cl45_read(bp, params->port,
052a38e0
EG		 4990 ext_phy_type,
4991 ext_phy_addr,
4992 MDIO_AN_DEVAD,
4993 MDIO_AN_REG_LINK_STATUS,
4994 &an1000_status);
6bbca910
YR		 4995 if (an1000_status & (1<<1)) {
4996 ext_phy_link_up = 1;
4997 vars->line_speed = SPEED_1000;
4998 DP(NETIF_MSG_LINK,
4999 "port %x: External link"
5000 " up in 1G\n", params->port);
5001 } else if (ext_phy_link_up) {
5002 ext_phy_link_up = 1;
5003 vars->line_speed = SPEED_10000;
5004 DP(NETIF_MSG_LINK,
5005 "port %x: External link"
5006 " up in 10G\n", params->port);
ea4e040a
YR		 5007 }
5008 }
6bbca910
YR		 5009
5010
ea4e040a
YR		 5011 break;
5012 }
5013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5014 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5015 ext_phy_addr,
5016 MDIO_PMA_DEVAD,
5017 MDIO_PMA_REG_LASI_STATUS, &val2);
5018 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5019 ext_phy_addr,
5020 MDIO_PMA_DEVAD,
5021 MDIO_PMA_REG_LASI_STATUS, &val1);
5022 DP(NETIF_MSG_LINK,
5023 "10G-base-T LASI status 0x%x->0x%x\n",
5024 val2, val1);
5025 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5026 ext_phy_addr,
5027 MDIO_PMA_DEVAD,
5028 MDIO_PMA_REG_STATUS, &val2);
5029 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5030 ext_phy_addr,
5031 MDIO_PMA_DEVAD,
5032 MDIO_PMA_REG_STATUS, &val1);
5033 DP(NETIF_MSG_LINK,
5034 "10G-base-T PMA status 0x%x->0x%x\n",
5035 val2, val1);
5036 ext_phy_link_up = ((val1 & 4) == 4);
5037 /* if link is up
5038 * print the AN outcome of the SFX7101 PHY
5039 */
5040 if (ext_phy_link_up) {
5041 bnx2x_cl45_read(bp, params->port,
5042 ext_phy_type,
5043 ext_phy_addr,
5044 MDIO_AN_DEVAD,
5045 MDIO_AN_REG_MASTER_STATUS,
5046 &val2);
57963ed9 5047 vars->line_speed = SPEED_10000;
ea4e040a
YR		 5048 DP(NETIF_MSG_LINK,
5049 "SFX7101 AN status 0x%x->Master=%x\n",
5050 val2,
5051 (val2 & (1<<14)));
5052 }
5053 break;
28577185 5054 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
28577185 5055 /* Check 10G-BaseT link status */
2f904460 5056 /* Check PMD signal ok */
28577185 5057 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2f904460
EG		 5058 ext_phy_addr,
5059 MDIO_AN_DEVAD,
5060 0xFFFA,
5061 &val1);
28577185
EG		 5062 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5063 ext_phy_addr,
2f904460
EG		 5064 MDIO_PMA_DEVAD,
5065 MDIO_PMA_REG_8481_PMD_SIGNAL,
5066 &val2);
5067 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5068
5069 /* Check link 10G */
5070 if (val2 & (1<<11)) {
28577185
EG		 5071 vars->line_speed = SPEED_10000;
5072 ext_phy_link_up = 1;
2f904460
EG		 5073 bnx2x_8481_set_10G_led_mode(params,
5074 ext_phy_type,
5075 ext_phy_addr);
5076 } else { /* Check Legacy speed link */
5077 u16 legacy_status, legacy_speed;
5078
5079 /* Enable expansion register 0x42
5080 (Operation mode status) */
5081 bnx2x_cl45_write(bp, params->port,
5082 ext_phy_type,
5083 ext_phy_addr,
5084 MDIO_AN_DEVAD,
5085 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5086 0xf42);
ea4e040a 5087
2f904460
EG		 5088 /* Get legacy speed operation status */
5089 bnx2x_cl45_read(bp, params->port,
5090 ext_phy_type,
5091 ext_phy_addr,
5092 MDIO_AN_DEVAD,
5093 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5094 &legacy_status);
5095
5096 DP(NETIF_MSG_LINK, "Legacy speed status"
5097 " = 0x%x\n", legacy_status);
5098 ext_phy_link_up = ((legacy_status & (1<<11))
5099 == (1<<11));
5100 if (ext_phy_link_up) {
5101 legacy_speed = (legacy_status & (3<<9));
5102 if (legacy_speed == (0<<9))
5103 vars->line_speed = SPEED_10;
5104 else if (legacy_speed == (1<<9))
5105 vars->line_speed =
5106 SPEED_100;
5107 else if (legacy_speed == (2<<9))
5108 vars->line_speed =
5109 SPEED_1000;
5110 else /* Should not happen */
5111 vars->line_speed = 0;
5112
5113 if (legacy_status & (1<<8))
5114 vars->duplex = DUPLEX_FULL;
5115 else
5116 vars->duplex = DUPLEX_HALF;
5117
5118 DP(NETIF_MSG_LINK, "Link is up "
5119 "in %dMbps, is_duplex_full"
5120 "= %d\n",
5121 vars->line_speed,
5122 (vars->duplex == DUPLEX_FULL));
5123 bnx2x_8481_set_legacy_led_mode(params,
5124 ext_phy_type,
5125 ext_phy_addr);
28577185
EG		 5126 }
5127 }
5128
5129 break;
ea4e040a
YR		 5130 default:
5131 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5132 params->ext_phy_config);
5133 ext_phy_link_up = 0;
5134 break;
5135 }
5136
5137 } else { /* SerDes */
5138 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5139 switch (ext_phy_type) {
5140 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5141 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5142 ext_phy_link_up = 1;
5143 break;
5144
5145 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5146 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5147 ext_phy_link_up = 1;
5148 break;
5149
5150 default:
5151 DP(NETIF_MSG_LINK,
5152 "BAD SerDes ext_phy_config 0x%x\n",
5153 params->ext_phy_config);
5154 ext_phy_link_up = 0;
5155 break;
5156 }
5157 }
5158
5159 return ext_phy_link_up;
5160}
5161
5162static void bnx2x_link_int_enable(struct link_params *params)
5163{
5164 u8 port = params->port;
5165 u32 ext_phy_type;
5166 u32 mask;
5167 struct bnx2x *bp = params->bp;
5168 /* setting the status to report on link up
5169 for either XGXS or SerDes */
5170
5171 if (params->switch_cfg == SWITCH_CFG_10G) {
5172 mask = (NIG_MASK_XGXS0_LINK10G |
5173 NIG_MASK_XGXS0_LINK_STATUS);
5174 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5175 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5176 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5177 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5178 (ext_phy_type !=
5179 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5180 mask |= NIG_MASK_MI_INT;
5181 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5182 }
5183
5184 } else { /* SerDes */
5185 mask = NIG_MASK_SERDES0_LINK_STATUS;
5186 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5187 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5188 if ((ext_phy_type !=
5189 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5190 (ext_phy_type !=
5191 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5192 mask |= NIG_MASK_MI_INT;
5193 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5194 }
5195 }
5196 bnx2x_bits_en(bp,
5197 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5198 mask);
5199 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
5200 (params->switch_cfg == SWITCH_CFG_10G),
5201 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5202
5203 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5204 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5205 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5206 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5207 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5208 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5209 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5210}
5211
2f904460
EG		 5212static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5213 u8 is_mi_int)
5214{
5215 u32 latch_status = 0, is_mi_int_status;
5216 /* Disable the MI INT ( external phy int )
5217 * by writing 1 to the status register. Link down indication
5218 * is high-active-signal, so in this case we need to write the
5219 * status to clear the XOR
5220 */
5221 /* Read Latched signals */
5222 latch_status = REG_RD(bp,
5223 NIG_REG_LATCH_STATUS_0 + port*8);
5224 is_mi_int_status = REG_RD(bp,
5225 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5226 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5227 "latch_status = 0x%x\n",
5228 is_mi_int, is_mi_int_status, latch_status);
5229 /* Handle only those with latched-signal=up.*/
5230 if (latch_status & 1) {
5231 /* For all latched-signal=up,Write original_signal to status */
5232 if (is_mi_int)
5233 bnx2x_bits_en(bp,
5234 NIG_REG_STATUS_INTERRUPT_PORT0
5235 + port*4,
5236 NIG_STATUS_EMAC0_MI_INT);
5237 else
5238 bnx2x_bits_dis(bp,
5239 NIG_REG_STATUS_INTERRUPT_PORT0
5240 + port*4,
5241 NIG_STATUS_EMAC0_MI_INT);
5242 /* For all latched-signal=up : Re-Arm Latch signals */
5243 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5244 (latch_status & 0xfffe) | (latch_status & 1));
5245 }
5246}
ea4e040a
YR		 5247/*
5248 * link management
5249 */
5250static void bnx2x_link_int_ack(struct link_params *params,
2f904460
EG		 5251 struct link_vars *vars, u8 is_10g,
5252 u8 is_mi_int)
ea4e040a
YR		 5253{
5254 struct bnx2x *bp = params->bp;
5255 u8 port = params->port;
5256
5257 /* first reset all status
5258 * we assume only one line will be change at a time */
5259 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5260 (NIG_STATUS_XGXS0_LINK10G |
5261 NIG_STATUS_XGXS0_LINK_STATUS |
5262 NIG_STATUS_SERDES0_LINK_STATUS));
2f904460
EG		 5263 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5264 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
5265 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5266 }
ea4e040a
YR		 5267 if (vars->phy_link_up) {
5268 if (is_10g) {
5269 /* Disable the 10G link interrupt
5270 * by writing 1 to the status register
5271 */
5272 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5273 bnx2x_bits_en(bp,
5274 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5275 NIG_STATUS_XGXS0_LINK10G);
5276
5277 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5278 /* Disable the link interrupt
5279 * by writing 1 to the relevant lane
5280 * in the status register
5281 */
5282 u32 ser_lane = ((params->lane_config &
5283 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5284 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5285
2f904460
EG		 5286 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5287 vars->line_speed);
ea4e040a
YR		 5288 bnx2x_bits_en(bp,
5289 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5290 ((1 << ser_lane) <<
5291 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5292
5293 } else { /* SerDes */
5294 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5295 /* Disable the link interrupt
5296 * by writing 1 to the status register
5297 */
5298 bnx2x_bits_en(bp,
5299 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5300 NIG_STATUS_SERDES0_LINK_STATUS);
5301 }
5302
5303 } else { /* link_down */
5304 }
5305}
5306
5307static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5308{
5309 u8 *str_ptr = str;
5310 u32 mask = 0xf0000000;
5311 u8 shift = 8*4;
5312 u8 digit;
5313 if (len < 10) {
025dfdaf 5314 /* Need more than 10chars for this format */
ea4e040a
YR		 5315 *str_ptr = '\0';
5316 return -EINVAL;
5317 }
5318 while (shift > 0) {
5319
5320 shift -= 4;
5321 digit = ((num & mask) >> shift);
5322 if (digit < 0xa)
5323 *str_ptr = digit + '0';
5324 else
5325 *str_ptr = digit - 0xa + 'a';
5326 str_ptr++;
5327 mask = mask >> 4;
5328 if (shift == 4*4) {
5329 *str_ptr = ':';
5330 str_ptr++;
5331 }
5332 }
5333 *str_ptr = '\0';
5334 return 0;
5335}
5336
5337
57963ed9
YR		 5338static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
5339 u32 ext_phy_type)
ea4e040a
YR		 5340{
5341 u32 cnt = 0;
5342 u16 ctrl = 0;
5343 /* Enable EMAC0 in to enable MDIO */
5344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
5345 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
5346 msleep(5);
5347
5348 /* take ext phy out of reset */
5349 bnx2x_set_gpio(bp,
17de50b7
EG		 5350 MISC_REGISTERS_GPIO_2,
5351 MISC_REGISTERS_GPIO_HIGH,
5352 port);
ea4e040a
YR		 5353
5354 bnx2x_set_gpio(bp,
17de50b7
EG		 5355 MISC_REGISTERS_GPIO_1,
5356 MISC_REGISTERS_GPIO_HIGH,
5357 port);
ea4e040a
YR		 5358
5359 /* wait for 5ms */
5360 msleep(5);
5361
5362 for (cnt = 0; cnt < 1000; cnt++) {
5363 msleep(1);
5364 bnx2x_cl45_read(bp, port,
57963ed9 5365 ext_phy_type,
ea4e040a
YR		 5366 ext_phy_addr,
5367 MDIO_PMA_DEVAD,
5368 MDIO_PMA_REG_CTRL,
356e2385 5369 &ctrl);
ea4e040a
YR		 5370 if (!(ctrl & (1<<15))) {
5371 DP(NETIF_MSG_LINK, "Reset completed\n\n");
5372 break;
5373 }
5374 }
5375}
5376
17de50b7 5377static void bnx2x_turn_off_sf(struct bnx2x *bp, u8 port)
ea4e040a
YR		 5378{
5379 /* put sf to reset */
ea4e040a 5380 bnx2x_set_gpio(bp,
17de50b7
EG		 5381 MISC_REGISTERS_GPIO_1,
5382 MISC_REGISTERS_GPIO_LOW,
5383 port);
5384 bnx2x_set_gpio(bp,
5385 MISC_REGISTERS_GPIO_2,
5386 MISC_REGISTERS_GPIO_LOW,
5387 port);
ea4e040a
YR		 5388}
5389
5390u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5391 u8 *version, u16 len)
5392{
0376d5b2 5393 struct bnx2x *bp;
ea4e040a 5394 u32 ext_phy_type = 0;
a35da8db 5395 u32 spirom_ver = 0;
97b41dad 5396 u8 status;
ea4e040a
YR		 5397
5398 if (version == NULL || params == NULL)
5399 return -EINVAL;
0376d5b2 5400 bp = params->bp;
ea4e040a 5401
a35da8db
EG		 5402 spirom_ver = REG_RD(bp, params->shmem_base +
5403 offsetof(struct shmem_region,
5404 port_mb[params->port].ext_phy_fw_version));
5405
97b41dad 5406 status = 0;
ea4e040a
YR		 5407 /* reset the returned value to zero */
5408 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 5409 switch (ext_phy_type) {
5410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5411
5412 if (len < 5)
5413 return -EINVAL;
5414
a35da8db
EG		 5415 version[0] = (spirom_ver & 0xFF);
5416 version[1] = (spirom_ver & 0xFF00) >> 8;
5417 version[2] = (spirom_ver & 0xFF0000) >> 16;
5418 version[3] = (spirom_ver & 0xFF000000) >> 24;
ea4e040a
YR		 5419 version[4] = '\0';
5420
ea4e040a
YR		 5421 break;
5422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5423 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4d295db0 5424 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
ea4e040a 5425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
589abe3a 5426 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
b1607af5
EG		 5427 status = bnx2x_format_ver(spirom_ver, version, len);
5428 break;
9223dea6 5429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
b1607af5
EG		 5430 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5431 (spirom_ver & 0x7F);
a35da8db 5432 status = bnx2x_format_ver(spirom_ver, version, len);
ea4e040a 5433 break;
ea4e040a 5434 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
97b41dad
EG		 5435 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5436 version[0] = '\0';
ea4e040a
YR		 5437 break;
5438
5439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5440 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5441 " type is FAILURE!\n");
5442 status = -EINVAL;
5443 break;
5444
5445 default:
5446 break;
5447 }
5448 return status;
5449}
5450
5451static void bnx2x_set_xgxs_loopback(struct link_params *params,
5452 struct link_vars *vars,
5453 u8 is_10g)
5454{
5455 u8 port = params->port;
5456 struct bnx2x *bp = params->bp;
5457
5458 if (is_10g) {
6378c025 5459 u32 md_devad;
ea4e040a
YR		 5460
5461 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5462
5463 /* change the uni_phy_addr in the nig */
5464 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5465 port*0x18));
5466
5467 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5468
5469 bnx2x_cl45_write(bp, port, 0,
5470 params->phy_addr,
5471 5,
5472 (MDIO_REG_BANK_AER_BLOCK +
5473 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5474 0x2800);
5475
5476 bnx2x_cl45_write(bp, port, 0,
5477 params->phy_addr,
5478 5,
5479 (MDIO_REG_BANK_CL73_IEEEB0 +
5480 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5481 0x6041);
3858276b 5482 msleep(200);
ea4e040a
YR		 5483 /* set aer mmd back */
5484 bnx2x_set_aer_mmd(params, vars);
5485
5486 /* and md_devad */
5487 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5488 md_devad);
5489
5490 } else {
5491 u16 mii_control;
5492
5493 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5494
5495 CL45_RD_OVER_CL22(bp, port,
5496 params->phy_addr,
5497 MDIO_REG_BANK_COMBO_IEEE0,
5498 MDIO_COMBO_IEEE0_MII_CONTROL,
5499 &mii_control);
5500
5501 CL45_WR_OVER_CL22(bp, port,
5502 params->phy_addr,
5503 MDIO_REG_BANK_COMBO_IEEE0,
5504 MDIO_COMBO_IEEE0_MII_CONTROL,
5505 (mii_control |
5506 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5507 }
5508}
5509
5510
5511static void bnx2x_ext_phy_loopback(struct link_params *params)
5512{
5513 struct bnx2x *bp = params->bp;
5514 u8 ext_phy_addr;
5515 u32 ext_phy_type;
5516
5517 if (params->switch_cfg == SWITCH_CFG_10G) {
5518 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5519 /* CL37 Autoneg Enabled */
5520 ext_phy_addr = ((params->ext_phy_config &
5521 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
5522 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
5523 switch (ext_phy_type) {
5524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5525 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5526 DP(NETIF_MSG_LINK,
5527 "ext_phy_loopback: We should not get here\n");
5528 break;
5529 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5530 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5531 break;
5532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5533 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5534 break;
589abe3a
EG		 5535 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5536 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5537 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5538 ext_phy_addr,
5539 MDIO_PMA_DEVAD,
5540 MDIO_PMA_REG_CTRL,
5541 0x0001);
5542 break;
ea4e040a
YR		 5543 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5544 /* SFX7101_XGXS_TEST1 */
5545 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5546 ext_phy_addr,
5547 MDIO_XS_DEVAD,
5548 MDIO_XS_SFX7101_XGXS_TEST1,
5549 0x100);
5550 DP(NETIF_MSG_LINK,
5551 "ext_phy_loopback: set ext phy loopback\n");
5552 break;
5553 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5554
5555 break;
5556 } /* switch external PHY type */
5557 } else {
5558 /* serdes */
5559 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5560 ext_phy_addr = (params->ext_phy_config &
5561 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5562 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5563 }
5564}
5565
5566
5567/*
5568 *------------------------------------------------------------------------
5569 * bnx2x_override_led_value -
5570 *
5571 * Override the led value of the requsted led
5572 *
5573 *------------------------------------------------------------------------
5574 */
5575u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5576 u32 led_idx, u32 value)
5577{
5578 u32 reg_val;
5579
5580 /* If port 0 then use EMAC0, else use EMAC1*/
5581 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5582
5583 DP(NETIF_MSG_LINK,
5584 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5585 port, led_idx, value);
5586
5587 switch (led_idx) {
5588 case 0: /* 10MB led */
5589 /* Read the current value of the LED register in
5590 the EMAC block */
5591 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5592 /* Set the OVERRIDE bit to 1 */
5593 reg_val |= EMAC_LED_OVERRIDE;
5594 /* If value is 1, set the 10M_OVERRIDE bit,
5595 otherwise reset it.*/
5596 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5597 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5598 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5599 break;
5600 case 1: /*100MB led */
5601 /*Read the current value of the LED register in
5602 the EMAC block */
5603 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5604 /* Set the OVERRIDE bit to 1 */
5605 reg_val |= EMAC_LED_OVERRIDE;
5606 /* If value is 1, set the 100M_OVERRIDE bit,
5607 otherwise reset it.*/
5608 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5609 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5610 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5611 break;
5612 case 2: /* 1000MB led */
5613 /* Read the current value of the LED register in the
5614 EMAC block */
5615 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5616 /* Set the OVERRIDE bit to 1 */
5617 reg_val |= EMAC_LED_OVERRIDE;
5618 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5619 reset it. */
5620 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5621 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5622 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5623 break;
5624 case 3: /* 2500MB led */
5625 /* Read the current value of the LED register in the
5626 EMAC block*/
5627 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5628 /* Set the OVERRIDE bit to 1 */
5629 reg_val |= EMAC_LED_OVERRIDE;
5630 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5631 reset it.*/
5632 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5633 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5634 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5635 break;
5636 case 4: /*10G led */
5637 if (port == 0) {
5638 REG_WR(bp, NIG_REG_LED_10G_P0,
5639 value);
5640 } else {
5641 REG_WR(bp, NIG_REG_LED_10G_P1,
5642 value);
5643 }
5644 break;
5645 case 5: /* TRAFFIC led */
5646 /* Find if the traffic control is via BMAC or EMAC */
5647 if (port == 0)
5648 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5649 else
5650 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5651
5652 /* Override the traffic led in the EMAC:*/
5653 if (reg_val == 1) {
5654 /* Read the current value of the LED register in
5655 the EMAC block */
5656 reg_val = REG_RD(bp, emac_base +
5657 EMAC_REG_EMAC_LED);
5658 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5659 reg_val |= EMAC_LED_OVERRIDE;
5660 /* If value is 1, set the TRAFFIC bit, otherwise
5661 reset it.*/
5662 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5663 (reg_val & ~EMAC_LED_TRAFFIC);
5664 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5665 } else { /* Override the traffic led in the BMAC: */
5666 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5667 + port*4, 1);
5668 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5669 value);
5670 }
5671 break;
5672 default:
5673 DP(NETIF_MSG_LINK,
5674 "bnx2x_override_led_value() unknown led index %d "
5675 "(should be 0-5)\n", led_idx);
5676 return -EINVAL;
5677 }
5678
5679 return 0;
5680}
5681
5682
5683u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5684 u16 hw_led_mode, u32 chip_id)
5685{
5686 u8 rc = 0;
345b5d52
EG		 5687 u32 tmp;
5688 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
ea4e040a
YR		 5689 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5690 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5691 speed, hw_led_mode);
5692 switch (mode) {
5693 case LED_MODE_OFF:
5694 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5695 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5696 SHARED_HW_CFG_LED_MAC1);
345b5d52
EG		 5697
5698 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5699 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
ea4e040a
YR		 5700 break;
5701
5702 case LED_MODE_OPER:
5703 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5704 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5705 port*4, 0);
5706 /* Set blinking rate to ~15.9Hz */
5707 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5708 LED_BLINK_RATE_VAL);
5709 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5710 port*4, 1);
345b5d52 5711 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3196a88a 5712 EMAC_WR(bp, EMAC_REG_EMAC_LED,
345b5d52
EG		 5713 (tmp & (~EMAC_LED_OVERRIDE)));
5714
34f80b04
EG		 5715 if (!CHIP_IS_E1H(bp) &&
5716 ((speed == SPEED_2500) ||
ea4e040a
YR		 5717 (speed == SPEED_1000) ||
5718 (speed == SPEED_100) ||
5719 (speed == SPEED_10))) {
5720 /* On Everest 1 Ax chip versions for speeds less than
5721 10G LED scheme is different */
5722 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5723 + port*4, 1);
5724 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5725 port*4, 0);
5726 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5727 port*4, 1);
5728 }
5729 break;
5730
5731 default:
5732 rc = -EINVAL;
5733 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5734 mode);
5735 break;
5736 }
5737 return rc;
5738
5739}
5740
5741u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5742{
5743 struct bnx2x *bp = params->bp;
5744 u16 gp_status = 0;
5745
5746 CL45_RD_OVER_CL22(bp, params->port,
5747 params->phy_addr,
5748 MDIO_REG_BANK_GP_STATUS,
5749 MDIO_GP_STATUS_TOP_AN_STATUS1,
5750 &gp_status);
5751 /* link is up only if both local phy and external phy are up */
5752 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
2f904460 5753 bnx2x_ext_phy_is_link_up(params, vars, 1))
ea4e040a
YR		 5754 return 0;
5755
5756 return -ESRCH;
5757}
5758
5759static u8 bnx2x_link_initialize(struct link_params *params,
5760 struct link_vars *vars)
5761{
5762 struct bnx2x *bp = params->bp;
5763 u8 port = params->port;
5764 u8 rc = 0;
57963ed9
YR		 5765 u8 non_ext_phy;
5766 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a
YR		 5767 /* Activate the external PHY */
5768 bnx2x_ext_phy_reset(params, vars);
5769
5770 bnx2x_set_aer_mmd(params, vars);
5771
5772 if (vars->phy_flags & PHY_XGXS_FLAG)
5773 bnx2x_set_master_ln(params);
5774
5775 rc = bnx2x_reset_unicore(params);
5776 /* reset the SerDes and wait for reset bit return low */
5777 if (rc != 0)
5778 return rc;
5779
5780 bnx2x_set_aer_mmd(params, vars);
5781
5782 /* setting the masterLn_def again after the reset */
5783 if (vars->phy_flags & PHY_XGXS_FLAG) {
5784 bnx2x_set_master_ln(params);
5785 bnx2x_set_swap_lanes(params);
5786 }
5787
ea4e040a 5788 if (vars->phy_flags & PHY_XGXS_FLAG) {
44722d1d 5789 if ((params->req_line_speed &&
ea4e040a 5790 ((params->req_line_speed == SPEED_100) ||
44722d1d
EG		 5791 (params->req_line_speed == SPEED_10))) ||
5792 (!params->req_line_speed &&
5793 (params->speed_cap_mask >=
5794 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5795 (params->speed_cap_mask <
5796 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5797 )) {
ea4e040a
YR		 5798 vars->phy_flags |= PHY_SGMII_FLAG;
5799 } else {
5800 vars->phy_flags &= ~PHY_SGMII_FLAG;
5801 }
5802 }
57963ed9
YR		 5803 /* In case of external phy existance, the line speed would be the
5804 line speed linked up by the external phy. In case it is direct only,
5805 then the line_speed during initialization will be equal to the
5806 req_line_speed*/
5807 vars->line_speed = params->req_line_speed;
ea4e040a 5808
8c99e7b0 5809 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
ea4e040a 5810
57963ed9
YR		 5811 /* init ext phy and enable link state int */
5812 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
8660d8c3 5813 (params->loopback_mode == LOOPBACK_XGXS_10));
57963ed9
YR		 5814
5815 if (non_ext_phy ||
589abe3a 5816 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
28577185 5817 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
8660d8c3
EG		 5818 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
5819 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
57963ed9
YR		 5820 if (params->req_line_speed == SPEED_AUTO_NEG)
5821 bnx2x_set_parallel_detection(params, vars->phy_flags);
5822 bnx2x_init_internal_phy(params, vars);
ea4e040a
YR		 5823 }
5824
57963ed9
YR		 5825 if (!non_ext_phy)
5826 rc |= bnx2x_ext_phy_init(params, vars);
ea4e040a
YR		 5827
5828 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
57963ed9
YR		 5829 (NIG_STATUS_XGXS0_LINK10G |
5830 NIG_STATUS_XGXS0_LINK_STATUS |
5831 NIG_STATUS_SERDES0_LINK_STATUS));
ea4e040a
YR		 5832
5833 return rc;
5834
5835}
5836
5837
5838u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5839{
5840 struct bnx2x *bp = params->bp;
5841
5842 u32 val;
3196a88a 5843 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
ea4e040a
YR		 5844 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
5845 params->req_line_speed, params->req_flow_ctrl);
5846 vars->link_status = 0;
57963ed9
YR		 5847 vars->phy_link_up = 0;
5848 vars->link_up = 0;
5849 vars->line_speed = 0;
5850 vars->duplex = DUPLEX_FULL;
c0700f90 5851 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
57963ed9
YR		 5852 vars->mac_type = MAC_TYPE_NONE;
5853
ea4e040a
YR		 5854 if (params->switch_cfg == SWITCH_CFG_1G)
5855 vars->phy_flags = PHY_SERDES_FLAG;
5856 else
5857 vars->phy_flags = PHY_XGXS_FLAG;
5858
3196a88a 5859
ea4e040a
YR		 5860 /* disable attentions */
5861 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5862 (NIG_MASK_XGXS0_LINK_STATUS |
5863 NIG_MASK_XGXS0_LINK10G |
5864 NIG_MASK_SERDES0_LINK_STATUS |
5865 NIG_MASK_MI_INT));
5866
5867 bnx2x_emac_init(params, vars);
5868
5869 if (CHIP_REV_IS_FPGA(bp)) {
5870 vars->link_up = 1;
5871 vars->line_speed = SPEED_10000;
5872 vars->duplex = DUPLEX_FULL;
c0700f90 5873 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a 5874 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
34f80b04
EG		 5875 /* enable on E1.5 FPGA */
5876 if (CHIP_IS_E1H(bp)) {
5877 vars->flow_ctrl |=
c0700f90 5878 (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX);
34f80b04
EG		 5879 vars->link_status |=
5880 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
5881 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
5882 }
ea4e040a
YR		 5883
5884 bnx2x_emac_enable(params, vars, 0);
5885 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5886 /* disable drain */
5887 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5888 + params->port*4, 0);
5889
5890 /* update shared memory */
5891 bnx2x_update_mng(params, vars->link_status);
5892
5893 return 0;
5894
5895 } else
5896 if (CHIP_REV_IS_EMUL(bp)) {
5897
5898 vars->link_up = 1;
5899 vars->line_speed = SPEED_10000;
5900 vars->duplex = DUPLEX_FULL;
c0700f90 5901 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5902 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5903
5904 bnx2x_bmac_enable(params, vars, 0);
5905
5906 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5907 /* Disable drain */
5908 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5909 + params->port*4, 0);
5910
5911 /* update shared memory */
5912 bnx2x_update_mng(params, vars->link_status);
5913
5914 return 0;
5915
5916 } else
5917 if (params->loopback_mode == LOOPBACK_BMAC) {
5918 vars->link_up = 1;
5919 vars->line_speed = SPEED_10000;
5920 vars->duplex = DUPLEX_FULL;
c0700f90 5921 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5922 vars->mac_type = MAC_TYPE_BMAC;
5923
5924 vars->phy_flags = PHY_XGXS_FLAG;
5925
5926 bnx2x_phy_deassert(params, vars->phy_flags);
5927 /* set bmac loopback */
5928 bnx2x_bmac_enable(params, vars, 1);
5929
5930 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5931 params->port*4, 0);
5932 } else if (params->loopback_mode == LOOPBACK_EMAC) {
5933 vars->link_up = 1;
5934 vars->line_speed = SPEED_1000;
5935 vars->duplex = DUPLEX_FULL;
c0700f90 5936 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5937 vars->mac_type = MAC_TYPE_EMAC;
5938
5939 vars->phy_flags = PHY_XGXS_FLAG;
5940
5941 bnx2x_phy_deassert(params, vars->phy_flags);
5942 /* set bmac loopback */
5943 bnx2x_emac_enable(params, vars, 1);
5944 bnx2x_emac_program(params, vars->line_speed,
5945 vars->duplex);
5946 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5947 params->port*4, 0);
5948 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
5949 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5950 vars->link_up = 1;
5951 vars->line_speed = SPEED_10000;
5952 vars->duplex = DUPLEX_FULL;
c0700f90 5953 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
ea4e040a
YR		 5954
5955 vars->phy_flags = PHY_XGXS_FLAG;
5956
5957 val = REG_RD(bp,
5958 NIG_REG_XGXS0_CTRL_PHY_ADDR+
5959 params->port*0x18);
5960 params->phy_addr = (u8)val;
5961
5962 bnx2x_phy_deassert(params, vars->phy_flags);
5963 bnx2x_link_initialize(params, vars);
5964
5965 vars->mac_type = MAC_TYPE_BMAC;
5966
5967 bnx2x_bmac_enable(params, vars, 0);
5968
5969 if (params->loopback_mode == LOOPBACK_XGXS_10) {
5970 /* set 10G XGXS loopback */
5971 bnx2x_set_xgxs_loopback(params, vars, 1);
5972 } else {
5973 /* set external phy loopback */
5974 bnx2x_ext_phy_loopback(params);
5975 }
5976 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
5977 params->port*4, 0);
ba71d313
EG		 5978
5979 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
5980 vars->line_speed, params->hw_led_mode,
5981 params->chip_id);
5982
ea4e040a
YR		 5983 } else
5984 /* No loopback */
5985 {
5986
5987 bnx2x_phy_deassert(params, vars->phy_flags);
5988 switch (params->switch_cfg) {
5989 case SWITCH_CFG_1G:
5990 vars->phy_flags |= PHY_SERDES_FLAG;
5991 if ((params->ext_phy_config &
5992 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
5993 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
5994 vars->phy_flags |=
5995 PHY_SGMII_FLAG;
5996 }
5997
5998 val = REG_RD(bp,
5999 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6000 params->port*0x10);
6001
6002 params->phy_addr = (u8)val;
6003
6004 break;
6005 case SWITCH_CFG_10G:
6006 vars->phy_flags |= PHY_XGXS_FLAG;
6007 val = REG_RD(bp,
6008 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6009 params->port*0x18);
6010 params->phy_addr = (u8)val;
6011
6012 break;
6013 default:
6014 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6015 return -EINVAL;
6016 break;
6017 }
f5372251 6018 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
ea4e040a
YR		 6019
6020 bnx2x_link_initialize(params, vars);
57963ed9 6021 msleep(30);
ea4e040a
YR		 6022 bnx2x_link_int_enable(params);
6023 }
6024 return 0;
6025}
6026
589abe3a
EG		 6027static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6028{
6029 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6030
6031 /* Set serial boot control for external load */
6032 bnx2x_cl45_write(bp, port,
6033 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6034 MDIO_PMA_DEVAD,
6035 MDIO_PMA_REG_GEN_CTRL, 0x0001);
589abe3a
EG		 6036}
6037
6038u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6039 u8 reset_ext_phy)
ea4e040a
YR		 6040{
6041
6042 struct bnx2x *bp = params->bp;
6043 u32 ext_phy_config = params->ext_phy_config;
6044 u16 hw_led_mode = params->hw_led_mode;
6045 u32 chip_id = params->chip_id;
6046 u8 port = params->port;
6047 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
4d295db0
EG		 6048 u32 val = REG_RD(bp, params->shmem_base +
6049 offsetof(struct shmem_region, dev_info.
6050 port_feature_config[params->port].
6051 config));
6052
ea4e040a
YR		 6053 /* disable attentions */
6054
6055 vars->link_status = 0;
6056 bnx2x_update_mng(params, vars->link_status);
6057 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6058 (NIG_MASK_XGXS0_LINK_STATUS |
6059 NIG_MASK_XGXS0_LINK10G |
6060 NIG_MASK_SERDES0_LINK_STATUS |
6061 NIG_MASK_MI_INT));
6062
6063 /* activate nig drain */
6064 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6065
6066 /* disable nig egress interface */
6067 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6068 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6069
6070 /* Stop BigMac rx */
6071 bnx2x_bmac_rx_disable(bp, port);
6072
6073 /* disable emac */
6074 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6075
6076 msleep(10);
6077 /* The PHY reset is controled by GPIO 1
6078 * Hold it as vars low
6079 */
6080 /* clear link led */
6081 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
589abe3a
EG		 6082 if (reset_ext_phy) {
6083 switch (ext_phy_type) {
6084 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6086 break;
4d295db0
EG		 6087
6088 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6089 {
6090
6091 /* Disable Transmitter */
6092 u8 ext_phy_addr = ((params->ext_phy_config &
6093 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6094 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6095 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6096 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6097 bnx2x_sfp_set_transmitter(bp, port,
6098 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6099 ext_phy_addr, 0);
6100 break;
6101 }
589abe3a
EG		 6102 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6103 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6104 "low power mode\n",
6105 port);
6106 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6107 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6108 port);
6109 break;
6110 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6111 {
6112 u8 ext_phy_addr = ((params->ext_phy_config &
6113 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6114 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6115 /* Set soft reset */
6116 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6117 break;
6118 }
6119 default:
ea4e040a 6120 /* HW reset */
ea4e040a 6121 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
17de50b7
EG		 6122 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6123 port);
ea4e040a 6124 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
17de50b7
EG		 6125 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6126 port);
ea4e040a 6127 DP(NETIF_MSG_LINK, "reset external PHY\n");
ea4e040a
YR		 6128 }
6129 }
6130 /* reset the SerDes/XGXS */
6131 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6132 (0x1ff << (port*16)));
6133
6134 /* reset BigMac */
6135 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6137
6138 /* disable nig ingress interface */
6139 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6140 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6141 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6142 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6143 vars->link_up = 0;
6144 return 0;
6145}
6146
57963ed9
YR		 6147static u8 bnx2x_update_link_down(struct link_params *params,
6148 struct link_vars *vars)
6149{
6150 struct bnx2x *bp = params->bp;
6151 u8 port = params->port;
6152 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6153 bnx2x_set_led(bp, port, LED_MODE_OFF,
6154 0, params->hw_led_mode,
6155 params->chip_id);
6156
6157 /* indicate no mac active */
6158 vars->mac_type = MAC_TYPE_NONE;
6159
6160 /* update shared memory */
6161 vars->link_status = 0;
6162 vars->line_speed = 0;
6163 bnx2x_update_mng(params, vars->link_status);
6164
6165 /* activate nig drain */
6166 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6167
6c55c3cd
EG		 6168 /* disable emac */
6169 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6170
6171 msleep(10);
6172
57963ed9
YR		 6173 /* reset BigMac */
6174 bnx2x_bmac_rx_disable(bp, params->port);
6175 REG_WR(bp, GRCBASE_MISC +
6176 MISC_REGISTERS_RESET_REG_2_CLEAR,
6177 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6178 return 0;
6179}
6180
6181static u8 bnx2x_update_link_up(struct link_params *params,
6182 struct link_vars *vars,
6183 u8 link_10g, u32 gp_status)
6184{
6185 struct bnx2x *bp = params->bp;
6186 u8 port = params->port;
6187 u8 rc = 0;
6188 vars->link_status |= LINK_STATUS_LINK_UP;
6189 if (link_10g) {
6190 bnx2x_bmac_enable(params, vars, 0);
6191 bnx2x_set_led(bp, port, LED_MODE_OPER,
6192 SPEED_10000, params->hw_led_mode,
6193 params->chip_id);
6194
6195 } else {
6196 bnx2x_emac_enable(params, vars, 0);
6197 rc = bnx2x_emac_program(params, vars->line_speed,
6198 vars->duplex);
6199
6200 /* AN complete? */
6201 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6202 if (!(vars->phy_flags &
6203 PHY_SGMII_FLAG))
ed8680a7 6204 bnx2x_set_gmii_tx_driver(params);
57963ed9
YR		 6205 }
6206 }
6207
6208 /* PBF - link up */
6209 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6210 vars->line_speed);
6211
6212 /* disable drain */
6213 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6214
6215 /* update shared memory */
6216 bnx2x_update_mng(params, vars->link_status);
6c55c3cd 6217 msleep(20);
57963ed9
YR		 6218 return rc;
6219}
ea4e040a
YR		 6220/* This function should called upon link interrupt */
6221/* In case vars->link_up, driver needs to
6222 1. Update the pbf
6223 2. Disable drain
6224 3. Update the shared memory
6225 4. Indicate link up
6226 5. Set LEDs
6227 Otherwise,
6228 1. Update shared memory
6229 2. Reset BigMac
6230 3. Report link down
6231 4. Unset LEDs
6232*/
6233u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6234{
6235 struct bnx2x *bp = params->bp;
6236 u8 port = params->port;
ea4e040a 6237 u16 gp_status;
57963ed9
YR		 6238 u8 link_10g;
6239 u8 ext_phy_link_up, rc = 0;
6240 u32 ext_phy_type;
2f904460 6241 u8 is_mi_int = 0;
ea4e040a
YR		 6242
6243 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
2f904460
EG		 6244 port, (vars->phy_flags & PHY_XGXS_FLAG),
6245 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
ea4e040a 6246
2f904460
EG		 6247 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6248 port*0x18) > 0);
ea4e040a 6249 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
2f904460
EG		 6250 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6251 is_mi_int,
6252 REG_RD(bp,
6253 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
ea4e040a
YR		 6254
6255 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6256 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6257 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6258
6c55c3cd
EG		 6259 /* disable emac */
6260 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6261
57963ed9 6262 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
ea4e040a 6263
57963ed9 6264 /* Check external link change only for non-direct */
2f904460 6265 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
57963ed9
YR		 6266
6267 /* Read gp_status */
6268 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6269 MDIO_REG_BANK_GP_STATUS,
6270 MDIO_GP_STATUS_TOP_AN_STATUS1,
6271 &gp_status);
ea4e040a 6272
2f904460
EG		 6273 rc = bnx2x_link_settings_status(params, vars, gp_status,
6274 ext_phy_link_up);
ea4e040a
YR		 6275 if (rc != 0)
6276 return rc;
6277
6278 /* anything 10 and over uses the bmac */
6279 link_10g = ((vars->line_speed == SPEED_10000) ||
6280 (vars->line_speed == SPEED_12000) ||
6281 (vars->line_speed == SPEED_12500) ||
6282 (vars->line_speed == SPEED_13000) ||
6283 (vars->line_speed == SPEED_15000) ||
6284 (vars->line_speed == SPEED_16000));
6285
2f904460 6286 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
ea4e040a 6287
57963ed9
YR		 6288 /* In case external phy link is up, and internal link is down
6289 ( not initialized yet probably after link initialization, it needs
6290 to be initialized.
6291 Note that after link down-up as result of cable plug,
6292 the xgxs link would probably become up again without the need to
6293 initialize it*/
ea4e040a 6294
57963ed9
YR		 6295 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6296 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
589abe3a 6297 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
57963ed9
YR		 6298 (ext_phy_link_up && !vars->phy_link_up))
6299 bnx2x_init_internal_phy(params, vars);
ea4e040a 6300
57963ed9
YR		 6301 /* link is up only if both local phy and external phy are up */
6302 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
ea4e040a 6303
57963ed9
YR		 6304 if (vars->link_up)
6305 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6306 else
6307 rc = bnx2x_update_link_down(params, vars);
ea4e040a
YR		 6308
6309 return rc;
6310}
6311
6bbca910
YR		 6312static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6313{
6314 u8 ext_phy_addr[PORT_MAX];
6315 u16 val;
6316 s8 port;
6317
6318 /* PART1 - Reset both phys */
6319 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6320 /* Extract the ext phy address for the port */
6321 u32 ext_phy_config = REG_RD(bp, shmem_base +
6322 offsetof(struct shmem_region,
6323 dev_info.port_hw_config[port].external_phy_config));
6324
6325 /* disable attentions */
6326 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6327 (NIG_MASK_XGXS0_LINK_STATUS |
6328 NIG_MASK_XGXS0_LINK10G |
6329 NIG_MASK_SERDES0_LINK_STATUS |
6330 NIG_MASK_MI_INT));
6331
6332 ext_phy_addr[port] =
6333 ((ext_phy_config &
6334 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6335 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6336
6337 /* Need to take the phy out of low power mode in order
6338 to write to access its registers */
6339 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6340 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6341
6342 /* Reset the phy */
6343 bnx2x_cl45_write(bp, port,
6344 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6345 ext_phy_addr[port],
6346 MDIO_PMA_DEVAD,
6347 MDIO_PMA_REG_CTRL,
6348 1<<15);
6349 }
6350
6351 /* Add delay of 150ms after reset */
6352 msleep(150);
6353
6354 /* PART2 - Download firmware to both phys */
6355 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6356 u16 fw_ver1;
6357
6358 bnx2x_bcm8073_external_rom_boot(bp, port,
a35da8db 6359 ext_phy_addr[port], shmem_base);
6bbca910
YR		 6360
6361 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6362 ext_phy_addr[port],
6363 MDIO_PMA_DEVAD,
6364 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
16b311cc 6365 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6bbca910 6366 DP(NETIF_MSG_LINK,
16b311cc
EG		 6367 "bnx2x_8073_common_init_phy port %x:"
6368 "Download failed. fw version = 0x%x\n",
6369 port, fw_ver1);
6bbca910
YR		 6370 return -EINVAL;
6371 }
6372
6373 /* Only set bit 10 = 1 (Tx power down) */
6374 bnx2x_cl45_read(bp, port,
6375 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6376 ext_phy_addr[port],
6377 MDIO_PMA_DEVAD,
6378 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6379
6380 /* Phase1 of TX_POWER_DOWN reset */
6381 bnx2x_cl45_write(bp, port,
6382 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6383 ext_phy_addr[port],
6384 MDIO_PMA_DEVAD,
6385 MDIO_PMA_REG_TX_POWER_DOWN,
6386 (val | 1<<10));
6387 }
6388
6389 /* Toggle Transmitter: Power down and then up with 600ms
6390 delay between */
6391 msleep(600);
6392
6393 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6394 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
f5372251 6395 /* Phase2 of POWER_DOWN_RESET */
6bbca910
YR		 6396 /* Release bit 10 (Release Tx power down) */
6397 bnx2x_cl45_read(bp, port,
6398 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6399 ext_phy_addr[port],
6400 MDIO_PMA_DEVAD,
6401 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6402
6403 bnx2x_cl45_write(bp, port,
6404 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6405 ext_phy_addr[port],
6406 MDIO_PMA_DEVAD,
6407 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6408 msleep(15);
6409
6410 /* Read modify write the SPI-ROM version select register */
6411 bnx2x_cl45_read(bp, port,
6412 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6413 ext_phy_addr[port],
6414 MDIO_PMA_DEVAD,
6415 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6416 bnx2x_cl45_write(bp, port,
6417 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6418 ext_phy_addr[port],
6419 MDIO_PMA_DEVAD,
6420 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6421
6422 /* set GPIO2 back to LOW */
6423 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6424 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6425 }
6426 return 0;
6427
6428}
6429
4d295db0
EG		 6430static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6431{
6432 u8 ext_phy_addr[PORT_MAX];
6433 s8 port;
6434 u32 swap_val, swap_override;
6435 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6436 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6437 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6438
6439 bnx2x_hw_reset(bp, 1 ^ (swap_val && swap_override));
6440 msleep(5);
6441
6442 /* PART1 - Reset both phys */
6443 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6444 /* Extract the ext phy address for the port */
6445 u32 ext_phy_config = REG_RD(bp, shmem_base +
6446 offsetof(struct shmem_region,
6447 dev_info.port_hw_config[port].external_phy_config));
6448
6449 /* disable attentions */
6450 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6451 (NIG_MASK_XGXS0_LINK_STATUS |
6452 NIG_MASK_XGXS0_LINK10G |
6453 NIG_MASK_SERDES0_LINK_STATUS |
6454 NIG_MASK_MI_INT));
6455
6456 ext_phy_addr[port] = ((ext_phy_config &
6457 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6458 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6459
6460 /* Reset the phy */
6461 bnx2x_cl45_write(bp, port,
6462 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6463 ext_phy_addr[port],
6464 MDIO_PMA_DEVAD,
6465 MDIO_PMA_REG_CTRL,
6466 1<<15);
6467 }
6468
6469 /* Add delay of 150ms after reset */
6470 msleep(150);
6471
6472 /* PART2 - Download firmware to both phys */
6473 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6474 u16 fw_ver1;
6475
6476 bnx2x_bcm8727_external_rom_boot(bp, port,
6477 ext_phy_addr[port], shmem_base);
6478
6479 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6480 ext_phy_addr[port],
6481 MDIO_PMA_DEVAD,
6482 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6483 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6484 DP(NETIF_MSG_LINK,
6485 "bnx2x_8073_common_init_phy port %x:"
6486 "Download failed. fw version = 0x%x\n",
6487 port, fw_ver1);
6488 return -EINVAL;
6489 }
6490
6491 }
6492
6493
6494
6495 return 0;
6496}
6497
589abe3a
EG		 6498
6499static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6500{
6501 u8 ext_phy_addr;
6502 u32 val;
6503 s8 port;
6504 /* Use port1 because of the static port-swap */
6505 /* Enable the module detection interrupt */
6506 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6507 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6508 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6509 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6510
6511 bnx2x_hw_reset(bp, 1);
6512 msleep(5);
6513 for (port = 0; port < PORT_MAX; port++) {
6514 /* Extract the ext phy address for the port */
6515 u32 ext_phy_config = REG_RD(bp, shmem_base +
6516 offsetof(struct shmem_region,
6517 dev_info.port_hw_config[port].external_phy_config));
6518
6519 ext_phy_addr =
6520 ((ext_phy_config &
6521 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6522 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6523 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6524 ext_phy_addr);
6525
6526 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6527
6528 /* Set fault module detected LED on */
6529 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6530 MISC_REGISTERS_GPIO_HIGH,
6531 port);
6532 }
6533
6534 return 0;
6535}
6536
6bbca910
YR		 6537u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6538{
6539 u8 rc = 0;
6540 u32 ext_phy_type;
6541
f5372251 6542 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6bbca910
YR		 6543
6544 /* Read the ext_phy_type for arbitrary port(0) */
6545 ext_phy_type = XGXS_EXT_PHY_TYPE(
6546 REG_RD(bp, shmem_base +
6547 offsetof(struct shmem_region,
6548 dev_info.port_hw_config[0].external_phy_config)));
6549
6550 switch (ext_phy_type) {
6551 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6552 {
6553 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6554 break;
6555 }
4d295db0
EG		 6556
6557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6558 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6559 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6560 break;
6561
589abe3a
EG		 6562 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6563 /* GPIO1 affects both ports, so there's need to pull
6564 it for single port alone */
6565 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6566
6567 break;
6bbca910
YR		 6568 default:
6569 DP(NETIF_MSG_LINK,
6570 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6571 ext_phy_type);
6572 break;
6573 }
6574
6575 return rc;
6576}
6577
6578
6579
ea4e040a
YR		 6580static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
6581{
6582 u16 val, cnt;
6583
6584 bnx2x_cl45_read(bp, port,
6585 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6586 phy_addr,
6587 MDIO_PMA_DEVAD,
6588 MDIO_PMA_REG_7101_RESET, &val);
6589
6590 for (cnt = 0; cnt < 10; cnt++) {
6591 msleep(50);
6592 /* Writes a self-clearing reset */
6593 bnx2x_cl45_write(bp, port,
6594 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6595 phy_addr,
6596 MDIO_PMA_DEVAD,
6597 MDIO_PMA_REG_7101_RESET,
6598 (val | (1<<15)));
6599 /* Wait for clear */
6600 bnx2x_cl45_read(bp, port,
6601 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6602 phy_addr,
6603 MDIO_PMA_DEVAD,
6604 MDIO_PMA_REG_7101_RESET, &val);
6605
6606 if ((val & (1<<15)) == 0)
6607 break;
6608 }
6609}
6610#define RESERVED_SIZE 256
6611/* max application is 160K bytes - data at end of RAM */
6378c025 6612#define MAX_APP_SIZE (160*1024 - RESERVED_SIZE)
ea4e040a
YR		 6613
6614/* Header is 14 bytes */
6615#define HEADER_SIZE 14
6616#define DATA_OFFSET HEADER_SIZE
6617
6618#define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
6619 bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
6620 ext_phy_addr, \
6621 MDIO_PCS_DEVAD, \
6622 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
6623
6624/* Programs an image to DSP's flash via the SPI port*/
6625static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
6626 u8 ext_phy_addr,
6627 char data[], u32 size)
6628{
6629 const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
6630 /* Doesn't include last trans!*/
6631 const u16 last_trans_size = size%4; /* Num bytes on last trans */
6632 u16 trans_cnt, byte_cnt;
6633 u32 data_index;
6634 u16 tmp;
6635 u16 code_started = 0;
6636 u16 image_revision1, image_revision2;
6637 u16 cnt;
6638
6639 DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
6640 /* Going to flash*/
6641 if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
6642 /* This very often will be the case, because the image is built
6643 with 160Kbytes size whereas the total image size must actually
6644 be 160Kbytes-RESERVED_SIZE */
6645 DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
6646 "truncated to %d bytes\n", size, MAX_APP_SIZE);
6647 size = MAX_APP_SIZE+HEADER_SIZE;
6648 }
6649 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
3196a88a 6650 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
ea4e040a
YR		 6651 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
6652 and issuing a reset.*/
6653
6654 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
17de50b7 6655 MISC_REGISTERS_GPIO_HIGH, port);
ea4e040a
YR		 6656
6657 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
6658
6659 /* wait 0.5 sec */
6660 for (cnt = 0; cnt < 100; cnt++)
6661 msleep(5);
6662
6663 /* Make sure we can access the DSP
6664 And it's in the correct mode (waiting for download) */
6665
6666 bnx2x_cl45_read(bp, port,
6667 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6668 ext_phy_addr,
6669 MDIO_PCS_DEVAD,
6670 MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
6671
6672 if (tmp != 0x000A) {
6673 DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
6674 "Expected 0x000A, read 0x%04X\n", tmp);
6675 DP(NETIF_MSG_LINK, "Download failed\n");
6676 return -EINVAL;
6677 }
6678
6679 /* Mux the SPI interface away from the internal processor */
6680 bnx2x_cl45_write(bp, port,
6681 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6682 ext_phy_addr,
6683 MDIO_PCS_DEVAD,
6684 MDIO_PCS_REG_7101_SPI_MUX, 1);
6685
6686 /* Reset the SPI port */
6687 bnx2x_cl45_write(bp, port,
6688 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6689 ext_phy_addr,
6690 MDIO_PCS_DEVAD,
6691 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6692 bnx2x_cl45_write(bp, port,
6693 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6694 ext_phy_addr,
6695 MDIO_PCS_DEVAD,
6696 MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
6697 (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
6698 bnx2x_cl45_write(bp, port,
6699 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6700 ext_phy_addr,
6701 MDIO_PCS_DEVAD,
6702 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
6703
6704 /* Erase the flash */
6705 bnx2x_cl45_write(bp, port,
6706 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6707 ext_phy_addr,
6708 MDIO_PCS_DEVAD,
6709 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6710 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6711
6712 bnx2x_cl45_write(bp, port,
6713 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6714 ext_phy_addr,
6715 MDIO_PCS_DEVAD,
6716 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6717 1);
6718
6719 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6720 bnx2x_cl45_write(bp, port,
6721 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6722 ext_phy_addr,
6723 MDIO_PCS_DEVAD,
6724 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6725 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
6726
6727 bnx2x_cl45_write(bp, port,
6728 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6729 ext_phy_addr,
6730 MDIO_PCS_DEVAD,
6731 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6732 1);
6733 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6734
6735 /* Wait 10 seconds, the maximum time for the erase to complete */
6736 DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
6737 for (cnt = 0; cnt < 1000; cnt++)
6738 msleep(10);
6739
6740 DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
6741 data_index = 0;
6742 for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
6743 bnx2x_cl45_write(bp, port,
6744 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6745 ext_phy_addr,
6746 MDIO_PCS_DEVAD,
6747 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6748 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6749
6750 bnx2x_cl45_write(bp, port,
6751 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6752 ext_phy_addr,
6753 MDIO_PCS_DEVAD,
6754 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6755 1);
6756 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6757
6758 bnx2x_cl45_write(bp, port,
6759 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6760 ext_phy_addr,
6761 MDIO_PCS_DEVAD,
6762 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6763 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6764
6765 /* Bits 23-16 of address */
6766 bnx2x_cl45_write(bp, port,
6767 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6768 ext_phy_addr,
6769 MDIO_PCS_DEVAD,
6770 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6771 (data_index>>16));
6772 /* Bits 15-8 of address */
6773 bnx2x_cl45_write(bp, port,
6774 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6775 ext_phy_addr,
6776 MDIO_PCS_DEVAD,
6777 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6778 (data_index>>8));
6779
6780 /* Bits 7-0 of address */
6781 bnx2x_cl45_write(bp, port,
6782 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6783 ext_phy_addr,
6784 MDIO_PCS_DEVAD,
6785 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6786 ((u16)data_index));
6787
6788 byte_cnt = 0;
6789 while (byte_cnt < 4 && data_index < size) {
6790 bnx2x_cl45_write(bp, port,
6791 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6792 ext_phy_addr,
6793 MDIO_PCS_DEVAD,
6794 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6795 data[data_index++]);
6796 byte_cnt++;
6797 }
6798
6799 bnx2x_cl45_write(bp, port,
6800 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6801 ext_phy_addr,
6802 MDIO_PCS_DEVAD,
6803 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6804 byte_cnt+4);
6805
6806 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6807 msleep(5); /* Wait 5 ms minimum between transs */
6808
6809 /* Let the user know something's going on.*/
6810 /* a pacifier ever 4K */
6811 if ((data_index % 1023) == 0)
6812 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
6813 }
6814
6815 DP(NETIF_MSG_LINK, "\n");
6816 /* Transfer the last block if there is data remaining */
6817 if (last_trans_size) {
6818 bnx2x_cl45_write(bp, port,
6819 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6820 ext_phy_addr,
6821 MDIO_PCS_DEVAD,
6822 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6823 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
6824
6825 bnx2x_cl45_write(bp, port,
6826 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6827 ext_phy_addr,
6828 MDIO_PCS_DEVAD,
6829 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6830 1);
6831
6832 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6833
6834 bnx2x_cl45_write(bp, port,
6835 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6836 ext_phy_addr,
6837 MDIO_PCS_DEVAD,
6838 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6839 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
6840
6841 /* Bits 23-16 of address */
6842 bnx2x_cl45_write(bp, port,
6843 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6844 ext_phy_addr,
6845 MDIO_PCS_DEVAD,
6846 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6847 (data_index>>16));
6848 /* Bits 15-8 of address */
6849 bnx2x_cl45_write(bp, port,
6850 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6851 ext_phy_addr,
6852 MDIO_PCS_DEVAD,
6853 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6854 (data_index>>8));
6855
6856 /* Bits 7-0 of address */
6857 bnx2x_cl45_write(bp, port,
6858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6859 ext_phy_addr,
6860 MDIO_PCS_DEVAD,
6861 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6862 ((u16)data_index));
6863
6864 byte_cnt = 0;
6865 while (byte_cnt < last_trans_size && data_index < size) {
6866 /* Bits 7-0 of address */
6867 bnx2x_cl45_write(bp, port,
6868 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6869 ext_phy_addr,
6870 MDIO_PCS_DEVAD,
6871 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
6872 data[data_index++]);
6873 byte_cnt++;
6874 }
6875
6876 bnx2x_cl45_write(bp, port,
6877 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6878 ext_phy_addr,
6879 MDIO_PCS_DEVAD,
6880 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
6881 byte_cnt+4);
6882
6883 SPI_START_TRANSFER(bp, port, ext_phy_addr);
6884 }
6885
6886 /* DSP Remove Download Mode */
17de50b7
EG		 6887 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6888 MISC_REGISTERS_GPIO_LOW, port);
ea4e040a
YR		 6889
6890 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
6891
6892 /* wait 0.5 sec to allow it to run */
6893 for (cnt = 0; cnt < 100; cnt++)
6894 msleep(5);
6895
17de50b7 6896 bnx2x_hw_reset(bp, port);
ea4e040a
YR		 6897
6898 for (cnt = 0; cnt < 100; cnt++)
6899 msleep(5);
6900
6901 /* Check that the code is started. In case the download
6902 checksum failed, the code won't be started. */
6903 bnx2x_cl45_read(bp, port,
6904 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6905 ext_phy_addr,
6906 MDIO_PCS_DEVAD,
6907 MDIO_PCS_REG_7101_DSP_ACCESS,
6908 &tmp);
6909
6910 code_started = (tmp & (1<<4));
6911 if (!code_started) {
6912 DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
6913 return -EINVAL;
6914 }
6915
6916 /* Verify that the file revision is now equal to the image
6917 revision within the DSP */
6918 bnx2x_cl45_read(bp, port,
6919 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6920 ext_phy_addr,
6921 MDIO_PMA_DEVAD,
6922 MDIO_PMA_REG_7101_VER1,
6923 &image_revision1);
6924
6925 bnx2x_cl45_read(bp, port,
6926 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6927 ext_phy_addr,
6928 MDIO_PMA_DEVAD,
6929 MDIO_PMA_REG_7101_VER2,
6930 &image_revision2);
6931
3196a88a 6932 if (data[0x14e] != (image_revision2&0xFF) ||
ea4e040a
YR		 6933 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
6934 data[0x150] != (image_revision1&0xFF) ||
6935 data[0x151] != ((image_revision1&0xFF00)>>8)) {
6936 DP(NETIF_MSG_LINK, "Download failed.\n");
6937 return -EINVAL;
6938 }
6939 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
6940 return 0;
6941}
6942
6943u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
6944 u8 driver_loaded, char data[], u32 size)
6945{
6946 u8 rc = 0;
6947 u32 ext_phy_type;
6948 u8 ext_phy_addr;
6949 ext_phy_addr = ((ext_phy_config &
6950 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6951 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6952
6953 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6954
6955 switch (ext_phy_type) {
6956 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6957 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6958 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
6959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
6960 DP(NETIF_MSG_LINK,
6961 "Flash download not supported for this ext phy\n");
6962 rc = -EINVAL;
6963 break;
6964 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6965 /* Take ext phy out of reset */
6966 if (!driver_loaded)
57963ed9 6967 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
ea4e040a
YR		 6968 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
6969 data, size);
6970 if (!driver_loaded)
17de50b7 6971 bnx2x_turn_off_sf(bp, port);
ea4e040a
YR		 6972 break;
6973 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6974 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
6975 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
6976 default:
6977 DP(NETIF_MSG_LINK, "Invalid ext phy type\n");
6978 rc = -EINVAL;
6979 break;
6980 }
6981 return rc;
6982}
6983
Linux 6.x block layer and io_uring tree(s)