Commit | Line | Data |
---|---|---|
cd88ccee | 1 | /* Copyright 2008-2011 Broadcom Corporation |
ea4e040a YR |
2 | * |
3 | * Unless you and Broadcom execute a separate written software license | |
4 | * agreement governing use of this software, this software is licensed to you | |
5 | * under the terms of the GNU General Public License version 2, available | |
6 | * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). | |
7 | * | |
8 | * Notwithstanding the above, under no circumstances may you combine this | |
9 | * software in any way with any other Broadcom software provided under a | |
10 | * license other than the GPL, without Broadcom's express prior written | |
11 | * consent. | |
12 | * | |
13 | * Written by Yaniv Rosner | |
14 | * | |
15 | */ | |
16 | ||
7995c64e JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
ea4e040a YR |
19 | #include <linux/kernel.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/netdevice.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ethtool.h> | |
25 | #include <linux/mutex.h> | |
ea4e040a | 26 | |
ea4e040a YR |
27 | #include "bnx2x.h" |
28 | ||
29 | /********************************************************/ | |
3196a88a | 30 | #define ETH_HLEN 14 |
cd88ccee YR |
31 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
32 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
ea4e040a YR |
33 | #define ETH_MIN_PACKET_SIZE 60 |
34 | #define ETH_MAX_PACKET_SIZE 1500 | |
35 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
36 | #define MDIO_ACCESS_TIMEOUT 1000 | |
cd88ccee | 37 | #define BMAC_CONTROL_RX_ENABLE 2 |
ea4e040a YR |
38 | |
39 | /***********************************************************/ | |
3196a88a | 40 | /* Shortcut definitions */ |
ea4e040a YR |
41 | /***********************************************************/ |
42 | ||
2f904460 EG |
43 | #define NIG_LATCH_BC_ENABLE_MI_INT 0 |
44 | ||
45 | #define NIG_STATUS_EMAC0_MI_INT \ | |
46 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT | |
ea4e040a YR |
47 | #define NIG_STATUS_XGXS0_LINK10G \ |
48 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | |
49 | #define NIG_STATUS_XGXS0_LINK_STATUS \ | |
50 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | |
51 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ | |
52 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | |
53 | #define NIG_STATUS_SERDES0_LINK_STATUS \ | |
54 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | |
55 | #define NIG_MASK_MI_INT \ | |
56 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | |
57 | #define NIG_MASK_XGXS0_LINK10G \ | |
58 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G | |
59 | #define NIG_MASK_XGXS0_LINK_STATUS \ | |
60 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS | |
61 | #define NIG_MASK_SERDES0_LINK_STATUS \ | |
62 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS | |
63 | ||
64 | #define MDIO_AN_CL73_OR_37_COMPLETE \ | |
65 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ | |
66 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) | |
67 | ||
68 | #define XGXS_RESET_BITS \ | |
69 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ | |
70 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ | |
71 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ | |
72 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ | |
73 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) | |
74 | ||
75 | #define SERDES_RESET_BITS \ | |
76 | (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ | |
77 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ | |
78 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ | |
79 | MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) | |
80 | ||
81 | #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 | |
82 | #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 | |
cd88ccee | 83 | #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM |
3196a88a | 84 | #define AUTONEG_PARALLEL \ |
ea4e040a | 85 | SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION |
3196a88a | 86 | #define AUTONEG_SGMII_FIBER_AUTODET \ |
ea4e040a | 87 | SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT |
3196a88a | 88 | #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY |
ea4e040a YR |
89 | |
90 | #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ | |
91 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE | |
92 | #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ | |
93 | MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE | |
94 | #define GP_STATUS_SPEED_MASK \ | |
95 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK | |
96 | #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M | |
97 | #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M | |
98 | #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G | |
99 | #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G | |
100 | #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G | |
101 | #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G | |
102 | #define GP_STATUS_10G_HIG \ | |
103 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG | |
104 | #define GP_STATUS_10G_CX4 \ | |
105 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 | |
106 | #define GP_STATUS_12G_HIG \ | |
107 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG | |
108 | #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G | |
109 | #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G | |
110 | #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G | |
111 | #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G | |
112 | #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX | |
113 | #define GP_STATUS_10G_KX4 \ | |
114 | MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 | |
115 | ||
cd88ccee YR |
116 | #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD |
117 | #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD | |
ea4e040a | 118 | #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD |
cd88ccee | 119 | #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 |
ea4e040a YR |
120 | #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD |
121 | #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD | |
122 | #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD | |
123 | #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD | |
124 | #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD | |
125 | #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD | |
126 | #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD | |
cd88ccee YR |
127 | #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD |
128 | #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD | |
129 | #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD | |
130 | #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD | |
ea4e040a YR |
131 | #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD |
132 | #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD | |
cd88ccee YR |
133 | #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD |
134 | #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD | |
135 | #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD | |
136 | #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD | |
137 | #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD | |
138 | #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD | |
ea4e040a YR |
139 | |
140 | #define PHY_XGXS_FLAG 0x1 | |
141 | #define PHY_SGMII_FLAG 0x2 | |
142 | #define PHY_SERDES_FLAG 0x4 | |
143 | ||
589abe3a EG |
144 | /* */ |
145 | #define SFP_EEPROM_CON_TYPE_ADDR 0x2 | |
cd88ccee | 146 | #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 |
589abe3a EG |
147 | #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 |
148 | ||
4d295db0 EG |
149 | |
150 | #define SFP_EEPROM_COMP_CODE_ADDR 0x3 | |
151 | #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) | |
152 | #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) | |
153 | #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) | |
154 | ||
589abe3a EG |
155 | #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8 |
156 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 | |
cd88ccee | 157 | #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 |
4d295db0 | 158 | |
cd88ccee | 159 | #define SFP_EEPROM_OPTIONS_ADDR 0x40 |
589abe3a | 160 | #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 |
cd88ccee | 161 | #define SFP_EEPROM_OPTIONS_SIZE 2 |
589abe3a | 162 | |
cd88ccee YR |
163 | #define EDC_MODE_LINEAR 0x0022 |
164 | #define EDC_MODE_LIMITING 0x0044 | |
165 | #define EDC_MODE_PASSIVE_DAC 0x0055 | |
4d295db0 EG |
166 | |
167 | ||
bcab15c5 VZ |
168 | #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) |
169 | #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) | |
ea4e040a YR |
170 | /**********************************************************/ |
171 | /* INTERFACE */ | |
172 | /**********************************************************/ | |
e10bc84d | 173 | |
cd2be89b | 174 | #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 175 | bnx2x_cl45_write(_bp, _phy, \ |
7aa0711f | 176 | (_phy)->def_md_devad, \ |
ea4e040a YR |
177 | (_bank + (_addr & 0xf)), \ |
178 | _val) | |
179 | ||
cd2be89b | 180 | #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ |
e10bc84d | 181 | bnx2x_cl45_read(_bp, _phy, \ |
7aa0711f | 182 | (_phy)->def_md_devad, \ |
ea4e040a YR |
183 | (_bank + (_addr & 0xf)), \ |
184 | _val) | |
185 | ||
ea4e040a YR |
186 | static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) |
187 | { | |
188 | u32 val = REG_RD(bp, reg); | |
189 | ||
190 | val |= bits; | |
191 | REG_WR(bp, reg, val); | |
192 | return val; | |
193 | } | |
194 | ||
195 | static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |
196 | { | |
197 | u32 val = REG_RD(bp, reg); | |
198 | ||
199 | val &= ~bits; | |
200 | REG_WR(bp, reg, val); | |
201 | return val; | |
202 | } | |
203 | ||
bcab15c5 VZ |
204 | /******************************************************************/ |
205 | /* ETS section */ | |
206 | /******************************************************************/ | |
207 | void bnx2x_ets_disabled(struct link_params *params) | |
208 | { | |
209 | /* ETS disabled configuration*/ | |
210 | struct bnx2x *bp = params->bp; | |
211 | ||
212 | DP(NETIF_MSG_LINK, "ETS disabled configuration\n"); | |
213 | ||
2cf7acf9 | 214 | /* |
bcab15c5 VZ |
215 | * mapping between entry priority to client number (0,1,2 -debug and |
216 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) | |
217 | * 3bits client num. | |
218 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
219 | * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 | |
220 | */ | |
221 | ||
222 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); | |
2cf7acf9 | 223 | /* |
bcab15c5 VZ |
224 | * Bitmap of 5bits length. Each bit specifies whether the entry behaves |
225 | * as strict. Bits 0,1,2 - debug and management entries, 3 - | |
226 | * COS0 entry, 4 - COS1 entry. | |
227 | * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT | |
228 | * bit4 bit3 bit2 bit1 bit0 | |
229 | * MCP and debug are strict | |
230 | */ | |
231 | ||
232 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); | |
233 | /* defines which entries (clients) are subjected to WFQ arbitration */ | |
234 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); | |
2cf7acf9 YR |
235 | /* |
236 | * For strict priority entries defines the number of consecutive | |
237 | * slots for the highest priority. | |
238 | */ | |
bcab15c5 | 239 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); |
2cf7acf9 | 240 | /* |
bcab15c5 VZ |
241 | * mapping between the CREDIT_WEIGHT registers and actual client |
242 | * numbers | |
243 | */ | |
244 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); | |
245 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); | |
246 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); | |
247 | ||
248 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); | |
249 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); | |
250 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); | |
251 | /* ETS mode disable */ | |
252 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
2cf7acf9 | 253 | /* |
bcab15c5 VZ |
254 | * If ETS mode is enabled (there is no strict priority) defines a WFQ |
255 | * weight for COS0/COS1. | |
256 | */ | |
257 | REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); | |
258 | REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); | |
259 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ | |
260 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); | |
261 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); | |
262 | /* Defines the number of consecutive slots for the strict priority */ | |
263 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
264 | } | |
265 | ||
65a001ba | 266 | static void bnx2x_ets_bw_limit_common(const struct link_params *params) |
bcab15c5 VZ |
267 | { |
268 | /* ETS disabled configuration */ | |
269 | struct bnx2x *bp = params->bp; | |
270 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
2cf7acf9 YR |
271 | /* |
272 | * defines which entries (clients) are subjected to WFQ arbitration | |
273 | * COS0 0x8 | |
274 | * COS1 0x10 | |
275 | */ | |
bcab15c5 | 276 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); |
2cf7acf9 YR |
277 | /* |
278 | * mapping between the ARB_CREDIT_WEIGHT registers and actual | |
279 | * client numbers (WEIGHT_0 does not actually have to represent | |
280 | * client 0) | |
281 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
282 | * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 | |
283 | */ | |
bcab15c5 VZ |
284 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); |
285 | ||
286 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, | |
287 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
288 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, | |
289 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
290 | ||
291 | /* ETS mode enabled*/ | |
292 | REG_WR(bp, PBF_REG_ETS_ENABLED, 1); | |
293 | ||
294 | /* Defines the number of consecutive slots for the strict priority */ | |
295 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); | |
2cf7acf9 YR |
296 | /* |
297 | * Bitmap of 5bits length. Each bit specifies whether the entry behaves | |
298 | * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 | |
299 | * entry, 4 - COS1 entry. | |
300 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
301 | * bit4 bit3 bit2 bit1 bit0 | |
302 | * MCP and debug are strict | |
303 | */ | |
bcab15c5 VZ |
304 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); |
305 | ||
306 | /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ | |
307 | REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, | |
308 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
309 | REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, | |
310 | ETS_BW_LIMIT_CREDIT_UPPER_BOUND); | |
311 | } | |
312 | ||
313 | void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw, | |
314 | const u32 cos1_bw) | |
315 | { | |
316 | /* ETS disabled configuration*/ | |
317 | struct bnx2x *bp = params->bp; | |
318 | const u32 total_bw = cos0_bw + cos1_bw; | |
319 | u32 cos0_credit_weight = 0; | |
320 | u32 cos1_credit_weight = 0; | |
321 | ||
322 | DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); | |
323 | ||
324 | if ((0 == total_bw) || | |
325 | (0 == cos0_bw) || | |
326 | (0 == cos1_bw)) { | |
cd88ccee | 327 | DP(NETIF_MSG_LINK, "Total BW can't be zero\n"); |
bcab15c5 VZ |
328 | return; |
329 | } | |
330 | ||
331 | cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
332 | total_bw; | |
333 | cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/ | |
334 | total_bw; | |
335 | ||
336 | bnx2x_ets_bw_limit_common(params); | |
337 | ||
338 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); | |
339 | REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); | |
340 | ||
341 | REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); | |
342 | REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); | |
343 | } | |
344 | ||
345 | u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos) | |
346 | { | |
347 | /* ETS disabled configuration*/ | |
348 | struct bnx2x *bp = params->bp; | |
349 | u32 val = 0; | |
350 | ||
bcab15c5 | 351 | DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); |
2cf7acf9 | 352 | /* |
bcab15c5 VZ |
353 | * Bitmap of 5bits length. Each bit specifies whether the entry behaves |
354 | * as strict. Bits 0,1,2 - debug and management entries, | |
355 | * 3 - COS0 entry, 4 - COS1 entry. | |
356 | * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT | |
357 | * bit4 bit3 bit2 bit1 bit0 | |
358 | * MCP and debug are strict | |
359 | */ | |
360 | REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); | |
2cf7acf9 | 361 | /* |
bcab15c5 VZ |
362 | * For strict priority entries defines the number of consecutive slots |
363 | * for the highest priority. | |
364 | */ | |
365 | REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); | |
366 | /* ETS mode disable */ | |
367 | REG_WR(bp, PBF_REG_ETS_ENABLED, 0); | |
368 | /* Defines the number of consecutive slots for the strict priority */ | |
369 | REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); | |
370 | ||
371 | /* Defines the number of consecutive slots for the strict priority */ | |
372 | REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); | |
373 | ||
2cf7acf9 YR |
374 | /* |
375 | * mapping between entry priority to client number (0,1,2 -debug and | |
376 | * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) | |
377 | * 3bits client num. | |
378 | * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | |
379 | * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 | |
380 | * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 | |
381 | */ | |
bcab15c5 VZ |
382 | val = (0 == strict_cos) ? 0x2318 : 0x22E0; |
383 | REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); | |
384 | ||
385 | return 0; | |
386 | } | |
387 | /******************************************************************/ | |
388 | /* ETS section */ | |
389 | /******************************************************************/ | |
390 | ||
391 | static void bnx2x_bmac2_get_pfc_stat(struct link_params *params, | |
392 | u32 pfc_frames_sent[2], | |
393 | u32 pfc_frames_received[2]) | |
394 | { | |
395 | /* Read pfc statistic */ | |
396 | struct bnx2x *bp = params->bp; | |
397 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
398 | NIG_REG_INGRESS_BMAC0_MEM; | |
399 | ||
400 | DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n"); | |
401 | ||
402 | REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP, | |
403 | pfc_frames_sent, 2); | |
404 | ||
405 | REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP, | |
406 | pfc_frames_received, 2); | |
407 | ||
408 | } | |
409 | static void bnx2x_emac_get_pfc_stat(struct link_params *params, | |
410 | u32 pfc_frames_sent[2], | |
411 | u32 pfc_frames_received[2]) | |
412 | { | |
413 | /* Read pfc statistic */ | |
414 | struct bnx2x *bp = params->bp; | |
415 | u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
416 | u32 val_xon = 0; | |
417 | u32 val_xoff = 0; | |
418 | ||
419 | DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n"); | |
420 | ||
421 | /* PFC received frames */ | |
422 | val_xoff = REG_RD(bp, emac_base + | |
423 | EMAC_REG_RX_PFC_STATS_XOFF_RCVD); | |
424 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; | |
425 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); | |
426 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; | |
427 | ||
428 | pfc_frames_received[0] = val_xon + val_xoff; | |
429 | ||
430 | /* PFC received sent */ | |
431 | val_xoff = REG_RD(bp, emac_base + | |
432 | EMAC_REG_RX_PFC_STATS_XOFF_SENT); | |
433 | val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; | |
434 | val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); | |
435 | val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; | |
436 | ||
437 | pfc_frames_sent[0] = val_xon + val_xoff; | |
438 | } | |
439 | ||
440 | void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars, | |
441 | u32 pfc_frames_sent[2], | |
442 | u32 pfc_frames_received[2]) | |
443 | { | |
444 | /* Read pfc statistic */ | |
445 | struct bnx2x *bp = params->bp; | |
446 | u32 val = 0; | |
447 | DP(NETIF_MSG_LINK, "pfc statistic\n"); | |
448 | ||
449 | if (!vars->link_up) | |
450 | return; | |
451 | ||
452 | val = REG_RD(bp, MISC_REG_RESET_REG_2); | |
453 | if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) | |
454 | == 0) { | |
455 | DP(NETIF_MSG_LINK, "About to read stats from EMAC\n"); | |
456 | bnx2x_emac_get_pfc_stat(params, pfc_frames_sent, | |
457 | pfc_frames_received); | |
458 | } else { | |
459 | DP(NETIF_MSG_LINK, "About to read stats from BMAC\n"); | |
460 | bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent, | |
461 | pfc_frames_received); | |
462 | } | |
463 | } | |
464 | /******************************************************************/ | |
465 | /* MAC/PBF section */ | |
466 | /******************************************************************/ | |
ea4e040a | 467 | static void bnx2x_emac_init(struct link_params *params, |
cd88ccee | 468 | struct link_vars *vars) |
ea4e040a YR |
469 | { |
470 | /* reset and unreset the emac core */ | |
471 | struct bnx2x *bp = params->bp; | |
472 | u8 port = params->port; | |
473 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
474 | u32 val; | |
475 | u16 timeout; | |
476 | ||
477 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 478 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
479 | udelay(5); |
480 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 481 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
ea4e040a YR |
482 | |
483 | /* init emac - use read-modify-write */ | |
484 | /* self clear reset */ | |
485 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
3196a88a | 486 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); |
ea4e040a YR |
487 | |
488 | timeout = 200; | |
3196a88a | 489 | do { |
ea4e040a YR |
490 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); |
491 | DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val); | |
492 | if (!timeout) { | |
493 | DP(NETIF_MSG_LINK, "EMAC timeout!\n"); | |
494 | return; | |
495 | } | |
496 | timeout--; | |
3196a88a | 497 | } while (val & EMAC_MODE_RESET); |
ea4e040a YR |
498 | |
499 | /* Set mac address */ | |
500 | val = ((params->mac_addr[0] << 8) | | |
501 | params->mac_addr[1]); | |
3196a88a | 502 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); |
ea4e040a YR |
503 | |
504 | val = ((params->mac_addr[2] << 24) | | |
505 | (params->mac_addr[3] << 16) | | |
506 | (params->mac_addr[4] << 8) | | |
507 | params->mac_addr[5]); | |
3196a88a | 508 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); |
ea4e040a YR |
509 | } |
510 | ||
511 | static u8 bnx2x_emac_enable(struct link_params *params, | |
cd88ccee | 512 | struct link_vars *vars, u8 lb) |
ea4e040a YR |
513 | { |
514 | struct bnx2x *bp = params->bp; | |
515 | u8 port = params->port; | |
516 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
517 | u32 val; | |
518 | ||
519 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); | |
520 | ||
521 | /* enable emac and not bmac */ | |
522 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); | |
523 | ||
524 | /* for paladium */ | |
525 | if (CHIP_REV_IS_EMUL(bp)) { | |
526 | /* Use lane 1 (of lanes 0-3) */ | |
527 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); | |
cd88ccee | 528 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
529 | } |
530 | /* for fpga */ | |
531 | else | |
532 | ||
533 | if (CHIP_REV_IS_FPGA(bp)) { | |
534 | /* Use lane 1 (of lanes 0-3) */ | |
535 | DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n"); | |
536 | ||
537 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); | |
cd88ccee | 538 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
539 | } else |
540 | /* ASIC */ | |
541 | if (vars->phy_flags & PHY_XGXS_FLAG) { | |
542 | u32 ser_lane = ((params->lane_config & | |
cd88ccee YR |
543 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
544 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a YR |
545 | |
546 | DP(NETIF_MSG_LINK, "XGXS\n"); | |
547 | /* select the master lanes (out of 0-3) */ | |
cd88ccee | 548 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); |
ea4e040a | 549 | /* select XGXS */ |
cd88ccee | 550 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); |
ea4e040a YR |
551 | |
552 | } else { /* SerDes */ | |
553 | DP(NETIF_MSG_LINK, "SerDes\n"); | |
554 | /* select SerDes */ | |
cd88ccee | 555 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); |
ea4e040a YR |
556 | } |
557 | ||
811a2f2d | 558 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, |
cd88ccee | 559 | EMAC_RX_MODE_RESET); |
811a2f2d | 560 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, |
cd88ccee | 561 | EMAC_TX_MODE_RESET); |
ea4e040a YR |
562 | |
563 | if (CHIP_REV_IS_SLOW(bp)) { | |
564 | /* config GMII mode */ | |
565 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
cd88ccee | 566 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); |
ea4e040a YR |
567 | } else { /* ASIC */ |
568 | /* pause enable/disable */ | |
569 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, | |
570 | EMAC_RX_MODE_FLOW_EN); | |
ea4e040a YR |
571 | |
572 | bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
bcab15c5 VZ |
573 | (EMAC_TX_MODE_EXT_PAUSE_EN | |
574 | EMAC_TX_MODE_FLOW_EN)); | |
575 | if (!(params->feature_config_flags & | |
576 | FEATURE_CONFIG_PFC_ENABLED)) { | |
577 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) | |
578 | bnx2x_bits_en(bp, emac_base + | |
579 | EMAC_REG_EMAC_RX_MODE, | |
580 | EMAC_RX_MODE_FLOW_EN); | |
581 | ||
582 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) | |
583 | bnx2x_bits_en(bp, emac_base + | |
584 | EMAC_REG_EMAC_TX_MODE, | |
585 | (EMAC_TX_MODE_EXT_PAUSE_EN | | |
586 | EMAC_TX_MODE_FLOW_EN)); | |
587 | } else | |
588 | bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, | |
589 | EMAC_TX_MODE_FLOW_EN); | |
ea4e040a YR |
590 | } |
591 | ||
592 | /* KEEP_VLAN_TAG, promiscuous */ | |
593 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | |
594 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | |
bcab15c5 | 595 | |
2cf7acf9 YR |
596 | /* |
597 | * Setting this bit causes MAC control frames (except for pause | |
598 | * frames) to be passed on for processing. This setting has no | |
599 | * affect on the operation of the pause frames. This bit effects | |
600 | * all packets regardless of RX Parser packet sorting logic. | |
601 | * Turn the PFC off to make sure we are in Xon state before | |
602 | * enabling it. | |
603 | */ | |
bcab15c5 VZ |
604 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); |
605 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
606 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
607 | /* Enable PFC again */ | |
608 | EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, | |
609 | EMAC_REG_RX_PFC_MODE_RX_EN | | |
610 | EMAC_REG_RX_PFC_MODE_TX_EN | | |
611 | EMAC_REG_RX_PFC_MODE_PRIORITIES); | |
612 | ||
613 | EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, | |
614 | ((0x0101 << | |
615 | EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | | |
616 | (0x00ff << | |
617 | EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); | |
618 | val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; | |
619 | } | |
3196a88a | 620 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); |
ea4e040a YR |
621 | |
622 | /* Set Loopback */ | |
623 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); | |
624 | if (lb) | |
625 | val |= 0x810; | |
626 | else | |
627 | val &= ~0x810; | |
3196a88a | 628 | EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); |
ea4e040a | 629 | |
6c55c3cd EG |
630 | /* enable emac */ |
631 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); | |
632 | ||
ea4e040a | 633 | /* enable emac for jumbo packets */ |
3196a88a | 634 | EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, |
ea4e040a YR |
635 | (EMAC_RX_MTU_SIZE_JUMBO_ENA | |
636 | (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); | |
637 | ||
638 | /* strip CRC */ | |
639 | REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); | |
640 | ||
641 | /* disable the NIG in/out to the bmac */ | |
642 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); | |
643 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
644 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); | |
645 | ||
646 | /* enable the NIG in/out to the emac */ | |
647 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); | |
648 | val = 0; | |
bcab15c5 VZ |
649 | if ((params->feature_config_flags & |
650 | FEATURE_CONFIG_PFC_ENABLED) || | |
651 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
652 | val = 1; |
653 | ||
654 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); | |
655 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); | |
656 | ||
657 | if (CHIP_REV_IS_EMUL(bp)) { | |
658 | /* take the BigMac out of reset */ | |
cd88ccee YR |
659 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, |
660 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
ea4e040a YR |
661 | |
662 | /* enable access for bmac registers */ | |
663 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); | |
6f65497b EG |
664 | } else |
665 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); | |
ea4e040a YR |
666 | |
667 | vars->mac_type = MAC_TYPE_EMAC; | |
668 | return 0; | |
669 | } | |
670 | ||
bcab15c5 VZ |
671 | static void bnx2x_update_pfc_bmac1(struct link_params *params, |
672 | struct link_vars *vars) | |
673 | { | |
674 | u32 wb_data[2]; | |
675 | struct bnx2x *bp = params->bp; | |
676 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
677 | NIG_REG_INGRESS_BMAC0_MEM; | |
678 | ||
679 | u32 val = 0x14; | |
680 | if ((!(params->feature_config_flags & | |
681 | FEATURE_CONFIG_PFC_ENABLED)) && | |
682 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
683 | /* Enable BigMAC to react on received Pause packets */ | |
684 | val |= (1<<5); | |
685 | wb_data[0] = val; | |
686 | wb_data[1] = 0; | |
687 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); | |
688 | ||
689 | /* tx control */ | |
690 | val = 0xc0; | |
691 | if (!(params->feature_config_flags & | |
692 | FEATURE_CONFIG_PFC_ENABLED) && | |
693 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
694 | val |= 0x800000; | |
695 | wb_data[0] = val; | |
696 | wb_data[1] = 0; | |
697 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); | |
698 | } | |
699 | ||
700 | static void bnx2x_update_pfc_bmac2(struct link_params *params, | |
701 | struct link_vars *vars, | |
702 | u8 is_lb) | |
f2e0899f DK |
703 | { |
704 | /* | |
705 | * Set rx control: Strip CRC and enable BigMAC to relay | |
706 | * control packets to the system as well | |
707 | */ | |
708 | u32 wb_data[2]; | |
709 | struct bnx2x *bp = params->bp; | |
710 | u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : | |
711 | NIG_REG_INGRESS_BMAC0_MEM; | |
712 | u32 val = 0x14; | |
ea4e040a | 713 | |
bcab15c5 VZ |
714 | if ((!(params->feature_config_flags & |
715 | FEATURE_CONFIG_PFC_ENABLED)) && | |
716 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) | |
f2e0899f DK |
717 | /* Enable BigMAC to react on received Pause packets */ |
718 | val |= (1<<5); | |
719 | wb_data[0] = val; | |
720 | wb_data[1] = 0; | |
cd88ccee | 721 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); |
f2e0899f | 722 | udelay(30); |
ea4e040a | 723 | |
f2e0899f DK |
724 | /* Tx control */ |
725 | val = 0xc0; | |
bcab15c5 VZ |
726 | if (!(params->feature_config_flags & |
727 | FEATURE_CONFIG_PFC_ENABLED) && | |
728 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
f2e0899f DK |
729 | val |= 0x800000; |
730 | wb_data[0] = val; | |
731 | wb_data[1] = 0; | |
bcab15c5 VZ |
732 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); |
733 | ||
734 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { | |
735 | DP(NETIF_MSG_LINK, "PFC is enabled\n"); | |
736 | /* Enable PFC RX & TX & STATS and set 8 COS */ | |
737 | wb_data[0] = 0x0; | |
738 | wb_data[0] |= (1<<0); /* RX */ | |
739 | wb_data[0] |= (1<<1); /* TX */ | |
740 | wb_data[0] |= (1<<2); /* Force initial Xon */ | |
741 | wb_data[0] |= (1<<3); /* 8 cos */ | |
742 | wb_data[0] |= (1<<5); /* STATS */ | |
743 | wb_data[1] = 0; | |
744 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, | |
745 | wb_data, 2); | |
746 | /* Clear the force Xon */ | |
747 | wb_data[0] &= ~(1<<2); | |
748 | } else { | |
749 | DP(NETIF_MSG_LINK, "PFC is disabled\n"); | |
750 | /* disable PFC RX & TX & STATS and set 8 COS */ | |
751 | wb_data[0] = 0x8; | |
752 | wb_data[1] = 0; | |
753 | } | |
754 | ||
755 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); | |
f2e0899f | 756 | |
2cf7acf9 YR |
757 | /* |
758 | * Set Time (based unit is 512 bit time) between automatic | |
759 | * re-sending of PP packets amd enable automatic re-send of | |
760 | * Per-Priroity Packet as long as pp_gen is asserted and | |
761 | * pp_disable is low. | |
762 | */ | |
f2e0899f | 763 | val = 0x8000; |
bcab15c5 VZ |
764 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) |
765 | val |= (1<<16); /* enable automatic re-send */ | |
766 | ||
f2e0899f DK |
767 | wb_data[0] = val; |
768 | wb_data[1] = 0; | |
769 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, | |
cd88ccee | 770 | wb_data, 2); |
f2e0899f DK |
771 | |
772 | /* mac control */ | |
773 | val = 0x3; /* Enable RX and TX */ | |
774 | if (is_lb) { | |
775 | val |= 0x4; /* Local loopback */ | |
776 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
777 | } | |
bcab15c5 VZ |
778 | /* When PFC enabled, Pass pause frames towards the NIG. */ |
779 | if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) | |
780 | val |= ((1<<6)|(1<<5)); | |
f2e0899f DK |
781 | |
782 | wb_data[0] = val; | |
783 | wb_data[1] = 0; | |
cd88ccee | 784 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
785 | } |
786 | ||
bcab15c5 VZ |
787 | static void bnx2x_update_pfc_brb(struct link_params *params, |
788 | struct link_vars *vars, | |
789 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
790 | { | |
791 | struct bnx2x *bp = params->bp; | |
792 | int set_pfc = params->feature_config_flags & | |
793 | FEATURE_CONFIG_PFC_ENABLED; | |
794 | ||
795 | /* default - pause configuration */ | |
796 | u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE; | |
797 | u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE; | |
798 | u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE; | |
799 | u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE; | |
800 | ||
801 | if (set_pfc && pfc_params) | |
802 | /* First COS */ | |
803 | if (!pfc_params->cos0_pauseable) { | |
804 | pause_xoff_th = | |
805 | PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE; | |
806 | pause_xon_th = | |
807 | PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE; | |
808 | full_xoff_th = | |
809 | PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE; | |
810 | full_xon_th = | |
811 | PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE; | |
812 | } | |
2cf7acf9 YR |
813 | /* |
814 | * The number of free blocks below which the pause signal to class 0 | |
815 | * of MAC #n is asserted. n=0,1 | |
816 | */ | |
bcab15c5 | 817 | REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th); |
2cf7acf9 YR |
818 | /* |
819 | * The number of free blocks above which the pause signal to class 0 | |
820 | * of MAC #n is de-asserted. n=0,1 | |
821 | */ | |
bcab15c5 | 822 | REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th); |
2cf7acf9 YR |
823 | /* |
824 | * The number of free blocks below which the full signal to class 0 | |
825 | * of MAC #n is asserted. n=0,1 | |
826 | */ | |
bcab15c5 | 827 | REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th); |
2cf7acf9 YR |
828 | /* |
829 | * The number of free blocks above which the full signal to class 0 | |
830 | * of MAC #n is de-asserted. n=0,1 | |
831 | */ | |
bcab15c5 VZ |
832 | REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th); |
833 | ||
834 | if (set_pfc && pfc_params) { | |
835 | /* Second COS */ | |
836 | if (pfc_params->cos1_pauseable) { | |
837 | pause_xoff_th = | |
838 | PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE; | |
839 | pause_xon_th = | |
840 | PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE; | |
841 | full_xoff_th = | |
842 | PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE; | |
843 | full_xon_th = | |
844 | PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE; | |
845 | } else { | |
846 | pause_xoff_th = | |
847 | PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE; | |
848 | pause_xon_th = | |
849 | PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE; | |
850 | full_xoff_th = | |
851 | PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE; | |
852 | full_xon_th = | |
853 | PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE; | |
854 | } | |
2cf7acf9 | 855 | /* |
bcab15c5 VZ |
856 | * The number of free blocks below which the pause signal to |
857 | * class 1 of MAC #n is asserted. n=0,1 | |
2cf7acf9 | 858 | */ |
bcab15c5 | 859 | REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th); |
2cf7acf9 | 860 | /* |
bcab15c5 VZ |
861 | * The number of free blocks above which the pause signal to |
862 | * class 1 of MAC #n is de-asserted. n=0,1 | |
2cf7acf9 | 863 | */ |
bcab15c5 | 864 | REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th); |
2cf7acf9 | 865 | /* |
bcab15c5 VZ |
866 | * The number of free blocks below which the full signal to |
867 | * class 1 of MAC #n is asserted. n=0,1 | |
2cf7acf9 | 868 | */ |
bcab15c5 | 869 | REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th); |
2cf7acf9 | 870 | /* |
bcab15c5 VZ |
871 | * The number of free blocks above which the full signal to |
872 | * class 1 of MAC #n is de-asserted. n=0,1 | |
2cf7acf9 | 873 | */ |
bcab15c5 VZ |
874 | REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th); |
875 | } | |
876 | } | |
877 | ||
878 | static void bnx2x_update_pfc_nig(struct link_params *params, | |
879 | struct link_vars *vars, | |
880 | struct bnx2x_nig_brb_pfc_port_params *nig_params) | |
881 | { | |
882 | u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; | |
883 | u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0; | |
884 | u32 pkt_priority_to_cos = 0; | |
885 | u32 val; | |
886 | struct bnx2x *bp = params->bp; | |
887 | int port = params->port; | |
888 | int set_pfc = params->feature_config_flags & | |
889 | FEATURE_CONFIG_PFC_ENABLED; | |
890 | DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); | |
891 | ||
2cf7acf9 | 892 | /* |
bcab15c5 VZ |
893 | * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set |
894 | * MAC control frames (that are not pause packets) | |
895 | * will be forwarded to the XCM. | |
896 | */ | |
897 | xcm_mask = REG_RD(bp, | |
898 | port ? NIG_REG_LLH1_XCM_MASK : | |
899 | NIG_REG_LLH0_XCM_MASK); | |
2cf7acf9 | 900 | /* |
bcab15c5 VZ |
901 | * nig params will override non PFC params, since it's possible to |
902 | * do transition from PFC to SAFC | |
903 | */ | |
904 | if (set_pfc) { | |
905 | pause_enable = 0; | |
906 | llfc_out_en = 0; | |
907 | llfc_enable = 0; | |
908 | ppp_enable = 1; | |
909 | xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
910 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
911 | xcm0_out_en = 0; | |
912 | p0_hwpfc_enable = 1; | |
913 | } else { | |
914 | if (nig_params) { | |
915 | llfc_out_en = nig_params->llfc_out_en; | |
916 | llfc_enable = nig_params->llfc_enable; | |
917 | pause_enable = nig_params->pause_enable; | |
918 | } else /*defaul non PFC mode - PAUSE */ | |
919 | pause_enable = 1; | |
920 | ||
921 | xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : | |
922 | NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); | |
923 | xcm0_out_en = 1; | |
924 | } | |
925 | ||
926 | REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : | |
927 | NIG_REG_LLFC_OUT_EN_0, llfc_out_en); | |
928 | REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : | |
929 | NIG_REG_LLFC_ENABLE_0, llfc_enable); | |
930 | REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : | |
931 | NIG_REG_PAUSE_ENABLE_0, pause_enable); | |
932 | ||
933 | REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : | |
934 | NIG_REG_PPP_ENABLE_0, ppp_enable); | |
935 | ||
936 | REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : | |
937 | NIG_REG_LLH0_XCM_MASK, xcm_mask); | |
938 | ||
939 | REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); | |
940 | ||
941 | /* output enable for RX_XCM # IF */ | |
942 | REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en); | |
943 | ||
944 | /* HW PFC TX enable */ | |
945 | REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable); | |
946 | ||
947 | /* 0x2 = BMAC, 0x1= EMAC */ | |
948 | switch (vars->mac_type) { | |
949 | case MAC_TYPE_EMAC: | |
950 | val = 1; | |
951 | break; | |
952 | case MAC_TYPE_BMAC: | |
953 | val = 0; | |
954 | break; | |
955 | default: | |
956 | val = 0; | |
957 | break; | |
958 | } | |
959 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val); | |
960 | ||
961 | if (nig_params) { | |
962 | pkt_priority_to_cos = nig_params->pkt_priority_to_cos; | |
963 | ||
964 | REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK : | |
965 | NIG_REG_P0_RX_COS0_PRIORITY_MASK, | |
966 | nig_params->rx_cos0_priority_mask); | |
967 | ||
968 | REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK : | |
969 | NIG_REG_P0_RX_COS1_PRIORITY_MASK, | |
970 | nig_params->rx_cos1_priority_mask); | |
971 | ||
972 | REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : | |
973 | NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, | |
974 | nig_params->llfc_high_priority_classes); | |
975 | ||
976 | REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : | |
977 | NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, | |
978 | nig_params->llfc_low_priority_classes); | |
979 | } | |
980 | REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : | |
981 | NIG_REG_P0_PKT_PRIORITY_TO_COS, | |
982 | pkt_priority_to_cos); | |
983 | } | |
984 | ||
985 | ||
986 | void bnx2x_update_pfc(struct link_params *params, | |
987 | struct link_vars *vars, | |
988 | struct bnx2x_nig_brb_pfc_port_params *pfc_params) | |
989 | { | |
2cf7acf9 | 990 | /* |
bcab15c5 VZ |
991 | * The PFC and pause are orthogonal to one another, meaning when |
992 | * PFC is enabled, the pause are disabled, and when PFC is | |
993 | * disabled, pause are set according to the pause result. | |
994 | */ | |
995 | u32 val; | |
996 | struct bnx2x *bp = params->bp; | |
997 | ||
998 | /* update NIG params */ | |
999 | bnx2x_update_pfc_nig(params, vars, pfc_params); | |
1000 | ||
1001 | /* update BRB params */ | |
1002 | bnx2x_update_pfc_brb(params, vars, pfc_params); | |
1003 | ||
1004 | if (!vars->link_up) | |
1005 | return; | |
1006 | ||
1007 | val = REG_RD(bp, MISC_REG_RESET_REG_2); | |
1008 | if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) | |
1009 | == 0) { | |
1010 | DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n"); | |
1011 | bnx2x_emac_enable(params, vars, 0); | |
1012 | return; | |
1013 | } | |
1014 | ||
1015 | DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n"); | |
1016 | if (CHIP_IS_E2(bp)) | |
1017 | bnx2x_update_pfc_bmac2(params, vars, 0); | |
1018 | else | |
1019 | bnx2x_update_pfc_bmac1(params, vars); | |
1020 | ||
1021 | val = 0; | |
1022 | if ((params->feature_config_flags & | |
1023 | FEATURE_CONFIG_PFC_ENABLED) || | |
1024 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
1025 | val = 1; | |
1026 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); | |
1027 | } | |
f2e0899f DK |
1028 | |
1029 | static u8 bnx2x_bmac1_enable(struct link_params *params, | |
1030 | struct link_vars *vars, | |
cd88ccee | 1031 | u8 is_lb) |
ea4e040a YR |
1032 | { |
1033 | struct bnx2x *bp = params->bp; | |
1034 | u8 port = params->port; | |
1035 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1036 | NIG_REG_INGRESS_BMAC0_MEM; | |
1037 | u32 wb_data[2]; | |
1038 | u32 val; | |
1039 | ||
f2e0899f | 1040 | DP(NETIF_MSG_LINK, "Enabling BigMAC1\n"); |
ea4e040a YR |
1041 | |
1042 | /* XGXS control */ | |
1043 | wb_data[0] = 0x3c; | |
1044 | wb_data[1] = 0; | |
cd88ccee YR |
1045 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, |
1046 | wb_data, 2); | |
ea4e040a YR |
1047 | |
1048 | /* tx MAC SA */ | |
1049 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
1050 | (params->mac_addr[3] << 16) | | |
1051 | (params->mac_addr[4] << 8) | | |
1052 | params->mac_addr[5]); | |
1053 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
1054 | params->mac_addr[1]); | |
cd88ccee | 1055 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); |
ea4e040a | 1056 | |
ea4e040a YR |
1057 | /* mac control */ |
1058 | val = 0x3; | |
1059 | if (is_lb) { | |
1060 | val |= 0x4; | |
1061 | DP(NETIF_MSG_LINK, "enable bmac loopback\n"); | |
1062 | } | |
1063 | wb_data[0] = val; | |
1064 | wb_data[1] = 0; | |
cd88ccee | 1065 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); |
ea4e040a | 1066 | |
ea4e040a YR |
1067 | /* set rx mtu */ |
1068 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
1069 | wb_data[1] = 0; | |
cd88ccee | 1070 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); |
ea4e040a | 1071 | |
bcab15c5 | 1072 | bnx2x_update_pfc_bmac1(params, vars); |
ea4e040a YR |
1073 | |
1074 | /* set tx mtu */ | |
1075 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
1076 | wb_data[1] = 0; | |
cd88ccee | 1077 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); |
ea4e040a YR |
1078 | |
1079 | /* set cnt max size */ | |
1080 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
1081 | wb_data[1] = 0; | |
cd88ccee | 1082 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
ea4e040a YR |
1083 | |
1084 | /* configure safc */ | |
1085 | wb_data[0] = 0x1000200; | |
1086 | wb_data[1] = 0; | |
1087 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, | |
1088 | wb_data, 2); | |
1089 | /* fix for emulation */ | |
1090 | if (CHIP_REV_IS_EMUL(bp)) { | |
1091 | wb_data[0] = 0xf000; | |
1092 | wb_data[1] = 0; | |
cd88ccee | 1093 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, |
ea4e040a YR |
1094 | wb_data, 2); |
1095 | } | |
1096 | ||
f2e0899f DK |
1097 | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static u8 bnx2x_bmac2_enable(struct link_params *params, | |
1102 | struct link_vars *vars, | |
1103 | u8 is_lb) | |
1104 | { | |
1105 | struct bnx2x *bp = params->bp; | |
1106 | u8 port = params->port; | |
1107 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
1108 | NIG_REG_INGRESS_BMAC0_MEM; | |
1109 | u32 wb_data[2]; | |
1110 | ||
1111 | DP(NETIF_MSG_LINK, "Enabling BigMAC2\n"); | |
1112 | ||
1113 | wb_data[0] = 0; | |
1114 | wb_data[1] = 0; | |
cd88ccee | 1115 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); |
f2e0899f DK |
1116 | udelay(30); |
1117 | ||
1118 | /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ | |
1119 | wb_data[0] = 0x3c; | |
1120 | wb_data[1] = 0; | |
cd88ccee YR |
1121 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, |
1122 | wb_data, 2); | |
f2e0899f DK |
1123 | |
1124 | udelay(30); | |
1125 | ||
1126 | /* tx MAC SA */ | |
1127 | wb_data[0] = ((params->mac_addr[2] << 24) | | |
1128 | (params->mac_addr[3] << 16) | | |
1129 | (params->mac_addr[4] << 8) | | |
1130 | params->mac_addr[5]); | |
1131 | wb_data[1] = ((params->mac_addr[0] << 8) | | |
1132 | params->mac_addr[1]); | |
1133 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, | |
cd88ccee | 1134 | wb_data, 2); |
f2e0899f DK |
1135 | |
1136 | udelay(30); | |
1137 | ||
1138 | /* Configure SAFC */ | |
1139 | wb_data[0] = 0x1000200; | |
1140 | wb_data[1] = 0; | |
1141 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, | |
cd88ccee | 1142 | wb_data, 2); |
f2e0899f DK |
1143 | udelay(30); |
1144 | ||
1145 | /* set rx mtu */ | |
1146 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
1147 | wb_data[1] = 0; | |
cd88ccee | 1148 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
1149 | udelay(30); |
1150 | ||
1151 | /* set tx mtu */ | |
1152 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; | |
1153 | wb_data[1] = 0; | |
cd88ccee | 1154 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); |
f2e0899f DK |
1155 | udelay(30); |
1156 | /* set cnt max size */ | |
1157 | wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2; | |
1158 | wb_data[1] = 0; | |
cd88ccee | 1159 | REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); |
f2e0899f | 1160 | udelay(30); |
bcab15c5 | 1161 | bnx2x_update_pfc_bmac2(params, vars, is_lb); |
f2e0899f DK |
1162 | |
1163 | return 0; | |
1164 | } | |
1165 | ||
8d96286a | 1166 | static u8 bnx2x_bmac_enable(struct link_params *params, |
f2e0899f DK |
1167 | struct link_vars *vars, |
1168 | u8 is_lb) | |
1169 | { | |
1170 | u8 rc, port = params->port; | |
1171 | struct bnx2x *bp = params->bp; | |
1172 | u32 val; | |
1173 | /* reset and unreset the BigMac */ | |
1174 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
cd88ccee | 1175 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
1d9c05d4 | 1176 | msleep(1); |
f2e0899f DK |
1177 | |
1178 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, | |
cd88ccee | 1179 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
f2e0899f DK |
1180 | |
1181 | /* enable access for bmac registers */ | |
1182 | REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); | |
1183 | ||
1184 | /* Enable BMAC according to BMAC type*/ | |
1185 | if (CHIP_IS_E2(bp)) | |
1186 | rc = bnx2x_bmac2_enable(params, vars, is_lb); | |
1187 | else | |
1188 | rc = bnx2x_bmac1_enable(params, vars, is_lb); | |
ea4e040a YR |
1189 | REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); |
1190 | REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); | |
1191 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); | |
1192 | val = 0; | |
bcab15c5 VZ |
1193 | if ((params->feature_config_flags & |
1194 | FEATURE_CONFIG_PFC_ENABLED) || | |
1195 | (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) | |
ea4e040a YR |
1196 | val = 1; |
1197 | REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); | |
1198 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); | |
1199 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); | |
1200 | REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); | |
1201 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); | |
1202 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); | |
1203 | ||
1204 | vars->mac_type = MAC_TYPE_BMAC; | |
f2e0899f | 1205 | return rc; |
ea4e040a YR |
1206 | } |
1207 | ||
ea4e040a YR |
1208 | |
1209 | static void bnx2x_update_mng(struct link_params *params, u32 link_status) | |
1210 | { | |
1211 | struct bnx2x *bp = params->bp; | |
ab6ad5a4 | 1212 | |
ea4e040a | 1213 | REG_WR(bp, params->shmem_base + |
cd88ccee YR |
1214 | offsetof(struct shmem_region, |
1215 | port_mb[params->port].link_status), link_status); | |
ea4e040a YR |
1216 | } |
1217 | ||
1218 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port) | |
1219 | { | |
1220 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | |
cd88ccee | 1221 | NIG_REG_INGRESS_BMAC0_MEM; |
ea4e040a | 1222 | u32 wb_data[2]; |
3196a88a | 1223 | u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); |
ea4e040a YR |
1224 | |
1225 | /* Only if the bmac is out of reset */ | |
1226 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | |
1227 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && | |
1228 | nig_bmac_enable) { | |
1229 | ||
f2e0899f DK |
1230 | if (CHIP_IS_E2(bp)) { |
1231 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
1232 | REG_RD_DMAE(bp, bmac_addr + | |
cd88ccee YR |
1233 | BIGMAC2_REGISTER_BMAC_CONTROL, |
1234 | wb_data, 2); | |
f2e0899f DK |
1235 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; |
1236 | REG_WR_DMAE(bp, bmac_addr + | |
cd88ccee YR |
1237 | BIGMAC2_REGISTER_BMAC_CONTROL, |
1238 | wb_data, 2); | |
f2e0899f DK |
1239 | } else { |
1240 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | |
1241 | REG_RD_DMAE(bp, bmac_addr + | |
1242 | BIGMAC_REGISTER_BMAC_CONTROL, | |
1243 | wb_data, 2); | |
1244 | wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; | |
1245 | REG_WR_DMAE(bp, bmac_addr + | |
1246 | BIGMAC_REGISTER_BMAC_CONTROL, | |
1247 | wb_data, 2); | |
1248 | } | |
ea4e040a YR |
1249 | msleep(1); |
1250 | } | |
1251 | } | |
1252 | ||
1253 | static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl, | |
cd88ccee | 1254 | u32 line_speed) |
ea4e040a YR |
1255 | { |
1256 | struct bnx2x *bp = params->bp; | |
1257 | u8 port = params->port; | |
1258 | u32 init_crd, crd; | |
1259 | u32 count = 1000; | |
ea4e040a YR |
1260 | |
1261 | /* disable port */ | |
1262 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); | |
1263 | ||
1264 | /* wait for init credit */ | |
1265 | init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); | |
1266 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
1267 | DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); | |
1268 | ||
1269 | while ((init_crd != crd) && count) { | |
1270 | msleep(5); | |
1271 | ||
1272 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
1273 | count--; | |
1274 | } | |
1275 | crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); | |
1276 | if (init_crd != crd) { | |
1277 | DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", | |
1278 | init_crd, crd); | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | ||
c0700f90 | 1282 | if (flow_ctrl & BNX2X_FLOW_CTRL_RX || |
8c99e7b0 YR |
1283 | line_speed == SPEED_10 || |
1284 | line_speed == SPEED_100 || | |
1285 | line_speed == SPEED_1000 || | |
1286 | line_speed == SPEED_2500) { | |
1287 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); | |
ea4e040a YR |
1288 | /* update threshold */ |
1289 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); | |
1290 | /* update init credit */ | |
cd88ccee | 1291 | init_crd = 778; /* (800-18-4) */ |
ea4e040a YR |
1292 | |
1293 | } else { | |
1294 | u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + | |
1295 | ETH_OVREHEAD)/16; | |
8c99e7b0 | 1296 | REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); |
ea4e040a YR |
1297 | /* update threshold */ |
1298 | REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); | |
1299 | /* update init credit */ | |
1300 | switch (line_speed) { | |
ea4e040a YR |
1301 | case SPEED_10000: |
1302 | init_crd = thresh + 553 - 22; | |
1303 | break; | |
1304 | ||
1305 | case SPEED_12000: | |
1306 | init_crd = thresh + 664 - 22; | |
1307 | break; | |
1308 | ||
1309 | case SPEED_13000: | |
1310 | init_crd = thresh + 742 - 22; | |
1311 | break; | |
1312 | ||
1313 | case SPEED_16000: | |
1314 | init_crd = thresh + 778 - 22; | |
1315 | break; | |
1316 | default: | |
1317 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", | |
1318 | line_speed); | |
1319 | return -EINVAL; | |
ea4e040a YR |
1320 | } |
1321 | } | |
1322 | REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); | |
1323 | DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n", | |
1324 | line_speed, init_crd); | |
1325 | ||
1326 | /* probe the credit changes */ | |
1327 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); | |
1328 | msleep(5); | |
1329 | REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); | |
1330 | ||
1331 | /* enable port */ | |
1332 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); | |
1333 | return 0; | |
1334 | } | |
1335 | ||
2cf7acf9 YR |
1336 | /* |
1337 | * get_emac_base | |
1338 | * | |
1339 | * @param cb | |
1340 | * @param mdc_mdio_access | |
1341 | * @param port | |
1342 | * | |
1343 | * @return u32 | |
1344 | * | |
1345 | * This function selects the MDC/MDIO access (through emac0 or | |
1346 | * emac1) depend on the mdc_mdio_access, port, port swapped. Each | |
1347 | * phy has a default access mode, which could also be overridden | |
1348 | * by nvram configuration. This parameter, whether this is the | |
1349 | * default phy configuration, or the nvram overrun | |
1350 | * configuration, is passed here as mdc_mdio_access and selects | |
1351 | * the emac_base for the CL45 read/writes operations | |
1352 | */ | |
c18aa15d YR |
1353 | static u32 bnx2x_get_emac_base(struct bnx2x *bp, |
1354 | u32 mdc_mdio_access, u8 port) | |
ea4e040a | 1355 | { |
c18aa15d YR |
1356 | u32 emac_base = 0; |
1357 | switch (mdc_mdio_access) { | |
1358 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: | |
1359 | break; | |
1360 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: | |
1361 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) | |
1362 | emac_base = GRCBASE_EMAC1; | |
1363 | else | |
1364 | emac_base = GRCBASE_EMAC0; | |
1365 | break; | |
1366 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: | |
589abe3a EG |
1367 | if (REG_RD(bp, NIG_REG_PORT_SWAP)) |
1368 | emac_base = GRCBASE_EMAC0; | |
1369 | else | |
1370 | emac_base = GRCBASE_EMAC1; | |
ea4e040a | 1371 | break; |
c18aa15d YR |
1372 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: |
1373 | emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
1374 | break; | |
1375 | case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: | |
6378c025 | 1376 | emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
ea4e040a YR |
1377 | break; |
1378 | default: | |
ea4e040a YR |
1379 | break; |
1380 | } | |
1381 | return emac_base; | |
1382 | ||
1383 | } | |
1384 | ||
2cf7acf9 YR |
1385 | /******************************************************************/ |
1386 | /* CL45 access functions */ | |
1387 | /******************************************************************/ | |
65a001ba YR |
1388 | static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, |
1389 | u8 devad, u16 reg, u16 val) | |
ea4e040a YR |
1390 | { |
1391 | u32 tmp, saved_mode; | |
1392 | u8 i, rc = 0; | |
2cf7acf9 YR |
1393 | /* |
1394 | * Set clause 45 mode, slow down the MDIO clock to 2.5MHz | |
ea4e040a YR |
1395 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1396 | */ | |
589abe3a | 1397 | |
e10bc84d | 1398 | saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
ea4e040a YR |
1399 | tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL | |
1400 | EMAC_MDIO_MODE_CLOCK_CNT); | |
1401 | tmp |= (EMAC_MDIO_MODE_CLAUSE_45 | | |
1402 | (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); | |
e10bc84d YR |
1403 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp); |
1404 | REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
ea4e040a YR |
1405 | udelay(40); |
1406 | ||
1407 | /* address */ | |
1408 | ||
e10bc84d | 1409 | tmp = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
1410 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
1411 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 1412 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
1413 | |
1414 | for (i = 0; i < 50; i++) { | |
1415 | udelay(10); | |
1416 | ||
cd88ccee | 1417 | tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
ea4e040a YR |
1418 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
1419 | udelay(5); | |
1420 | break; | |
1421 | } | |
1422 | } | |
1423 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
1424 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
1425 | rc = -EFAULT; | |
1426 | } else { | |
1427 | /* data */ | |
e10bc84d | 1428 | tmp = ((phy->addr << 21) | (devad << 16) | val | |
ea4e040a YR |
1429 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | |
1430 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 1431 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
ea4e040a YR |
1432 | |
1433 | for (i = 0; i < 50; i++) { | |
1434 | udelay(10); | |
1435 | ||
e10bc84d | 1436 | tmp = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 1437 | EMAC_REG_EMAC_MDIO_COMM); |
ea4e040a YR |
1438 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
1439 | udelay(5); | |
1440 | break; | |
1441 | } | |
1442 | } | |
1443 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | |
1444 | DP(NETIF_MSG_LINK, "write phy register failed\n"); | |
1445 | rc = -EFAULT; | |
1446 | } | |
1447 | } | |
1448 | ||
1449 | /* Restore the saved mode */ | |
e10bc84d | 1450 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); |
ea4e040a YR |
1451 | |
1452 | return rc; | |
1453 | } | |
1454 | ||
65a001ba YR |
1455 | static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, |
1456 | u8 devad, u16 reg, u16 *ret_val) | |
ea4e040a YR |
1457 | { |
1458 | u32 val, saved_mode; | |
1459 | u16 i; | |
1460 | u8 rc = 0; | |
2cf7acf9 YR |
1461 | /* |
1462 | * Set clause 45 mode, slow down the MDIO clock to 2.5MHz | |
ea4e040a YR |
1463 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1464 | */ | |
589abe3a | 1465 | |
e10bc84d YR |
1466 | saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
1467 | val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL | | |
cd88ccee | 1468 | EMAC_MDIO_MODE_CLOCK_CNT)); |
ea4e040a | 1469 | val |= (EMAC_MDIO_MODE_CLAUSE_45 | |
ab6ad5a4 | 1470 | (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); |
e10bc84d YR |
1471 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); |
1472 | REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | |
ea4e040a YR |
1473 | udelay(40); |
1474 | ||
1475 | /* address */ | |
e10bc84d | 1476 | val = ((phy->addr << 21) | (devad << 16) | reg | |
ea4e040a YR |
1477 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
1478 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 1479 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
1480 | |
1481 | for (i = 0; i < 50; i++) { | |
1482 | udelay(10); | |
1483 | ||
e10bc84d | 1484 | val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
ea4e040a YR |
1485 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
1486 | udelay(5); | |
1487 | break; | |
1488 | } | |
1489 | } | |
1490 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
1491 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
1492 | ||
1493 | *ret_val = 0; | |
1494 | rc = -EFAULT; | |
1495 | ||
1496 | } else { | |
1497 | /* data */ | |
e10bc84d | 1498 | val = ((phy->addr << 21) | (devad << 16) | |
ea4e040a YR |
1499 | EMAC_MDIO_COMM_COMMAND_READ_45 | |
1500 | EMAC_MDIO_COMM_START_BUSY); | |
e10bc84d | 1501 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
ea4e040a YR |
1502 | |
1503 | for (i = 0; i < 50; i++) { | |
1504 | udelay(10); | |
1505 | ||
e10bc84d | 1506 | val = REG_RD(bp, phy->mdio_ctrl + |
cd88ccee | 1507 | EMAC_REG_EMAC_MDIO_COMM); |
ea4e040a YR |
1508 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
1509 | *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); | |
1510 | break; | |
1511 | } | |
1512 | } | |
1513 | if (val & EMAC_MDIO_COMM_START_BUSY) { | |
1514 | DP(NETIF_MSG_LINK, "read phy register failed\n"); | |
1515 | ||
1516 | *ret_val = 0; | |
1517 | rc = -EFAULT; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | /* Restore the saved mode */ | |
e10bc84d | 1522 | REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode); |
ea4e040a YR |
1523 | |
1524 | return rc; | |
1525 | } | |
1526 | ||
e10bc84d YR |
1527 | u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr, |
1528 | u8 devad, u16 reg, u16 *ret_val) | |
1529 | { | |
1530 | u8 phy_index; | |
2cf7acf9 | 1531 | /* |
e10bc84d YR |
1532 | * Probe for the phy according to the given phy_addr, and execute |
1533 | * the read request on it | |
1534 | */ | |
1535 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
1536 | if (params->phy[phy_index].addr == phy_addr) { | |
1537 | return bnx2x_cl45_read(params->bp, | |
1538 | ¶ms->phy[phy_index], devad, | |
1539 | reg, ret_val); | |
1540 | } | |
1541 | } | |
1542 | return -EINVAL; | |
1543 | } | |
1544 | ||
1545 | u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr, | |
1546 | u8 devad, u16 reg, u16 val) | |
1547 | { | |
1548 | u8 phy_index; | |
2cf7acf9 | 1549 | /* |
e10bc84d YR |
1550 | * Probe for the phy according to the given phy_addr, and execute |
1551 | * the write request on it | |
1552 | */ | |
1553 | for (phy_index = 0; phy_index < params->num_phys; phy_index++) { | |
1554 | if (params->phy[phy_index].addr == phy_addr) { | |
1555 | return bnx2x_cl45_write(params->bp, | |
1556 | ¶ms->phy[phy_index], devad, | |
1557 | reg, val); | |
1558 | } | |
1559 | } | |
1560 | return -EINVAL; | |
1561 | } | |
1562 | ||
f2e0899f DK |
1563 | static void bnx2x_set_aer_mmd_xgxs(struct link_params *params, |
1564 | struct bnx2x_phy *phy) | |
ea4e040a | 1565 | { |
ea4e040a | 1566 | u32 ser_lane; |
f2e0899f DK |
1567 | u16 offset, aer_val; |
1568 | struct bnx2x *bp = params->bp; | |
ea4e040a YR |
1569 | ser_lane = ((params->lane_config & |
1570 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
1571 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
1572 | ||
f2e0899f DK |
1573 | offset = phy->addr + ser_lane; |
1574 | if (CHIP_IS_E2(bp)) | |
82a0d475 | 1575 | aer_val = 0x3800 + offset - 1; |
f2e0899f DK |
1576 | else |
1577 | aer_val = 0x3800 + offset; | |
cd2be89b | 1578 | CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, |
cd88ccee | 1579 | MDIO_AER_BLOCK_AER_REG, aer_val); |
f2e0899f DK |
1580 | } |
1581 | static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp, | |
1582 | struct bnx2x_phy *phy) | |
1583 | { | |
cd2be89b | 1584 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1585 | MDIO_REG_BANK_AER_BLOCK, |
1586 | MDIO_AER_BLOCK_AER_REG, 0x3800); | |
ea4e040a YR |
1587 | } |
1588 | ||
de6eae1f YR |
1589 | /******************************************************************/ |
1590 | /* Internal phy section */ | |
1591 | /******************************************************************/ | |
ea4e040a | 1592 | |
de6eae1f YR |
1593 | static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) |
1594 | { | |
1595 | u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
ea4e040a | 1596 | |
de6eae1f YR |
1597 | /* Set Clause 22 */ |
1598 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); | |
1599 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); | |
1600 | udelay(500); | |
1601 | REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); | |
1602 | udelay(500); | |
1603 | /* Set Clause 45 */ | |
1604 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); | |
ea4e040a YR |
1605 | } |
1606 | ||
de6eae1f | 1607 | static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) |
ea4e040a | 1608 | { |
de6eae1f | 1609 | u32 val; |
ea4e040a | 1610 | |
de6eae1f | 1611 | DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n"); |
ea4e040a | 1612 | |
de6eae1f | 1613 | val = SERDES_RESET_BITS << (port*16); |
c1b73990 | 1614 | |
de6eae1f YR |
1615 | /* reset and unreset the SerDes/XGXS */ |
1616 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
1617 | udelay(500); | |
1618 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
ea4e040a | 1619 | |
de6eae1f | 1620 | bnx2x_set_serdes_access(bp, port); |
ea4e040a | 1621 | |
cd88ccee YR |
1622 | REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, |
1623 | DEFAULT_PHY_DEV_ADDR); | |
de6eae1f YR |
1624 | } |
1625 | ||
1626 | static void bnx2x_xgxs_deassert(struct link_params *params) | |
1627 | { | |
1628 | struct bnx2x *bp = params->bp; | |
1629 | u8 port; | |
1630 | u32 val; | |
1631 | DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n"); | |
1632 | port = params->port; | |
1633 | ||
1634 | val = XGXS_RESET_BITS << (port*16); | |
1635 | ||
1636 | /* reset and unreset the SerDes/XGXS */ | |
1637 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); | |
1638 | udelay(500); | |
1639 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); | |
1640 | ||
cd88ccee | 1641 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0); |
de6eae1f | 1642 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, |
cd88ccee | 1643 | params->phy[INT_PHY].def_md_devad); |
de6eae1f YR |
1644 | } |
1645 | ||
a22f0788 | 1646 | |
de6eae1f | 1647 | void bnx2x_link_status_update(struct link_params *params, |
cd88ccee | 1648 | struct link_vars *vars) |
de6eae1f YR |
1649 | { |
1650 | struct bnx2x *bp = params->bp; | |
1651 | u8 link_10g; | |
1652 | u8 port = params->port; | |
1653 | ||
de6eae1f | 1654 | vars->link_status = REG_RD(bp, params->shmem_base + |
cd88ccee YR |
1655 | offsetof(struct shmem_region, |
1656 | port_mb[port].link_status)); | |
de6eae1f YR |
1657 | |
1658 | vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); | |
1659 | ||
1660 | if (vars->link_up) { | |
1661 | DP(NETIF_MSG_LINK, "phy link up\n"); | |
1662 | ||
1663 | vars->phy_link_up = 1; | |
1664 | vars->duplex = DUPLEX_FULL; | |
1665 | switch (vars->link_status & | |
cd88ccee | 1666 | LINK_STATUS_SPEED_AND_DUPLEX_MASK) { |
de6eae1f YR |
1667 | case LINK_10THD: |
1668 | vars->duplex = DUPLEX_HALF; | |
1669 | /* fall thru */ | |
1670 | case LINK_10TFD: | |
1671 | vars->line_speed = SPEED_10; | |
1672 | break; | |
1673 | ||
1674 | case LINK_100TXHD: | |
1675 | vars->duplex = DUPLEX_HALF; | |
1676 | /* fall thru */ | |
1677 | case LINK_100T4: | |
1678 | case LINK_100TXFD: | |
1679 | vars->line_speed = SPEED_100; | |
1680 | break; | |
1681 | ||
1682 | case LINK_1000THD: | |
1683 | vars->duplex = DUPLEX_HALF; | |
1684 | /* fall thru */ | |
1685 | case LINK_1000TFD: | |
1686 | vars->line_speed = SPEED_1000; | |
1687 | break; | |
1688 | ||
1689 | case LINK_2500THD: | |
1690 | vars->duplex = DUPLEX_HALF; | |
1691 | /* fall thru */ | |
1692 | case LINK_2500TFD: | |
1693 | vars->line_speed = SPEED_2500; | |
1694 | break; | |
1695 | ||
1696 | case LINK_10GTFD: | |
1697 | vars->line_speed = SPEED_10000; | |
1698 | break; | |
1699 | ||
1700 | case LINK_12GTFD: | |
1701 | vars->line_speed = SPEED_12000; | |
1702 | break; | |
1703 | ||
1704 | case LINK_12_5GTFD: | |
1705 | vars->line_speed = SPEED_12500; | |
1706 | break; | |
1707 | ||
1708 | case LINK_13GTFD: | |
1709 | vars->line_speed = SPEED_13000; | |
1710 | break; | |
1711 | ||
1712 | case LINK_15GTFD: | |
1713 | vars->line_speed = SPEED_15000; | |
1714 | break; | |
1715 | ||
1716 | case LINK_16GTFD: | |
1717 | vars->line_speed = SPEED_16000; | |
1718 | break; | |
1719 | ||
1720 | default: | |
1721 | break; | |
1722 | } | |
de6eae1f YR |
1723 | vars->flow_ctrl = 0; |
1724 | if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) | |
1725 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; | |
1726 | ||
1727 | if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) | |
1728 | vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; | |
1729 | ||
1730 | if (!vars->flow_ctrl) | |
1731 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
1732 | ||
1733 | if (vars->line_speed && | |
1734 | ((vars->line_speed == SPEED_10) || | |
1735 | (vars->line_speed == SPEED_100))) { | |
1736 | vars->phy_flags |= PHY_SGMII_FLAG; | |
1737 | } else { | |
1738 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
1739 | } | |
1740 | ||
1741 | /* anything 10 and over uses the bmac */ | |
1742 | link_10g = ((vars->line_speed == SPEED_10000) || | |
1743 | (vars->line_speed == SPEED_12000) || | |
1744 | (vars->line_speed == SPEED_12500) || | |
1745 | (vars->line_speed == SPEED_13000) || | |
1746 | (vars->line_speed == SPEED_15000) || | |
1747 | (vars->line_speed == SPEED_16000)); | |
1748 | if (link_10g) | |
1749 | vars->mac_type = MAC_TYPE_BMAC; | |
1750 | else | |
1751 | vars->mac_type = MAC_TYPE_EMAC; | |
1752 | ||
1753 | } else { /* link down */ | |
1754 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
1755 | ||
1756 | vars->phy_link_up = 0; | |
1757 | ||
1758 | vars->line_speed = 0; | |
1759 | vars->duplex = DUPLEX_FULL; | |
1760 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
1761 | ||
1762 | /* indicate no mac active */ | |
1763 | vars->mac_type = MAC_TYPE_NONE; | |
1764 | } | |
1765 | ||
1766 | DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n", | |
1767 | vars->link_status, vars->phy_link_up); | |
1768 | DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", | |
1769 | vars->line_speed, vars->duplex, vars->flow_ctrl); | |
1770 | } | |
1771 | ||
1772 | ||
1773 | static void bnx2x_set_master_ln(struct link_params *params, | |
1774 | struct bnx2x_phy *phy) | |
1775 | { | |
1776 | struct bnx2x *bp = params->bp; | |
1777 | u16 new_master_ln, ser_lane; | |
cd88ccee | 1778 | ser_lane = ((params->lane_config & |
de6eae1f | 1779 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
cd88ccee | 1780 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); |
de6eae1f YR |
1781 | |
1782 | /* set the master_ln for AN */ | |
cd2be89b | 1783 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1784 | MDIO_REG_BANK_XGXS_BLOCK2, |
1785 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
1786 | &new_master_ln); | |
de6eae1f | 1787 | |
cd2be89b | 1788 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1789 | MDIO_REG_BANK_XGXS_BLOCK2 , |
1790 | MDIO_XGXS_BLOCK2_TEST_MODE_LANE, | |
1791 | (new_master_ln | ser_lane)); | |
de6eae1f YR |
1792 | } |
1793 | ||
1794 | static u8 bnx2x_reset_unicore(struct link_params *params, | |
1795 | struct bnx2x_phy *phy, | |
1796 | u8 set_serdes) | |
1797 | { | |
1798 | struct bnx2x *bp = params->bp; | |
1799 | u16 mii_control; | |
1800 | u16 i; | |
cd2be89b | 1801 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1802 | MDIO_REG_BANK_COMBO_IEEE0, |
1803 | MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); | |
de6eae1f YR |
1804 | |
1805 | /* reset the unicore */ | |
cd2be89b | 1806 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1807 | MDIO_REG_BANK_COMBO_IEEE0, |
1808 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1809 | (mii_control | | |
1810 | MDIO_COMBO_IEEO_MII_CONTROL_RESET)); | |
de6eae1f YR |
1811 | if (set_serdes) |
1812 | bnx2x_set_serdes_access(bp, params->port); | |
1813 | ||
1814 | /* wait for the reset to self clear */ | |
1815 | for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { | |
1816 | udelay(5); | |
1817 | ||
1818 | /* the reset erased the previous bank value */ | |
cd2be89b | 1819 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1820 | MDIO_REG_BANK_COMBO_IEEE0, |
1821 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
1822 | &mii_control); | |
de6eae1f YR |
1823 | |
1824 | if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { | |
1825 | udelay(5); | |
1826 | return 0; | |
1827 | } | |
1828 | } | |
ea4e040a YR |
1829 | |
1830 | DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n"); | |
1831 | return -EINVAL; | |
1832 | ||
1833 | } | |
1834 | ||
e10bc84d YR |
1835 | static void bnx2x_set_swap_lanes(struct link_params *params, |
1836 | struct bnx2x_phy *phy) | |
ea4e040a YR |
1837 | { |
1838 | struct bnx2x *bp = params->bp; | |
2cf7acf9 YR |
1839 | /* |
1840 | * Each two bits represents a lane number: | |
1841 | * No swap is 0123 => 0x1b no need to enable the swap | |
1842 | */ | |
ea4e040a YR |
1843 | u16 ser_lane, rx_lane_swap, tx_lane_swap; |
1844 | ||
1845 | ser_lane = ((params->lane_config & | |
cd88ccee YR |
1846 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> |
1847 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
ea4e040a | 1848 | rx_lane_swap = ((params->lane_config & |
cd88ccee YR |
1849 | PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> |
1850 | PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); | |
ea4e040a | 1851 | tx_lane_swap = ((params->lane_config & |
cd88ccee YR |
1852 | PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> |
1853 | PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); | |
ea4e040a YR |
1854 | |
1855 | if (rx_lane_swap != 0x1b) { | |
cd2be89b | 1856 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1857 | MDIO_REG_BANK_XGXS_BLOCK2, |
1858 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, | |
1859 | (rx_lane_swap | | |
1860 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | | |
1861 | MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); | |
ea4e040a | 1862 | } else { |
cd2be89b | 1863 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1864 | MDIO_REG_BANK_XGXS_BLOCK2, |
1865 | MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); | |
ea4e040a YR |
1866 | } |
1867 | ||
1868 | if (tx_lane_swap != 0x1b) { | |
cd2be89b | 1869 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1870 | MDIO_REG_BANK_XGXS_BLOCK2, |
1871 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, | |
1872 | (tx_lane_swap | | |
1873 | MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); | |
ea4e040a | 1874 | } else { |
cd2be89b | 1875 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1876 | MDIO_REG_BANK_XGXS_BLOCK2, |
1877 | MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); | |
ea4e040a YR |
1878 | } |
1879 | } | |
1880 | ||
e10bc84d YR |
1881 | static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy, |
1882 | struct link_params *params) | |
ea4e040a YR |
1883 | { |
1884 | struct bnx2x *bp = params->bp; | |
1885 | u16 control2; | |
cd2be89b | 1886 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1887 | MDIO_REG_BANK_SERDES_DIGITAL, |
1888 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
1889 | &control2); | |
7aa0711f | 1890 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
18afb0a6 YR |
1891 | control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; |
1892 | else | |
1893 | control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; | |
7aa0711f YR |
1894 | DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", |
1895 | phy->speed_cap_mask, control2); | |
cd2be89b | 1896 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1897 | MDIO_REG_BANK_SERDES_DIGITAL, |
1898 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, | |
1899 | control2); | |
ea4e040a | 1900 | |
e10bc84d | 1901 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
c18aa15d | 1902 | (phy->speed_cap_mask & |
18afb0a6 | 1903 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { |
ea4e040a YR |
1904 | DP(NETIF_MSG_LINK, "XGXS\n"); |
1905 | ||
cd2be89b | 1906 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1907 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1908 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | |
1909 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | |
ea4e040a | 1910 | |
cd2be89b | 1911 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1912 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1913 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
1914 | &control2); | |
ea4e040a YR |
1915 | |
1916 | ||
1917 | control2 |= | |
1918 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | |
1919 | ||
cd2be89b | 1920 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1921 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
1922 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | |
1923 | control2); | |
ea4e040a YR |
1924 | |
1925 | /* Disable parallel detection of HiG */ | |
cd2be89b | 1926 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1927 | MDIO_REG_BANK_XGXS_BLOCK2, |
1928 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | |
1929 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | |
1930 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | |
ea4e040a YR |
1931 | } |
1932 | } | |
1933 | ||
e10bc84d YR |
1934 | static void bnx2x_set_autoneg(struct bnx2x_phy *phy, |
1935 | struct link_params *params, | |
cd88ccee YR |
1936 | struct link_vars *vars, |
1937 | u8 enable_cl73) | |
ea4e040a YR |
1938 | { |
1939 | struct bnx2x *bp = params->bp; | |
1940 | u16 reg_val; | |
1941 | ||
1942 | /* CL37 Autoneg */ | |
cd2be89b | 1943 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1944 | MDIO_REG_BANK_COMBO_IEEE0, |
1945 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a YR |
1946 | |
1947 | /* CL37 Autoneg Enabled */ | |
8c99e7b0 | 1948 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
1949 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; |
1950 | else /* CL37 Autoneg Disabled */ | |
1951 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
1952 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); | |
1953 | ||
cd2be89b | 1954 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1955 | MDIO_REG_BANK_COMBO_IEEE0, |
1956 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a YR |
1957 | |
1958 | /* Enable/Disable Autodetection */ | |
1959 | ||
cd2be89b | 1960 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1961 | MDIO_REG_BANK_SERDES_DIGITAL, |
1962 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); | |
239d686d EG |
1963 | reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | |
1964 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); | |
1965 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; | |
8c99e7b0 | 1966 | if (vars->line_speed == SPEED_AUTO_NEG) |
ea4e040a YR |
1967 | reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; |
1968 | else | |
1969 | reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; | |
1970 | ||
cd2be89b | 1971 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1972 | MDIO_REG_BANK_SERDES_DIGITAL, |
1973 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); | |
ea4e040a YR |
1974 | |
1975 | /* Enable TetonII and BAM autoneg */ | |
cd2be89b | 1976 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
1977 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
1978 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
ea4e040a | 1979 | ®_val); |
8c99e7b0 | 1980 | if (vars->line_speed == SPEED_AUTO_NEG) { |
ea4e040a YR |
1981 | /* Enable BAM aneg Mode and TetonII aneg Mode */ |
1982 | reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
1983 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
1984 | } else { | |
1985 | /* TetonII and BAM Autoneg Disabled */ | |
1986 | reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | | |
1987 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); | |
1988 | } | |
cd2be89b | 1989 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1990 | MDIO_REG_BANK_BAM_NEXT_PAGE, |
1991 | MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, | |
1992 | reg_val); | |
ea4e040a | 1993 | |
239d686d EG |
1994 | if (enable_cl73) { |
1995 | /* Enable Cl73 FSM status bits */ | |
cd2be89b | 1996 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
1997 | MDIO_REG_BANK_CL73_USERB0, |
1998 | MDIO_CL73_USERB0_CL73_UCTRL, | |
1999 | 0xe); | |
239d686d EG |
2000 | |
2001 | /* Enable BAM Station Manager*/ | |
cd2be89b | 2002 | CL22_WR_OVER_CL45(bp, phy, |
239d686d EG |
2003 | MDIO_REG_BANK_CL73_USERB0, |
2004 | MDIO_CL73_USERB0_CL73_BAM_CTRL1, | |
2005 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | | |
2006 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | | |
2007 | MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); | |
2008 | ||
7846e471 | 2009 | /* Advertise CL73 link speeds */ |
cd2be89b | 2010 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2011 | MDIO_REG_BANK_CL73_IEEEB1, |
2012 | MDIO_CL73_IEEEB1_AN_ADV2, | |
2013 | ®_val); | |
7aa0711f | 2014 | if (phy->speed_cap_mask & |
7846e471 YR |
2015 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
2016 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; | |
7aa0711f | 2017 | if (phy->speed_cap_mask & |
7846e471 YR |
2018 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) |
2019 | reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; | |
239d686d | 2020 | |
cd2be89b | 2021 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2022 | MDIO_REG_BANK_CL73_IEEEB1, |
2023 | MDIO_CL73_IEEEB1_AN_ADV2, | |
2024 | reg_val); | |
239d686d | 2025 | |
239d686d EG |
2026 | /* CL73 Autoneg Enabled */ |
2027 | reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; | |
2028 | ||
2029 | } else /* CL73 Autoneg Disabled */ | |
2030 | reg_val = 0; | |
ea4e040a | 2031 | |
cd2be89b | 2032 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2033 | MDIO_REG_BANK_CL73_IEEEB0, |
2034 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); | |
ea4e040a YR |
2035 | } |
2036 | ||
2037 | /* program SerDes, forced speed */ | |
e10bc84d YR |
2038 | static void bnx2x_program_serdes(struct bnx2x_phy *phy, |
2039 | struct link_params *params, | |
cd88ccee | 2040 | struct link_vars *vars) |
ea4e040a YR |
2041 | { |
2042 | struct bnx2x *bp = params->bp; | |
2043 | u16 reg_val; | |
2044 | ||
57937203 | 2045 | /* program duplex, disable autoneg and sgmii*/ |
cd2be89b | 2046 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2047 | MDIO_REG_BANK_COMBO_IEEE0, |
2048 | MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); | |
ea4e040a | 2049 | reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | |
57937203 EG |
2050 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
2051 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); | |
7aa0711f | 2052 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a | 2053 | reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; |
cd2be89b | 2054 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2055 | MDIO_REG_BANK_COMBO_IEEE0, |
2056 | MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); | |
ea4e040a | 2057 | |
2cf7acf9 YR |
2058 | /* |
2059 | * program speed | |
2060 | * - needed only if the speed is greater than 1G (2.5G or 10G) | |
2061 | */ | |
cd2be89b | 2062 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2063 | MDIO_REG_BANK_SERDES_DIGITAL, |
2064 | MDIO_SERDES_DIGITAL_MISC1, ®_val); | |
8c99e7b0 YR |
2065 | /* clearing the speed value before setting the right speed */ |
2066 | DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); | |
2067 | ||
2068 | reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | | |
2069 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
2070 | ||
2071 | if (!((vars->line_speed == SPEED_1000) || | |
2072 | (vars->line_speed == SPEED_100) || | |
2073 | (vars->line_speed == SPEED_10))) { | |
2074 | ||
ea4e040a YR |
2075 | reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | |
2076 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); | |
8c99e7b0 | 2077 | if (vars->line_speed == SPEED_10000) |
ea4e040a YR |
2078 | reg_val |= |
2079 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; | |
8c99e7b0 | 2080 | if (vars->line_speed == SPEED_13000) |
ea4e040a YR |
2081 | reg_val |= |
2082 | MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G; | |
8c99e7b0 YR |
2083 | } |
2084 | ||
cd2be89b | 2085 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2086 | MDIO_REG_BANK_SERDES_DIGITAL, |
2087 | MDIO_SERDES_DIGITAL_MISC1, reg_val); | |
8c99e7b0 | 2088 | |
ea4e040a YR |
2089 | } |
2090 | ||
e10bc84d YR |
2091 | static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy, |
2092 | struct link_params *params) | |
ea4e040a YR |
2093 | { |
2094 | struct bnx2x *bp = params->bp; | |
2095 | u16 val = 0; | |
2096 | ||
2097 | /* configure the 48 bits for BAM AN */ | |
2098 | ||
2099 | /* set extended capabilities */ | |
7aa0711f | 2100 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) |
ea4e040a | 2101 | val |= MDIO_OVER_1G_UP1_2_5G; |
7aa0711f | 2102 | if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) |
ea4e040a | 2103 | val |= MDIO_OVER_1G_UP1_10G; |
cd2be89b | 2104 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2105 | MDIO_REG_BANK_OVER_1G, |
2106 | MDIO_OVER_1G_UP1, val); | |
ea4e040a | 2107 | |
cd2be89b | 2108 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2109 | MDIO_REG_BANK_OVER_1G, |
2110 | MDIO_OVER_1G_UP3, 0x400); | |
ea4e040a YR |
2111 | } |
2112 | ||
e10bc84d YR |
2113 | static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy, |
2114 | struct link_params *params, u16 *ieee_fc) | |
ea4e040a | 2115 | { |
d5cb9e99 | 2116 | struct bnx2x *bp = params->bp; |
8c99e7b0 | 2117 | *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; |
2cf7acf9 YR |
2118 | /* |
2119 | * Resolve pause mode and advertisement. | |
2120 | * Please refer to Table 28B-3 of the 802.3ab-1999 spec | |
2121 | */ | |
ea4e040a | 2122 | |
7aa0711f | 2123 | switch (phy->req_flow_ctrl) { |
c0700f90 | 2124 | case BNX2X_FLOW_CTRL_AUTO: |
cd88ccee YR |
2125 | if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) |
2126 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
2127 | else | |
8c99e7b0 | 2128 | *ieee_fc |= |
cd88ccee | 2129 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
ea4e040a | 2130 | break; |
c0700f90 | 2131 | case BNX2X_FLOW_CTRL_TX: |
cd88ccee | 2132 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
ea4e040a YR |
2133 | break; |
2134 | ||
c0700f90 DM |
2135 | case BNX2X_FLOW_CTRL_RX: |
2136 | case BNX2X_FLOW_CTRL_BOTH: | |
8c99e7b0 | 2137 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
ea4e040a YR |
2138 | break; |
2139 | ||
c0700f90 | 2140 | case BNX2X_FLOW_CTRL_NONE: |
ea4e040a | 2141 | default: |
8c99e7b0 | 2142 | *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; |
ea4e040a YR |
2143 | break; |
2144 | } | |
d5cb9e99 | 2145 | DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); |
8c99e7b0 | 2146 | } |
ea4e040a | 2147 | |
e10bc84d YR |
2148 | static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy, |
2149 | struct link_params *params, | |
cd88ccee | 2150 | u16 ieee_fc) |
8c99e7b0 YR |
2151 | { |
2152 | struct bnx2x *bp = params->bp; | |
7846e471 | 2153 | u16 val; |
8c99e7b0 | 2154 | /* for AN, we are always publishing full duplex */ |
ea4e040a | 2155 | |
cd2be89b | 2156 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2157 | MDIO_REG_BANK_COMBO_IEEE0, |
2158 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); | |
cd2be89b | 2159 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2160 | MDIO_REG_BANK_CL73_IEEEB1, |
2161 | MDIO_CL73_IEEEB1_AN_ADV1, &val); | |
7846e471 YR |
2162 | val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; |
2163 | val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); | |
cd2be89b | 2164 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2165 | MDIO_REG_BANK_CL73_IEEEB1, |
2166 | MDIO_CL73_IEEEB1_AN_ADV1, val); | |
ea4e040a YR |
2167 | } |
2168 | ||
e10bc84d YR |
2169 | static void bnx2x_restart_autoneg(struct bnx2x_phy *phy, |
2170 | struct link_params *params, | |
2171 | u8 enable_cl73) | |
ea4e040a YR |
2172 | { |
2173 | struct bnx2x *bp = params->bp; | |
3a36f2ef | 2174 | u16 mii_control; |
239d686d | 2175 | |
ea4e040a | 2176 | DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n"); |
3a36f2ef | 2177 | /* Enable and restart BAM/CL37 aneg */ |
ea4e040a | 2178 | |
239d686d | 2179 | if (enable_cl73) { |
cd2be89b | 2180 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2181 | MDIO_REG_BANK_CL73_IEEEB0, |
2182 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
2183 | &mii_control); | |
239d686d | 2184 | |
cd2be89b | 2185 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2186 | MDIO_REG_BANK_CL73_IEEEB0, |
2187 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
2188 | (mii_control | | |
2189 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | | |
2190 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); | |
239d686d EG |
2191 | } else { |
2192 | ||
cd2be89b | 2193 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2194 | MDIO_REG_BANK_COMBO_IEEE0, |
2195 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
2196 | &mii_control); | |
239d686d EG |
2197 | DP(NETIF_MSG_LINK, |
2198 | "bnx2x_restart_autoneg mii_control before = 0x%x\n", | |
2199 | mii_control); | |
cd2be89b | 2200 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2201 | MDIO_REG_BANK_COMBO_IEEE0, |
2202 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
2203 | (mii_control | | |
2204 | MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | | |
2205 | MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); | |
239d686d | 2206 | } |
ea4e040a YR |
2207 | } |
2208 | ||
e10bc84d YR |
2209 | static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy, |
2210 | struct link_params *params, | |
cd88ccee | 2211 | struct link_vars *vars) |
ea4e040a YR |
2212 | { |
2213 | struct bnx2x *bp = params->bp; | |
2214 | u16 control1; | |
2215 | ||
2216 | /* in SGMII mode, the unicore is always slave */ | |
2217 | ||
cd2be89b | 2218 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2219 | MDIO_REG_BANK_SERDES_DIGITAL, |
2220 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
2221 | &control1); | |
ea4e040a YR |
2222 | control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; |
2223 | /* set sgmii mode (and not fiber) */ | |
2224 | control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | | |
2225 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | | |
2226 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); | |
cd2be89b | 2227 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2228 | MDIO_REG_BANK_SERDES_DIGITAL, |
2229 | MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, | |
2230 | control1); | |
ea4e040a YR |
2231 | |
2232 | /* if forced speed */ | |
8c99e7b0 | 2233 | if (!(vars->line_speed == SPEED_AUTO_NEG)) { |
ea4e040a YR |
2234 | /* set speed, disable autoneg */ |
2235 | u16 mii_control; | |
2236 | ||
cd2be89b | 2237 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2238 | MDIO_REG_BANK_COMBO_IEEE0, |
2239 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
2240 | &mii_control); | |
ea4e040a YR |
2241 | mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | |
2242 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| | |
2243 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); | |
2244 | ||
8c99e7b0 | 2245 | switch (vars->line_speed) { |
ea4e040a YR |
2246 | case SPEED_100: |
2247 | mii_control |= | |
2248 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; | |
2249 | break; | |
2250 | case SPEED_1000: | |
2251 | mii_control |= | |
2252 | MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; | |
2253 | break; | |
2254 | case SPEED_10: | |
2255 | /* there is nothing to set for 10M */ | |
2256 | break; | |
2257 | default: | |
2258 | /* invalid speed for SGMII */ | |
8c99e7b0 YR |
2259 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
2260 | vars->line_speed); | |
ea4e040a YR |
2261 | break; |
2262 | } | |
2263 | ||
2264 | /* setting the full duplex */ | |
7aa0711f | 2265 | if (phy->req_duplex == DUPLEX_FULL) |
ea4e040a YR |
2266 | mii_control |= |
2267 | MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; | |
cd2be89b | 2268 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2269 | MDIO_REG_BANK_COMBO_IEEE0, |
2270 | MDIO_COMBO_IEEE0_MII_CONTROL, | |
2271 | mii_control); | |
ea4e040a YR |
2272 | |
2273 | } else { /* AN mode */ | |
2274 | /* enable and restart AN */ | |
e10bc84d | 2275 | bnx2x_restart_autoneg(phy, params, 0); |
ea4e040a YR |
2276 | } |
2277 | } | |
2278 | ||
2279 | ||
2280 | /* | |
2281 | * link management | |
2282 | */ | |
2283 | ||
2284 | static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result) | |
8c99e7b0 | 2285 | { /* LD LP */ |
cd88ccee YR |
2286 | switch (pause_result) { /* ASYM P ASYM P */ |
2287 | case 0xb: /* 1 0 1 1 */ | |
c0700f90 | 2288 | vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; |
ea4e040a YR |
2289 | break; |
2290 | ||
cd88ccee | 2291 | case 0xe: /* 1 1 1 0 */ |
c0700f90 | 2292 | vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; |
ea4e040a YR |
2293 | break; |
2294 | ||
cd88ccee YR |
2295 | case 0x5: /* 0 1 0 1 */ |
2296 | case 0x7: /* 0 1 1 1 */ | |
2297 | case 0xd: /* 1 1 0 1 */ | |
2298 | case 0xf: /* 1 1 1 1 */ | |
c0700f90 | 2299 | vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; |
ea4e040a YR |
2300 | break; |
2301 | ||
2302 | default: | |
2303 | break; | |
2304 | } | |
7aa0711f YR |
2305 | if (pause_result & (1<<0)) |
2306 | vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; | |
2307 | if (pause_result & (1<<1)) | |
2308 | vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; | |
ea4e040a YR |
2309 | } |
2310 | ||
e10bc84d YR |
2311 | static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, |
2312 | struct link_params *params) | |
15ddd2d0 YR |
2313 | { |
2314 | struct bnx2x *bp = params->bp; | |
2315 | u16 pd_10g, status2_1000x; | |
7aa0711f YR |
2316 | if (phy->req_line_speed != SPEED_AUTO_NEG) |
2317 | return 0; | |
cd2be89b | 2318 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2319 | MDIO_REG_BANK_SERDES_DIGITAL, |
2320 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
2321 | &status2_1000x); | |
cd2be89b | 2322 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2323 | MDIO_REG_BANK_SERDES_DIGITAL, |
2324 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | |
2325 | &status2_1000x); | |
15ddd2d0 YR |
2326 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { |
2327 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | |
2328 | params->port); | |
2329 | return 1; | |
2330 | } | |
2331 | ||
cd2be89b | 2332 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2333 | MDIO_REG_BANK_10G_PARALLEL_DETECT, |
2334 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | |
2335 | &pd_10g); | |
15ddd2d0 YR |
2336 | |
2337 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | |
2338 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | |
2339 | params->port); | |
2340 | return 1; | |
2341 | } | |
2342 | return 0; | |
2343 | } | |
ea4e040a | 2344 | |
e10bc84d YR |
2345 | static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy, |
2346 | struct link_params *params, | |
2347 | struct link_vars *vars, | |
2348 | u32 gp_status) | |
ea4e040a YR |
2349 | { |
2350 | struct bnx2x *bp = params->bp; | |
3196a88a EG |
2351 | u16 ld_pause; /* local driver */ |
2352 | u16 lp_pause; /* link partner */ | |
ea4e040a YR |
2353 | u16 pause_result; |
2354 | ||
c0700f90 | 2355 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a YR |
2356 | |
2357 | /* resolve from gp_status in case of AN complete and not sgmii */ | |
7aa0711f YR |
2358 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) |
2359 | vars->flow_ctrl = phy->req_flow_ctrl; | |
2360 | else if (phy->req_line_speed != SPEED_AUTO_NEG) | |
2361 | vars->flow_ctrl = params->req_fc_auto_adv; | |
2362 | else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | |
2363 | (!(vars->phy_flags & PHY_SGMII_FLAG))) { | |
e10bc84d | 2364 | if (bnx2x_direct_parallel_detect_used(phy, params)) { |
15ddd2d0 YR |
2365 | vars->flow_ctrl = params->req_fc_auto_adv; |
2366 | return; | |
2367 | } | |
7846e471 YR |
2368 | if ((gp_status & |
2369 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
2370 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | |
2371 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | |
2372 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { | |
2373 | ||
cd2be89b | 2374 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2375 | MDIO_REG_BANK_CL73_IEEEB1, |
2376 | MDIO_CL73_IEEEB1_AN_ADV1, | |
2377 | &ld_pause); | |
cd2be89b | 2378 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2379 | MDIO_REG_BANK_CL73_IEEEB1, |
2380 | MDIO_CL73_IEEEB1_AN_LP_ADV1, | |
2381 | &lp_pause); | |
7846e471 YR |
2382 | pause_result = (ld_pause & |
2383 | MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) | |
2384 | >> 8; | |
2385 | pause_result |= (lp_pause & | |
2386 | MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) | |
2387 | >> 10; | |
2388 | DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", | |
2389 | pause_result); | |
2390 | } else { | |
cd2be89b | 2391 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2392 | MDIO_REG_BANK_COMBO_IEEE0, |
2393 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV, | |
2394 | &ld_pause); | |
cd2be89b | 2395 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2396 | MDIO_REG_BANK_COMBO_IEEE0, |
2397 | MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, | |
2398 | &lp_pause); | |
7846e471 | 2399 | pause_result = (ld_pause & |
ea4e040a | 2400 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; |
7846e471 | 2401 | pause_result |= (lp_pause & |
cd88ccee | 2402 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; |
7846e471 YR |
2403 | DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", |
2404 | pause_result); | |
2405 | } | |
ea4e040a | 2406 | bnx2x_pause_resolve(vars, pause_result); |
ea4e040a YR |
2407 | } |
2408 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); | |
2409 | } | |
2410 | ||
e10bc84d YR |
2411 | static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy, |
2412 | struct link_params *params) | |
239d686d EG |
2413 | { |
2414 | struct bnx2x *bp = params->bp; | |
2415 | u16 rx_status, ustat_val, cl37_fsm_recieved; | |
2416 | DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n"); | |
2417 | /* Step 1: Make sure signal is detected */ | |
cd2be89b | 2418 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2419 | MDIO_REG_BANK_RX0, |
2420 | MDIO_RX0_RX_STATUS, | |
2421 | &rx_status); | |
239d686d EG |
2422 | if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != |
2423 | (MDIO_RX0_RX_STATUS_SIGDET)) { | |
2424 | DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73." | |
2425 | "rx_status(0x80b0) = 0x%x\n", rx_status); | |
cd2be89b | 2426 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2427 | MDIO_REG_BANK_CL73_IEEEB0, |
2428 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
2429 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); | |
239d686d EG |
2430 | return; |
2431 | } | |
2432 | /* Step 2: Check CL73 state machine */ | |
cd2be89b | 2433 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2434 | MDIO_REG_BANK_CL73_USERB0, |
2435 | MDIO_CL73_USERB0_CL73_USTAT1, | |
2436 | &ustat_val); | |
239d686d EG |
2437 | if ((ustat_val & |
2438 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
2439 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != | |
2440 | (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | | |
2441 | MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { | |
2442 | DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " | |
2443 | "ustat_val(0x8371) = 0x%x\n", ustat_val); | |
2444 | return; | |
2445 | } | |
2cf7acf9 YR |
2446 | /* |
2447 | * Step 3: Check CL37 Message Pages received to indicate LP | |
2448 | * supports only CL37 | |
2449 | */ | |
cd2be89b | 2450 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2451 | MDIO_REG_BANK_REMOTE_PHY, |
2452 | MDIO_REMOTE_PHY_MISC_RX_STATUS, | |
2453 | &cl37_fsm_recieved); | |
239d686d EG |
2454 | if ((cl37_fsm_recieved & |
2455 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
2456 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != | |
2457 | (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | | |
2458 | MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { | |
2459 | DP(NETIF_MSG_LINK, "No CL37 FSM were received. " | |
2460 | "misc_rx_status(0x8330) = 0x%x\n", | |
2461 | cl37_fsm_recieved); | |
2462 | return; | |
2463 | } | |
2cf7acf9 YR |
2464 | /* |
2465 | * The combined cl37/cl73 fsm state information indicating that | |
2466 | * we are connected to a device which does not support cl73, but | |
2467 | * does support cl37 BAM. In this case we disable cl73 and | |
2468 | * restart cl37 auto-neg | |
2469 | */ | |
2470 | ||
239d686d | 2471 | /* Disable CL73 */ |
cd2be89b | 2472 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2473 | MDIO_REG_BANK_CL73_IEEEB0, |
2474 | MDIO_CL73_IEEEB0_CL73_AN_CONTROL, | |
2475 | 0); | |
239d686d | 2476 | /* Restart CL37 autoneg */ |
e10bc84d | 2477 | bnx2x_restart_autoneg(phy, params, 0); |
239d686d EG |
2478 | DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n"); |
2479 | } | |
7aa0711f YR |
2480 | |
2481 | static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy, | |
2482 | struct link_params *params, | |
2483 | struct link_vars *vars, | |
2484 | u32 gp_status) | |
2485 | { | |
2486 | if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) | |
2487 | vars->link_status |= | |
2488 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
2489 | ||
2490 | if (bnx2x_direct_parallel_detect_used(phy, params)) | |
2491 | vars->link_status |= | |
2492 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
2493 | } | |
2494 | ||
b7737c9b YR |
2495 | static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy, |
2496 | struct link_params *params, | |
2497 | struct link_vars *vars) | |
ea4e040a YR |
2498 | { |
2499 | struct bnx2x *bp = params->bp; | |
cd88ccee | 2500 | u16 new_line_speed, gp_status; |
ea4e040a | 2501 | u8 rc = 0; |
c18aa15d | 2502 | |
b7737c9b | 2503 | /* Read gp_status */ |
cd2be89b | 2504 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2505 | MDIO_REG_BANK_GP_STATUS, |
2506 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
2507 | &gp_status); | |
7f02c4ad | 2508 | |
7aa0711f YR |
2509 | if (phy->req_line_speed == SPEED_AUTO_NEG) |
2510 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; | |
ea4e040a YR |
2511 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
2512 | DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n", | |
2513 | gp_status); | |
2514 | ||
2515 | vars->phy_link_up = 1; | |
2516 | vars->link_status |= LINK_STATUS_LINK_UP; | |
2517 | ||
2518 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | |
2519 | vars->duplex = DUPLEX_FULL; | |
2520 | else | |
2521 | vars->duplex = DUPLEX_HALF; | |
2522 | ||
7aa0711f YR |
2523 | if (SINGLE_MEDIA_DIRECT(params)) { |
2524 | bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status); | |
2525 | if (phy->req_line_speed == SPEED_AUTO_NEG) | |
2526 | bnx2x_xgxs_an_resolve(phy, params, vars, | |
2527 | gp_status); | |
2528 | } | |
ea4e040a YR |
2529 | |
2530 | switch (gp_status & GP_STATUS_SPEED_MASK) { | |
2531 | case GP_STATUS_10M: | |
6c55c3cd | 2532 | new_line_speed = SPEED_10; |
ea4e040a YR |
2533 | if (vars->duplex == DUPLEX_FULL) |
2534 | vars->link_status |= LINK_10TFD; | |
2535 | else | |
2536 | vars->link_status |= LINK_10THD; | |
2537 | break; | |
2538 | ||
2539 | case GP_STATUS_100M: | |
6c55c3cd | 2540 | new_line_speed = SPEED_100; |
ea4e040a YR |
2541 | if (vars->duplex == DUPLEX_FULL) |
2542 | vars->link_status |= LINK_100TXFD; | |
2543 | else | |
2544 | vars->link_status |= LINK_100TXHD; | |
2545 | break; | |
2546 | ||
2547 | case GP_STATUS_1G: | |
2548 | case GP_STATUS_1G_KX: | |
6c55c3cd | 2549 | new_line_speed = SPEED_1000; |
ea4e040a YR |
2550 | if (vars->duplex == DUPLEX_FULL) |
2551 | vars->link_status |= LINK_1000TFD; | |
2552 | else | |
2553 | vars->link_status |= LINK_1000THD; | |
2554 | break; | |
2555 | ||
2556 | case GP_STATUS_2_5G: | |
6c55c3cd | 2557 | new_line_speed = SPEED_2500; |
ea4e040a YR |
2558 | if (vars->duplex == DUPLEX_FULL) |
2559 | vars->link_status |= LINK_2500TFD; | |
2560 | else | |
2561 | vars->link_status |= LINK_2500THD; | |
2562 | break; | |
2563 | ||
2564 | case GP_STATUS_5G: | |
2565 | case GP_STATUS_6G: | |
2566 | DP(NETIF_MSG_LINK, | |
2567 | "link speed unsupported gp_status 0x%x\n", | |
2568 | gp_status); | |
2569 | return -EINVAL; | |
ab6ad5a4 | 2570 | |
ea4e040a YR |
2571 | case GP_STATUS_10G_KX4: |
2572 | case GP_STATUS_10G_HIG: | |
2573 | case GP_STATUS_10G_CX4: | |
6c55c3cd | 2574 | new_line_speed = SPEED_10000; |
ea4e040a YR |
2575 | vars->link_status |= LINK_10GTFD; |
2576 | break; | |
2577 | ||
2578 | case GP_STATUS_12G_HIG: | |
6c55c3cd | 2579 | new_line_speed = SPEED_12000; |
ea4e040a YR |
2580 | vars->link_status |= LINK_12GTFD; |
2581 | break; | |
2582 | ||
2583 | case GP_STATUS_12_5G: | |
6c55c3cd | 2584 | new_line_speed = SPEED_12500; |
ea4e040a YR |
2585 | vars->link_status |= LINK_12_5GTFD; |
2586 | break; | |
2587 | ||
2588 | case GP_STATUS_13G: | |
6c55c3cd | 2589 | new_line_speed = SPEED_13000; |
ea4e040a YR |
2590 | vars->link_status |= LINK_13GTFD; |
2591 | break; | |
2592 | ||
2593 | case GP_STATUS_15G: | |
6c55c3cd | 2594 | new_line_speed = SPEED_15000; |
ea4e040a YR |
2595 | vars->link_status |= LINK_15GTFD; |
2596 | break; | |
2597 | ||
2598 | case GP_STATUS_16G: | |
6c55c3cd | 2599 | new_line_speed = SPEED_16000; |
ea4e040a YR |
2600 | vars->link_status |= LINK_16GTFD; |
2601 | break; | |
2602 | ||
2603 | default: | |
2604 | DP(NETIF_MSG_LINK, | |
2605 | "link speed unsupported gp_status 0x%x\n", | |
2606 | gp_status); | |
ab6ad5a4 | 2607 | return -EINVAL; |
ea4e040a YR |
2608 | } |
2609 | ||
6c55c3cd | 2610 | vars->line_speed = new_line_speed; |
ea4e040a | 2611 | |
ea4e040a YR |
2612 | } else { /* link_down */ |
2613 | DP(NETIF_MSG_LINK, "phy link down\n"); | |
2614 | ||
2615 | vars->phy_link_up = 0; | |
57963ed9 | 2616 | |
ea4e040a | 2617 | vars->duplex = DUPLEX_FULL; |
c0700f90 | 2618 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
ea4e040a | 2619 | vars->mac_type = MAC_TYPE_NONE; |
239d686d | 2620 | |
c18aa15d YR |
2621 | if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
2622 | SINGLE_MEDIA_DIRECT(params)) { | |
239d686d | 2623 | /* Check signal is detected */ |
c18aa15d | 2624 | bnx2x_check_fallback_to_cl37(phy, params); |
239d686d | 2625 | } |
ea4e040a YR |
2626 | } |
2627 | ||
2381a55c | 2628 | DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n", |
ea4e040a | 2629 | gp_status, vars->phy_link_up, vars->line_speed); |
a22f0788 YR |
2630 | DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", |
2631 | vars->duplex, vars->flow_ctrl, vars->link_status); | |
ea4e040a YR |
2632 | return rc; |
2633 | } | |
2634 | ||
ed8680a7 | 2635 | static void bnx2x_set_gmii_tx_driver(struct link_params *params) |
ea4e040a YR |
2636 | { |
2637 | struct bnx2x *bp = params->bp; | |
e10bc84d | 2638 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; |
ea4e040a YR |
2639 | u16 lp_up2; |
2640 | u16 tx_driver; | |
c2c8b03e | 2641 | u16 bank; |
ea4e040a YR |
2642 | |
2643 | /* read precomp */ | |
cd2be89b | 2644 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2645 | MDIO_REG_BANK_OVER_1G, |
2646 | MDIO_OVER_1G_LP_UP2, &lp_up2); | |
ea4e040a | 2647 | |
ea4e040a YR |
2648 | /* bits [10:7] at lp_up2, positioned at [15:12] */ |
2649 | lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> | |
2650 | MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << | |
2651 | MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); | |
2652 | ||
c2c8b03e EG |
2653 | if (lp_up2 == 0) |
2654 | return; | |
2655 | ||
2656 | for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; | |
2657 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { | |
cd2be89b | 2658 | CL22_RD_OVER_CL45(bp, phy, |
cd88ccee YR |
2659 | bank, |
2660 | MDIO_TX0_TX_DRIVER, &tx_driver); | |
c2c8b03e EG |
2661 | |
2662 | /* replace tx_driver bits [15:12] */ | |
2663 | if (lp_up2 != | |
2664 | (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { | |
2665 | tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; | |
2666 | tx_driver |= lp_up2; | |
cd2be89b | 2667 | CL22_WR_OVER_CL45(bp, phy, |
cd88ccee YR |
2668 | bank, |
2669 | MDIO_TX0_TX_DRIVER, tx_driver); | |
c2c8b03e | 2670 | } |
ea4e040a YR |
2671 | } |
2672 | } | |
2673 | ||
2674 | static u8 bnx2x_emac_program(struct link_params *params, | |
b7737c9b | 2675 | struct link_vars *vars) |
ea4e040a YR |
2676 | { |
2677 | struct bnx2x *bp = params->bp; | |
2678 | u8 port = params->port; | |
2679 | u16 mode = 0; | |
2680 | ||
2681 | DP(NETIF_MSG_LINK, "setting link speed & duplex\n"); | |
2682 | bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + | |
cd88ccee YR |
2683 | EMAC_REG_EMAC_MODE, |
2684 | (EMAC_MODE_25G_MODE | | |
2685 | EMAC_MODE_PORT_MII_10M | | |
2686 | EMAC_MODE_HALF_DUPLEX)); | |
b7737c9b | 2687 | switch (vars->line_speed) { |
ea4e040a YR |
2688 | case SPEED_10: |
2689 | mode |= EMAC_MODE_PORT_MII_10M; | |
2690 | break; | |
2691 | ||
2692 | case SPEED_100: | |
2693 | mode |= EMAC_MODE_PORT_MII; | |
2694 | break; | |
2695 | ||
2696 | case SPEED_1000: | |
2697 | mode |= EMAC_MODE_PORT_GMII; | |
2698 | break; | |
2699 | ||
2700 | case SPEED_2500: | |
2701 | mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); | |
2702 | break; | |
2703 | ||
2704 | default: | |
2705 | /* 10G not valid for EMAC */ | |
b7737c9b YR |
2706 | DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", |
2707 | vars->line_speed); | |
ea4e040a YR |
2708 | return -EINVAL; |
2709 | } | |
2710 | ||
b7737c9b | 2711 | if (vars->duplex == DUPLEX_HALF) |
ea4e040a YR |
2712 | mode |= EMAC_MODE_HALF_DUPLEX; |
2713 | bnx2x_bits_en(bp, | |
cd88ccee YR |
2714 | GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, |
2715 | mode); | |
ea4e040a | 2716 | |
7f02c4ad | 2717 | bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); |
ea4e040a YR |
2718 | return 0; |
2719 | } | |
2720 | ||
de6eae1f YR |
2721 | static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, |
2722 | struct link_params *params) | |
b7737c9b | 2723 | { |
de6eae1f YR |
2724 | |
2725 | u16 bank, i = 0; | |
2726 | struct bnx2x *bp = params->bp; | |
2727 | ||
2728 | for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; | |
2729 | bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { | |
cd2be89b | 2730 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
2731 | bank, |
2732 | MDIO_RX0_RX_EQ_BOOST, | |
2733 | phy->rx_preemphasis[i]); | |
2734 | } | |
2735 | ||
2736 | for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; | |
2737 | bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { | |
cd2be89b | 2738 | CL22_WR_OVER_CL45(bp, phy, |
de6eae1f YR |
2739 | bank, |
2740 | MDIO_TX0_TX_DRIVER, | |
2741 | phy->tx_preemphasis[i]); | |
2742 | } | |
2743 | } | |
2744 | ||
2745 | static void bnx2x_init_internal_phy(struct bnx2x_phy *phy, | |
2746 | struct link_params *params, | |
2747 | struct link_vars *vars) | |
2748 | { | |
2749 | struct bnx2x *bp = params->bp; | |
2750 | u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) || | |
2751 | (params->loopback_mode == LOOPBACK_XGXS)); | |
2752 | if (!(vars->phy_flags & PHY_SGMII_FLAG)) { | |
2753 | if (SINGLE_MEDIA_DIRECT(params) && | |
2754 | (params->feature_config_flags & | |
2755 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) | |
2756 | bnx2x_set_preemphasis(phy, params); | |
2757 | ||
2758 | /* forced speed requested? */ | |
2759 | if (vars->line_speed != SPEED_AUTO_NEG || | |
2760 | (SINGLE_MEDIA_DIRECT(params) && | |
cd88ccee | 2761 | params->loopback_mode == LOOPBACK_EXT)) { |
de6eae1f YR |
2762 | DP(NETIF_MSG_LINK, "not SGMII, no AN\n"); |
2763 | ||
2764 | /* disable autoneg */ | |
2765 | bnx2x_set_autoneg(phy, params, vars, 0); | |
2766 | ||
2767 | /* program speed and duplex */ | |
2768 | bnx2x_program_serdes(phy, params, vars); | |
2769 | ||
2770 | } else { /* AN_mode */ | |
2771 | DP(NETIF_MSG_LINK, "not SGMII, AN\n"); | |
2772 | ||
2773 | /* AN enabled */ | |
2774 | bnx2x_set_brcm_cl37_advertisment(phy, params); | |
2775 | ||
2776 | /* program duplex & pause advertisement (for aneg) */ | |
2777 | bnx2x_set_ieee_aneg_advertisment(phy, params, | |
cd88ccee | 2778 | vars->ieee_fc); |
de6eae1f YR |
2779 | |
2780 | /* enable autoneg */ | |
2781 | bnx2x_set_autoneg(phy, params, vars, enable_cl73); | |
2782 | ||
2783 | /* enable and restart AN */ | |
2784 | bnx2x_restart_autoneg(phy, params, enable_cl73); | |
2785 | } | |
2786 | ||
2787 | } else { /* SGMII mode */ | |
2788 | DP(NETIF_MSG_LINK, "SGMII\n"); | |
2789 | ||
2790 | bnx2x_initialize_sgmii_process(phy, params, vars); | |
2791 | } | |
2792 | } | |
2793 | ||
2794 | static u8 bnx2x_init_serdes(struct bnx2x_phy *phy, | |
2795 | struct link_params *params, | |
2796 | struct link_vars *vars) | |
2797 | { | |
2798 | u8 rc; | |
2799 | vars->phy_flags |= PHY_SGMII_FLAG; | |
b7737c9b | 2800 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
f2e0899f | 2801 | bnx2x_set_aer_mmd_serdes(params->bp, phy); |
b7737c9b YR |
2802 | rc = bnx2x_reset_unicore(params, phy, 1); |
2803 | /* reset the SerDes and wait for reset bit return low */ | |
2804 | if (rc != 0) | |
2805 | return rc; | |
f2e0899f | 2806 | bnx2x_set_aer_mmd_serdes(params->bp, phy); |
b7737c9b YR |
2807 | |
2808 | return rc; | |
2809 | } | |
2810 | ||
2811 | static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy, | |
2812 | struct link_params *params, | |
2813 | struct link_vars *vars) | |
2814 | { | |
2815 | u8 rc; | |
2816 | vars->phy_flags = PHY_XGXS_FLAG; | |
2817 | if ((phy->req_line_speed && | |
2818 | ((phy->req_line_speed == SPEED_100) || | |
2819 | (phy->req_line_speed == SPEED_10))) || | |
2820 | (!phy->req_line_speed && | |
2821 | (phy->speed_cap_mask >= | |
2822 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && | |
2823 | (phy->speed_cap_mask < | |
2824 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) | |
2825 | )) | |
2826 | vars->phy_flags |= PHY_SGMII_FLAG; | |
2827 | else | |
2828 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
2829 | ||
2830 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
f2e0899f | 2831 | bnx2x_set_aer_mmd_xgxs(params, phy); |
b7737c9b YR |
2832 | bnx2x_set_master_ln(params, phy); |
2833 | ||
2834 | rc = bnx2x_reset_unicore(params, phy, 0); | |
2835 | /* reset the SerDes and wait for reset bit return low */ | |
2836 | if (rc != 0) | |
2837 | return rc; | |
2838 | ||
f2e0899f | 2839 | bnx2x_set_aer_mmd_xgxs(params, phy); |
e10bc84d | 2840 | |
b7737c9b YR |
2841 | /* setting the masterLn_def again after the reset */ |
2842 | bnx2x_set_master_ln(params, phy); | |
2843 | bnx2x_set_swap_lanes(params, phy); | |
2844 | ||
2845 | return rc; | |
2846 | } | |
c18aa15d | 2847 | |
de6eae1f YR |
2848 | static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, |
2849 | struct bnx2x_phy *phy) | |
ea4e040a | 2850 | { |
de6eae1f YR |
2851 | u16 cnt, ctrl; |
2852 | /* Wait for soft reset to get cleared upto 1 sec */ | |
2853 | for (cnt = 0; cnt < 1000; cnt++) { | |
2854 | bnx2x_cl45_read(bp, phy, | |
2855 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl); | |
2856 | if (!(ctrl & (1<<15))) | |
2857 | break; | |
2858 | msleep(1); | |
2859 | } | |
2860 | DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); | |
2861 | return cnt; | |
ea4e040a YR |
2862 | } |
2863 | ||
de6eae1f | 2864 | static void bnx2x_link_int_enable(struct link_params *params) |
a35da8db | 2865 | { |
de6eae1f YR |
2866 | u8 port = params->port; |
2867 | u32 mask; | |
2868 | struct bnx2x *bp = params->bp; | |
c18aa15d | 2869 | |
2cf7acf9 | 2870 | /* Setting the status to report on link up for either XGXS or SerDes */ |
de6eae1f YR |
2871 | if (params->switch_cfg == SWITCH_CFG_10G) { |
2872 | mask = (NIG_MASK_XGXS0_LINK10G | | |
2873 | NIG_MASK_XGXS0_LINK_STATUS); | |
2874 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); | |
2875 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
2876 | params->phy[INT_PHY].type != | |
2877 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { | |
2878 | mask |= NIG_MASK_MI_INT; | |
2879 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
2880 | } | |
2881 | ||
2882 | } else { /* SerDes */ | |
2883 | mask = NIG_MASK_SERDES0_LINK_STATUS; | |
2884 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); | |
2885 | if (!(SINGLE_MEDIA_DIRECT(params)) && | |
2886 | params->phy[INT_PHY].type != | |
2887 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { | |
2888 | mask |= NIG_MASK_MI_INT; | |
2889 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | |
2890 | } | |
2891 | } | |
2892 | bnx2x_bits_en(bp, | |
2893 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
2894 | mask); | |
2895 | ||
2896 | DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, | |
2897 | (params->switch_cfg == SWITCH_CFG_10G), | |
2898 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
2899 | DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", | |
2900 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
2901 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | |
2902 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); | |
2903 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", | |
2904 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
2905 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
a35da8db EG |
2906 | } |
2907 | ||
a22f0788 YR |
2908 | static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, |
2909 | u8 exp_mi_int) | |
a35da8db | 2910 | { |
a22f0788 YR |
2911 | u32 latch_status = 0; |
2912 | ||
2cf7acf9 | 2913 | /* |
a22f0788 YR |
2914 | * Disable the MI INT ( external phy int ) by writing 1 to the |
2915 | * status register. Link down indication is high-active-signal, | |
2916 | * so in this case we need to write the status to clear the XOR | |
de6eae1f YR |
2917 | */ |
2918 | /* Read Latched signals */ | |
2919 | latch_status = REG_RD(bp, | |
a22f0788 YR |
2920 | NIG_REG_LATCH_STATUS_0 + port*8); |
2921 | DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); | |
de6eae1f | 2922 | /* Handle only those with latched-signal=up.*/ |
a22f0788 YR |
2923 | if (exp_mi_int) |
2924 | bnx2x_bits_en(bp, | |
2925 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
2926 | + port*4, | |
2927 | NIG_STATUS_EMAC0_MI_INT); | |
2928 | else | |
2929 | bnx2x_bits_dis(bp, | |
2930 | NIG_REG_STATUS_INTERRUPT_PORT0 | |
2931 | + port*4, | |
2932 | NIG_STATUS_EMAC0_MI_INT); | |
2933 | ||
de6eae1f | 2934 | if (latch_status & 1) { |
a22f0788 | 2935 | |
de6eae1f YR |
2936 | /* For all latched-signal=up : Re-Arm Latch signals */ |
2937 | REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, | |
cd88ccee | 2938 | (latch_status & 0xfffe) | (latch_status & 1)); |
de6eae1f | 2939 | } |
a22f0788 | 2940 | /* For all latched-signal=up,Write original_signal to status */ |
a35da8db EG |
2941 | } |
2942 | ||
de6eae1f | 2943 | static void bnx2x_link_int_ack(struct link_params *params, |
cd88ccee | 2944 | struct link_vars *vars, u8 is_10g) |
b1607af5 | 2945 | { |
e10bc84d | 2946 | struct bnx2x *bp = params->bp; |
de6eae1f | 2947 | u8 port = params->port; |
e10bc84d | 2948 | |
2cf7acf9 YR |
2949 | /* |
2950 | * First reset all status we assume only one line will be | |
2951 | * change at a time | |
2952 | */ | |
de6eae1f | 2953 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
cd88ccee YR |
2954 | (NIG_STATUS_XGXS0_LINK10G | |
2955 | NIG_STATUS_XGXS0_LINK_STATUS | | |
2956 | NIG_STATUS_SERDES0_LINK_STATUS)); | |
de6eae1f YR |
2957 | if (vars->phy_link_up) { |
2958 | if (is_10g) { | |
2cf7acf9 YR |
2959 | /* |
2960 | * Disable the 10G link interrupt by writing 1 to the | |
2961 | * status register | |
de6eae1f YR |
2962 | */ |
2963 | DP(NETIF_MSG_LINK, "10G XGXS phy link up\n"); | |
2964 | bnx2x_bits_en(bp, | |
2965 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2966 | NIG_STATUS_XGXS0_LINK10G); | |
b1607af5 | 2967 | |
de6eae1f | 2968 | } else if (params->switch_cfg == SWITCH_CFG_10G) { |
2cf7acf9 YR |
2969 | /* |
2970 | * Disable the link interrupt by writing 1 to the | |
2971 | * relevant lane in the status register | |
de6eae1f YR |
2972 | */ |
2973 | u32 ser_lane = ((params->lane_config & | |
2974 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> | |
2975 | PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); | |
b1607af5 | 2976 | |
de6eae1f YR |
2977 | DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n", |
2978 | vars->line_speed); | |
2979 | bnx2x_bits_en(bp, | |
2980 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2981 | ((1 << ser_lane) << | |
2982 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE)); | |
ea4e040a | 2983 | |
de6eae1f YR |
2984 | } else { /* SerDes */ |
2985 | DP(NETIF_MSG_LINK, "SerDes phy link up\n"); | |
2cf7acf9 YR |
2986 | /* |
2987 | * Disable the link interrupt by writing 1 to the status | |
2988 | * register | |
de6eae1f YR |
2989 | */ |
2990 | bnx2x_bits_en(bp, | |
2991 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | |
2992 | NIG_STATUS_SERDES0_LINK_STATUS); | |
2993 | } | |
ea4e040a | 2994 | |
ea4e040a | 2995 | } |
ea4e040a | 2996 | } |
ea4e040a | 2997 | |
de6eae1f YR |
2998 | static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len) |
2999 | { | |
3000 | u8 *str_ptr = str; | |
3001 | u32 mask = 0xf0000000; | |
3002 | u8 shift = 8*4; | |
3003 | u8 digit; | |
a22f0788 | 3004 | u8 remove_leading_zeros = 1; |
de6eae1f YR |
3005 | if (*len < 10) { |
3006 | /* Need more than 10chars for this format */ | |
3007 | *str_ptr = '\0'; | |
a22f0788 | 3008 | (*len)--; |
de6eae1f | 3009 | return -EINVAL; |
ea4e040a | 3010 | } |
de6eae1f | 3011 | while (shift > 0) { |
ea4e040a | 3012 | |
de6eae1f YR |
3013 | shift -= 4; |
3014 | digit = ((num & mask) >> shift); | |
a22f0788 YR |
3015 | if (digit == 0 && remove_leading_zeros) { |
3016 | mask = mask >> 4; | |
3017 | continue; | |
3018 | } else if (digit < 0xa) | |
de6eae1f YR |
3019 | *str_ptr = digit + '0'; |
3020 | else | |
3021 | *str_ptr = digit - 0xa + 'a'; | |
a22f0788 | 3022 | remove_leading_zeros = 0; |
de6eae1f | 3023 | str_ptr++; |
a22f0788 | 3024 | (*len)--; |
de6eae1f YR |
3025 | mask = mask >> 4; |
3026 | if (shift == 4*4) { | |
a22f0788 | 3027 | *str_ptr = '.'; |
de6eae1f | 3028 | str_ptr++; |
a22f0788 YR |
3029 | (*len)--; |
3030 | remove_leading_zeros = 1; | |
ea4e040a | 3031 | } |
ea4e040a | 3032 | } |
de6eae1f | 3033 | return 0; |
ea4e040a YR |
3034 | } |
3035 | ||
a22f0788 | 3036 | |
de6eae1f | 3037 | static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
ea4e040a | 3038 | { |
de6eae1f YR |
3039 | str[0] = '\0'; |
3040 | (*len)--; | |
3041 | return 0; | |
3042 | } | |
ea4e040a | 3043 | |
de6eae1f YR |
3044 | u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded, |
3045 | u8 *version, u16 len) | |
3046 | { | |
3047 | struct bnx2x *bp; | |
3048 | u32 spirom_ver = 0; | |
3049 | u8 status = 0; | |
3050 | u8 *ver_p = version; | |
a22f0788 | 3051 | u16 remain_len = len; |
de6eae1f YR |
3052 | if (version == NULL || params == NULL) |
3053 | return -EINVAL; | |
3054 | bp = params->bp; | |
ea4e040a | 3055 | |
de6eae1f YR |
3056 | /* Extract first external phy*/ |
3057 | version[0] = '\0'; | |
3058 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); | |
ea4e040a | 3059 | |
a22f0788 | 3060 | if (params->phy[EXT_PHY1].format_fw_ver) { |
de6eae1f YR |
3061 | status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, |
3062 | ver_p, | |
a22f0788 YR |
3063 | &remain_len); |
3064 | ver_p += (len - remain_len); | |
3065 | } | |
3066 | if ((params->num_phys == MAX_PHYS) && | |
3067 | (params->phy[EXT_PHY2].ver_addr != 0)) { | |
cd88ccee | 3068 | spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); |
a22f0788 YR |
3069 | if (params->phy[EXT_PHY2].format_fw_ver) { |
3070 | *ver_p = '/'; | |
3071 | ver_p++; | |
3072 | remain_len--; | |
3073 | status |= params->phy[EXT_PHY2].format_fw_ver( | |
3074 | spirom_ver, | |
3075 | ver_p, | |
3076 | &remain_len); | |
3077 | ver_p = version + (len - remain_len); | |
3078 | } | |
3079 | } | |
3080 | *ver_p = '\0'; | |
de6eae1f | 3081 | return status; |
6bbca910 | 3082 | } |
ea4e040a | 3083 | |
de6eae1f YR |
3084 | static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, |
3085 | struct link_params *params) | |
589abe3a | 3086 | { |
de6eae1f | 3087 | u8 port = params->port; |
589abe3a | 3088 | struct bnx2x *bp = params->bp; |
589abe3a | 3089 | |
de6eae1f YR |
3090 | if (phy->req_line_speed != SPEED_1000) { |
3091 | u32 md_devad; | |
589abe3a | 3092 | |
de6eae1f | 3093 | DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); |
589abe3a | 3094 | |
de6eae1f YR |
3095 | /* change the uni_phy_addr in the nig */ |
3096 | md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + | |
cd88ccee | 3097 | port*0x18)); |
cc1cb004 | 3098 | |
de6eae1f | 3099 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5); |
589abe3a | 3100 | |
de6eae1f | 3101 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
3102 | 5, |
3103 | (MDIO_REG_BANK_AER_BLOCK + | |
3104 | (MDIO_AER_BLOCK_AER_REG & 0xf)), | |
3105 | 0x2800); | |
589abe3a | 3106 | |
de6eae1f | 3107 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
3108 | 5, |
3109 | (MDIO_REG_BANK_CL73_IEEEB0 + | |
3110 | (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), | |
3111 | 0x6041); | |
de6eae1f YR |
3112 | msleep(200); |
3113 | /* set aer mmd back */ | |
f2e0899f | 3114 | bnx2x_set_aer_mmd_xgxs(params, phy); |
589abe3a | 3115 | |
de6eae1f | 3116 | /* and md_devad */ |
cd88ccee | 3117 | REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad); |
de6eae1f YR |
3118 | } else { |
3119 | u16 mii_ctrl; | |
3120 | DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); | |
3121 | bnx2x_cl45_read(bp, phy, 5, | |
3122 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
3123 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
3124 | &mii_ctrl); | |
3125 | bnx2x_cl45_write(bp, phy, 5, | |
3126 | (MDIO_REG_BANK_COMBO_IEEE0 + | |
3127 | (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), | |
3128 | mii_ctrl | | |
3129 | MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); | |
3130 | } | |
589abe3a EG |
3131 | } |
3132 | ||
7f02c4ad YR |
3133 | u8 bnx2x_set_led(struct link_params *params, |
3134 | struct link_vars *vars, u8 mode, u32 speed) | |
4d295db0 | 3135 | { |
de6eae1f YR |
3136 | u8 port = params->port; |
3137 | u16 hw_led_mode = params->hw_led_mode; | |
7f02c4ad | 3138 | u8 rc = 0, phy_idx; |
de6eae1f YR |
3139 | u32 tmp; |
3140 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | |
589abe3a | 3141 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
3142 | DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode); |
3143 | DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", | |
3144 | speed, hw_led_mode); | |
7f02c4ad YR |
3145 | /* In case */ |
3146 | for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) { | |
3147 | if (params->phy[phy_idx].set_link_led) { | |
3148 | params->phy[phy_idx].set_link_led( | |
3149 | ¶ms->phy[phy_idx], params, mode); | |
3150 | } | |
3151 | } | |
3152 | ||
de6eae1f | 3153 | switch (mode) { |
7f02c4ad | 3154 | case LED_MODE_FRONT_PANEL_OFF: |
de6eae1f YR |
3155 | case LED_MODE_OFF: |
3156 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); | |
3157 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, | |
cd88ccee | 3158 | SHARED_HW_CFG_LED_MAC1); |
589abe3a | 3159 | |
de6eae1f YR |
3160 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
3161 | EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); | |
3162 | break; | |
589abe3a | 3163 | |
de6eae1f | 3164 | case LED_MODE_OPER: |
2cf7acf9 | 3165 | /* |
7f02c4ad YR |
3166 | * For all other phys, OPER mode is same as ON, so in case |
3167 | * link is down, do nothing | |
2cf7acf9 | 3168 | */ |
7f02c4ad YR |
3169 | if (!vars->link_up) |
3170 | break; | |
3171 | case LED_MODE_ON: | |
1f48353a YR |
3172 | if (params->phy[EXT_PHY1].type == |
3173 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 && | |
3174 | CHIP_IS_E2(bp) && params->num_phys == 2) { | |
2cf7acf9 YR |
3175 | /* |
3176 | * This is a work-around for E2+8727 Configurations | |
3177 | */ | |
1f48353a YR |
3178 | if (mode == LED_MODE_ON || |
3179 | speed == SPEED_10000){ | |
3180 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); | |
3181 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
3182 | ||
3183 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); | |
3184 | EMAC_WR(bp, EMAC_REG_EMAC_LED, | |
3185 | (tmp | EMAC_LED_OVERRIDE)); | |
3186 | return rc; | |
3187 | } | |
3188 | } else if (SINGLE_MEDIA_DIRECT(params)) { | |
2cf7acf9 YR |
3189 | /* |
3190 | * This is a work-around for HW issue found when link | |
3191 | * is up in CL73 | |
3192 | */ | |
de6eae1f YR |
3193 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); |
3194 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | |
3195 | } else { | |
cd88ccee | 3196 | REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode); |
de6eae1f | 3197 | } |
589abe3a | 3198 | |
cd88ccee | 3199 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); |
de6eae1f YR |
3200 | /* Set blinking rate to ~15.9Hz */ |
3201 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, | |
cd88ccee | 3202 | LED_BLINK_RATE_VAL); |
de6eae1f | 3203 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + |
cd88ccee | 3204 | port*4, 1); |
de6eae1f | 3205 | tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); |
cd88ccee | 3206 | EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE))); |
589abe3a | 3207 | |
de6eae1f YR |
3208 | if (CHIP_IS_E1(bp) && |
3209 | ((speed == SPEED_2500) || | |
3210 | (speed == SPEED_1000) || | |
3211 | (speed == SPEED_100) || | |
3212 | (speed == SPEED_10))) { | |
2cf7acf9 YR |
3213 | /* |
3214 | * On Everest 1 Ax chip versions for speeds less than | |
3215 | * 10G LED scheme is different | |
3216 | */ | |
de6eae1f | 3217 | REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 |
cd88ccee | 3218 | + port*4, 1); |
de6eae1f | 3219 | REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + |
cd88ccee | 3220 | port*4, 0); |
de6eae1f | 3221 | REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + |
cd88ccee | 3222 | port*4, 1); |
de6eae1f YR |
3223 | } |
3224 | break; | |
589abe3a | 3225 | |
de6eae1f YR |
3226 | default: |
3227 | rc = -EINVAL; | |
3228 | DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n", | |
3229 | mode); | |
3230 | break; | |
589abe3a | 3231 | } |
de6eae1f | 3232 | return rc; |
589abe3a | 3233 | |
4d295db0 EG |
3234 | } |
3235 | ||
2cf7acf9 | 3236 | /* |
a22f0788 YR |
3237 | * This function comes to reflect the actual link state read DIRECTLY from the |
3238 | * HW | |
3239 | */ | |
3240 | u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars, | |
3241 | u8 is_serdes) | |
4d295db0 EG |
3242 | { |
3243 | struct bnx2x *bp = params->bp; | |
de6eae1f | 3244 | u16 gp_status = 0, phy_index = 0; |
a22f0788 YR |
3245 | u8 ext_phy_link_up = 0, serdes_phy_type; |
3246 | struct link_vars temp_vars; | |
4d295db0 | 3247 | |
cd2be89b | 3248 | CL22_RD_OVER_CL45(bp, ¶ms->phy[INT_PHY], |
cd88ccee YR |
3249 | MDIO_REG_BANK_GP_STATUS, |
3250 | MDIO_GP_STATUS_TOP_AN_STATUS1, | |
3251 | &gp_status); | |
de6eae1f | 3252 | /* link is up only if both local phy and external phy are up */ |
a22f0788 YR |
3253 | if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) |
3254 | return -ESRCH; | |
3255 | ||
3256 | switch (params->num_phys) { | |
3257 | case 1: | |
3258 | /* No external PHY */ | |
3259 | return 0; | |
3260 | case 2: | |
3261 | ext_phy_link_up = params->phy[EXT_PHY1].read_status( | |
3262 | ¶ms->phy[EXT_PHY1], | |
3263 | params, &temp_vars); | |
3264 | break; | |
3265 | case 3: /* Dual Media */ | |
de6eae1f YR |
3266 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
3267 | phy_index++) { | |
a22f0788 YR |
3268 | serdes_phy_type = ((params->phy[phy_index].media_type == |
3269 | ETH_PHY_SFP_FIBER) || | |
3270 | (params->phy[phy_index].media_type == | |
3271 | ETH_PHY_XFP_FIBER)); | |
3272 | ||
3273 | if (is_serdes != serdes_phy_type) | |
3274 | continue; | |
3275 | if (params->phy[phy_index].read_status) { | |
3276 | ext_phy_link_up |= | |
de6eae1f YR |
3277 | params->phy[phy_index].read_status( |
3278 | ¶ms->phy[phy_index], | |
3279 | params, &temp_vars); | |
a22f0788 | 3280 | } |
de6eae1f | 3281 | } |
a22f0788 | 3282 | break; |
4d295db0 | 3283 | } |
a22f0788 YR |
3284 | if (ext_phy_link_up) |
3285 | return 0; | |
de6eae1f YR |
3286 | return -ESRCH; |
3287 | } | |
4d295db0 | 3288 | |
de6eae1f YR |
3289 | static u8 bnx2x_link_initialize(struct link_params *params, |
3290 | struct link_vars *vars) | |
3291 | { | |
3292 | u8 rc = 0; | |
3293 | u8 phy_index, non_ext_phy; | |
3294 | struct bnx2x *bp = params->bp; | |
2cf7acf9 YR |
3295 | /* |
3296 | * In case of external phy existence, the line speed would be the | |
3297 | * line speed linked up by the external phy. In case it is direct | |
3298 | * only, then the line_speed during initialization will be | |
3299 | * equal to the req_line_speed | |
3300 | */ | |
de6eae1f | 3301 | vars->line_speed = params->phy[INT_PHY].req_line_speed; |
4d295db0 | 3302 | |
2cf7acf9 | 3303 | /* |
de6eae1f YR |
3304 | * Initialize the internal phy in case this is a direct board |
3305 | * (no external phys), or this board has external phy which requires | |
3306 | * to first. | |
3307 | */ | |
4d295db0 | 3308 | |
de6eae1f YR |
3309 | if (params->phy[INT_PHY].config_init) |
3310 | params->phy[INT_PHY].config_init( | |
3311 | ¶ms->phy[INT_PHY], | |
3312 | params, vars); | |
4d295db0 | 3313 | |
de6eae1f YR |
3314 | /* init ext phy and enable link state int */ |
3315 | non_ext_phy = (SINGLE_MEDIA_DIRECT(params) || | |
3316 | (params->loopback_mode == LOOPBACK_XGXS)); | |
4d295db0 | 3317 | |
de6eae1f YR |
3318 | if (non_ext_phy || |
3319 | (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || | |
3320 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
3321 | struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; | |
3322 | if (vars->line_speed == SPEED_AUTO_NEG) | |
3323 | bnx2x_set_parallel_detection(phy, params); | |
3324 | bnx2x_init_internal_phy(phy, params, vars); | |
4d295db0 EG |
3325 | } |
3326 | ||
de6eae1f YR |
3327 | /* Init external phy*/ |
3328 | if (!non_ext_phy) | |
3329 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
3330 | phy_index++) { | |
2cf7acf9 | 3331 | /* |
a22f0788 YR |
3332 | * No need to initialize second phy in case of first |
3333 | * phy only selection. In case of second phy, we do | |
3334 | * need to initialize the first phy, since they are | |
3335 | * connected. | |
2cf7acf9 | 3336 | */ |
a22f0788 YR |
3337 | if (phy_index == EXT_PHY2 && |
3338 | (bnx2x_phy_selection(params) == | |
3339 | PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { | |
2cf7acf9 | 3340 | DP(NETIF_MSG_LINK, "Ignoring second phy\n"); |
a22f0788 YR |
3341 | continue; |
3342 | } | |
de6eae1f YR |
3343 | params->phy[phy_index].config_init( |
3344 | ¶ms->phy[phy_index], | |
3345 | params, vars); | |
3346 | } | |
4d295db0 | 3347 | |
de6eae1f YR |
3348 | /* Reset the interrupt indication after phy was initialized */ |
3349 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + | |
3350 | params->port*4, | |
3351 | (NIG_STATUS_XGXS0_LINK10G | | |
3352 | NIG_STATUS_XGXS0_LINK_STATUS | | |
3353 | NIG_STATUS_SERDES0_LINK_STATUS | | |
3354 | NIG_MASK_MI_INT)); | |
3355 | return rc; | |
3356 | } | |
4d295db0 | 3357 | |
de6eae1f YR |
3358 | static void bnx2x_int_link_reset(struct bnx2x_phy *phy, |
3359 | struct link_params *params) | |
3360 | { | |
3361 | /* reset the SerDes/XGXS */ | |
cd88ccee YR |
3362 | REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
3363 | (0x1ff << (params->port*16))); | |
589abe3a EG |
3364 | } |
3365 | ||
de6eae1f YR |
3366 | static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy, |
3367 | struct link_params *params) | |
4d295db0 | 3368 | { |
de6eae1f YR |
3369 | struct bnx2x *bp = params->bp; |
3370 | u8 gpio_port; | |
3371 | /* HW reset */ | |
f2e0899f DK |
3372 | if (CHIP_IS_E2(bp)) |
3373 | gpio_port = BP_PATH(bp); | |
3374 | else | |
3375 | gpio_port = params->port; | |
de6eae1f | 3376 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee YR |
3377 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
3378 | gpio_port); | |
de6eae1f | 3379 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee YR |
3380 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
3381 | gpio_port); | |
de6eae1f | 3382 | DP(NETIF_MSG_LINK, "reset external PHY\n"); |
4d295db0 | 3383 | } |
589abe3a | 3384 | |
de6eae1f YR |
3385 | static u8 bnx2x_update_link_down(struct link_params *params, |
3386 | struct link_vars *vars) | |
589abe3a EG |
3387 | { |
3388 | struct bnx2x *bp = params->bp; | |
de6eae1f | 3389 | u8 port = params->port; |
589abe3a | 3390 | |
de6eae1f | 3391 | DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port); |
7f02c4ad | 3392 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
589abe3a | 3393 | |
de6eae1f YR |
3394 | /* indicate no mac active */ |
3395 | vars->mac_type = MAC_TYPE_NONE; | |
ab6ad5a4 | 3396 | |
de6eae1f YR |
3397 | /* update shared memory */ |
3398 | vars->link_status = 0; | |
3399 | vars->line_speed = 0; | |
3400 | bnx2x_update_mng(params, vars->link_status); | |
589abe3a | 3401 | |
de6eae1f YR |
3402 | /* activate nig drain */ |
3403 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
4d295db0 | 3404 | |
de6eae1f YR |
3405 | /* disable emac */ |
3406 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
3407 | ||
3408 | msleep(10); | |
3409 | ||
3410 | /* reset BigMac */ | |
3411 | bnx2x_bmac_rx_disable(bp, params->port); | |
cd88ccee YR |
3412 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
3413 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
589abe3a EG |
3414 | return 0; |
3415 | } | |
de6eae1f YR |
3416 | |
3417 | static u8 bnx2x_update_link_up(struct link_params *params, | |
3418 | struct link_vars *vars, | |
3419 | u8 link_10g) | |
589abe3a EG |
3420 | { |
3421 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
3422 | u8 port = params->port; |
3423 | u8 rc = 0; | |
4d295db0 | 3424 | |
de6eae1f | 3425 | vars->link_status |= LINK_STATUS_LINK_UP; |
7f02c4ad | 3426 | |
de6eae1f YR |
3427 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) |
3428 | vars->link_status |= | |
3429 | LINK_STATUS_TX_FLOW_CONTROL_ENABLED; | |
589abe3a | 3430 | |
de6eae1f YR |
3431 | if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) |
3432 | vars->link_status |= | |
3433 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | |
7f02c4ad | 3434 | |
de6eae1f YR |
3435 | if (link_10g) { |
3436 | bnx2x_bmac_enable(params, vars, 0); | |
7f02c4ad YR |
3437 | bnx2x_set_led(params, vars, |
3438 | LED_MODE_OPER, SPEED_10000); | |
de6eae1f YR |
3439 | } else { |
3440 | rc = bnx2x_emac_program(params, vars); | |
cc1cb004 | 3441 | |
de6eae1f | 3442 | bnx2x_emac_enable(params, vars, 0); |
cc1cb004 | 3443 | |
de6eae1f YR |
3444 | /* AN complete? */ |
3445 | if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) | |
3446 | && (!(vars->phy_flags & PHY_SGMII_FLAG)) && | |
3447 | SINGLE_MEDIA_DIRECT(params)) | |
3448 | bnx2x_set_gmii_tx_driver(params); | |
3449 | } | |
cc1cb004 | 3450 | |
de6eae1f | 3451 | /* PBF - link up */ |
f2e0899f DK |
3452 | if (!(CHIP_IS_E2(bp))) |
3453 | rc |= bnx2x_pbf_update(params, vars->flow_ctrl, | |
3454 | vars->line_speed); | |
589abe3a | 3455 | |
de6eae1f YR |
3456 | /* disable drain */ |
3457 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); | |
589abe3a | 3458 | |
de6eae1f YR |
3459 | /* update shared memory */ |
3460 | bnx2x_update_mng(params, vars->link_status); | |
3461 | msleep(20); | |
3462 | return rc; | |
589abe3a | 3463 | } |
2cf7acf9 | 3464 | /* |
de6eae1f YR |
3465 | * The bnx2x_link_update function should be called upon link |
3466 | * interrupt. | |
3467 | * Link is considered up as follows: | |
3468 | * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs | |
3469 | * to be up | |
3470 | * - SINGLE_MEDIA - The link between the 577xx and the external | |
3471 | * phy (XGXS) need to up as well as the external link of the | |
3472 | * phy (PHY_EXT1) | |
3473 | * - DUAL_MEDIA - The link between the 577xx and the first | |
3474 | * external phy needs to be up, and at least one of the 2 | |
3475 | * external phy link must be up. | |
3476 | */ | |
3477 | u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) | |
4d295db0 | 3478 | { |
de6eae1f YR |
3479 | struct bnx2x *bp = params->bp; |
3480 | struct link_vars phy_vars[MAX_PHYS]; | |
3481 | u8 port = params->port; | |
3482 | u8 link_10g, phy_index; | |
3483 | u8 ext_phy_link_up = 0, cur_link_up, rc = 0; | |
3484 | u8 is_mi_int = 0; | |
3485 | u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; | |
3486 | u8 active_external_phy = INT_PHY; | |
3487 | vars->link_status = 0; | |
3488 | for (phy_index = INT_PHY; phy_index < params->num_phys; | |
3489 | phy_index++) { | |
3490 | phy_vars[phy_index].flow_ctrl = 0; | |
3491 | phy_vars[phy_index].link_status = 0; | |
3492 | phy_vars[phy_index].line_speed = 0; | |
3493 | phy_vars[phy_index].duplex = DUPLEX_FULL; | |
3494 | phy_vars[phy_index].phy_link_up = 0; | |
3495 | phy_vars[phy_index].link_up = 0; | |
3496 | } | |
4d295db0 | 3497 | |
de6eae1f YR |
3498 | DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", |
3499 | port, (vars->phy_flags & PHY_XGXS_FLAG), | |
3500 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); | |
4d295db0 | 3501 | |
de6eae1f | 3502 | is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + |
cd88ccee | 3503 | port*0x18) > 0); |
de6eae1f YR |
3504 | DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", |
3505 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | |
3506 | is_mi_int, | |
cd88ccee | 3507 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); |
4d295db0 | 3508 | |
de6eae1f YR |
3509 | DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n", |
3510 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | |
3511 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); | |
4d295db0 | 3512 | |
de6eae1f YR |
3513 | /* disable emac */ |
3514 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
4d295db0 | 3515 | |
2cf7acf9 YR |
3516 | /* |
3517 | * Step 1: | |
3518 | * Check external link change only for external phys, and apply | |
3519 | * priority selection between them in case the link on both phys | |
3520 | * is up. Note that the instead of the common vars, a temporary | |
3521 | * vars argument is used since each phy may have different link/ | |
3522 | * speed/duplex result | |
3523 | */ | |
de6eae1f YR |
3524 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; |
3525 | phy_index++) { | |
3526 | struct bnx2x_phy *phy = ¶ms->phy[phy_index]; | |
3527 | if (!phy->read_status) | |
3528 | continue; | |
3529 | /* Read link status and params of this ext phy */ | |
3530 | cur_link_up = phy->read_status(phy, params, | |
3531 | &phy_vars[phy_index]); | |
3532 | if (cur_link_up) { | |
3533 | DP(NETIF_MSG_LINK, "phy in index %d link is up\n", | |
3534 | phy_index); | |
3535 | } else { | |
3536 | DP(NETIF_MSG_LINK, "phy in index %d link is down\n", | |
3537 | phy_index); | |
3538 | continue; | |
3539 | } | |
e10bc84d | 3540 | |
de6eae1f YR |
3541 | if (!ext_phy_link_up) { |
3542 | ext_phy_link_up = 1; | |
3543 | active_external_phy = phy_index; | |
a22f0788 YR |
3544 | } else { |
3545 | switch (bnx2x_phy_selection(params)) { | |
3546 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
3547 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
2cf7acf9 | 3548 | /* |
a22f0788 YR |
3549 | * In this option, the first PHY makes sure to pass the |
3550 | * traffic through itself only. | |
3551 | * Its not clear how to reset the link on the second phy | |
2cf7acf9 | 3552 | */ |
a22f0788 YR |
3553 | active_external_phy = EXT_PHY1; |
3554 | break; | |
3555 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
2cf7acf9 | 3556 | /* |
a22f0788 YR |
3557 | * In this option, the first PHY makes sure to pass the |
3558 | * traffic through the second PHY. | |
2cf7acf9 | 3559 | */ |
a22f0788 YR |
3560 | active_external_phy = EXT_PHY2; |
3561 | break; | |
3562 | default: | |
2cf7acf9 | 3563 | /* |
a22f0788 YR |
3564 | * Link indication on both PHYs with the following cases |
3565 | * is invalid: | |
3566 | * - FIRST_PHY means that second phy wasn't initialized, | |
3567 | * hence its link is expected to be down | |
3568 | * - SECOND_PHY means that first phy should not be able | |
3569 | * to link up by itself (using configuration) | |
3570 | * - DEFAULT should be overriden during initialiazation | |
2cf7acf9 | 3571 | */ |
a22f0788 YR |
3572 | DP(NETIF_MSG_LINK, "Invalid link indication" |
3573 | "mpc=0x%x. DISABLING LINK !!!\n", | |
3574 | params->multi_phy_config); | |
3575 | ext_phy_link_up = 0; | |
3576 | break; | |
3577 | } | |
589abe3a | 3578 | } |
589abe3a | 3579 | } |
de6eae1f | 3580 | prev_line_speed = vars->line_speed; |
2cf7acf9 YR |
3581 | /* |
3582 | * Step 2: | |
3583 | * Read the status of the internal phy. In case of | |
3584 | * DIRECT_SINGLE_MEDIA board, this link is the external link, | |
3585 | * otherwise this is the link between the 577xx and the first | |
3586 | * external phy | |
3587 | */ | |
de6eae1f YR |
3588 | if (params->phy[INT_PHY].read_status) |
3589 | params->phy[INT_PHY].read_status( | |
3590 | ¶ms->phy[INT_PHY], | |
3591 | params, vars); | |
2cf7acf9 | 3592 | /* |
de6eae1f YR |
3593 | * The INT_PHY flow control reside in the vars. This include the |
3594 | * case where the speed or flow control are not set to AUTO. | |
3595 | * Otherwise, the active external phy flow control result is set | |
3596 | * to the vars. The ext_phy_line_speed is needed to check if the | |
3597 | * speed is different between the internal phy and external phy. | |
3598 | * This case may be result of intermediate link speed change. | |
4d295db0 | 3599 | */ |
de6eae1f YR |
3600 | if (active_external_phy > INT_PHY) { |
3601 | vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; | |
2cf7acf9 | 3602 | /* |
de6eae1f YR |
3603 | * Link speed is taken from the XGXS. AN and FC result from |
3604 | * the external phy. | |
4d295db0 | 3605 | */ |
de6eae1f | 3606 | vars->link_status |= phy_vars[active_external_phy].link_status; |
a22f0788 | 3607 | |
2cf7acf9 | 3608 | /* |
a22f0788 YR |
3609 | * if active_external_phy is first PHY and link is up - disable |
3610 | * disable TX on second external PHY | |
3611 | */ | |
3612 | if (active_external_phy == EXT_PHY1) { | |
3613 | if (params->phy[EXT_PHY2].phy_specific_func) { | |
3614 | DP(NETIF_MSG_LINK, "Disabling TX on" | |
3615 | " EXT_PHY2\n"); | |
3616 | params->phy[EXT_PHY2].phy_specific_func( | |
3617 | ¶ms->phy[EXT_PHY2], | |
3618 | params, DISABLE_TX); | |
3619 | } | |
3620 | } | |
3621 | ||
de6eae1f YR |
3622 | ext_phy_line_speed = phy_vars[active_external_phy].line_speed; |
3623 | vars->duplex = phy_vars[active_external_phy].duplex; | |
3624 | if (params->phy[active_external_phy].supported & | |
3625 | SUPPORTED_FIBRE) | |
3626 | vars->link_status |= LINK_STATUS_SERDES_LINK; | |
3627 | DP(NETIF_MSG_LINK, "Active external phy selected: %x\n", | |
3628 | active_external_phy); | |
3629 | } | |
a22f0788 YR |
3630 | |
3631 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
3632 | phy_index++) { | |
3633 | if (params->phy[phy_index].flags & | |
3634 | FLAGS_REARM_LATCH_SIGNAL) { | |
3635 | bnx2x_rearm_latch_signal(bp, port, | |
3636 | phy_index == | |
3637 | active_external_phy); | |
3638 | break; | |
3639 | } | |
3640 | } | |
de6eae1f YR |
3641 | DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," |
3642 | " ext_phy_line_speed = %d\n", vars->flow_ctrl, | |
3643 | vars->link_status, ext_phy_line_speed); | |
2cf7acf9 | 3644 | /* |
de6eae1f YR |
3645 | * Upon link speed change set the NIG into drain mode. Comes to |
3646 | * deals with possible FIFO glitch due to clk change when speed | |
3647 | * is decreased without link down indicator | |
3648 | */ | |
4d295db0 | 3649 | |
de6eae1f YR |
3650 | if (vars->phy_link_up) { |
3651 | if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && | |
3652 | (ext_phy_line_speed != vars->line_speed)) { | |
3653 | DP(NETIF_MSG_LINK, "Internal link speed %d is" | |
3654 | " different than the external" | |
3655 | " link speed %d\n", vars->line_speed, | |
3656 | ext_phy_line_speed); | |
3657 | vars->phy_link_up = 0; | |
3658 | } else if (prev_line_speed != vars->line_speed) { | |
cd88ccee YR |
3659 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, |
3660 | 0); | |
de6eae1f YR |
3661 | msleep(1); |
3662 | } | |
3663 | } | |
e10bc84d | 3664 | |
de6eae1f YR |
3665 | /* anything 10 and over uses the bmac */ |
3666 | link_10g = ((vars->line_speed == SPEED_10000) || | |
3667 | (vars->line_speed == SPEED_12000) || | |
3668 | (vars->line_speed == SPEED_12500) || | |
3669 | (vars->line_speed == SPEED_13000) || | |
3670 | (vars->line_speed == SPEED_15000) || | |
3671 | (vars->line_speed == SPEED_16000)); | |
589abe3a | 3672 | |
a22f0788 | 3673 | bnx2x_link_int_ack(params, vars, link_10g); |
589abe3a | 3674 | |
2cf7acf9 YR |
3675 | /* |
3676 | * In case external phy link is up, and internal link is down | |
3677 | * (not initialized yet probably after link initialization, it | |
3678 | * needs to be initialized. | |
3679 | * Note that after link down-up as result of cable plug, the xgxs | |
3680 | * link would probably become up again without the need | |
3681 | * initialize it | |
3682 | */ | |
de6eae1f YR |
3683 | if (!(SINGLE_MEDIA_DIRECT(params))) { |
3684 | DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d," | |
3685 | " init_preceding = %d\n", ext_phy_link_up, | |
3686 | vars->phy_link_up, | |
3687 | params->phy[EXT_PHY1].flags & | |
3688 | FLAGS_INIT_XGXS_FIRST); | |
3689 | if (!(params->phy[EXT_PHY1].flags & | |
3690 | FLAGS_INIT_XGXS_FIRST) | |
3691 | && ext_phy_link_up && !vars->phy_link_up) { | |
3692 | vars->line_speed = ext_phy_line_speed; | |
3693 | if (vars->line_speed < SPEED_1000) | |
3694 | vars->phy_flags |= PHY_SGMII_FLAG; | |
3695 | else | |
3696 | vars->phy_flags &= ~PHY_SGMII_FLAG; | |
3697 | bnx2x_init_internal_phy(¶ms->phy[INT_PHY], | |
3698 | params, | |
3699 | vars); | |
4d295db0 | 3700 | } |
589abe3a | 3701 | } |
2cf7acf9 YR |
3702 | /* |
3703 | * Link is up only if both local phy and external phy (in case of | |
3704 | * non-direct board) are up | |
4d295db0 | 3705 | */ |
de6eae1f YR |
3706 | vars->link_up = (vars->phy_link_up && |
3707 | (ext_phy_link_up || | |
3708 | SINGLE_MEDIA_DIRECT(params))); | |
3709 | ||
3710 | if (vars->link_up) | |
3711 | rc = bnx2x_update_link_up(params, vars, link_10g); | |
4d295db0 | 3712 | else |
de6eae1f | 3713 | rc = bnx2x_update_link_down(params, vars); |
589abe3a | 3714 | |
4d295db0 | 3715 | return rc; |
589abe3a EG |
3716 | } |
3717 | ||
589abe3a | 3718 | |
de6eae1f YR |
3719 | /*****************************************************************************/ |
3720 | /* External Phy section */ | |
3721 | /*****************************************************************************/ | |
3722 | void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) | |
3723 | { | |
3724 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 3725 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
de6eae1f YR |
3726 | msleep(1); |
3727 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 3728 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); |
de6eae1f | 3729 | } |
589abe3a | 3730 | |
de6eae1f YR |
3731 | static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, |
3732 | u32 spirom_ver, u32 ver_addr) | |
3733 | { | |
3734 | DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", | |
3735 | (u16)(spirom_ver>>16), (u16)spirom_ver, port); | |
4d295db0 | 3736 | |
de6eae1f YR |
3737 | if (ver_addr) |
3738 | REG_WR(bp, ver_addr, spirom_ver); | |
589abe3a EG |
3739 | } |
3740 | ||
de6eae1f YR |
3741 | static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, |
3742 | struct bnx2x_phy *phy, | |
3743 | u8 port) | |
6bbca910 | 3744 | { |
de6eae1f YR |
3745 | u16 fw_ver1, fw_ver2; |
3746 | ||
3747 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, | |
cd88ccee | 3748 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); |
de6eae1f | 3749 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, |
cd88ccee | 3750 | MDIO_PMA_REG_ROM_VER2, &fw_ver2); |
de6eae1f YR |
3751 | bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), |
3752 | phy->ver_addr); | |
ea4e040a | 3753 | } |
ab6ad5a4 | 3754 | |
de6eae1f YR |
3755 | static void bnx2x_ext_phy_set_pause(struct link_params *params, |
3756 | struct bnx2x_phy *phy, | |
3757 | struct link_vars *vars) | |
ea4e040a | 3758 | { |
ea4e040a | 3759 | u16 val; |
de6eae1f YR |
3760 | struct bnx2x *bp = params->bp; |
3761 | /* read modify write pause advertizing */ | |
3762 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); | |
ea4e040a | 3763 | |
de6eae1f | 3764 | val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; |
ea4e040a | 3765 | |
de6eae1f YR |
3766 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ |
3767 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); | |
3768 | if ((vars->ieee_fc & | |
3769 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
3770 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
cd88ccee | 3771 | val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; |
de6eae1f YR |
3772 | } |
3773 | if ((vars->ieee_fc & | |
3774 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
3775 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
3776 | val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; | |
3777 | } | |
3778 | DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); | |
3779 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); | |
3780 | } | |
3781 | ||
3782 | static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, | |
3783 | struct link_params *params, | |
3784 | struct link_vars *vars) | |
3785 | { | |
3786 | struct bnx2x *bp = params->bp; | |
3787 | u16 ld_pause; /* local */ | |
3788 | u16 lp_pause; /* link partner */ | |
3789 | u16 pause_result; | |
3790 | u8 ret = 0; | |
3791 | /* read twice */ | |
3792 | ||
3793 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
3794 | ||
3795 | if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) | |
3796 | vars->flow_ctrl = phy->req_flow_ctrl; | |
3797 | else if (phy->req_line_speed != SPEED_AUTO_NEG) | |
3798 | vars->flow_ctrl = params->req_fc_auto_adv; | |
3799 | else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { | |
3800 | ret = 1; | |
3801 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
3802 | MDIO_AN_DEVAD, |
3803 | MDIO_AN_REG_ADV_PAUSE, &ld_pause); | |
de6eae1f | 3804 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
3805 | MDIO_AN_DEVAD, |
3806 | MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); | |
de6eae1f YR |
3807 | pause_result = (ld_pause & |
3808 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; | |
3809 | pause_result |= (lp_pause & | |
3810 | MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; | |
3811 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", | |
3812 | pause_result); | |
3813 | bnx2x_pause_resolve(vars, pause_result); | |
3814 | } | |
3815 | return ret; | |
3816 | } | |
3817 | ||
3818 | static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, | |
3819 | struct bnx2x_phy *phy, | |
3820 | struct link_vars *vars) | |
3821 | { | |
3822 | u16 val; | |
3823 | bnx2x_cl45_read(bp, phy, | |
3824 | MDIO_AN_DEVAD, | |
3825 | MDIO_AN_REG_STATUS, &val); | |
3826 | bnx2x_cl45_read(bp, phy, | |
3827 | MDIO_AN_DEVAD, | |
3828 | MDIO_AN_REG_STATUS, &val); | |
3829 | if (val & (1<<5)) | |
3830 | vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
3831 | if ((val & (1<<0)) == 0) | |
3832 | vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; | |
3833 | } | |
3834 | ||
3835 | /******************************************************************/ | |
3836 | /* common BCM8073/BCM8727 PHY SECTION */ | |
3837 | /******************************************************************/ | |
3838 | static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy, | |
3839 | struct link_params *params, | |
3840 | struct link_vars *vars) | |
3841 | { | |
3842 | struct bnx2x *bp = params->bp; | |
3843 | if (phy->req_line_speed == SPEED_10 || | |
3844 | phy->req_line_speed == SPEED_100) { | |
3845 | vars->flow_ctrl = phy->req_flow_ctrl; | |
3846 | return; | |
3847 | } | |
3848 | ||
3849 | if (bnx2x_ext_phy_resolve_fc(phy, params, vars) && | |
3850 | (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { | |
3851 | u16 pause_result; | |
3852 | u16 ld_pause; /* local */ | |
3853 | u16 lp_pause; /* link partner */ | |
3854 | bnx2x_cl45_read(bp, phy, | |
3855 | MDIO_AN_DEVAD, | |
3856 | MDIO_AN_REG_CL37_FC_LD, &ld_pause); | |
3857 | ||
3858 | bnx2x_cl45_read(bp, phy, | |
3859 | MDIO_AN_DEVAD, | |
3860 | MDIO_AN_REG_CL37_FC_LP, &lp_pause); | |
3861 | pause_result = (ld_pause & | |
3862 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; | |
3863 | pause_result |= (lp_pause & | |
3864 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; | |
3865 | ||
3866 | bnx2x_pause_resolve(vars, pause_result); | |
3867 | DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", | |
3868 | pause_result); | |
3869 | } | |
3870 | } | |
5c99274b | 3871 | static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, |
de6eae1f YR |
3872 | struct bnx2x_phy *phy, |
3873 | u8 port) | |
3874 | { | |
5c99274b YR |
3875 | u32 count = 0; |
3876 | u16 fw_ver1, fw_msgout; | |
3877 | u8 rc = 0; | |
3878 | ||
de6eae1f YR |
3879 | /* Boot port from external ROM */ |
3880 | /* EDC grst */ | |
3881 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3882 | MDIO_PMA_DEVAD, |
3883 | MDIO_PMA_REG_GEN_CTRL, | |
3884 | 0x0001); | |
de6eae1f YR |
3885 | |
3886 | /* ucode reboot and rst */ | |
3887 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3888 | MDIO_PMA_DEVAD, |
3889 | MDIO_PMA_REG_GEN_CTRL, | |
3890 | 0x008c); | |
de6eae1f YR |
3891 | |
3892 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3893 | MDIO_PMA_DEVAD, |
3894 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
de6eae1f YR |
3895 | |
3896 | /* Reset internal microprocessor */ | |
3897 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3898 | MDIO_PMA_DEVAD, |
3899 | MDIO_PMA_REG_GEN_CTRL, | |
3900 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
de6eae1f YR |
3901 | |
3902 | /* Release srst bit */ | |
3903 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3904 | MDIO_PMA_DEVAD, |
3905 | MDIO_PMA_REG_GEN_CTRL, | |
3906 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f | 3907 | |
5c99274b YR |
3908 | /* Delay 100ms per the PHY specifications */ |
3909 | msleep(100); | |
3910 | ||
3911 | /* 8073 sometimes taking longer to download */ | |
3912 | do { | |
3913 | count++; | |
3914 | if (count > 300) { | |
3915 | DP(NETIF_MSG_LINK, | |
3916 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
3917 | "Download failed. fw version = 0x%x\n", | |
3918 | port, fw_ver1); | |
3919 | rc = -EINVAL; | |
3920 | break; | |
3921 | } | |
3922 | ||
3923 | bnx2x_cl45_read(bp, phy, | |
3924 | MDIO_PMA_DEVAD, | |
3925 | MDIO_PMA_REG_ROM_VER1, &fw_ver1); | |
3926 | bnx2x_cl45_read(bp, phy, | |
3927 | MDIO_PMA_DEVAD, | |
3928 | MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); | |
3929 | ||
3930 | msleep(1); | |
3931 | } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || | |
3932 | ((fw_msgout & 0xff) != 0x03 && (phy->type == | |
3933 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); | |
de6eae1f YR |
3934 | |
3935 | /* Clear ser_boot_ctl bit */ | |
3936 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
3937 | MDIO_PMA_DEVAD, |
3938 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f | 3939 | bnx2x_save_bcm_spirom_ver(bp, phy, port); |
5c99274b YR |
3940 | |
3941 | DP(NETIF_MSG_LINK, | |
3942 | "bnx2x_8073_8727_external_rom_boot port %x:" | |
3943 | "Download complete. fw version = 0x%x\n", | |
3944 | port, fw_ver1); | |
3945 | ||
3946 | return rc; | |
de6eae1f YR |
3947 | } |
3948 | ||
de6eae1f YR |
3949 | /******************************************************************/ |
3950 | /* BCM8073 PHY SECTION */ | |
3951 | /******************************************************************/ | |
3952 | static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) | |
3953 | { | |
3954 | /* This is only required for 8073A1, version 102 only */ | |
3955 | u16 val; | |
3956 | ||
3957 | /* Read 8073 HW revision*/ | |
3958 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
3959 | MDIO_PMA_DEVAD, |
3960 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
3961 | |
3962 | if (val != 1) { | |
3963 | /* No need to workaround in 8073 A1 */ | |
3964 | return 0; | |
3965 | } | |
3966 | ||
3967 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
3968 | MDIO_PMA_DEVAD, |
3969 | MDIO_PMA_REG_ROM_VER2, &val); | |
de6eae1f YR |
3970 | |
3971 | /* SNR should be applied only for version 0x102 */ | |
3972 | if (val != 0x102) | |
3973 | return 0; | |
3974 | ||
3975 | return 1; | |
3976 | } | |
3977 | ||
3978 | static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) | |
3979 | { | |
3980 | u16 val, cnt, cnt1 ; | |
3981 | ||
3982 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
3983 | MDIO_PMA_DEVAD, |
3984 | MDIO_PMA_REG_8073_CHIP_REV, &val); | |
de6eae1f YR |
3985 | |
3986 | if (val > 0) { | |
3987 | /* No need to workaround in 8073 A1 */ | |
3988 | return 0; | |
3989 | } | |
3990 | /* XAUI workaround in 8073 A0: */ | |
3991 | ||
2cf7acf9 YR |
3992 | /* |
3993 | * After loading the boot ROM and restarting Autoneg, poll | |
3994 | * Dev1, Reg $C820: | |
3995 | */ | |
de6eae1f YR |
3996 | |
3997 | for (cnt = 0; cnt < 1000; cnt++) { | |
3998 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
3999 | MDIO_PMA_DEVAD, |
4000 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
4001 | &val); | |
2cf7acf9 YR |
4002 | /* |
4003 | * If bit [14] = 0 or bit [13] = 0, continue on with | |
4004 | * system initialization (XAUI work-around not required, as | |
4005 | * these bits indicate 2.5G or 1G link up). | |
4006 | */ | |
de6eae1f YR |
4007 | if (!(val & (1<<14)) || !(val & (1<<13))) { |
4008 | DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); | |
4009 | return 0; | |
4010 | } else if (!(val & (1<<15))) { | |
2cf7acf9 YR |
4011 | DP(NETIF_MSG_LINK, "bit 15 went off\n"); |
4012 | /* | |
4013 | * If bit 15 is 0, then poll Dev1, Reg $C841 until it's | |
4014 | * MSB (bit15) goes to 1 (indicating that the XAUI | |
4015 | * workaround has completed), then continue on with | |
4016 | * system initialization. | |
4017 | */ | |
de6eae1f YR |
4018 | for (cnt1 = 0; cnt1 < 1000; cnt1++) { |
4019 | bnx2x_cl45_read(bp, phy, | |
4020 | MDIO_PMA_DEVAD, | |
4021 | MDIO_PMA_REG_8073_XAUI_WA, &val); | |
4022 | if (val & (1<<15)) { | |
4023 | DP(NETIF_MSG_LINK, | |
4024 | "XAUI workaround has completed\n"); | |
4025 | return 0; | |
4026 | } | |
4027 | msleep(3); | |
4028 | } | |
4029 | break; | |
4030 | } | |
4031 | msleep(3); | |
4032 | } | |
4033 | DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); | |
4034 | return -EINVAL; | |
4035 | } | |
4036 | ||
4037 | static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) | |
4038 | { | |
4039 | /* Force KR or KX */ | |
4040 | bnx2x_cl45_write(bp, phy, | |
4041 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
4042 | bnx2x_cl45_write(bp, phy, | |
4043 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); | |
4044 | bnx2x_cl45_write(bp, phy, | |
4045 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); | |
4046 | bnx2x_cl45_write(bp, phy, | |
4047 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
4048 | } | |
4049 | ||
6bbca910 | 4050 | static void bnx2x_8073_set_pause_cl37(struct link_params *params, |
e10bc84d YR |
4051 | struct bnx2x_phy *phy, |
4052 | struct link_vars *vars) | |
ea4e040a | 4053 | { |
6bbca910 | 4054 | u16 cl37_val; |
e10bc84d YR |
4055 | struct bnx2x *bp = params->bp; |
4056 | bnx2x_cl45_read(bp, phy, | |
62b29a5d | 4057 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); |
6bbca910 YR |
4058 | |
4059 | cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
4060 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | |
e10bc84d | 4061 | bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); |
6bbca910 YR |
4062 | if ((vars->ieee_fc & |
4063 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == | |
4064 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { | |
4065 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | |
4066 | } | |
4067 | if ((vars->ieee_fc & | |
4068 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == | |
4069 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { | |
4070 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | |
4071 | } | |
4072 | if ((vars->ieee_fc & | |
4073 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == | |
4074 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { | |
4075 | cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | |
4076 | } | |
4077 | DP(NETIF_MSG_LINK, | |
4078 | "Ext phy AN advertize cl37 0x%x\n", cl37_val); | |
4079 | ||
e10bc84d | 4080 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 4081 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); |
6bbca910 | 4082 | msleep(500); |
ea4e040a YR |
4083 | } |
4084 | ||
de6eae1f YR |
4085 | static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy, |
4086 | struct link_params *params, | |
4087 | struct link_vars *vars) | |
ea4e040a | 4088 | { |
e10bc84d | 4089 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4090 | u16 val = 0, tmp1; |
4091 | u8 gpio_port; | |
4092 | DP(NETIF_MSG_LINK, "Init 8073\n"); | |
e10bc84d | 4093 | |
f2e0899f DK |
4094 | if (CHIP_IS_E2(bp)) |
4095 | gpio_port = BP_PATH(bp); | |
4096 | else | |
4097 | gpio_port = params->port; | |
de6eae1f YR |
4098 | /* Restore normal power mode*/ |
4099 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 4100 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
e10bc84d | 4101 | |
de6eae1f | 4102 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 4103 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); |
ea4e040a | 4104 | |
de6eae1f YR |
4105 | /* enable LASI */ |
4106 | bnx2x_cl45_write(bp, phy, | |
4107 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2)); | |
4108 | bnx2x_cl45_write(bp, phy, | |
4109 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004); | |
c2c8b03e | 4110 | |
de6eae1f | 4111 | bnx2x_8073_set_pause_cl37(params, phy, vars); |
57963ed9 | 4112 | |
e10bc84d | 4113 | bnx2x_cl45_read(bp, phy, |
de6eae1f | 4114 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); |
2f904460 | 4115 | |
de6eae1f YR |
4116 | bnx2x_cl45_read(bp, phy, |
4117 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1); | |
2f904460 | 4118 | |
de6eae1f | 4119 | DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); |
a1e4be39 | 4120 | |
74d7a119 YR |
4121 | /* Swap polarity if required - Must be done only in non-1G mode */ |
4122 | if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
4123 | /* Configure the 8073 to swap _P and _N of the KR lines */ | |
4124 | DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n"); | |
4125 | /* 10G Rx/Tx and 1G Tx signal polarity swap */ | |
4126 | bnx2x_cl45_read(bp, phy, | |
4127 | MDIO_PMA_DEVAD, | |
4128 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); | |
4129 | bnx2x_cl45_write(bp, phy, | |
4130 | MDIO_PMA_DEVAD, | |
4131 | MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, | |
4132 | (val | (3<<9))); | |
4133 | } | |
4134 | ||
4135 | ||
de6eae1f | 4136 | /* Enable CL37 BAM */ |
121839be YR |
4137 | if (REG_RD(bp, params->shmem_base + |
4138 | offsetof(struct shmem_region, dev_info. | |
4139 | port_hw_config[params->port].default_cfg)) & | |
4140 | PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { | |
57963ed9 | 4141 | |
121839be YR |
4142 | bnx2x_cl45_read(bp, phy, |
4143 | MDIO_AN_DEVAD, | |
4144 | MDIO_AN_REG_8073_BAM, &val); | |
4145 | bnx2x_cl45_write(bp, phy, | |
4146 | MDIO_AN_DEVAD, | |
4147 | MDIO_AN_REG_8073_BAM, val | 1); | |
4148 | DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n"); | |
4149 | } | |
de6eae1f YR |
4150 | if (params->loopback_mode == LOOPBACK_EXT) { |
4151 | bnx2x_807x_force_10G(bp, phy); | |
4152 | DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n"); | |
4153 | return 0; | |
4154 | } else { | |
4155 | bnx2x_cl45_write(bp, phy, | |
4156 | MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); | |
4157 | } | |
4158 | if (phy->req_line_speed != SPEED_AUTO_NEG) { | |
4159 | if (phy->req_line_speed == SPEED_10000) { | |
4160 | val = (1<<7); | |
4161 | } else if (phy->req_line_speed == SPEED_2500) { | |
4162 | val = (1<<5); | |
2cf7acf9 YR |
4163 | /* |
4164 | * Note that 2.5G works only when used with 1G | |
4165 | * advertisment | |
4166 | */ | |
de6eae1f YR |
4167 | } else |
4168 | val = (1<<5); | |
4169 | } else { | |
4170 | val = 0; | |
4171 | if (phy->speed_cap_mask & | |
4172 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) | |
4173 | val |= (1<<7); | |
57963ed9 | 4174 | |
2cf7acf9 | 4175 | /* Note that 2.5G works only when used with 1G advertisment */ |
de6eae1f YR |
4176 | if (phy->speed_cap_mask & |
4177 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | | |
4178 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | |
4179 | val |= (1<<5); | |
4180 | DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); | |
4181 | } | |
57963ed9 | 4182 | |
de6eae1f YR |
4183 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); |
4184 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); | |
57963ed9 | 4185 | |
de6eae1f YR |
4186 | if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && |
4187 | (phy->req_line_speed == SPEED_AUTO_NEG)) || | |
4188 | (phy->req_line_speed == SPEED_2500)) { | |
4189 | u16 phy_ver; | |
4190 | /* Allow 2.5G for A1 and above */ | |
4191 | bnx2x_cl45_read(bp, phy, | |
4192 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, | |
4193 | &phy_ver); | |
4194 | DP(NETIF_MSG_LINK, "Add 2.5G\n"); | |
4195 | if (phy_ver > 0) | |
4196 | tmp1 |= 1; | |
4197 | else | |
4198 | tmp1 &= 0xfffe; | |
4199 | } else { | |
4200 | DP(NETIF_MSG_LINK, "Disable 2.5G\n"); | |
4201 | tmp1 &= 0xfffe; | |
4202 | } | |
57963ed9 | 4203 | |
de6eae1f YR |
4204 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); |
4205 | /* Add support for CL37 (passive mode) II */ | |
57963ed9 | 4206 | |
de6eae1f YR |
4207 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); |
4208 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, | |
4209 | (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? | |
4210 | 0x20 : 0x40))); | |
57963ed9 | 4211 | |
de6eae1f YR |
4212 | /* Add support for CL37 (passive mode) III */ |
4213 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
57963ed9 | 4214 | |
2cf7acf9 YR |
4215 | /* |
4216 | * The SNR will improve about 2db by changing BW and FEE main | |
4217 | * tap. Rest commands are executed after link is up | |
4218 | * Change FFE main cursor to 5 in EDC register | |
4219 | */ | |
de6eae1f YR |
4220 | if (bnx2x_8073_is_snr_needed(bp, phy)) |
4221 | bnx2x_cl45_write(bp, phy, | |
4222 | MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, | |
4223 | 0xFB0C); | |
57963ed9 | 4224 | |
de6eae1f YR |
4225 | /* Enable FEC (Forware Error Correction) Request in the AN */ |
4226 | bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); | |
4227 | tmp1 |= (1<<15); | |
4228 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); | |
57963ed9 | 4229 | |
de6eae1f | 4230 | bnx2x_ext_phy_set_pause(params, phy, vars); |
57963ed9 | 4231 | |
de6eae1f YR |
4232 | /* Restart autoneg */ |
4233 | msleep(500); | |
4234 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
4235 | DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", | |
4236 | ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); | |
4237 | return 0; | |
b7737c9b | 4238 | } |
ea4e040a | 4239 | |
de6eae1f | 4240 | static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
4241 | struct link_params *params, |
4242 | struct link_vars *vars) | |
4243 | { | |
4244 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4245 | u8 link_up = 0; |
4246 | u16 val1, val2; | |
4247 | u16 link_status = 0; | |
4248 | u16 an1000_status = 0; | |
a35da8db | 4249 | |
de6eae1f YR |
4250 | bnx2x_cl45_read(bp, phy, |
4251 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
b7737c9b | 4252 | |
de6eae1f | 4253 | DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); |
ea4e040a | 4254 | |
de6eae1f YR |
4255 | /* clear the interrupt LASI status register */ |
4256 | bnx2x_cl45_read(bp, phy, | |
4257 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
4258 | bnx2x_cl45_read(bp, phy, | |
4259 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); | |
4260 | DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); | |
4261 | /* Clear MSG-OUT */ | |
4262 | bnx2x_cl45_read(bp, phy, | |
4263 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
4264 | ||
4265 | /* Check the LASI */ | |
4266 | bnx2x_cl45_read(bp, phy, | |
4267 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2); | |
4268 | ||
4269 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); | |
4270 | ||
4271 | /* Check the link status */ | |
4272 | bnx2x_cl45_read(bp, phy, | |
4273 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); | |
4274 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | |
4275 | ||
4276 | bnx2x_cl45_read(bp, phy, | |
4277 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
4278 | bnx2x_cl45_read(bp, phy, | |
4279 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
4280 | link_up = ((val1 & 4) == 4); | |
4281 | DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); | |
4282 | ||
4283 | if (link_up && | |
4284 | ((phy->req_line_speed != SPEED_10000))) { | |
4285 | if (bnx2x_8073_xaui_wa(bp, phy) != 0) | |
4286 | return 0; | |
62b29a5d | 4287 | } |
de6eae1f YR |
4288 | bnx2x_cl45_read(bp, phy, |
4289 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
4290 | bnx2x_cl45_read(bp, phy, | |
4291 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); | |
62b29a5d | 4292 | |
de6eae1f YR |
4293 | /* Check the link status on 1.1.2 */ |
4294 | bnx2x_cl45_read(bp, phy, | |
4295 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
4296 | bnx2x_cl45_read(bp, phy, | |
4297 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
4298 | DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," | |
4299 | "an_link_status=0x%x\n", val2, val1, an1000_status); | |
62b29a5d | 4300 | |
de6eae1f YR |
4301 | link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); |
4302 | if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { | |
2cf7acf9 YR |
4303 | /* |
4304 | * The SNR will improve about 2dbby changing the BW and FEE main | |
4305 | * tap. The 1st write to change FFE main tap is set before | |
4306 | * restart AN. Change PLL Bandwidth in EDC register | |
4307 | */ | |
62b29a5d | 4308 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
4309 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, |
4310 | 0x26BC); | |
62b29a5d | 4311 | |
de6eae1f | 4312 | /* Change CDR Bandwidth in EDC register */ |
62b29a5d | 4313 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
4314 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, |
4315 | 0x0333); | |
4316 | } | |
4317 | bnx2x_cl45_read(bp, phy, | |
4318 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, | |
4319 | &link_status); | |
62b29a5d | 4320 | |
de6eae1f YR |
4321 | /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ |
4322 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { | |
4323 | link_up = 1; | |
4324 | vars->line_speed = SPEED_10000; | |
4325 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", | |
4326 | params->port); | |
4327 | } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { | |
4328 | link_up = 1; | |
4329 | vars->line_speed = SPEED_2500; | |
4330 | DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n", | |
4331 | params->port); | |
4332 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { | |
4333 | link_up = 1; | |
4334 | vars->line_speed = SPEED_1000; | |
4335 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
4336 | params->port); | |
4337 | } else { | |
4338 | link_up = 0; | |
4339 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
4340 | params->port); | |
62b29a5d | 4341 | } |
de6eae1f YR |
4342 | |
4343 | if (link_up) { | |
74d7a119 YR |
4344 | /* Swap polarity if required */ |
4345 | if (params->lane_config & | |
4346 | PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { | |
4347 | /* Configure the 8073 to swap P and N of the KR lines */ | |
4348 | bnx2x_cl45_read(bp, phy, | |
4349 | MDIO_XS_DEVAD, | |
4350 | MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); | |
2cf7acf9 YR |
4351 | /* |
4352 | * Set bit 3 to invert Rx in 1G mode and clear this bit | |
4353 | * when it`s in 10G mode. | |
4354 | */ | |
74d7a119 YR |
4355 | if (vars->line_speed == SPEED_1000) { |
4356 | DP(NETIF_MSG_LINK, "Swapping 1G polarity for" | |
4357 | "the 8073\n"); | |
4358 | val1 |= (1<<3); | |
4359 | } else | |
4360 | val1 &= ~(1<<3); | |
4361 | ||
4362 | bnx2x_cl45_write(bp, phy, | |
4363 | MDIO_XS_DEVAD, | |
4364 | MDIO_XS_REG_8073_RX_CTRL_PCIE, | |
4365 | val1); | |
4366 | } | |
de6eae1f YR |
4367 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); |
4368 | bnx2x_8073_resolve_fc(phy, params, vars); | |
791f18c0 | 4369 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
4370 | } |
4371 | return link_up; | |
b7737c9b YR |
4372 | } |
4373 | ||
de6eae1f YR |
4374 | static void bnx2x_8073_link_reset(struct bnx2x_phy *phy, |
4375 | struct link_params *params) | |
4376 | { | |
4377 | struct bnx2x *bp = params->bp; | |
4378 | u8 gpio_port; | |
f2e0899f DK |
4379 | if (CHIP_IS_E2(bp)) |
4380 | gpio_port = BP_PATH(bp); | |
4381 | else | |
4382 | gpio_port = params->port; | |
de6eae1f YR |
4383 | DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n", |
4384 | gpio_port); | |
4385 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
4386 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
4387 | gpio_port); | |
de6eae1f YR |
4388 | } |
4389 | ||
4390 | /******************************************************************/ | |
4391 | /* BCM8705 PHY SECTION */ | |
4392 | /******************************************************************/ | |
4393 | static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
4394 | struct link_params *params, |
4395 | struct link_vars *vars) | |
4396 | { | |
4397 | struct bnx2x *bp = params->bp; | |
de6eae1f | 4398 | DP(NETIF_MSG_LINK, "init 8705\n"); |
b7737c9b YR |
4399 | /* Restore normal power mode*/ |
4400 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 4401 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
4402 | /* HW reset */ |
4403 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
4404 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
b7737c9b YR |
4405 | bnx2x_wait_reset_complete(bp, phy); |
4406 | ||
de6eae1f YR |
4407 | bnx2x_cl45_write(bp, phy, |
4408 | MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); | |
4409 | bnx2x_cl45_write(bp, phy, | |
4410 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); | |
4411 | bnx2x_cl45_write(bp, phy, | |
4412 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); | |
4413 | bnx2x_cl45_write(bp, phy, | |
4414 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); | |
4415 | /* BCM8705 doesn't have microcode, hence the 0 */ | |
4416 | bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); | |
4417 | return 0; | |
4418 | } | |
4d295db0 | 4419 | |
de6eae1f YR |
4420 | static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy, |
4421 | struct link_params *params, | |
4422 | struct link_vars *vars) | |
4423 | { | |
4424 | u8 link_up = 0; | |
4425 | u16 val1, rx_sd; | |
4426 | struct bnx2x *bp = params->bp; | |
4427 | DP(NETIF_MSG_LINK, "read status 8705\n"); | |
4428 | bnx2x_cl45_read(bp, phy, | |
4429 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
4430 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 4431 | |
de6eae1f YR |
4432 | bnx2x_cl45_read(bp, phy, |
4433 | MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); | |
4434 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
62b29a5d | 4435 | |
de6eae1f YR |
4436 | bnx2x_cl45_read(bp, phy, |
4437 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); | |
c2c8b03e | 4438 | |
de6eae1f YR |
4439 | bnx2x_cl45_read(bp, phy, |
4440 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
4441 | bnx2x_cl45_read(bp, phy, | |
4442 | MDIO_PMA_DEVAD, 0xc809, &val1); | |
c2c8b03e | 4443 | |
de6eae1f YR |
4444 | DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); |
4445 | link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); | |
4446 | if (link_up) { | |
4447 | vars->line_speed = SPEED_10000; | |
4448 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
62b29a5d | 4449 | } |
de6eae1f YR |
4450 | return link_up; |
4451 | } | |
d90d96ba | 4452 | |
de6eae1f YR |
4453 | /******************************************************************/ |
4454 | /* SFP+ module Section */ | |
4455 | /******************************************************************/ | |
4456 | static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, | |
4457 | struct bnx2x_phy *phy, | |
4458 | u8 port, | |
4459 | u8 tx_en) | |
4460 | { | |
4461 | u16 val; | |
d90d96ba | 4462 | |
de6eae1f YR |
4463 | DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n", |
4464 | tx_en, port); | |
4465 | /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ | |
4466 | bnx2x_cl45_read(bp, phy, | |
4467 | MDIO_PMA_DEVAD, | |
4468 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4469 | &val); | |
d90d96ba | 4470 | |
de6eae1f YR |
4471 | if (tx_en) |
4472 | val &= ~(1<<15); | |
4473 | else | |
4474 | val |= (1<<15); | |
b7737c9b | 4475 | |
de6eae1f YR |
4476 | bnx2x_cl45_write(bp, phy, |
4477 | MDIO_PMA_DEVAD, | |
4478 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4479 | val); | |
b7737c9b YR |
4480 | } |
4481 | ||
de6eae1f YR |
4482 | static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
4483 | struct link_params *params, | |
cd88ccee | 4484 | u16 addr, u8 byte_cnt, u8 *o_buf) |
b7737c9b YR |
4485 | { |
4486 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4487 | u16 val = 0; |
4488 | u16 i; | |
4489 | if (byte_cnt > 16) { | |
4490 | DP(NETIF_MSG_LINK, "Reading from eeprom is" | |
4491 | " is limited to 0xf\n"); | |
4492 | return -EINVAL; | |
4493 | } | |
4494 | /* Set the read command byte count */ | |
62b29a5d | 4495 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 4496 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, |
cd88ccee | 4497 | (byte_cnt | 0xa000)); |
ea4e040a | 4498 | |
de6eae1f YR |
4499 | /* Set the read command address */ |
4500 | bnx2x_cl45_write(bp, phy, | |
4501 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
cd88ccee | 4502 | addr); |
ea4e040a | 4503 | |
de6eae1f | 4504 | /* Activate read command */ |
62b29a5d | 4505 | bnx2x_cl45_write(bp, phy, |
de6eae1f | 4506 | MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, |
cd88ccee | 4507 | 0x2c0f); |
ea4e040a | 4508 | |
de6eae1f YR |
4509 | /* Wait up to 500us for command complete status */ |
4510 | for (i = 0; i < 100; i++) { | |
4511 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
4512 | MDIO_PMA_DEVAD, |
4513 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
4514 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
4515 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
4516 | break; | |
4517 | udelay(5); | |
62b29a5d | 4518 | } |
62b29a5d | 4519 | |
de6eae1f YR |
4520 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
4521 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
4522 | DP(NETIF_MSG_LINK, | |
4523 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
4524 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
4525 | return -EINVAL; | |
62b29a5d | 4526 | } |
e10bc84d | 4527 | |
de6eae1f YR |
4528 | /* Read the buffer */ |
4529 | for (i = 0; i < byte_cnt; i++) { | |
62b29a5d | 4530 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
4531 | MDIO_PMA_DEVAD, |
4532 | MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f | 4533 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); |
62b29a5d | 4534 | } |
6bbca910 | 4535 | |
de6eae1f YR |
4536 | for (i = 0; i < 100; i++) { |
4537 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
4538 | MDIO_PMA_DEVAD, |
4539 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
4540 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
4541 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 4542 | return 0; |
de6eae1f YR |
4543 | msleep(1); |
4544 | } | |
4545 | return -EINVAL; | |
b7737c9b | 4546 | } |
4d295db0 | 4547 | |
de6eae1f YR |
4548 | static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
4549 | struct link_params *params, | |
cd88ccee | 4550 | u16 addr, u8 byte_cnt, u8 *o_buf) |
b7737c9b | 4551 | { |
b7737c9b | 4552 | struct bnx2x *bp = params->bp; |
de6eae1f | 4553 | u16 val, i; |
ea4e040a | 4554 | |
de6eae1f YR |
4555 | if (byte_cnt > 16) { |
4556 | DP(NETIF_MSG_LINK, "Reading from eeprom is" | |
4557 | " is limited to 0xf\n"); | |
4558 | return -EINVAL; | |
4559 | } | |
4d295db0 | 4560 | |
de6eae1f YR |
4561 | /* Need to read from 1.8000 to clear it */ |
4562 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
4563 | MDIO_PMA_DEVAD, |
4564 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
4565 | &val); | |
4d295db0 | 4566 | |
de6eae1f | 4567 | /* Set the read command byte count */ |
62b29a5d | 4568 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4569 | MDIO_PMA_DEVAD, |
4570 | MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, | |
4571 | ((byte_cnt < 2) ? 2 : byte_cnt)); | |
ea4e040a | 4572 | |
de6eae1f | 4573 | /* Set the read command address */ |
62b29a5d | 4574 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4575 | MDIO_PMA_DEVAD, |
4576 | MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, | |
4577 | addr); | |
de6eae1f | 4578 | /* Set the destination address */ |
62b29a5d | 4579 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4580 | MDIO_PMA_DEVAD, |
4581 | 0x8004, | |
4582 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); | |
62b29a5d | 4583 | |
de6eae1f | 4584 | /* Activate read command */ |
62b29a5d | 4585 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4586 | MDIO_PMA_DEVAD, |
4587 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, | |
4588 | 0x8002); | |
2cf7acf9 YR |
4589 | /* |
4590 | * Wait appropriate time for two-wire command to finish before | |
4591 | * polling the status register | |
4592 | */ | |
de6eae1f | 4593 | msleep(1); |
4d295db0 | 4594 | |
de6eae1f YR |
4595 | /* Wait up to 500us for command complete status */ |
4596 | for (i = 0; i < 100; i++) { | |
62b29a5d | 4597 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
4598 | MDIO_PMA_DEVAD, |
4599 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
4600 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
4601 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) | |
4602 | break; | |
4603 | udelay(5); | |
62b29a5d | 4604 | } |
4d295db0 | 4605 | |
de6eae1f YR |
4606 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != |
4607 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { | |
4608 | DP(NETIF_MSG_LINK, | |
4609 | "Got bad status 0x%x when reading from SFP+ EEPROM\n", | |
4610 | (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); | |
65a001ba | 4611 | return -EFAULT; |
de6eae1f | 4612 | } |
62b29a5d | 4613 | |
de6eae1f YR |
4614 | /* Read the buffer */ |
4615 | for (i = 0; i < byte_cnt; i++) { | |
4616 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
4617 | MDIO_PMA_DEVAD, |
4618 | MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); | |
de6eae1f YR |
4619 | o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); |
4620 | } | |
4d295db0 | 4621 | |
de6eae1f YR |
4622 | for (i = 0; i < 100; i++) { |
4623 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
4624 | MDIO_PMA_DEVAD, |
4625 | MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); | |
de6eae1f YR |
4626 | if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == |
4627 | MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) | |
6f38ad93 | 4628 | return 0; |
de6eae1f | 4629 | msleep(1); |
62b29a5d YR |
4630 | } |
4631 | ||
de6eae1f | 4632 | return -EINVAL; |
b7737c9b YR |
4633 | } |
4634 | ||
cd88ccee YR |
4635 | u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, |
4636 | struct link_params *params, u16 addr, | |
4637 | u8 byte_cnt, u8 *o_buf) | |
b7737c9b | 4638 | { |
de6eae1f YR |
4639 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) |
4640 | return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | |
cd88ccee | 4641 | byte_cnt, o_buf); |
de6eae1f YR |
4642 | else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) |
4643 | return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | |
cd88ccee | 4644 | byte_cnt, o_buf); |
de6eae1f | 4645 | return -EINVAL; |
b7737c9b YR |
4646 | } |
4647 | ||
de6eae1f YR |
4648 | static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
4649 | struct link_params *params, | |
cd88ccee | 4650 | u16 *edc_mode) |
b7737c9b YR |
4651 | { |
4652 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
4653 | u8 val, check_limiting_mode = 0; |
4654 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 4655 | |
de6eae1f YR |
4656 | /* First check for copper cable */ |
4657 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4658 | params, | |
4659 | SFP_EEPROM_CON_TYPE_ADDR, | |
4660 | 1, | |
4661 | &val) != 0) { | |
4662 | DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); | |
4663 | return -EINVAL; | |
4664 | } | |
a1e4be39 | 4665 | |
de6eae1f YR |
4666 | switch (val) { |
4667 | case SFP_EEPROM_CON_TYPE_VAL_COPPER: | |
4668 | { | |
4669 | u8 copper_module_type; | |
62b29a5d | 4670 | |
2cf7acf9 YR |
4671 | /* |
4672 | * Check if its active cable (includes SFP+ module) | |
4673 | * of passive cable | |
4674 | */ | |
de6eae1f YR |
4675 | if (bnx2x_read_sfp_module_eeprom(phy, |
4676 | params, | |
4677 | SFP_EEPROM_FC_TX_TECH_ADDR, | |
4678 | 1, | |
4679 | &copper_module_type) != | |
4680 | 0) { | |
4681 | DP(NETIF_MSG_LINK, | |
4682 | "Failed to read copper-cable-type" | |
4683 | " from SFP+ EEPROM\n"); | |
4684 | return -EINVAL; | |
4685 | } | |
4f60dab1 | 4686 | |
de6eae1f YR |
4687 | if (copper_module_type & |
4688 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { | |
4689 | DP(NETIF_MSG_LINK, "Active Copper cable detected\n"); | |
4690 | check_limiting_mode = 1; | |
4691 | } else if (copper_module_type & | |
4692 | SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { | |
4693 | DP(NETIF_MSG_LINK, "Passive Copper" | |
4694 | " cable detected\n"); | |
4695 | *edc_mode = | |
4696 | EDC_MODE_PASSIVE_DAC; | |
4697 | } else { | |
4698 | DP(NETIF_MSG_LINK, "Unknown copper-cable-" | |
4699 | "type 0x%x !!!\n", copper_module_type); | |
4700 | return -EINVAL; | |
4701 | } | |
4702 | break; | |
62b29a5d | 4703 | } |
de6eae1f YR |
4704 | case SFP_EEPROM_CON_TYPE_VAL_LC: |
4705 | DP(NETIF_MSG_LINK, "Optic module detected\n"); | |
4706 | check_limiting_mode = 1; | |
4707 | break; | |
4708 | default: | |
4709 | DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", | |
4710 | val); | |
4711 | return -EINVAL; | |
62b29a5d | 4712 | } |
2f904460 | 4713 | |
de6eae1f YR |
4714 | if (check_limiting_mode) { |
4715 | u8 options[SFP_EEPROM_OPTIONS_SIZE]; | |
4716 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4717 | params, | |
4718 | SFP_EEPROM_OPTIONS_ADDR, | |
4719 | SFP_EEPROM_OPTIONS_SIZE, | |
4720 | options) != 0) { | |
4721 | DP(NETIF_MSG_LINK, "Failed to read Option" | |
4722 | " field from module EEPROM\n"); | |
4723 | return -EINVAL; | |
4724 | } | |
4725 | if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) | |
4726 | *edc_mode = EDC_MODE_LINEAR; | |
4727 | else | |
4728 | *edc_mode = EDC_MODE_LIMITING; | |
62b29a5d | 4729 | } |
de6eae1f | 4730 | DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); |
62b29a5d | 4731 | return 0; |
b7737c9b | 4732 | } |
2cf7acf9 YR |
4733 | /* |
4734 | * This function read the relevant field from the module (SFP+), and verify it | |
4735 | * is compliant with this board | |
4736 | */ | |
de6eae1f YR |
4737 | static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy, |
4738 | struct link_params *params) | |
b7737c9b YR |
4739 | { |
4740 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
4741 | u32 val, cmd; |
4742 | u32 fw_resp, fw_cmd_param; | |
de6eae1f YR |
4743 | char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1]; |
4744 | char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1]; | |
a22f0788 | 4745 | phy->flags &= ~FLAGS_SFP_NOT_APPROVED; |
de6eae1f YR |
4746 | val = REG_RD(bp, params->shmem_base + |
4747 | offsetof(struct shmem_region, dev_info. | |
4748 | port_feature_config[params->port].config)); | |
4749 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
4750 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { | |
4751 | DP(NETIF_MSG_LINK, "NOT enforcing module verification\n"); | |
4752 | return 0; | |
4753 | } | |
ea4e040a | 4754 | |
a22f0788 YR |
4755 | if (params->feature_config_flags & |
4756 | FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { | |
4757 | /* Use specific phy request */ | |
4758 | cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; | |
4759 | } else if (params->feature_config_flags & | |
4760 | FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { | |
4761 | /* Use first phy request only in case of non-dual media*/ | |
4762 | if (DUAL_MEDIA(params)) { | |
4763 | DP(NETIF_MSG_LINK, "FW does not support OPT MDL " | |
4764 | "verification\n"); | |
4765 | return -EINVAL; | |
4766 | } | |
4767 | cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; | |
4768 | } else { | |
4769 | /* No support in OPT MDL detection */ | |
de6eae1f | 4770 | DP(NETIF_MSG_LINK, "FW does not support OPT MDL " |
a22f0788 | 4771 | "verification\n"); |
de6eae1f YR |
4772 | return -EINVAL; |
4773 | } | |
523224a3 | 4774 | |
a22f0788 YR |
4775 | fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); |
4776 | fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); | |
de6eae1f YR |
4777 | if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { |
4778 | DP(NETIF_MSG_LINK, "Approved module\n"); | |
4779 | return 0; | |
4780 | } | |
b7737c9b | 4781 | |
de6eae1f YR |
4782 | /* format the warning message */ |
4783 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4784 | params, | |
cd88ccee YR |
4785 | SFP_EEPROM_VENDOR_NAME_ADDR, |
4786 | SFP_EEPROM_VENDOR_NAME_SIZE, | |
4787 | (u8 *)vendor_name)) | |
de6eae1f YR |
4788 | vendor_name[0] = '\0'; |
4789 | else | |
4790 | vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; | |
4791 | if (bnx2x_read_sfp_module_eeprom(phy, | |
4792 | params, | |
cd88ccee YR |
4793 | SFP_EEPROM_PART_NO_ADDR, |
4794 | SFP_EEPROM_PART_NO_SIZE, | |
4795 | (u8 *)vendor_pn)) | |
de6eae1f YR |
4796 | vendor_pn[0] = '\0'; |
4797 | else | |
4798 | vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; | |
4799 | ||
4800 | netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected," | |
4801 | " Port %d from %s part number %s\n", | |
4802 | params->port, vendor_name, vendor_pn); | |
a22f0788 | 4803 | phy->flags |= FLAGS_SFP_NOT_APPROVED; |
de6eae1f | 4804 | return -EINVAL; |
b7737c9b | 4805 | } |
7aa0711f | 4806 | |
de6eae1f YR |
4807 | static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy, |
4808 | struct link_params *params) | |
7aa0711f | 4809 | |
4d295db0 | 4810 | { |
de6eae1f | 4811 | u8 val; |
4d295db0 | 4812 | struct bnx2x *bp = params->bp; |
de6eae1f | 4813 | u16 timeout; |
2cf7acf9 YR |
4814 | /* |
4815 | * Initialization time after hot-plug may take up to 300ms for | |
4816 | * some phys type ( e.g. JDSU ) | |
4817 | */ | |
4818 | ||
de6eae1f YR |
4819 | for (timeout = 0; timeout < 60; timeout++) { |
4820 | if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val) | |
4821 | == 0) { | |
4822 | DP(NETIF_MSG_LINK, "SFP+ module initialization " | |
4823 | "took %d ms\n", timeout * 5); | |
4824 | return 0; | |
4825 | } | |
4826 | msleep(5); | |
4827 | } | |
4828 | return -EINVAL; | |
4829 | } | |
4d295db0 | 4830 | |
de6eae1f YR |
4831 | static void bnx2x_8727_power_module(struct bnx2x *bp, |
4832 | struct bnx2x_phy *phy, | |
4833 | u8 is_power_up) { | |
4834 | /* Make sure GPIOs are not using for LED mode */ | |
4835 | u16 val; | |
4836 | /* | |
2cf7acf9 | 4837 | * In the GPIO register, bit 4 is use to determine if the GPIOs are |
de6eae1f YR |
4838 | * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for |
4839 | * output | |
4840 | * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0 | |
4841 | * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1 | |
4842 | * where the 1st bit is the over-current(only input), and 2nd bit is | |
4843 | * for power( only output ) | |
2cf7acf9 | 4844 | * |
de6eae1f YR |
4845 | * In case of NOC feature is disabled and power is up, set GPIO control |
4846 | * as input to enable listening of over-current indication | |
4847 | */ | |
4848 | if (phy->flags & FLAGS_NOC) | |
4849 | return; | |
4850 | if (!(phy->flags & | |
4851 | FLAGS_NOC) && is_power_up) | |
4852 | val = (1<<4); | |
4853 | else | |
4854 | /* | |
4855 | * Set GPIO control to OUTPUT, and set the power bit | |
4856 | * to according to the is_power_up | |
4857 | */ | |
4858 | val = ((!(is_power_up)) << 1); | |
4d295db0 | 4859 | |
de6eae1f YR |
4860 | bnx2x_cl45_write(bp, phy, |
4861 | MDIO_PMA_DEVAD, | |
4862 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
4863 | val); | |
4864 | } | |
4d295db0 | 4865 | |
de6eae1f YR |
4866 | static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp, |
4867 | struct bnx2x_phy *phy, | |
4868 | u16 edc_mode) | |
4869 | { | |
4870 | u16 cur_limiting_mode; | |
4d295db0 | 4871 | |
de6eae1f | 4872 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
4873 | MDIO_PMA_DEVAD, |
4874 | MDIO_PMA_REG_ROM_VER2, | |
4875 | &cur_limiting_mode); | |
de6eae1f YR |
4876 | DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", |
4877 | cur_limiting_mode); | |
4878 | ||
4879 | if (edc_mode == EDC_MODE_LIMITING) { | |
cd88ccee | 4880 | DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n"); |
e10bc84d | 4881 | bnx2x_cl45_write(bp, phy, |
62b29a5d | 4882 | MDIO_PMA_DEVAD, |
de6eae1f YR |
4883 | MDIO_PMA_REG_ROM_VER2, |
4884 | EDC_MODE_LIMITING); | |
4885 | } else { /* LRM mode ( default )*/ | |
4d295db0 | 4886 | |
de6eae1f | 4887 | DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); |
4d295db0 | 4888 | |
2cf7acf9 YR |
4889 | /* |
4890 | * Changing to LRM mode takes quite few seconds. So do it only | |
4891 | * if current mode is limiting (default is LRM) | |
4892 | */ | |
de6eae1f YR |
4893 | if (cur_limiting_mode != EDC_MODE_LIMITING) |
4894 | return 0; | |
4d295db0 | 4895 | |
de6eae1f | 4896 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4897 | MDIO_PMA_DEVAD, |
4898 | MDIO_PMA_REG_LRM_MODE, | |
4899 | 0); | |
de6eae1f | 4900 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4901 | MDIO_PMA_DEVAD, |
4902 | MDIO_PMA_REG_ROM_VER2, | |
4903 | 0x128); | |
de6eae1f | 4904 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4905 | MDIO_PMA_DEVAD, |
4906 | MDIO_PMA_REG_MISC_CTRL0, | |
4907 | 0x4008); | |
de6eae1f | 4908 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4909 | MDIO_PMA_DEVAD, |
4910 | MDIO_PMA_REG_LRM_MODE, | |
4911 | 0xaaaa); | |
4d295db0 | 4912 | } |
de6eae1f | 4913 | return 0; |
4d295db0 EG |
4914 | } |
4915 | ||
de6eae1f YR |
4916 | static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp, |
4917 | struct bnx2x_phy *phy, | |
cd88ccee | 4918 | u16 edc_mode) |
ea4e040a | 4919 | { |
de6eae1f YR |
4920 | u16 phy_identifier; |
4921 | u16 rom_ver2_val; | |
62b29a5d | 4922 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
4923 | MDIO_PMA_DEVAD, |
4924 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4925 | &phy_identifier); | |
ea4e040a | 4926 | |
de6eae1f | 4927 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4928 | MDIO_PMA_DEVAD, |
4929 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4930 | (phy_identifier & ~(1<<9))); | |
ea4e040a | 4931 | |
62b29a5d | 4932 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
4933 | MDIO_PMA_DEVAD, |
4934 | MDIO_PMA_REG_ROM_VER2, | |
4935 | &rom_ver2_val); | |
de6eae1f YR |
4936 | /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ |
4937 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
4938 | MDIO_PMA_DEVAD, |
4939 | MDIO_PMA_REG_ROM_VER2, | |
4940 | (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); | |
4d295db0 | 4941 | |
de6eae1f | 4942 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
4943 | MDIO_PMA_DEVAD, |
4944 | MDIO_PMA_REG_PHY_IDENTIFIER, | |
4945 | (phy_identifier | (1<<9))); | |
4d295db0 | 4946 | |
de6eae1f | 4947 | return 0; |
b7737c9b | 4948 | } |
ea4e040a | 4949 | |
a22f0788 YR |
4950 | static void bnx2x_8727_specific_func(struct bnx2x_phy *phy, |
4951 | struct link_params *params, | |
4952 | u32 action) | |
4953 | { | |
4954 | struct bnx2x *bp = params->bp; | |
4955 | ||
4956 | switch (action) { | |
4957 | case DISABLE_TX: | |
4958 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
4959 | break; | |
4960 | case ENABLE_TX: | |
4961 | if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) | |
4962 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 1); | |
4963 | break; | |
4964 | default: | |
4965 | DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", | |
4966 | action); | |
4967 | return; | |
4968 | } | |
4969 | } | |
4970 | ||
de6eae1f YR |
4971 | static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
4972 | struct link_params *params) | |
b7737c9b | 4973 | { |
b7737c9b | 4974 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
4975 | u16 edc_mode; |
4976 | u8 rc = 0; | |
ea4e040a | 4977 | |
de6eae1f YR |
4978 | u32 val = REG_RD(bp, params->shmem_base + |
4979 | offsetof(struct shmem_region, dev_info. | |
4980 | port_feature_config[params->port].config)); | |
62b29a5d | 4981 | |
de6eae1f YR |
4982 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
4983 | params->port); | |
4984 | ||
4985 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { | |
4986 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | |
4987 | return -EINVAL; | |
cd88ccee | 4988 | } else if (bnx2x_verify_sfp_module(phy, params) != 0) { |
de6eae1f YR |
4989 | /* check SFP+ module compatibility */ |
4990 | DP(NETIF_MSG_LINK, "Module verification failed!!\n"); | |
4991 | rc = -EINVAL; | |
4992 | /* Turn on fault module-detected led */ | |
4993 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
4994 | MISC_REGISTERS_GPIO_HIGH, | |
4995 | params->port); | |
4996 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) && | |
4997 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | |
4998 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { | |
4999 | /* Shutdown SFP+ module */ | |
5000 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); | |
5001 | bnx2x_8727_power_module(bp, phy, 0); | |
5002 | return rc; | |
5003 | } | |
5004 | } else { | |
5005 | /* Turn off fault module-detected led */ | |
5006 | DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n"); | |
5007 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
5008 | MISC_REGISTERS_GPIO_LOW, | |
5009 | params->port); | |
62b29a5d | 5010 | } |
b7737c9b | 5011 | |
de6eae1f YR |
5012 | /* power up the SFP module */ |
5013 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) | |
5014 | bnx2x_8727_power_module(bp, phy, 1); | |
c18aa15d | 5015 | |
2cf7acf9 YR |
5016 | /* |
5017 | * Check and set limiting mode / LRM mode on 8726. On 8727 it | |
5018 | * is done automatically | |
5019 | */ | |
de6eae1f YR |
5020 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) |
5021 | bnx2x_8726_set_limiting_mode(bp, phy, edc_mode); | |
5022 | else | |
5023 | bnx2x_8727_set_limiting_mode(bp, phy, edc_mode); | |
5024 | /* | |
5025 | * Enable transmit for this module if the module is approved, or | |
5026 | * if unapproved modules should also enable the Tx laser | |
5027 | */ | |
5028 | if (rc == 0 || | |
5029 | (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != | |
5030 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
5031 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 1); | |
5032 | else | |
5033 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
b7737c9b | 5034 | |
de6eae1f YR |
5035 | return rc; |
5036 | } | |
5037 | ||
5038 | void bnx2x_handle_module_detect_int(struct link_params *params) | |
b7737c9b YR |
5039 | { |
5040 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5041 | struct bnx2x_phy *phy = ¶ms->phy[EXT_PHY1]; |
5042 | u32 gpio_val; | |
5043 | u8 port = params->port; | |
4d295db0 | 5044 | |
de6eae1f YR |
5045 | /* Set valid module led off */ |
5046 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
5047 | MISC_REGISTERS_GPIO_HIGH, | |
5048 | params->port); | |
4d295db0 | 5049 | |
2cf7acf9 | 5050 | /* Get current gpio val reflecting module plugged in / out*/ |
de6eae1f | 5051 | gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port); |
62b29a5d | 5052 | |
de6eae1f YR |
5053 | /* Call the handling function in case module is detected */ |
5054 | if (gpio_val == 0) { | |
4d295db0 | 5055 | |
de6eae1f YR |
5056 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, |
5057 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, | |
5058 | port); | |
4d295db0 | 5059 | |
de6eae1f YR |
5060 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) |
5061 | bnx2x_sfp_module_detection(phy, params); | |
5062 | else | |
5063 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
5064 | } else { | |
5065 | u32 val = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
5066 | offsetof(struct shmem_region, dev_info. |
5067 | port_feature_config[params->port]. | |
5068 | config)); | |
4d295db0 | 5069 | |
de6eae1f YR |
5070 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, |
5071 | MISC_REGISTERS_GPIO_INT_OUTPUT_SET, | |
5072 | port); | |
2cf7acf9 YR |
5073 | /* |
5074 | * Module was plugged out. | |
5075 | * Disable transmit for this module | |
5076 | */ | |
de6eae1f YR |
5077 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
5078 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
5079 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
62b29a5d | 5080 | } |
de6eae1f | 5081 | } |
62b29a5d | 5082 | |
de6eae1f YR |
5083 | /******************************************************************/ |
5084 | /* common BCM8706/BCM8726 PHY SECTION */ | |
5085 | /******************************************************************/ | |
5086 | static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, | |
5087 | struct link_params *params, | |
5088 | struct link_vars *vars) | |
5089 | { | |
5090 | u8 link_up = 0; | |
5091 | u16 val1, val2, rx_sd, pcs_status; | |
5092 | struct bnx2x *bp = params->bp; | |
5093 | DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); | |
5094 | /* Clear RX Alarm*/ | |
62b29a5d | 5095 | bnx2x_cl45_read(bp, phy, |
de6eae1f YR |
5096 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2); |
5097 | /* clear LASI indication*/ | |
5098 | bnx2x_cl45_read(bp, phy, | |
5099 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
5100 | bnx2x_cl45_read(bp, phy, | |
5101 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2); | |
5102 | DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); | |
62b29a5d YR |
5103 | |
5104 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
5105 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); |
5106 | bnx2x_cl45_read(bp, phy, | |
5107 | MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); | |
5108 | bnx2x_cl45_read(bp, phy, | |
5109 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
5110 | bnx2x_cl45_read(bp, phy, | |
5111 | MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); | |
62b29a5d | 5112 | |
de6eae1f YR |
5113 | DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" |
5114 | " link_status 0x%x\n", rx_sd, pcs_status, val2); | |
2cf7acf9 YR |
5115 | /* |
5116 | * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status | |
5117 | * are set, or if the autoneg bit 1 is set | |
de6eae1f YR |
5118 | */ |
5119 | link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); | |
5120 | if (link_up) { | |
5121 | if (val2 & (1<<1)) | |
5122 | vars->line_speed = SPEED_1000; | |
5123 | else | |
5124 | vars->line_speed = SPEED_10000; | |
62b29a5d | 5125 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 | 5126 | vars->duplex = DUPLEX_FULL; |
de6eae1f | 5127 | } |
62b29a5d | 5128 | return link_up; |
b7737c9b | 5129 | } |
62b29a5d | 5130 | |
de6eae1f YR |
5131 | /******************************************************************/ |
5132 | /* BCM8706 PHY SECTION */ | |
5133 | /******************************************************************/ | |
5134 | static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, | |
b7737c9b YR |
5135 | struct link_params *params, |
5136 | struct link_vars *vars) | |
5137 | { | |
de6eae1f | 5138 | u16 cnt, val; |
b7737c9b | 5139 | struct bnx2x *bp = params->bp; |
de6eae1f | 5140 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, |
cd88ccee | 5141 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
5142 | /* HW reset */ |
5143 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
5144 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); | |
5145 | bnx2x_wait_reset_complete(bp, phy); | |
ea4e040a | 5146 | |
de6eae1f YR |
5147 | /* Wait until fw is loaded */ |
5148 | for (cnt = 0; cnt < 100; cnt++) { | |
5149 | bnx2x_cl45_read(bp, phy, | |
5150 | MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); | |
5151 | if (val) | |
5152 | break; | |
5153 | msleep(10); | |
5154 | } | |
5155 | DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt); | |
5156 | if ((params->feature_config_flags & | |
5157 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
5158 | u8 i; | |
5159 | u16 reg; | |
5160 | for (i = 0; i < 4; i++) { | |
5161 | reg = MDIO_XS_8706_REG_BANK_RX0 + | |
5162 | i*(MDIO_XS_8706_REG_BANK_RX1 - | |
5163 | MDIO_XS_8706_REG_BANK_RX0); | |
5164 | bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); | |
5165 | /* Clear first 3 bits of the control */ | |
5166 | val &= ~0x7; | |
5167 | /* Set control bits according to configuration */ | |
5168 | val |= (phy->rx_preemphasis[i] & 0x7); | |
5169 | DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706" | |
5170 | " reg 0x%x <-- val 0x%x\n", reg, val); | |
5171 | bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); | |
5172 | } | |
5173 | } | |
5174 | /* Force speed */ | |
5175 | if (phy->req_line_speed == SPEED_10000) { | |
5176 | DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n"); | |
ea4e040a | 5177 | |
de6eae1f YR |
5178 | bnx2x_cl45_write(bp, phy, |
5179 | MDIO_PMA_DEVAD, | |
5180 | MDIO_PMA_REG_DIGITAL_CTRL, 0x400); | |
5181 | bnx2x_cl45_write(bp, phy, | |
5182 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); | |
5183 | } else { | |
5184 | /* Force 1Gbps using autoneg with 1G advertisment */ | |
6bbca910 | 5185 | |
de6eae1f YR |
5186 | /* Allow CL37 through CL73 */ |
5187 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | |
5188 | bnx2x_cl45_write(bp, phy, | |
5189 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
6bbca910 | 5190 | |
de6eae1f YR |
5191 | /* Enable Full-Duplex advertisment on CL37 */ |
5192 | bnx2x_cl45_write(bp, phy, | |
5193 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); | |
5194 | /* Enable CL37 AN */ | |
5195 | bnx2x_cl45_write(bp, phy, | |
5196 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
5197 | /* 1G support */ | |
5198 | bnx2x_cl45_write(bp, phy, | |
5199 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); | |
6bbca910 | 5200 | |
de6eae1f YR |
5201 | /* Enable clause 73 AN */ |
5202 | bnx2x_cl45_write(bp, phy, | |
5203 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
5204 | bnx2x_cl45_write(bp, phy, | |
5205 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5206 | 0x0400); | |
5207 | bnx2x_cl45_write(bp, phy, | |
5208 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, | |
5209 | 0x0004); | |
5210 | } | |
5211 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
5212 | return 0; | |
5213 | } | |
ea4e040a | 5214 | |
de6eae1f YR |
5215 | static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy, |
5216 | struct link_params *params, | |
5217 | struct link_vars *vars) | |
5218 | { | |
5219 | return bnx2x_8706_8726_read_status(phy, params, vars); | |
5220 | } | |
6bbca910 | 5221 | |
de6eae1f YR |
5222 | /******************************************************************/ |
5223 | /* BCM8726 PHY SECTION */ | |
5224 | /******************************************************************/ | |
5225 | static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy, | |
5226 | struct link_params *params) | |
5227 | { | |
5228 | struct bnx2x *bp = params->bp; | |
5229 | DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n"); | |
5230 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); | |
5231 | } | |
62b29a5d | 5232 | |
de6eae1f YR |
5233 | static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy, |
5234 | struct link_params *params) | |
5235 | { | |
5236 | struct bnx2x *bp = params->bp; | |
5237 | /* Need to wait 100ms after reset */ | |
5238 | msleep(100); | |
62b29a5d | 5239 | |
de6eae1f YR |
5240 | /* Micro controller re-boot */ |
5241 | bnx2x_cl45_write(bp, phy, | |
5242 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); | |
62b29a5d | 5243 | |
de6eae1f YR |
5244 | /* Set soft reset */ |
5245 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
5246 | MDIO_PMA_DEVAD, |
5247 | MDIO_PMA_REG_GEN_CTRL, | |
5248 | MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); | |
62b29a5d | 5249 | |
de6eae1f | 5250 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
5251 | MDIO_PMA_DEVAD, |
5252 | MDIO_PMA_REG_MISC_CTRL1, 0x0001); | |
6bbca910 | 5253 | |
de6eae1f | 5254 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
5255 | MDIO_PMA_DEVAD, |
5256 | MDIO_PMA_REG_GEN_CTRL, | |
5257 | MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); | |
de6eae1f YR |
5258 | |
5259 | /* wait for 150ms for microcode load */ | |
5260 | msleep(150); | |
5261 | ||
5262 | /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ | |
5263 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
5264 | MDIO_PMA_DEVAD, |
5265 | MDIO_PMA_REG_MISC_CTRL1, 0x0000); | |
de6eae1f YR |
5266 | |
5267 | msleep(200); | |
5268 | bnx2x_save_bcm_spirom_ver(bp, phy, params->port); | |
b7737c9b YR |
5269 | } |
5270 | ||
de6eae1f | 5271 | static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy, |
b7737c9b YR |
5272 | struct link_params *params, |
5273 | struct link_vars *vars) | |
5274 | { | |
5275 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5276 | u16 val1; |
5277 | u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars); | |
62b29a5d YR |
5278 | if (link_up) { |
5279 | bnx2x_cl45_read(bp, phy, | |
de6eae1f YR |
5280 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, |
5281 | &val1); | |
5282 | if (val1 & (1<<15)) { | |
5283 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
5284 | link_up = 0; | |
5285 | vars->line_speed = 0; | |
5286 | } | |
62b29a5d YR |
5287 | } |
5288 | return link_up; | |
b7737c9b YR |
5289 | } |
5290 | ||
de6eae1f YR |
5291 | |
5292 | static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy, | |
5293 | struct link_params *params, | |
5294 | struct link_vars *vars) | |
b7737c9b YR |
5295 | { |
5296 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5297 | u32 val; |
5298 | u32 swap_val, swap_override, aeu_gpio_mask, offset; | |
5299 | DP(NETIF_MSG_LINK, "Initializing BCM8726\n"); | |
5300 | /* Restore normal power mode*/ | |
5301 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
5302 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
b7737c9b | 5303 | |
de6eae1f YR |
5304 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, |
5305 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); | |
62b29a5d | 5306 | |
de6eae1f YR |
5307 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
5308 | bnx2x_wait_reset_complete(bp, phy); | |
62b29a5d | 5309 | |
de6eae1f | 5310 | bnx2x_8726_external_rom_boot(phy, params); |
62b29a5d | 5311 | |
2cf7acf9 YR |
5312 | /* |
5313 | * Need to call module detected on initialization since the module | |
5314 | * detection triggered by actual module insertion might occur before | |
5315 | * driver is loaded, and when driver is loaded, it reset all | |
5316 | * registers, including the transmitter | |
5317 | */ | |
de6eae1f | 5318 | bnx2x_sfp_module_detection(phy, params); |
62b29a5d | 5319 | |
de6eae1f YR |
5320 | if (phy->req_line_speed == SPEED_1000) { |
5321 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
5322 | bnx2x_cl45_write(bp, phy, | |
5323 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
5324 | bnx2x_cl45_write(bp, phy, | |
5325 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
5326 | bnx2x_cl45_write(bp, phy, | |
5327 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5); | |
5328 | bnx2x_cl45_write(bp, phy, | |
5329 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5330 | 0x400); | |
5331 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && | |
5332 | (phy->speed_cap_mask & | |
5333 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && | |
5334 | ((phy->speed_cap_mask & | |
5335 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
5336 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
5337 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
5338 | /* Set Flow control */ | |
5339 | bnx2x_ext_phy_set_pause(params, phy, vars); | |
5340 | bnx2x_cl45_write(bp, phy, | |
5341 | MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); | |
5342 | bnx2x_cl45_write(bp, phy, | |
5343 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); | |
5344 | bnx2x_cl45_write(bp, phy, | |
5345 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); | |
5346 | bnx2x_cl45_write(bp, phy, | |
5347 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); | |
5348 | bnx2x_cl45_write(bp, phy, | |
5349 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); | |
2cf7acf9 YR |
5350 | /* |
5351 | * Enable RX-ALARM control to receive interrupt for 1G speed | |
5352 | * change | |
5353 | */ | |
de6eae1f YR |
5354 | bnx2x_cl45_write(bp, phy, |
5355 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4); | |
5356 | bnx2x_cl45_write(bp, phy, | |
5357 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5358 | 0x400); | |
62b29a5d | 5359 | |
de6eae1f YR |
5360 | } else { /* Default 10G. Set only LASI control */ |
5361 | bnx2x_cl45_write(bp, phy, | |
5362 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1); | |
7aa0711f YR |
5363 | } |
5364 | ||
de6eae1f YR |
5365 | /* Set TX PreEmphasis if needed */ |
5366 | if ((params->feature_config_flags & | |
5367 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
5368 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," | |
5369 | "TX_CTRL2 0x%x\n", | |
5370 | phy->tx_preemphasis[0], | |
5371 | phy->tx_preemphasis[1]); | |
5372 | bnx2x_cl45_write(bp, phy, | |
5373 | MDIO_PMA_DEVAD, | |
5374 | MDIO_PMA_REG_8726_TX_CTRL1, | |
5375 | phy->tx_preemphasis[0]); | |
c18aa15d | 5376 | |
de6eae1f YR |
5377 | bnx2x_cl45_write(bp, phy, |
5378 | MDIO_PMA_DEVAD, | |
5379 | MDIO_PMA_REG_8726_TX_CTRL2, | |
5380 | phy->tx_preemphasis[1]); | |
5381 | } | |
ab6ad5a4 | 5382 | |
de6eae1f YR |
5383 | /* Set GPIO3 to trigger SFP+ module insertion/removal */ |
5384 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, | |
cd88ccee | 5385 | MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port); |
ea4e040a | 5386 | |
de6eae1f YR |
5387 | /* The GPIO should be swapped if the swap register is set and active */ |
5388 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
5389 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
ea4e040a | 5390 | |
de6eae1f YR |
5391 | /* Select function upon port-swap configuration */ |
5392 | if (params->port == 0) { | |
5393 | offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; | |
5394 | aeu_gpio_mask = (swap_val && swap_override) ? | |
5395 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 : | |
5396 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0; | |
5397 | } else { | |
5398 | offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; | |
5399 | aeu_gpio_mask = (swap_val && swap_override) ? | |
5400 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 : | |
5401 | AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1; | |
ea4e040a | 5402 | } |
de6eae1f YR |
5403 | val = REG_RD(bp, offset); |
5404 | /* add GPIO3 to group */ | |
5405 | val |= aeu_gpio_mask; | |
5406 | REG_WR(bp, offset, val); | |
5407 | return 0; | |
ab6ad5a4 | 5408 | |
ea4e040a YR |
5409 | } |
5410 | ||
de6eae1f YR |
5411 | static void bnx2x_8726_link_reset(struct bnx2x_phy *phy, |
5412 | struct link_params *params) | |
2f904460 | 5413 | { |
de6eae1f YR |
5414 | struct bnx2x *bp = params->bp; |
5415 | DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); | |
5416 | /* Set serial boot control for external load */ | |
5417 | bnx2x_cl45_write(bp, phy, | |
5418 | MDIO_PMA_DEVAD, | |
5419 | MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
5420 | } | |
5421 | ||
5422 | /******************************************************************/ | |
5423 | /* BCM8727 PHY SECTION */ | |
5424 | /******************************************************************/ | |
7f02c4ad YR |
5425 | |
5426 | static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy, | |
5427 | struct link_params *params, u8 mode) | |
5428 | { | |
5429 | struct bnx2x *bp = params->bp; | |
5430 | u16 led_mode_bitmask = 0; | |
5431 | u16 gpio_pins_bitmask = 0; | |
5432 | u16 val; | |
5433 | /* Only NOC flavor requires to set the LED specifically */ | |
5434 | if (!(phy->flags & FLAGS_NOC)) | |
5435 | return; | |
5436 | switch (mode) { | |
5437 | case LED_MODE_FRONT_PANEL_OFF: | |
5438 | case LED_MODE_OFF: | |
5439 | led_mode_bitmask = 0; | |
5440 | gpio_pins_bitmask = 0x03; | |
5441 | break; | |
5442 | case LED_MODE_ON: | |
5443 | led_mode_bitmask = 0; | |
5444 | gpio_pins_bitmask = 0x02; | |
5445 | break; | |
5446 | case LED_MODE_OPER: | |
5447 | led_mode_bitmask = 0x60; | |
5448 | gpio_pins_bitmask = 0x11; | |
5449 | break; | |
5450 | } | |
5451 | bnx2x_cl45_read(bp, phy, | |
5452 | MDIO_PMA_DEVAD, | |
5453 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
5454 | &val); | |
5455 | val &= 0xff8f; | |
5456 | val |= led_mode_bitmask; | |
5457 | bnx2x_cl45_write(bp, phy, | |
5458 | MDIO_PMA_DEVAD, | |
5459 | MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
5460 | val); | |
5461 | bnx2x_cl45_read(bp, phy, | |
5462 | MDIO_PMA_DEVAD, | |
5463 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
5464 | &val); | |
5465 | val &= 0xffe0; | |
5466 | val |= gpio_pins_bitmask; | |
5467 | bnx2x_cl45_write(bp, phy, | |
5468 | MDIO_PMA_DEVAD, | |
5469 | MDIO_PMA_REG_8727_GPIO_CTRL, | |
5470 | val); | |
5471 | } | |
de6eae1f YR |
5472 | static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy, |
5473 | struct link_params *params) { | |
5474 | u32 swap_val, swap_override; | |
5475 | u8 port; | |
2cf7acf9 | 5476 | /* |
de6eae1f YR |
5477 | * The PHY reset is controlled by GPIO 1. Fake the port number |
5478 | * to cancel the swap done in set_gpio() | |
2f904460 | 5479 | */ |
de6eae1f YR |
5480 | struct bnx2x *bp = params->bp; |
5481 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
5482 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
5483 | port = (swap_val && swap_override) ^ 1; | |
5484 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 5485 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
2f904460 | 5486 | } |
e10bc84d | 5487 | |
de6eae1f YR |
5488 | static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy, |
5489 | struct link_params *params, | |
5490 | struct link_vars *vars) | |
ea4e040a | 5491 | { |
de6eae1f YR |
5492 | u16 tmp1, val, mod_abs; |
5493 | u16 rx_alarm_ctrl_val; | |
5494 | u16 lasi_ctrl_val; | |
ea4e040a | 5495 | struct bnx2x *bp = params->bp; |
de6eae1f | 5496 | /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ |
ea4e040a | 5497 | |
de6eae1f YR |
5498 | bnx2x_wait_reset_complete(bp, phy); |
5499 | rx_alarm_ctrl_val = (1<<2) | (1<<5) ; | |
5500 | lasi_ctrl_val = 0x0004; | |
ea4e040a | 5501 | |
de6eae1f YR |
5502 | DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); |
5503 | /* enable LASI */ | |
5504 | bnx2x_cl45_write(bp, phy, | |
5505 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5506 | rx_alarm_ctrl_val); | |
ea4e040a | 5507 | |
de6eae1f YR |
5508 | bnx2x_cl45_write(bp, phy, |
5509 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val); | |
ea4e040a | 5510 | |
2cf7acf9 YR |
5511 | /* |
5512 | * Initially configure MOD_ABS to interrupt when module is | |
5513 | * presence( bit 8) | |
5514 | */ | |
de6eae1f YR |
5515 | bnx2x_cl45_read(bp, phy, |
5516 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
2cf7acf9 YR |
5517 | /* |
5518 | * Set EDC off by setting OPTXLOS signal input to low (bit 9). | |
5519 | * When the EDC is off it locks onto a reference clock and avoids | |
5520 | * becoming 'lost' | |
5521 | */ | |
7f02c4ad YR |
5522 | mod_abs &= ~(1<<8); |
5523 | if (!(phy->flags & FLAGS_NOC)) | |
5524 | mod_abs &= ~(1<<9); | |
de6eae1f YR |
5525 | bnx2x_cl45_write(bp, phy, |
5526 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 5527 | |
ea4e040a | 5528 | |
de6eae1f YR |
5529 | /* Make MOD_ABS give interrupt on change */ |
5530 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, | |
5531 | &val); | |
5532 | val |= (1<<12); | |
7f02c4ad YR |
5533 | if (phy->flags & FLAGS_NOC) |
5534 | val |= (3<<5); | |
b7737c9b | 5535 | |
2cf7acf9 | 5536 | /* |
7f02c4ad YR |
5537 | * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 |
5538 | * status which reflect SFP+ module over-current | |
5539 | */ | |
5540 | if (!(phy->flags & FLAGS_NOC)) | |
5541 | val &= 0xff8f; /* Reset bits 4-6 */ | |
de6eae1f YR |
5542 | bnx2x_cl45_write(bp, phy, |
5543 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val); | |
ea4e040a | 5544 | |
de6eae1f YR |
5545 | bnx2x_8727_power_module(bp, phy, 1); |
5546 | ||
5547 | bnx2x_cl45_read(bp, phy, | |
5548 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); | |
5549 | ||
5550 | bnx2x_cl45_read(bp, phy, | |
5551 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1); | |
5552 | ||
5553 | /* Set option 1G speed */ | |
5554 | if (phy->req_line_speed == SPEED_1000) { | |
5555 | DP(NETIF_MSG_LINK, "Setting 1G force\n"); | |
5556 | bnx2x_cl45_write(bp, phy, | |
5557 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); | |
5558 | bnx2x_cl45_write(bp, phy, | |
5559 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); | |
5560 | bnx2x_cl45_read(bp, phy, | |
5561 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); | |
5562 | DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); | |
2cf7acf9 | 5563 | /* |
a22f0788 YR |
5564 | * Power down the XAUI until link is up in case of dual-media |
5565 | * and 1G | |
5566 | */ | |
5567 | if (DUAL_MEDIA(params)) { | |
5568 | bnx2x_cl45_read(bp, phy, | |
5569 | MDIO_PMA_DEVAD, | |
5570 | MDIO_PMA_REG_8727_PCS_GP, &val); | |
5571 | val |= (3<<10); | |
5572 | bnx2x_cl45_write(bp, phy, | |
5573 | MDIO_PMA_DEVAD, | |
5574 | MDIO_PMA_REG_8727_PCS_GP, val); | |
5575 | } | |
de6eae1f YR |
5576 | } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && |
5577 | ((phy->speed_cap_mask & | |
5578 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && | |
5579 | ((phy->speed_cap_mask & | |
5580 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != | |
5581 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { | |
5582 | ||
5583 | DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); | |
5584 | bnx2x_cl45_write(bp, phy, | |
5585 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); | |
5586 | bnx2x_cl45_write(bp, phy, | |
5587 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); | |
5588 | } else { | |
2cf7acf9 | 5589 | /* |
de6eae1f YR |
5590 | * Since the 8727 has only single reset pin, need to set the 10G |
5591 | * registers although it is default | |
5592 | */ | |
5593 | bnx2x_cl45_write(bp, phy, | |
5594 | MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, | |
5595 | 0x0020); | |
5596 | bnx2x_cl45_write(bp, phy, | |
5597 | MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); | |
5598 | bnx2x_cl45_write(bp, phy, | |
5599 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); | |
5600 | bnx2x_cl45_write(bp, phy, | |
5601 | MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, | |
5602 | 0x0008); | |
ea4e040a | 5603 | } |
ea4e040a | 5604 | |
2cf7acf9 YR |
5605 | /* |
5606 | * Set 2-wire transfer rate of SFP+ module EEPROM | |
de6eae1f YR |
5607 | * to 100Khz since some DACs(direct attached cables) do |
5608 | * not work at 400Khz. | |
5609 | */ | |
5610 | bnx2x_cl45_write(bp, phy, | |
5611 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, | |
5612 | 0xa001); | |
b7737c9b | 5613 | |
de6eae1f YR |
5614 | /* Set TX PreEmphasis if needed */ |
5615 | if ((params->feature_config_flags & | |
5616 | FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { | |
5617 | DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", | |
5618 | phy->tx_preemphasis[0], | |
5619 | phy->tx_preemphasis[1]); | |
5620 | bnx2x_cl45_write(bp, phy, | |
5621 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, | |
5622 | phy->tx_preemphasis[0]); | |
ea4e040a | 5623 | |
de6eae1f YR |
5624 | bnx2x_cl45_write(bp, phy, |
5625 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, | |
5626 | phy->tx_preemphasis[1]); | |
5627 | } | |
ea4e040a | 5628 | |
de6eae1f | 5629 | return 0; |
ea4e040a YR |
5630 | } |
5631 | ||
de6eae1f YR |
5632 | static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy, |
5633 | struct link_params *params) | |
ea4e040a | 5634 | { |
ea4e040a | 5635 | struct bnx2x *bp = params->bp; |
de6eae1f YR |
5636 | u16 mod_abs, rx_alarm_status; |
5637 | u32 val = REG_RD(bp, params->shmem_base + | |
5638 | offsetof(struct shmem_region, dev_info. | |
5639 | port_feature_config[params->port]. | |
5640 | config)); | |
5641 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
5642 | MDIO_PMA_DEVAD, |
5643 | MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); | |
de6eae1f | 5644 | if (mod_abs & (1<<8)) { |
ea4e040a | 5645 | |
de6eae1f YR |
5646 | /* Module is absent */ |
5647 | DP(NETIF_MSG_LINK, "MOD_ABS indication " | |
5648 | "show module is absent\n"); | |
ea4e040a | 5649 | |
2cf7acf9 YR |
5650 | /* |
5651 | * 1. Set mod_abs to detect next module | |
5652 | * presence event | |
5653 | * 2. Set EDC off by setting OPTXLOS signal input to low | |
5654 | * (bit 9). | |
5655 | * When the EDC is off it locks onto a reference clock and | |
5656 | * avoids becoming 'lost'. | |
5657 | */ | |
7f02c4ad YR |
5658 | mod_abs &= ~(1<<8); |
5659 | if (!(phy->flags & FLAGS_NOC)) | |
5660 | mod_abs &= ~(1<<9); | |
de6eae1f | 5661 | bnx2x_cl45_write(bp, phy, |
cd88ccee YR |
5662 | MDIO_PMA_DEVAD, |
5663 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 5664 | |
2cf7acf9 YR |
5665 | /* |
5666 | * Clear RX alarm since it stays up as long as | |
5667 | * the mod_abs wasn't changed | |
5668 | */ | |
de6eae1f | 5669 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
5670 | MDIO_PMA_DEVAD, |
5671 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
ea4e040a | 5672 | |
de6eae1f YR |
5673 | } else { |
5674 | /* Module is present */ | |
5675 | DP(NETIF_MSG_LINK, "MOD_ABS indication " | |
5676 | "show module is present\n"); | |
2cf7acf9 YR |
5677 | /* |
5678 | * First disable transmitter, and if the module is ok, the | |
5679 | * module_detection will enable it | |
5680 | * 1. Set mod_abs to detect next module absent event ( bit 8) | |
5681 | * 2. Restore the default polarity of the OPRXLOS signal and | |
5682 | * this signal will then correctly indicate the presence or | |
5683 | * absence of the Rx signal. (bit 9) | |
5684 | */ | |
7f02c4ad YR |
5685 | mod_abs |= (1<<8); |
5686 | if (!(phy->flags & FLAGS_NOC)) | |
5687 | mod_abs |= (1<<9); | |
e10bc84d | 5688 | bnx2x_cl45_write(bp, phy, |
de6eae1f YR |
5689 | MDIO_PMA_DEVAD, |
5690 | MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); | |
ea4e040a | 5691 | |
2cf7acf9 YR |
5692 | /* |
5693 | * Clear RX alarm since it stays up as long as the mod_abs | |
5694 | * wasn't changed. This is need to be done before calling the | |
5695 | * module detection, otherwise it will clear* the link update | |
5696 | * alarm | |
5697 | */ | |
de6eae1f YR |
5698 | bnx2x_cl45_read(bp, phy, |
5699 | MDIO_PMA_DEVAD, | |
5700 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
ea4e040a | 5701 | |
ea4e040a | 5702 | |
de6eae1f YR |
5703 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
5704 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) | |
5705 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
5706 | ||
5707 | if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) | |
5708 | bnx2x_sfp_module_detection(phy, params); | |
5709 | else | |
5710 | DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n"); | |
ea4e040a | 5711 | } |
de6eae1f YR |
5712 | |
5713 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", | |
2cf7acf9 YR |
5714 | rx_alarm_status); |
5715 | /* No need to check link status in case of module plugged in/out */ | |
ea4e040a YR |
5716 | } |
5717 | ||
de6eae1f YR |
5718 | static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy, |
5719 | struct link_params *params, | |
5720 | struct link_vars *vars) | |
5721 | ||
ea4e040a YR |
5722 | { |
5723 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5724 | u8 link_up = 0; |
5725 | u16 link_status = 0; | |
a22f0788 YR |
5726 | u16 rx_alarm_status, lasi_ctrl, val1; |
5727 | ||
5728 | /* If PHY is not initialized, do not check link status */ | |
5729 | bnx2x_cl45_read(bp, phy, | |
5730 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, | |
5731 | &lasi_ctrl); | |
5732 | if (!lasi_ctrl) | |
5733 | return 0; | |
5734 | ||
de6eae1f YR |
5735 | /* Check the LASI */ |
5736 | bnx2x_cl45_read(bp, phy, | |
5737 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, | |
5738 | &rx_alarm_status); | |
5739 | vars->line_speed = 0; | |
5740 | DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); | |
5741 | ||
5742 | bnx2x_cl45_read(bp, phy, | |
5743 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
5744 | ||
5745 | DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); | |
5746 | ||
5747 | /* Clear MSG-OUT */ | |
5748 | bnx2x_cl45_read(bp, phy, | |
5749 | MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); | |
5750 | ||
2cf7acf9 | 5751 | /* |
de6eae1f YR |
5752 | * If a module is present and there is need to check |
5753 | * for over current | |
5754 | */ | |
5755 | if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { | |
5756 | /* Check over-current using 8727 GPIO0 input*/ | |
5757 | bnx2x_cl45_read(bp, phy, | |
5758 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, | |
5759 | &val1); | |
5760 | ||
5761 | if ((val1 & (1<<8)) == 0) { | |
5762 | DP(NETIF_MSG_LINK, "8727 Power fault has been detected" | |
5763 | " on port %d\n", params->port); | |
5764 | netdev_err(bp->dev, "Error: Power fault on Port %d has" | |
5765 | " been detected and the power to " | |
5766 | "that SFP+ module has been removed" | |
5767 | " to prevent failure of the card." | |
5768 | " Please remove the SFP+ module and" | |
5769 | " restart the system to clear this" | |
5770 | " error.\n", | |
2cf7acf9 YR |
5771 | params->port); |
5772 | /* Disable all RX_ALARMs except for mod_abs */ | |
de6eae1f YR |
5773 | bnx2x_cl45_write(bp, phy, |
5774 | MDIO_PMA_DEVAD, | |
5775 | MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5)); | |
5776 | ||
5777 | bnx2x_cl45_read(bp, phy, | |
5778 | MDIO_PMA_DEVAD, | |
5779 | MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
5780 | /* Wait for module_absent_event */ | |
5781 | val1 |= (1<<8); | |
5782 | bnx2x_cl45_write(bp, phy, | |
5783 | MDIO_PMA_DEVAD, | |
5784 | MDIO_PMA_REG_PHY_IDENTIFIER, val1); | |
5785 | /* Clear RX alarm */ | |
5786 | bnx2x_cl45_read(bp, phy, | |
5787 | MDIO_PMA_DEVAD, | |
5788 | MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); | |
5789 | return 0; | |
5790 | } | |
5791 | } /* Over current check */ | |
5792 | ||
5793 | /* When module absent bit is set, check module */ | |
5794 | if (rx_alarm_status & (1<<5)) { | |
5795 | bnx2x_8727_handle_mod_abs(phy, params); | |
5796 | /* Enable all mod_abs and link detection bits */ | |
5797 | bnx2x_cl45_write(bp, phy, | |
5798 | MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, | |
5799 | ((1<<5) | (1<<2))); | |
5800 | } | |
a22f0788 YR |
5801 | DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n"); |
5802 | bnx2x_8727_specific_func(phy, params, ENABLE_TX); | |
de6eae1f YR |
5803 | /* If transmitter is disabled, ignore false link up indication */ |
5804 | bnx2x_cl45_read(bp, phy, | |
5805 | MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1); | |
5806 | if (val1 & (1<<15)) { | |
5807 | DP(NETIF_MSG_LINK, "Tx is disabled\n"); | |
5808 | return 0; | |
5809 | } | |
5810 | ||
5811 | bnx2x_cl45_read(bp, phy, | |
5812 | MDIO_PMA_DEVAD, | |
5813 | MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); | |
5814 | ||
2cf7acf9 YR |
5815 | /* |
5816 | * Bits 0..2 --> speed detected, | |
5817 | * Bits 13..15--> link is down | |
5818 | */ | |
de6eae1f YR |
5819 | if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { |
5820 | link_up = 1; | |
5821 | vars->line_speed = SPEED_10000; | |
2cf7acf9 YR |
5822 | DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", |
5823 | params->port); | |
de6eae1f YR |
5824 | } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { |
5825 | link_up = 1; | |
5826 | vars->line_speed = SPEED_1000; | |
5827 | DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n", | |
5828 | params->port); | |
5829 | } else { | |
5830 | link_up = 0; | |
5831 | DP(NETIF_MSG_LINK, "port %x: External link is down\n", | |
5832 | params->port); | |
5833 | } | |
791f18c0 | 5834 | if (link_up) { |
de6eae1f | 5835 | bnx2x_ext_phy_resolve_fc(phy, params, vars); |
791f18c0 YR |
5836 | vars->duplex = DUPLEX_FULL; |
5837 | DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); | |
5838 | } | |
a22f0788 YR |
5839 | |
5840 | if ((DUAL_MEDIA(params)) && | |
5841 | (phy->req_line_speed == SPEED_1000)) { | |
5842 | bnx2x_cl45_read(bp, phy, | |
5843 | MDIO_PMA_DEVAD, | |
5844 | MDIO_PMA_REG_8727_PCS_GP, &val1); | |
2cf7acf9 | 5845 | /* |
a22f0788 YR |
5846 | * In case of dual-media board and 1G, power up the XAUI side, |
5847 | * otherwise power it down. For 10G it is done automatically | |
5848 | */ | |
5849 | if (link_up) | |
5850 | val1 &= ~(3<<10); | |
5851 | else | |
5852 | val1 |= (3<<10); | |
5853 | bnx2x_cl45_write(bp, phy, | |
5854 | MDIO_PMA_DEVAD, | |
5855 | MDIO_PMA_REG_8727_PCS_GP, val1); | |
5856 | } | |
de6eae1f | 5857 | return link_up; |
b7737c9b | 5858 | } |
ea4e040a | 5859 | |
de6eae1f YR |
5860 | static void bnx2x_8727_link_reset(struct bnx2x_phy *phy, |
5861 | struct link_params *params) | |
b7737c9b YR |
5862 | { |
5863 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
5864 | /* Disable Transmitter */ |
5865 | bnx2x_sfp_set_transmitter(bp, phy, params->port, 0); | |
a22f0788 YR |
5866 | /* Clear LASI */ |
5867 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0); | |
5868 | ||
ea4e040a | 5869 | } |
c18aa15d | 5870 | |
de6eae1f YR |
5871 | /******************************************************************/ |
5872 | /* BCM8481/BCM84823/BCM84833 PHY SECTION */ | |
5873 | /******************************************************************/ | |
5874 | static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy, | |
5875 | struct link_params *params) | |
ea4e040a | 5876 | { |
de6eae1f YR |
5877 | u16 val, fw_ver1, fw_ver2, cnt; |
5878 | struct bnx2x *bp = params->bp; | |
ea4e040a | 5879 | |
de6eae1f YR |
5880 | /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/ |
5881 | /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ | |
5882 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014); | |
5883 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
5884 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000); | |
5885 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300); | |
5886 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009); | |
ea4e040a | 5887 | |
de6eae1f YR |
5888 | for (cnt = 0; cnt < 100; cnt++) { |
5889 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
5890 | if (val & 1) | |
5891 | break; | |
5892 | udelay(5); | |
5893 | } | |
5894 | if (cnt == 100) { | |
5895 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n"); | |
5896 | bnx2x_save_spirom_version(bp, params->port, 0, | |
5897 | phy->ver_addr); | |
5898 | return; | |
5899 | } | |
ea4e040a | 5900 | |
ea4e040a | 5901 | |
de6eae1f YR |
5902 | /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ |
5903 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); | |
5904 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); | |
5905 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); | |
5906 | for (cnt = 0; cnt < 100; cnt++) { | |
5907 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); | |
5908 | if (val & 1) | |
5909 | break; | |
5910 | udelay(5); | |
5911 | } | |
5912 | if (cnt == 100) { | |
5913 | DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n"); | |
5914 | bnx2x_save_spirom_version(bp, params->port, 0, | |
5915 | phy->ver_addr); | |
5916 | return; | |
ea4e040a YR |
5917 | } |
5918 | ||
de6eae1f YR |
5919 | /* lower 16 bits of the register SPI_FW_STATUS */ |
5920 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); | |
5921 | /* upper 16 bits of register SPI_FW_STATUS */ | |
5922 | bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); | |
ea4e040a | 5923 | |
de6eae1f YR |
5924 | bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1, |
5925 | phy->ver_addr); | |
5926 | } | |
ea4e040a | 5927 | |
de6eae1f YR |
5928 | static void bnx2x_848xx_set_led(struct bnx2x *bp, |
5929 | struct bnx2x_phy *phy) | |
ea4e040a | 5930 | { |
de6eae1f | 5931 | u16 val; |
7846e471 | 5932 | |
de6eae1f YR |
5933 | /* PHYC_CTL_LED_CTL */ |
5934 | bnx2x_cl45_read(bp, phy, | |
5935 | MDIO_PMA_DEVAD, | |
5936 | MDIO_PMA_REG_8481_LINK_SIGNAL, &val); | |
5937 | val &= 0xFE00; | |
5938 | val |= 0x0092; | |
345b5d52 | 5939 | |
de6eae1f YR |
5940 | bnx2x_cl45_write(bp, phy, |
5941 | MDIO_PMA_DEVAD, | |
5942 | MDIO_PMA_REG_8481_LINK_SIGNAL, val); | |
ea4e040a | 5943 | |
de6eae1f YR |
5944 | bnx2x_cl45_write(bp, phy, |
5945 | MDIO_PMA_DEVAD, | |
5946 | MDIO_PMA_REG_8481_LED1_MASK, | |
5947 | 0x80); | |
ea4e040a | 5948 | |
de6eae1f YR |
5949 | bnx2x_cl45_write(bp, phy, |
5950 | MDIO_PMA_DEVAD, | |
5951 | MDIO_PMA_REG_8481_LED2_MASK, | |
5952 | 0x18); | |
ea4e040a | 5953 | |
f25b3c8b | 5954 | /* Select activity source by Tx and Rx, as suggested by PHY AE */ |
de6eae1f YR |
5955 | bnx2x_cl45_write(bp, phy, |
5956 | MDIO_PMA_DEVAD, | |
5957 | MDIO_PMA_REG_8481_LED3_MASK, | |
f25b3c8b YR |
5958 | 0x0006); |
5959 | ||
5960 | /* Select the closest activity blink rate to that in 10/100/1000 */ | |
5961 | bnx2x_cl45_write(bp, phy, | |
5962 | MDIO_PMA_DEVAD, | |
5963 | MDIO_PMA_REG_8481_LED3_BLINK, | |
5964 | 0); | |
5965 | ||
5966 | bnx2x_cl45_read(bp, phy, | |
5967 | MDIO_PMA_DEVAD, | |
5968 | MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val); | |
5969 | val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/ | |
5970 | ||
5971 | bnx2x_cl45_write(bp, phy, | |
5972 | MDIO_PMA_DEVAD, | |
5973 | MDIO_PMA_REG_84823_CTL_LED_CTL_1, val); | |
ea4e040a | 5974 | |
de6eae1f YR |
5975 | /* 'Interrupt Mask' */ |
5976 | bnx2x_cl45_write(bp, phy, | |
5977 | MDIO_AN_DEVAD, | |
5978 | 0xFFFB, 0xFFFD); | |
ea4e040a YR |
5979 | } |
5980 | ||
de6eae1f | 5981 | static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, |
a22f0788 YR |
5982 | struct link_params *params, |
5983 | struct link_vars *vars) | |
ea4e040a | 5984 | { |
c18aa15d | 5985 | struct bnx2x *bp = params->bp; |
de6eae1f | 5986 | u16 autoneg_val, an_1000_val, an_10_100_val; |
2cf7acf9 YR |
5987 | /* |
5988 | * This phy uses the NIG latch mechanism since link indication | |
5989 | * arrives through its LED4 and not via its LASI signal, so we | |
5990 | * get steady signal instead of clear on read | |
5991 | */ | |
de6eae1f YR |
5992 | bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, |
5993 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
ea4e040a | 5994 | |
de6eae1f YR |
5995 | bnx2x_cl45_write(bp, phy, |
5996 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); | |
ea4e040a | 5997 | |
de6eae1f | 5998 | bnx2x_848xx_set_led(bp, phy); |
ea4e040a | 5999 | |
de6eae1f YR |
6000 | /* set 1000 speed advertisement */ |
6001 | bnx2x_cl45_read(bp, phy, | |
6002 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
6003 | &an_1000_val); | |
57963ed9 | 6004 | |
de6eae1f YR |
6005 | bnx2x_ext_phy_set_pause(params, phy, vars); |
6006 | bnx2x_cl45_read(bp, phy, | |
6007 | MDIO_AN_DEVAD, | |
6008 | MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
6009 | &an_10_100_val); | |
6010 | bnx2x_cl45_read(bp, phy, | |
6011 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, | |
6012 | &autoneg_val); | |
6013 | /* Disable forced speed */ | |
6014 | autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); | |
6015 | an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); | |
ea4e040a | 6016 | |
de6eae1f YR |
6017 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
6018 | (phy->speed_cap_mask & | |
6019 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || | |
6020 | (phy->req_line_speed == SPEED_1000)) { | |
6021 | an_1000_val |= (1<<8); | |
6022 | autoneg_val |= (1<<9 | 1<<12); | |
6023 | if (phy->req_duplex == DUPLEX_FULL) | |
6024 | an_1000_val |= (1<<9); | |
6025 | DP(NETIF_MSG_LINK, "Advertising 1G\n"); | |
6026 | } else | |
6027 | an_1000_val &= ~((1<<8) | (1<<9)); | |
ea4e040a | 6028 | |
de6eae1f YR |
6029 | bnx2x_cl45_write(bp, phy, |
6030 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, | |
6031 | an_1000_val); | |
ea4e040a | 6032 | |
de6eae1f YR |
6033 | /* set 10 speed advertisement */ |
6034 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
6035 | (phy->speed_cap_mask & | |
6036 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL | | |
6037 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) { | |
6038 | an_10_100_val |= (1<<7); | |
6039 | /* Enable autoneg and restart autoneg for legacy speeds */ | |
6040 | autoneg_val |= (1<<9 | 1<<12); | |
b7737c9b | 6041 | |
de6eae1f YR |
6042 | if (phy->req_duplex == DUPLEX_FULL) |
6043 | an_10_100_val |= (1<<8); | |
6044 | DP(NETIF_MSG_LINK, "Advertising 100M\n"); | |
6045 | } | |
6046 | /* set 10 speed advertisement */ | |
6047 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && | |
6048 | (phy->speed_cap_mask & | |
6049 | (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL | | |
6050 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) { | |
6051 | an_10_100_val |= (1<<5); | |
6052 | autoneg_val |= (1<<9 | 1<<12); | |
6053 | if (phy->req_duplex == DUPLEX_FULL) | |
6054 | an_10_100_val |= (1<<6); | |
6055 | DP(NETIF_MSG_LINK, "Advertising 10M\n"); | |
6056 | } | |
b7737c9b | 6057 | |
de6eae1f YR |
6058 | /* Only 10/100 are allowed to work in FORCE mode */ |
6059 | if (phy->req_line_speed == SPEED_100) { | |
6060 | autoneg_val |= (1<<13); | |
6061 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
6062 | bnx2x_cl45_write(bp, phy, | |
6063 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
6064 | (1<<15 | 1<<9 | 7<<0)); | |
6065 | DP(NETIF_MSG_LINK, "Setting 100M force\n"); | |
6066 | } | |
6067 | if (phy->req_line_speed == SPEED_10) { | |
6068 | /* Enabled AUTO-MDIX when autoneg is disabled */ | |
6069 | bnx2x_cl45_write(bp, phy, | |
6070 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, | |
6071 | (1<<15 | 1<<9 | 7<<0)); | |
6072 | DP(NETIF_MSG_LINK, "Setting 10M force\n"); | |
6073 | } | |
b7737c9b | 6074 | |
de6eae1f YR |
6075 | bnx2x_cl45_write(bp, phy, |
6076 | MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, | |
6077 | an_10_100_val); | |
b7737c9b | 6078 | |
de6eae1f YR |
6079 | if (phy->req_duplex == DUPLEX_FULL) |
6080 | autoneg_val |= (1<<8); | |
b7737c9b | 6081 | |
de6eae1f YR |
6082 | bnx2x_cl45_write(bp, phy, |
6083 | MDIO_AN_DEVAD, | |
6084 | MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); | |
b7737c9b | 6085 | |
de6eae1f YR |
6086 | if (((phy->req_line_speed == SPEED_AUTO_NEG) && |
6087 | (phy->speed_cap_mask & | |
6088 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || | |
6089 | (phy->req_line_speed == SPEED_10000)) { | |
6090 | DP(NETIF_MSG_LINK, "Advertising 10G\n"); | |
6091 | /* Restart autoneg for 10G*/ | |
6092 | ||
6093 | bnx2x_cl45_write(bp, phy, | |
6094 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, | |
6095 | 0x3200); | |
6096 | } else if (phy->req_line_speed != SPEED_10 && | |
6097 | phy->req_line_speed != SPEED_100) { | |
6098 | bnx2x_cl45_write(bp, phy, | |
6099 | MDIO_AN_DEVAD, | |
6100 | MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, | |
6101 | 1); | |
b7737c9b | 6102 | } |
de6eae1f YR |
6103 | /* Save spirom version */ |
6104 | bnx2x_save_848xx_spirom_version(phy, params); | |
6105 | ||
6106 | return 0; | |
b7737c9b YR |
6107 | } |
6108 | ||
de6eae1f YR |
6109 | static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy, |
6110 | struct link_params *params, | |
6111 | struct link_vars *vars) | |
ea4e040a YR |
6112 | { |
6113 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
6114 | /* Restore normal power mode*/ |
6115 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 6116 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
b7737c9b | 6117 | |
de6eae1f YR |
6118 | /* HW reset */ |
6119 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
9bffeac1 | 6120 | bnx2x_wait_reset_complete(bp, phy); |
ab6ad5a4 | 6121 | |
de6eae1f YR |
6122 | bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
6123 | return bnx2x_848xx_cmn_config_init(phy, params, vars); | |
6124 | } | |
ea4e040a | 6125 | |
de6eae1f YR |
6126 | static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, |
6127 | struct link_params *params, | |
6128 | struct link_vars *vars) | |
6129 | { | |
6130 | struct bnx2x *bp = params->bp; | |
6a71bbe0 | 6131 | u8 port, initialize = 1; |
a22f0788 | 6132 | u16 val; |
de6eae1f | 6133 | u16 temp; |
a22f0788 YR |
6134 | u32 actual_phy_selection; |
6135 | u8 rc = 0; | |
7f02c4ad YR |
6136 | |
6137 | /* This is just for MDIO_CTL_REG_84823_MEDIA register. */ | |
6138 | ||
de6eae1f | 6139 | msleep(1); |
6a71bbe0 YR |
6140 | if (CHIP_IS_E2(bp)) |
6141 | port = BP_PATH(bp); | |
6142 | else | |
6143 | port = params->port; | |
de6eae1f YR |
6144 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, |
6145 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, | |
7f02c4ad | 6146 | port); |
9bffeac1 YR |
6147 | bnx2x_wait_reset_complete(bp, phy); |
6148 | /* Wait for GPHY to come out of reset */ | |
6149 | msleep(50); | |
2cf7acf9 YR |
6150 | /* |
6151 | * BCM84823 requires that XGXS links up first @ 10G for normal behavior | |
6152 | */ | |
de6eae1f YR |
6153 | temp = vars->line_speed; |
6154 | vars->line_speed = SPEED_10000; | |
a22f0788 YR |
6155 | bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); |
6156 | bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); | |
de6eae1f | 6157 | vars->line_speed = temp; |
a22f0788 YR |
6158 | |
6159 | /* Set dual-media configuration according to configuration */ | |
6160 | ||
6161 | bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, | |
6162 | MDIO_CTL_REG_84823_MEDIA, &val); | |
6163 | val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | | |
6164 | MDIO_CTL_REG_84823_MEDIA_LINE_MASK | | |
6165 | MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | | |
6166 | MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | | |
6167 | MDIO_CTL_REG_84823_MEDIA_FIBER_1G); | |
6168 | val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI | | |
6169 | MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L; | |
6170 | ||
6171 | actual_phy_selection = bnx2x_phy_selection(params); | |
6172 | ||
6173 | switch (actual_phy_selection) { | |
6174 | case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: | |
6175 | /* Do nothing. Essentialy this is like the priority copper */ | |
6176 | break; | |
6177 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
6178 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; | |
6179 | break; | |
6180 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
6181 | val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; | |
6182 | break; | |
6183 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
6184 | /* Do nothing here. The first PHY won't be initialized at all */ | |
6185 | break; | |
6186 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
6187 | val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; | |
6188 | initialize = 0; | |
6189 | break; | |
6190 | } | |
6191 | if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) | |
6192 | val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; | |
6193 | ||
6194 | bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, | |
6195 | MDIO_CTL_REG_84823_MEDIA, val); | |
6196 | DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", | |
6197 | params->multi_phy_config, val); | |
6198 | ||
6199 | if (initialize) | |
6200 | rc = bnx2x_848xx_cmn_config_init(phy, params, vars); | |
6201 | else | |
6202 | bnx2x_save_848xx_spirom_version(phy, params); | |
6203 | return rc; | |
de6eae1f | 6204 | } |
ea4e040a | 6205 | |
de6eae1f | 6206 | static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, |
cd88ccee YR |
6207 | struct link_params *params, |
6208 | struct link_vars *vars) | |
de6eae1f YR |
6209 | { |
6210 | struct bnx2x *bp = params->bp; | |
6211 | u16 val, val1, val2; | |
6212 | u8 link_up = 0; | |
ea4e040a | 6213 | |
de6eae1f YR |
6214 | /* Check 10G-BaseT link status */ |
6215 | /* Check PMD signal ok */ | |
6216 | bnx2x_cl45_read(bp, phy, | |
6217 | MDIO_AN_DEVAD, 0xFFFA, &val1); | |
6218 | bnx2x_cl45_read(bp, phy, | |
6219 | MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, | |
6220 | &val2); | |
6221 | DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); | |
ea4e040a | 6222 | |
de6eae1f YR |
6223 | /* Check link 10G */ |
6224 | if (val2 & (1<<11)) { | |
ea4e040a | 6225 | vars->line_speed = SPEED_10000; |
791f18c0 | 6226 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
6227 | link_up = 1; |
6228 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
6229 | } else { /* Check Legacy speed link */ | |
6230 | u16 legacy_status, legacy_speed; | |
ea4e040a | 6231 | |
de6eae1f YR |
6232 | /* Enable expansion register 0x42 (Operation mode status) */ |
6233 | bnx2x_cl45_write(bp, phy, | |
6234 | MDIO_AN_DEVAD, | |
6235 | MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); | |
ea4e040a | 6236 | |
de6eae1f YR |
6237 | /* Get legacy speed operation status */ |
6238 | bnx2x_cl45_read(bp, phy, | |
6239 | MDIO_AN_DEVAD, | |
6240 | MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, | |
6241 | &legacy_status); | |
ea4e040a | 6242 | |
de6eae1f YR |
6243 | DP(NETIF_MSG_LINK, "Legacy speed status" |
6244 | " = 0x%x\n", legacy_status); | |
6245 | link_up = ((legacy_status & (1<<11)) == (1<<11)); | |
6246 | if (link_up) { | |
6247 | legacy_speed = (legacy_status & (3<<9)); | |
6248 | if (legacy_speed == (0<<9)) | |
6249 | vars->line_speed = SPEED_10; | |
6250 | else if (legacy_speed == (1<<9)) | |
6251 | vars->line_speed = SPEED_100; | |
6252 | else if (legacy_speed == (2<<9)) | |
6253 | vars->line_speed = SPEED_1000; | |
6254 | else /* Should not happen */ | |
6255 | vars->line_speed = 0; | |
ea4e040a | 6256 | |
de6eae1f YR |
6257 | if (legacy_status & (1<<8)) |
6258 | vars->duplex = DUPLEX_FULL; | |
6259 | else | |
6260 | vars->duplex = DUPLEX_HALF; | |
ea4e040a | 6261 | |
de6eae1f YR |
6262 | DP(NETIF_MSG_LINK, "Link is up in %dMbps," |
6263 | " is_duplex_full= %d\n", vars->line_speed, | |
6264 | (vars->duplex == DUPLEX_FULL)); | |
6265 | /* Check legacy speed AN resolution */ | |
6266 | bnx2x_cl45_read(bp, phy, | |
6267 | MDIO_AN_DEVAD, | |
6268 | MDIO_AN_REG_8481_LEGACY_MII_STATUS, | |
6269 | &val); | |
6270 | if (val & (1<<5)) | |
6271 | vars->link_status |= | |
6272 | LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; | |
6273 | bnx2x_cl45_read(bp, phy, | |
6274 | MDIO_AN_DEVAD, | |
6275 | MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, | |
6276 | &val); | |
6277 | if ((val & (1<<0)) == 0) | |
6278 | vars->link_status |= | |
6279 | LINK_STATUS_PARALLEL_DETECTION_USED; | |
ea4e040a | 6280 | } |
ea4e040a | 6281 | } |
de6eae1f YR |
6282 | if (link_up) { |
6283 | DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n", | |
6284 | vars->line_speed); | |
6285 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
6286 | } | |
589abe3a | 6287 | |
de6eae1f | 6288 | return link_up; |
b7737c9b YR |
6289 | } |
6290 | ||
de6eae1f | 6291 | static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) |
b7737c9b | 6292 | { |
de6eae1f YR |
6293 | u8 status = 0; |
6294 | u32 spirom_ver; | |
6295 | spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); | |
6296 | status = bnx2x_format_ver(spirom_ver, str, len); | |
6297 | return status; | |
b7737c9b | 6298 | } |
de6eae1f YR |
6299 | |
6300 | static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy, | |
6301 | struct link_params *params) | |
b7737c9b | 6302 | { |
de6eae1f | 6303 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 6304 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); |
de6eae1f | 6305 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, |
cd88ccee | 6306 | MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); |
b7737c9b | 6307 | } |
de6eae1f | 6308 | |
b7737c9b YR |
6309 | static void bnx2x_8481_link_reset(struct bnx2x_phy *phy, |
6310 | struct link_params *params) | |
6311 | { | |
6312 | bnx2x_cl45_write(params->bp, phy, | |
6313 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); | |
6314 | bnx2x_cl45_write(params->bp, phy, | |
6315 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); | |
6316 | } | |
6317 | ||
6318 | static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy, | |
6319 | struct link_params *params) | |
6320 | { | |
6321 | struct bnx2x *bp = params->bp; | |
6a71bbe0 YR |
6322 | u8 port; |
6323 | if (CHIP_IS_E2(bp)) | |
6324 | port = BP_PATH(bp); | |
6325 | else | |
6326 | port = params->port; | |
b7737c9b | 6327 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, |
cd88ccee YR |
6328 | MISC_REGISTERS_GPIO_OUTPUT_LOW, |
6329 | port); | |
b7737c9b YR |
6330 | } |
6331 | ||
7f02c4ad YR |
6332 | static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy, |
6333 | struct link_params *params, u8 mode) | |
6334 | { | |
6335 | struct bnx2x *bp = params->bp; | |
6336 | u16 val; | |
6337 | ||
6338 | switch (mode) { | |
6339 | case LED_MODE_OFF: | |
6340 | ||
6341 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port); | |
6342 | ||
6343 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6344 | SHARED_HW_CFG_LED_EXTPHY1) { | |
6345 | ||
6346 | /* Set LED masks */ | |
6347 | bnx2x_cl45_write(bp, phy, | |
6348 | MDIO_PMA_DEVAD, | |
6349 | MDIO_PMA_REG_8481_LED1_MASK, | |
6350 | 0x0); | |
6351 | ||
6352 | bnx2x_cl45_write(bp, phy, | |
6353 | MDIO_PMA_DEVAD, | |
6354 | MDIO_PMA_REG_8481_LED2_MASK, | |
6355 | 0x0); | |
6356 | ||
6357 | bnx2x_cl45_write(bp, phy, | |
6358 | MDIO_PMA_DEVAD, | |
6359 | MDIO_PMA_REG_8481_LED3_MASK, | |
6360 | 0x0); | |
6361 | ||
6362 | bnx2x_cl45_write(bp, phy, | |
6363 | MDIO_PMA_DEVAD, | |
6364 | MDIO_PMA_REG_8481_LED5_MASK, | |
6365 | 0x0); | |
6366 | ||
6367 | } else { | |
6368 | bnx2x_cl45_write(bp, phy, | |
6369 | MDIO_PMA_DEVAD, | |
6370 | MDIO_PMA_REG_8481_LED1_MASK, | |
6371 | 0x0); | |
6372 | } | |
6373 | break; | |
6374 | case LED_MODE_FRONT_PANEL_OFF: | |
6375 | ||
6376 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", | |
6377 | params->port); | |
6378 | ||
6379 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6380 | SHARED_HW_CFG_LED_EXTPHY1) { | |
6381 | ||
6382 | /* Set LED masks */ | |
6383 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6384 | MDIO_PMA_DEVAD, |
6385 | MDIO_PMA_REG_8481_LED1_MASK, | |
6386 | 0x0); | |
7f02c4ad YR |
6387 | |
6388 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6389 | MDIO_PMA_DEVAD, |
6390 | MDIO_PMA_REG_8481_LED2_MASK, | |
6391 | 0x0); | |
7f02c4ad YR |
6392 | |
6393 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6394 | MDIO_PMA_DEVAD, |
6395 | MDIO_PMA_REG_8481_LED3_MASK, | |
6396 | 0x0); | |
7f02c4ad YR |
6397 | |
6398 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6399 | MDIO_PMA_DEVAD, |
6400 | MDIO_PMA_REG_8481_LED5_MASK, | |
6401 | 0x20); | |
7f02c4ad YR |
6402 | |
6403 | } else { | |
6404 | bnx2x_cl45_write(bp, phy, | |
6405 | MDIO_PMA_DEVAD, | |
6406 | MDIO_PMA_REG_8481_LED1_MASK, | |
6407 | 0x0); | |
6408 | } | |
6409 | break; | |
6410 | case LED_MODE_ON: | |
6411 | ||
6412 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port); | |
6413 | ||
6414 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6415 | SHARED_HW_CFG_LED_EXTPHY1) { | |
6416 | /* Set control reg */ | |
6417 | bnx2x_cl45_read(bp, phy, | |
6418 | MDIO_PMA_DEVAD, | |
6419 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6420 | &val); | |
6421 | val &= 0x8000; | |
6422 | val |= 0x2492; | |
6423 | ||
6424 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6425 | MDIO_PMA_DEVAD, |
6426 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6427 | val); | |
7f02c4ad YR |
6428 | |
6429 | /* Set LED masks */ | |
6430 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6431 | MDIO_PMA_DEVAD, |
6432 | MDIO_PMA_REG_8481_LED1_MASK, | |
6433 | 0x0); | |
7f02c4ad YR |
6434 | |
6435 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6436 | MDIO_PMA_DEVAD, |
6437 | MDIO_PMA_REG_8481_LED2_MASK, | |
6438 | 0x20); | |
7f02c4ad YR |
6439 | |
6440 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6441 | MDIO_PMA_DEVAD, |
6442 | MDIO_PMA_REG_8481_LED3_MASK, | |
6443 | 0x20); | |
7f02c4ad YR |
6444 | |
6445 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6446 | MDIO_PMA_DEVAD, |
6447 | MDIO_PMA_REG_8481_LED5_MASK, | |
6448 | 0x0); | |
7f02c4ad YR |
6449 | } else { |
6450 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6451 | MDIO_PMA_DEVAD, |
6452 | MDIO_PMA_REG_8481_LED1_MASK, | |
6453 | 0x20); | |
7f02c4ad YR |
6454 | } |
6455 | break; | |
6456 | ||
6457 | case LED_MODE_OPER: | |
6458 | ||
6459 | DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port); | |
6460 | ||
6461 | if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == | |
6462 | SHARED_HW_CFG_LED_EXTPHY1) { | |
6463 | ||
6464 | /* Set control reg */ | |
6465 | bnx2x_cl45_read(bp, phy, | |
6466 | MDIO_PMA_DEVAD, | |
6467 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6468 | &val); | |
6469 | ||
6470 | if (!((val & | |
cd88ccee YR |
6471 | MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) |
6472 | >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { | |
2cf7acf9 | 6473 | DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n"); |
7f02c4ad YR |
6474 | bnx2x_cl45_write(bp, phy, |
6475 | MDIO_PMA_DEVAD, | |
6476 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6477 | 0xa492); | |
6478 | } | |
6479 | ||
6480 | /* Set LED masks */ | |
6481 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6482 | MDIO_PMA_DEVAD, |
6483 | MDIO_PMA_REG_8481_LED1_MASK, | |
6484 | 0x10); | |
7f02c4ad YR |
6485 | |
6486 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6487 | MDIO_PMA_DEVAD, |
6488 | MDIO_PMA_REG_8481_LED2_MASK, | |
6489 | 0x80); | |
7f02c4ad YR |
6490 | |
6491 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6492 | MDIO_PMA_DEVAD, |
6493 | MDIO_PMA_REG_8481_LED3_MASK, | |
6494 | 0x98); | |
7f02c4ad YR |
6495 | |
6496 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6497 | MDIO_PMA_DEVAD, |
6498 | MDIO_PMA_REG_8481_LED5_MASK, | |
6499 | 0x40); | |
7f02c4ad YR |
6500 | |
6501 | } else { | |
6502 | bnx2x_cl45_write(bp, phy, | |
6503 | MDIO_PMA_DEVAD, | |
6504 | MDIO_PMA_REG_8481_LED1_MASK, | |
6505 | 0x80); | |
53eda06d YR |
6506 | |
6507 | /* Tell LED3 to blink on source */ | |
6508 | bnx2x_cl45_read(bp, phy, | |
6509 | MDIO_PMA_DEVAD, | |
6510 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6511 | &val); | |
6512 | val &= ~(7<<6); | |
6513 | val |= (1<<6); /* A83B[8:6]= 1 */ | |
6514 | bnx2x_cl45_write(bp, phy, | |
6515 | MDIO_PMA_DEVAD, | |
6516 | MDIO_PMA_REG_8481_LINK_SIGNAL, | |
6517 | val); | |
7f02c4ad YR |
6518 | } |
6519 | break; | |
6520 | } | |
6521 | } | |
de6eae1f YR |
6522 | /******************************************************************/ |
6523 | /* SFX7101 PHY SECTION */ | |
6524 | /******************************************************************/ | |
6525 | static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy, | |
6526 | struct link_params *params) | |
b7737c9b YR |
6527 | { |
6528 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
6529 | /* SFX7101_XGXS_TEST1 */ |
6530 | bnx2x_cl45_write(bp, phy, | |
6531 | MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); | |
589abe3a EG |
6532 | } |
6533 | ||
de6eae1f YR |
6534 | static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy, |
6535 | struct link_params *params, | |
6536 | struct link_vars *vars) | |
ea4e040a | 6537 | { |
de6eae1f | 6538 | u16 fw_ver1, fw_ver2, val; |
ea4e040a | 6539 | struct bnx2x *bp = params->bp; |
de6eae1f | 6540 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n"); |
ea4e040a | 6541 | |
de6eae1f YR |
6542 | /* Restore normal power mode*/ |
6543 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 6544 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); |
de6eae1f YR |
6545 | /* HW reset */ |
6546 | bnx2x_ext_phy_hw_reset(bp, params->port); | |
6547 | bnx2x_wait_reset_complete(bp, phy); | |
ea4e040a | 6548 | |
de6eae1f YR |
6549 | bnx2x_cl45_write(bp, phy, |
6550 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1); | |
6551 | DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n"); | |
6552 | bnx2x_cl45_write(bp, phy, | |
6553 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); | |
ea4e040a | 6554 | |
de6eae1f YR |
6555 | bnx2x_ext_phy_set_pause(params, phy, vars); |
6556 | /* Restart autoneg */ | |
6557 | bnx2x_cl45_read(bp, phy, | |
6558 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); | |
6559 | val |= 0x200; | |
6560 | bnx2x_cl45_write(bp, phy, | |
6561 | MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); | |
ea4e040a | 6562 | |
de6eae1f YR |
6563 | /* Save spirom version */ |
6564 | bnx2x_cl45_read(bp, phy, | |
6565 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); | |
ea4e040a | 6566 | |
de6eae1f YR |
6567 | bnx2x_cl45_read(bp, phy, |
6568 | MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); | |
6569 | bnx2x_save_spirom_version(bp, params->port, | |
6570 | (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); | |
6571 | return 0; | |
6572 | } | |
ea4e040a | 6573 | |
de6eae1f YR |
6574 | static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, |
6575 | struct link_params *params, | |
6576 | struct link_vars *vars) | |
57963ed9 YR |
6577 | { |
6578 | struct bnx2x *bp = params->bp; | |
de6eae1f YR |
6579 | u8 link_up; |
6580 | u16 val1, val2; | |
6581 | bnx2x_cl45_read(bp, phy, | |
6582 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2); | |
6583 | bnx2x_cl45_read(bp, phy, | |
6584 | MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1); | |
6585 | DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", | |
6586 | val2, val1); | |
6587 | bnx2x_cl45_read(bp, phy, | |
6588 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); | |
6589 | bnx2x_cl45_read(bp, phy, | |
6590 | MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); | |
6591 | DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", | |
6592 | val2, val1); | |
6593 | link_up = ((val1 & 4) == 4); | |
2cf7acf9 | 6594 | /* if link is up print the AN outcome of the SFX7101 PHY */ |
de6eae1f YR |
6595 | if (link_up) { |
6596 | bnx2x_cl45_read(bp, phy, | |
6597 | MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, | |
6598 | &val2); | |
6599 | vars->line_speed = SPEED_10000; | |
791f18c0 | 6600 | vars->duplex = DUPLEX_FULL; |
de6eae1f YR |
6601 | DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", |
6602 | val2, (val2 & (1<<14))); | |
6603 | bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); | |
6604 | bnx2x_ext_phy_resolve_fc(phy, params, vars); | |
6605 | } | |
6606 | return link_up; | |
6607 | } | |
6c55c3cd | 6608 | |
6c55c3cd | 6609 | |
de6eae1f YR |
6610 | static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) |
6611 | { | |
6612 | if (*len < 5) | |
6613 | return -EINVAL; | |
6614 | str[0] = (spirom_ver & 0xFF); | |
6615 | str[1] = (spirom_ver & 0xFF00) >> 8; | |
6616 | str[2] = (spirom_ver & 0xFF0000) >> 16; | |
6617 | str[3] = (spirom_ver & 0xFF000000) >> 24; | |
6618 | str[4] = '\0'; | |
6619 | *len -= 5; | |
57963ed9 YR |
6620 | return 0; |
6621 | } | |
6622 | ||
de6eae1f | 6623 | void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) |
57963ed9 | 6624 | { |
de6eae1f | 6625 | u16 val, cnt; |
7aa0711f | 6626 | |
de6eae1f | 6627 | bnx2x_cl45_read(bp, phy, |
cd88ccee YR |
6628 | MDIO_PMA_DEVAD, |
6629 | MDIO_PMA_REG_7101_RESET, &val); | |
57963ed9 | 6630 | |
de6eae1f YR |
6631 | for (cnt = 0; cnt < 10; cnt++) { |
6632 | msleep(50); | |
6633 | /* Writes a self-clearing reset */ | |
6634 | bnx2x_cl45_write(bp, phy, | |
cd88ccee YR |
6635 | MDIO_PMA_DEVAD, |
6636 | MDIO_PMA_REG_7101_RESET, | |
6637 | (val | (1<<15))); | |
de6eae1f YR |
6638 | /* Wait for clear */ |
6639 | bnx2x_cl45_read(bp, phy, | |
cd88ccee YR |
6640 | MDIO_PMA_DEVAD, |
6641 | MDIO_PMA_REG_7101_RESET, &val); | |
0c786f02 | 6642 | |
de6eae1f YR |
6643 | if ((val & (1<<15)) == 0) |
6644 | break; | |
57963ed9 | 6645 | } |
57963ed9 | 6646 | } |
ea4e040a | 6647 | |
de6eae1f YR |
6648 | static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy, |
6649 | struct link_params *params) { | |
6650 | /* Low power mode is controlled by GPIO 2 */ | |
6651 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 6652 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f YR |
6653 | /* The PHY reset is controlled by GPIO 1 */ |
6654 | bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, | |
cd88ccee | 6655 | MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); |
de6eae1f | 6656 | } |
ea4e040a | 6657 | |
7f02c4ad YR |
6658 | static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy, |
6659 | struct link_params *params, u8 mode) | |
6660 | { | |
6661 | u16 val = 0; | |
6662 | struct bnx2x *bp = params->bp; | |
6663 | switch (mode) { | |
6664 | case LED_MODE_FRONT_PANEL_OFF: | |
6665 | case LED_MODE_OFF: | |
6666 | val = 2; | |
6667 | break; | |
6668 | case LED_MODE_ON: | |
6669 | val = 1; | |
6670 | break; | |
6671 | case LED_MODE_OPER: | |
6672 | val = 0; | |
6673 | break; | |
6674 | } | |
6675 | bnx2x_cl45_write(bp, phy, | |
6676 | MDIO_PMA_DEVAD, | |
6677 | MDIO_PMA_REG_7107_LINK_LED_CNTL, | |
6678 | val); | |
6679 | } | |
6680 | ||
de6eae1f YR |
6681 | /******************************************************************/ |
6682 | /* STATIC PHY DECLARATION */ | |
6683 | /******************************************************************/ | |
ea4e040a | 6684 | |
de6eae1f YR |
6685 | static struct bnx2x_phy phy_null = { |
6686 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, | |
6687 | .addr = 0, | |
6688 | .flags = FLAGS_INIT_XGXS_FIRST, | |
6689 | .def_md_devad = 0, | |
6690 | .reserved = 0, | |
6691 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6692 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6693 | .mdio_ctrl = 0, | |
6694 | .supported = 0, | |
6695 | .media_type = ETH_PHY_NOT_PRESENT, | |
6696 | .ver_addr = 0, | |
cd88ccee YR |
6697 | .req_flow_ctrl = 0, |
6698 | .req_line_speed = 0, | |
6699 | .speed_cap_mask = 0, | |
de6eae1f YR |
6700 | .req_duplex = 0, |
6701 | .rsrv = 0, | |
6702 | .config_init = (config_init_t)NULL, | |
6703 | .read_status = (read_status_t)NULL, | |
6704 | .link_reset = (link_reset_t)NULL, | |
6705 | .config_loopback = (config_loopback_t)NULL, | |
6706 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6707 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6708 | .set_link_led = (set_link_led_t)NULL, |
6709 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 6710 | }; |
ea4e040a | 6711 | |
de6eae1f YR |
6712 | static struct bnx2x_phy phy_serdes = { |
6713 | .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, | |
6714 | .addr = 0xff, | |
6715 | .flags = 0, | |
6716 | .def_md_devad = 0, | |
6717 | .reserved = 0, | |
6718 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6719 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6720 | .mdio_ctrl = 0, | |
6721 | .supported = (SUPPORTED_10baseT_Half | | |
6722 | SUPPORTED_10baseT_Full | | |
6723 | SUPPORTED_100baseT_Half | | |
6724 | SUPPORTED_100baseT_Full | | |
6725 | SUPPORTED_1000baseT_Full | | |
6726 | SUPPORTED_2500baseX_Full | | |
6727 | SUPPORTED_TP | | |
6728 | SUPPORTED_Autoneg | | |
6729 | SUPPORTED_Pause | | |
6730 | SUPPORTED_Asym_Pause), | |
6731 | .media_type = ETH_PHY_UNSPECIFIED, | |
6732 | .ver_addr = 0, | |
6733 | .req_flow_ctrl = 0, | |
cd88ccee YR |
6734 | .req_line_speed = 0, |
6735 | .speed_cap_mask = 0, | |
de6eae1f YR |
6736 | .req_duplex = 0, |
6737 | .rsrv = 0, | |
6738 | .config_init = (config_init_t)bnx2x_init_serdes, | |
6739 | .read_status = (read_status_t)bnx2x_link_settings_status, | |
6740 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
6741 | .config_loopback = (config_loopback_t)NULL, | |
6742 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6743 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6744 | .set_link_led = (set_link_led_t)NULL, |
6745 | .phy_specific_func = (phy_specific_func_t)NULL | |
de6eae1f | 6746 | }; |
b7737c9b YR |
6747 | |
6748 | static struct bnx2x_phy phy_xgxs = { | |
6749 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | |
6750 | .addr = 0xff, | |
6751 | .flags = 0, | |
6752 | .def_md_devad = 0, | |
6753 | .reserved = 0, | |
6754 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6755 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6756 | .mdio_ctrl = 0, | |
6757 | .supported = (SUPPORTED_10baseT_Half | | |
6758 | SUPPORTED_10baseT_Full | | |
6759 | SUPPORTED_100baseT_Half | | |
6760 | SUPPORTED_100baseT_Full | | |
6761 | SUPPORTED_1000baseT_Full | | |
6762 | SUPPORTED_2500baseX_Full | | |
6763 | SUPPORTED_10000baseT_Full | | |
6764 | SUPPORTED_FIBRE | | |
6765 | SUPPORTED_Autoneg | | |
6766 | SUPPORTED_Pause | | |
6767 | SUPPORTED_Asym_Pause), | |
6768 | .media_type = ETH_PHY_UNSPECIFIED, | |
6769 | .ver_addr = 0, | |
6770 | .req_flow_ctrl = 0, | |
cd88ccee YR |
6771 | .req_line_speed = 0, |
6772 | .speed_cap_mask = 0, | |
b7737c9b YR |
6773 | .req_duplex = 0, |
6774 | .rsrv = 0, | |
6775 | .config_init = (config_init_t)bnx2x_init_xgxs, | |
6776 | .read_status = (read_status_t)bnx2x_link_settings_status, | |
6777 | .link_reset = (link_reset_t)bnx2x_int_link_reset, | |
6778 | .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback, | |
6779 | .format_fw_ver = (format_fw_ver_t)NULL, | |
6780 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6781 | .set_link_led = (set_link_led_t)NULL, |
6782 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6783 | }; |
6784 | ||
6785 | static struct bnx2x_phy phy_7101 = { | |
6786 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, | |
6787 | .addr = 0xff, | |
6788 | .flags = FLAGS_FAN_FAILURE_DET_REQ, | |
6789 | .def_md_devad = 0, | |
6790 | .reserved = 0, | |
6791 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6792 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6793 | .mdio_ctrl = 0, | |
6794 | .supported = (SUPPORTED_10000baseT_Full | | |
6795 | SUPPORTED_TP | | |
6796 | SUPPORTED_Autoneg | | |
6797 | SUPPORTED_Pause | | |
6798 | SUPPORTED_Asym_Pause), | |
6799 | .media_type = ETH_PHY_BASE_T, | |
6800 | .ver_addr = 0, | |
6801 | .req_flow_ctrl = 0, | |
cd88ccee YR |
6802 | .req_line_speed = 0, |
6803 | .speed_cap_mask = 0, | |
b7737c9b YR |
6804 | .req_duplex = 0, |
6805 | .rsrv = 0, | |
6806 | .config_init = (config_init_t)bnx2x_7101_config_init, | |
6807 | .read_status = (read_status_t)bnx2x_7101_read_status, | |
6808 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6809 | .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback, | |
6810 | .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver, | |
6811 | .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset, | |
7f02c4ad | 6812 | .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led, |
a22f0788 | 6813 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
6814 | }; |
6815 | static struct bnx2x_phy phy_8073 = { | |
6816 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, | |
6817 | .addr = 0xff, | |
6818 | .flags = FLAGS_HW_LOCK_REQUIRED, | |
6819 | .def_md_devad = 0, | |
6820 | .reserved = 0, | |
6821 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6822 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6823 | .mdio_ctrl = 0, | |
6824 | .supported = (SUPPORTED_10000baseT_Full | | |
6825 | SUPPORTED_2500baseX_Full | | |
6826 | SUPPORTED_1000baseT_Full | | |
6827 | SUPPORTED_FIBRE | | |
6828 | SUPPORTED_Autoneg | | |
6829 | SUPPORTED_Pause | | |
6830 | SUPPORTED_Asym_Pause), | |
6831 | .media_type = ETH_PHY_UNSPECIFIED, | |
6832 | .ver_addr = 0, | |
cd88ccee YR |
6833 | .req_flow_ctrl = 0, |
6834 | .req_line_speed = 0, | |
6835 | .speed_cap_mask = 0, | |
b7737c9b YR |
6836 | .req_duplex = 0, |
6837 | .rsrv = 0, | |
62b29a5d | 6838 | .config_init = (config_init_t)bnx2x_8073_config_init, |
b7737c9b YR |
6839 | .read_status = (read_status_t)bnx2x_8073_read_status, |
6840 | .link_reset = (link_reset_t)bnx2x_8073_link_reset, | |
6841 | .config_loopback = (config_loopback_t)NULL, | |
6842 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6843 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6844 | .set_link_led = (set_link_led_t)NULL, |
6845 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6846 | }; |
6847 | static struct bnx2x_phy phy_8705 = { | |
6848 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, | |
6849 | .addr = 0xff, | |
6850 | .flags = FLAGS_INIT_XGXS_FIRST, | |
6851 | .def_md_devad = 0, | |
6852 | .reserved = 0, | |
6853 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6854 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6855 | .mdio_ctrl = 0, | |
6856 | .supported = (SUPPORTED_10000baseT_Full | | |
6857 | SUPPORTED_FIBRE | | |
6858 | SUPPORTED_Pause | | |
6859 | SUPPORTED_Asym_Pause), | |
6860 | .media_type = ETH_PHY_XFP_FIBER, | |
6861 | .ver_addr = 0, | |
6862 | .req_flow_ctrl = 0, | |
6863 | .req_line_speed = 0, | |
6864 | .speed_cap_mask = 0, | |
6865 | .req_duplex = 0, | |
6866 | .rsrv = 0, | |
6867 | .config_init = (config_init_t)bnx2x_8705_config_init, | |
6868 | .read_status = (read_status_t)bnx2x_8705_read_status, | |
6869 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6870 | .config_loopback = (config_loopback_t)NULL, | |
6871 | .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver, | |
6872 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6873 | .set_link_led = (set_link_led_t)NULL, |
6874 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6875 | }; |
6876 | static struct bnx2x_phy phy_8706 = { | |
6877 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | |
6878 | .addr = 0xff, | |
6879 | .flags = FLAGS_INIT_XGXS_FIRST, | |
6880 | .def_md_devad = 0, | |
6881 | .reserved = 0, | |
6882 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6883 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6884 | .mdio_ctrl = 0, | |
6885 | .supported = (SUPPORTED_10000baseT_Full | | |
6886 | SUPPORTED_1000baseT_Full | | |
6887 | SUPPORTED_FIBRE | | |
6888 | SUPPORTED_Pause | | |
6889 | SUPPORTED_Asym_Pause), | |
6890 | .media_type = ETH_PHY_SFP_FIBER, | |
6891 | .ver_addr = 0, | |
6892 | .req_flow_ctrl = 0, | |
6893 | .req_line_speed = 0, | |
6894 | .speed_cap_mask = 0, | |
6895 | .req_duplex = 0, | |
6896 | .rsrv = 0, | |
6897 | .config_init = (config_init_t)bnx2x_8706_config_init, | |
6898 | .read_status = (read_status_t)bnx2x_8706_read_status, | |
6899 | .link_reset = (link_reset_t)bnx2x_common_ext_link_reset, | |
6900 | .config_loopback = (config_loopback_t)NULL, | |
6901 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6902 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6903 | .set_link_led = (set_link_led_t)NULL, |
6904 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6905 | }; |
6906 | ||
6907 | static struct bnx2x_phy phy_8726 = { | |
6908 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, | |
6909 | .addr = 0xff, | |
6910 | .flags = (FLAGS_HW_LOCK_REQUIRED | | |
6911 | FLAGS_INIT_XGXS_FIRST), | |
6912 | .def_md_devad = 0, | |
6913 | .reserved = 0, | |
6914 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6915 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6916 | .mdio_ctrl = 0, | |
6917 | .supported = (SUPPORTED_10000baseT_Full | | |
6918 | SUPPORTED_1000baseT_Full | | |
6919 | SUPPORTED_Autoneg | | |
6920 | SUPPORTED_FIBRE | | |
6921 | SUPPORTED_Pause | | |
6922 | SUPPORTED_Asym_Pause), | |
6923 | .media_type = ETH_PHY_SFP_FIBER, | |
6924 | .ver_addr = 0, | |
6925 | .req_flow_ctrl = 0, | |
6926 | .req_line_speed = 0, | |
6927 | .speed_cap_mask = 0, | |
6928 | .req_duplex = 0, | |
6929 | .rsrv = 0, | |
6930 | .config_init = (config_init_t)bnx2x_8726_config_init, | |
6931 | .read_status = (read_status_t)bnx2x_8726_read_status, | |
6932 | .link_reset = (link_reset_t)bnx2x_8726_link_reset, | |
6933 | .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback, | |
6934 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6935 | .hw_reset = (hw_reset_t)NULL, | |
a22f0788 YR |
6936 | .set_link_led = (set_link_led_t)NULL, |
6937 | .phy_specific_func = (phy_specific_func_t)NULL | |
b7737c9b YR |
6938 | }; |
6939 | ||
6940 | static struct bnx2x_phy phy_8727 = { | |
6941 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | |
6942 | .addr = 0xff, | |
6943 | .flags = FLAGS_FAN_FAILURE_DET_REQ, | |
6944 | .def_md_devad = 0, | |
6945 | .reserved = 0, | |
6946 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6947 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6948 | .mdio_ctrl = 0, | |
6949 | .supported = (SUPPORTED_10000baseT_Full | | |
6950 | SUPPORTED_1000baseT_Full | | |
b7737c9b YR |
6951 | SUPPORTED_FIBRE | |
6952 | SUPPORTED_Pause | | |
6953 | SUPPORTED_Asym_Pause), | |
6954 | .media_type = ETH_PHY_SFP_FIBER, | |
6955 | .ver_addr = 0, | |
6956 | .req_flow_ctrl = 0, | |
6957 | .req_line_speed = 0, | |
6958 | .speed_cap_mask = 0, | |
6959 | .req_duplex = 0, | |
6960 | .rsrv = 0, | |
6961 | .config_init = (config_init_t)bnx2x_8727_config_init, | |
6962 | .read_status = (read_status_t)bnx2x_8727_read_status, | |
6963 | .link_reset = (link_reset_t)bnx2x_8727_link_reset, | |
6964 | .config_loopback = (config_loopback_t)NULL, | |
6965 | .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver, | |
6966 | .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset, | |
7f02c4ad | 6967 | .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led, |
a22f0788 | 6968 | .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func |
b7737c9b YR |
6969 | }; |
6970 | static struct bnx2x_phy phy_8481 = { | |
6971 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, | |
6972 | .addr = 0xff, | |
a22f0788 YR |
6973 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
6974 | FLAGS_REARM_LATCH_SIGNAL, | |
b7737c9b YR |
6975 | .def_md_devad = 0, |
6976 | .reserved = 0, | |
6977 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6978 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
6979 | .mdio_ctrl = 0, | |
6980 | .supported = (SUPPORTED_10baseT_Half | | |
6981 | SUPPORTED_10baseT_Full | | |
6982 | SUPPORTED_100baseT_Half | | |
6983 | SUPPORTED_100baseT_Full | | |
6984 | SUPPORTED_1000baseT_Full | | |
6985 | SUPPORTED_10000baseT_Full | | |
6986 | SUPPORTED_TP | | |
6987 | SUPPORTED_Autoneg | | |
6988 | SUPPORTED_Pause | | |
6989 | SUPPORTED_Asym_Pause), | |
6990 | .media_type = ETH_PHY_BASE_T, | |
6991 | .ver_addr = 0, | |
6992 | .req_flow_ctrl = 0, | |
6993 | .req_line_speed = 0, | |
6994 | .speed_cap_mask = 0, | |
6995 | .req_duplex = 0, | |
6996 | .rsrv = 0, | |
6997 | .config_init = (config_init_t)bnx2x_8481_config_init, | |
6998 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
6999 | .link_reset = (link_reset_t)bnx2x_8481_link_reset, | |
7000 | .config_loopback = (config_loopback_t)NULL, | |
7001 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
7002 | .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset, | |
7f02c4ad | 7003 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 7004 | .phy_specific_func = (phy_specific_func_t)NULL |
b7737c9b YR |
7005 | }; |
7006 | ||
de6eae1f YR |
7007 | static struct bnx2x_phy phy_84823 = { |
7008 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, | |
7009 | .addr = 0xff, | |
a22f0788 YR |
7010 | .flags = FLAGS_FAN_FAILURE_DET_REQ | |
7011 | FLAGS_REARM_LATCH_SIGNAL, | |
de6eae1f YR |
7012 | .def_md_devad = 0, |
7013 | .reserved = 0, | |
7014 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
7015 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | |
7016 | .mdio_ctrl = 0, | |
7017 | .supported = (SUPPORTED_10baseT_Half | | |
7018 | SUPPORTED_10baseT_Full | | |
7019 | SUPPORTED_100baseT_Half | | |
7020 | SUPPORTED_100baseT_Full | | |
7021 | SUPPORTED_1000baseT_Full | | |
7022 | SUPPORTED_10000baseT_Full | | |
7023 | SUPPORTED_TP | | |
7024 | SUPPORTED_Autoneg | | |
7025 | SUPPORTED_Pause | | |
7026 | SUPPORTED_Asym_Pause), | |
7027 | .media_type = ETH_PHY_BASE_T, | |
7028 | .ver_addr = 0, | |
7029 | .req_flow_ctrl = 0, | |
7030 | .req_line_speed = 0, | |
7031 | .speed_cap_mask = 0, | |
7032 | .req_duplex = 0, | |
7033 | .rsrv = 0, | |
7034 | .config_init = (config_init_t)bnx2x_848x3_config_init, | |
7035 | .read_status = (read_status_t)bnx2x_848xx_read_status, | |
7036 | .link_reset = (link_reset_t)bnx2x_848x3_link_reset, | |
7037 | .config_loopback = (config_loopback_t)NULL, | |
7038 | .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver, | |
7039 | .hw_reset = (hw_reset_t)NULL, | |
7f02c4ad | 7040 | .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led, |
a22f0788 | 7041 | .phy_specific_func = (phy_specific_func_t)NULL |
de6eae1f YR |
7042 | }; |
7043 | ||
7044 | /*****************************************************************/ | |
7045 | /* */ | |
7046 | /* Populate the phy according. Main function: bnx2x_populate_phy */ | |
7047 | /* */ | |
7048 | /*****************************************************************/ | |
7049 | ||
7050 | static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, | |
7051 | struct bnx2x_phy *phy, u8 port, | |
7052 | u8 phy_index) | |
7053 | { | |
7054 | /* Get the 4 lanes xgxs config rx and tx */ | |
7055 | u32 rx = 0, tx = 0, i; | |
7056 | for (i = 0; i < 2; i++) { | |
2cf7acf9 | 7057 | /* |
de6eae1f YR |
7058 | * INT_PHY and EXT_PHY1 share the same value location in the |
7059 | * shmem. When num_phys is greater than 1, than this value | |
7060 | * applies only to EXT_PHY1 | |
7061 | */ | |
a22f0788 YR |
7062 | if (phy_index == INT_PHY || phy_index == EXT_PHY1) { |
7063 | rx = REG_RD(bp, shmem_base + | |
7064 | offsetof(struct shmem_region, | |
cd88ccee | 7065 | dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); |
a22f0788 YR |
7066 | |
7067 | tx = REG_RD(bp, shmem_base + | |
7068 | offsetof(struct shmem_region, | |
cd88ccee | 7069 | dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); |
a22f0788 YR |
7070 | } else { |
7071 | rx = REG_RD(bp, shmem_base + | |
7072 | offsetof(struct shmem_region, | |
cd88ccee | 7073 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
de6eae1f | 7074 | |
a22f0788 YR |
7075 | tx = REG_RD(bp, shmem_base + |
7076 | offsetof(struct shmem_region, | |
cd88ccee | 7077 | dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); |
a22f0788 | 7078 | } |
de6eae1f YR |
7079 | |
7080 | phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); | |
7081 | phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); | |
7082 | ||
7083 | phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); | |
7084 | phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); | |
7085 | } | |
7086 | } | |
7087 | ||
7088 | static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, | |
7089 | u8 phy_index, u8 port) | |
7090 | { | |
7091 | u32 ext_phy_config = 0; | |
7092 | switch (phy_index) { | |
7093 | case EXT_PHY1: | |
7094 | ext_phy_config = REG_RD(bp, shmem_base + | |
7095 | offsetof(struct shmem_region, | |
7096 | dev_info.port_hw_config[port].external_phy_config)); | |
7097 | break; | |
a22f0788 YR |
7098 | case EXT_PHY2: |
7099 | ext_phy_config = REG_RD(bp, shmem_base + | |
7100 | offsetof(struct shmem_region, | |
7101 | dev_info.port_hw_config[port].external_phy_config2)); | |
7102 | break; | |
de6eae1f YR |
7103 | default: |
7104 | DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index); | |
7105 | return -EINVAL; | |
7106 | } | |
7107 | ||
7108 | return ext_phy_config; | |
7109 | } | |
7110 | static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, | |
7111 | struct bnx2x_phy *phy) | |
7112 | { | |
7113 | u32 phy_addr; | |
7114 | u32 chip_id; | |
7115 | u32 switch_cfg = (REG_RD(bp, shmem_base + | |
7116 | offsetof(struct shmem_region, | |
7117 | dev_info.port_feature_config[port].link_config)) & | |
7118 | PORT_FEATURE_CONNECTED_SWITCH_MASK); | |
7119 | chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16; | |
7120 | switch (switch_cfg) { | |
7121 | case SWITCH_CFG_1G: | |
7122 | phy_addr = REG_RD(bp, | |
7123 | NIG_REG_SERDES0_CTRL_PHY_ADDR + | |
7124 | port * 0x10); | |
7125 | *phy = phy_serdes; | |
7126 | break; | |
7127 | case SWITCH_CFG_10G: | |
7128 | phy_addr = REG_RD(bp, | |
7129 | NIG_REG_XGXS0_CTRL_PHY_ADDR + | |
7130 | port * 0x18); | |
7131 | *phy = phy_xgxs; | |
7132 | break; | |
7133 | default: | |
7134 | DP(NETIF_MSG_LINK, "Invalid switch_cfg\n"); | |
7135 | return -EINVAL; | |
7136 | } | |
7137 | phy->addr = (u8)phy_addr; | |
7138 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, | |
7139 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, | |
7140 | port); | |
f2e0899f DK |
7141 | if (CHIP_IS_E2(bp)) |
7142 | phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; | |
7143 | else | |
7144 | phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; | |
de6eae1f YR |
7145 | |
7146 | DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", | |
7147 | port, phy->addr, phy->mdio_ctrl); | |
7148 | ||
7149 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); | |
7150 | return 0; | |
7151 | } | |
7152 | ||
7153 | static u8 bnx2x_populate_ext_phy(struct bnx2x *bp, | |
7154 | u8 phy_index, | |
7155 | u32 shmem_base, | |
a22f0788 | 7156 | u32 shmem2_base, |
de6eae1f YR |
7157 | u8 port, |
7158 | struct bnx2x_phy *phy) | |
7159 | { | |
7160 | u32 ext_phy_config, phy_type, config2; | |
7161 | u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; | |
7162 | ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, | |
7163 | phy_index, port); | |
7164 | phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
7165 | /* Select the phy type */ | |
7166 | switch (phy_type) { | |
7167 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
7168 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; | |
7169 | *phy = phy_8073; | |
7170 | break; | |
7171 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | |
7172 | *phy = phy_8705; | |
7173 | break; | |
7174 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | |
7175 | *phy = phy_8706; | |
7176 | break; | |
7177 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | |
7178 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
7179 | *phy = phy_8726; | |
7180 | break; | |
7181 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
7182 | /* BCM8727_NOC => BCM8727 no over current */ | |
7183 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
7184 | *phy = phy_8727; | |
7185 | phy->flags |= FLAGS_NOC; | |
7186 | break; | |
7187 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
7188 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | |
7189 | *phy = phy_8727; | |
7190 | break; | |
7191 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: | |
7192 | *phy = phy_8481; | |
7193 | break; | |
7194 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: | |
7195 | *phy = phy_84823; | |
7196 | break; | |
7197 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | |
7198 | *phy = phy_7101; | |
7199 | break; | |
7200 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
7201 | *phy = phy_null; | |
7202 | return -EINVAL; | |
7203 | default: | |
7204 | *phy = phy_null; | |
7205 | return 0; | |
7206 | } | |
7207 | ||
7208 | phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); | |
7209 | bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); | |
7210 | ||
2cf7acf9 YR |
7211 | /* |
7212 | * The shmem address of the phy version is located on different | |
7213 | * structures. In case this structure is too old, do not set | |
7214 | * the address | |
7215 | */ | |
de6eae1f YR |
7216 | config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, |
7217 | dev_info.shared_hw_config.config2)); | |
a22f0788 YR |
7218 | if (phy_index == EXT_PHY1) { |
7219 | phy->ver_addr = shmem_base + offsetof(struct shmem_region, | |
7220 | port_mb[port].ext_phy_fw_version); | |
de6eae1f | 7221 | |
cd88ccee YR |
7222 | /* Check specific mdc mdio settings */ |
7223 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) | |
7224 | mdc_mdio_access = config2 & | |
7225 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; | |
a22f0788 YR |
7226 | } else { |
7227 | u32 size = REG_RD(bp, shmem2_base); | |
de6eae1f | 7228 | |
a22f0788 YR |
7229 | if (size > |
7230 | offsetof(struct shmem2_region, ext_phy_fw_version2)) { | |
7231 | phy->ver_addr = shmem2_base + | |
7232 | offsetof(struct shmem2_region, | |
7233 | ext_phy_fw_version2[port]); | |
7234 | } | |
7235 | /* Check specific mdc mdio settings */ | |
7236 | if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) | |
7237 | mdc_mdio_access = (config2 & | |
7238 | SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> | |
7239 | (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - | |
7240 | SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); | |
7241 | } | |
de6eae1f YR |
7242 | phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); |
7243 | ||
2cf7acf9 | 7244 | /* |
de6eae1f YR |
7245 | * In case mdc/mdio_access of the external phy is different than the |
7246 | * mdc/mdio access of the XGXS, a HW lock must be taken in each access | |
7247 | * to prevent one port interfere with another port's CL45 operations. | |
7248 | */ | |
7249 | if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH) | |
7250 | phy->flags |= FLAGS_HW_LOCK_REQUIRED; | |
7251 | DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", | |
7252 | phy_type, port, phy_index); | |
7253 | DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", | |
7254 | phy->addr, phy->mdio_ctrl); | |
7255 | return 0; | |
7256 | } | |
7257 | ||
7258 | static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, | |
a22f0788 | 7259 | u32 shmem2_base, u8 port, struct bnx2x_phy *phy) |
de6eae1f YR |
7260 | { |
7261 | u8 status = 0; | |
7262 | phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; | |
7263 | if (phy_index == INT_PHY) | |
7264 | return bnx2x_populate_int_phy(bp, shmem_base, port, phy); | |
a22f0788 | 7265 | status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
7266 | port, phy); |
7267 | return status; | |
7268 | } | |
7269 | ||
7270 | static void bnx2x_phy_def_cfg(struct link_params *params, | |
7271 | struct bnx2x_phy *phy, | |
a22f0788 | 7272 | u8 phy_index) |
de6eae1f YR |
7273 | { |
7274 | struct bnx2x *bp = params->bp; | |
7275 | u32 link_config; | |
7276 | /* Populate the default phy configuration for MF mode */ | |
a22f0788 YR |
7277 | if (phy_index == EXT_PHY2) { |
7278 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 7279 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
7280 | port_feature_config[params->port].link_config2)); |
7281 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
7282 | offsetof(struct shmem_region, |
7283 | dev_info. | |
a22f0788 YR |
7284 | port_hw_config[params->port].speed_capability_mask2)); |
7285 | } else { | |
7286 | link_config = REG_RD(bp, params->shmem_base + | |
cd88ccee | 7287 | offsetof(struct shmem_region, dev_info. |
a22f0788 YR |
7288 | port_feature_config[params->port].link_config)); |
7289 | phy->speed_cap_mask = REG_RD(bp, params->shmem_base + | |
cd88ccee YR |
7290 | offsetof(struct shmem_region, |
7291 | dev_info. | |
7292 | port_hw_config[params->port].speed_capability_mask)); | |
a22f0788 YR |
7293 | } |
7294 | DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask" | |
7295 | " 0x%x\n", phy_index, link_config, phy->speed_cap_mask); | |
de6eae1f YR |
7296 | |
7297 | phy->req_duplex = DUPLEX_FULL; | |
7298 | switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { | |
7299 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | |
7300 | phy->req_duplex = DUPLEX_HALF; | |
7301 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | |
7302 | phy->req_line_speed = SPEED_10; | |
7303 | break; | |
7304 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | |
7305 | phy->req_duplex = DUPLEX_HALF; | |
7306 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | |
7307 | phy->req_line_speed = SPEED_100; | |
7308 | break; | |
7309 | case PORT_FEATURE_LINK_SPEED_1G: | |
7310 | phy->req_line_speed = SPEED_1000; | |
7311 | break; | |
7312 | case PORT_FEATURE_LINK_SPEED_2_5G: | |
7313 | phy->req_line_speed = SPEED_2500; | |
7314 | break; | |
7315 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | |
7316 | phy->req_line_speed = SPEED_10000; | |
7317 | break; | |
7318 | default: | |
7319 | phy->req_line_speed = SPEED_AUTO_NEG; | |
7320 | break; | |
7321 | } | |
7322 | ||
7323 | switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { | |
7324 | case PORT_FEATURE_FLOW_CONTROL_AUTO: | |
7325 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; | |
7326 | break; | |
7327 | case PORT_FEATURE_FLOW_CONTROL_TX: | |
7328 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; | |
7329 | break; | |
7330 | case PORT_FEATURE_FLOW_CONTROL_RX: | |
7331 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; | |
7332 | break; | |
7333 | case PORT_FEATURE_FLOW_CONTROL_BOTH: | |
7334 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; | |
7335 | break; | |
7336 | default: | |
7337 | phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7338 | break; | |
7339 | } | |
7340 | } | |
7341 | ||
a22f0788 YR |
7342 | u32 bnx2x_phy_selection(struct link_params *params) |
7343 | { | |
7344 | u32 phy_config_swapped, prio_cfg; | |
7345 | u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; | |
7346 | ||
7347 | phy_config_swapped = params->multi_phy_config & | |
7348 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
7349 | ||
7350 | prio_cfg = params->multi_phy_config & | |
7351 | PORT_HW_CFG_PHY_SELECTION_MASK; | |
7352 | ||
7353 | if (phy_config_swapped) { | |
7354 | switch (prio_cfg) { | |
7355 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: | |
7356 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; | |
7357 | break; | |
7358 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: | |
7359 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; | |
7360 | break; | |
7361 | case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: | |
7362 | return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; | |
7363 | break; | |
7364 | case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: | |
7365 | return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; | |
7366 | break; | |
7367 | } | |
7368 | } else | |
7369 | return_cfg = prio_cfg; | |
7370 | ||
7371 | return return_cfg; | |
7372 | } | |
7373 | ||
7374 | ||
de6eae1f YR |
7375 | u8 bnx2x_phy_probe(struct link_params *params) |
7376 | { | |
7377 | u8 phy_index, actual_phy_idx, link_cfg_idx; | |
a22f0788 | 7378 | u32 phy_config_swapped; |
de6eae1f YR |
7379 | struct bnx2x *bp = params->bp; |
7380 | struct bnx2x_phy *phy; | |
7381 | params->num_phys = 0; | |
7382 | DP(NETIF_MSG_LINK, "Begin phy probe\n"); | |
a22f0788 YR |
7383 | phy_config_swapped = params->multi_phy_config & |
7384 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
7385 | |
7386 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
7387 | phy_index++) { | |
7388 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); | |
7389 | actual_phy_idx = phy_index; | |
a22f0788 YR |
7390 | if (phy_config_swapped) { |
7391 | if (phy_index == EXT_PHY1) | |
7392 | actual_phy_idx = EXT_PHY2; | |
7393 | else if (phy_index == EXT_PHY2) | |
7394 | actual_phy_idx = EXT_PHY1; | |
7395 | } | |
7396 | DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x," | |
7397 | " actual_phy_idx %x\n", phy_config_swapped, | |
7398 | phy_index, actual_phy_idx); | |
de6eae1f YR |
7399 | phy = ¶ms->phy[actual_phy_idx]; |
7400 | if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, | |
a22f0788 | 7401 | params->shmem2_base, params->port, |
de6eae1f YR |
7402 | phy) != 0) { |
7403 | params->num_phys = 0; | |
7404 | DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n", | |
7405 | phy_index); | |
7406 | for (phy_index = INT_PHY; | |
7407 | phy_index < MAX_PHYS; | |
7408 | phy_index++) | |
7409 | *phy = phy_null; | |
7410 | return -EINVAL; | |
7411 | } | |
7412 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) | |
7413 | break; | |
7414 | ||
a22f0788 | 7415 | bnx2x_phy_def_cfg(params, phy, phy_index); |
de6eae1f YR |
7416 | params->num_phys++; |
7417 | } | |
7418 | ||
7419 | DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); | |
7420 | return 0; | |
7421 | } | |
7422 | ||
de6eae1f YR |
7423 | static void set_phy_vars(struct link_params *params) |
7424 | { | |
7425 | struct bnx2x *bp = params->bp; | |
a22f0788 YR |
7426 | u8 actual_phy_idx, phy_index, link_cfg_idx; |
7427 | u8 phy_config_swapped = params->multi_phy_config & | |
7428 | PORT_HW_CFG_PHY_SWAPPED_ENABLED; | |
de6eae1f YR |
7429 | for (phy_index = INT_PHY; phy_index < params->num_phys; |
7430 | phy_index++) { | |
a22f0788 | 7431 | link_cfg_idx = LINK_CONFIG_IDX(phy_index); |
de6eae1f | 7432 | actual_phy_idx = phy_index; |
a22f0788 YR |
7433 | if (phy_config_swapped) { |
7434 | if (phy_index == EXT_PHY1) | |
7435 | actual_phy_idx = EXT_PHY2; | |
7436 | else if (phy_index == EXT_PHY2) | |
7437 | actual_phy_idx = EXT_PHY1; | |
7438 | } | |
cd88ccee | 7439 | params->phy[actual_phy_idx].req_flow_ctrl = |
a22f0788 | 7440 | params->req_flow_ctrl[link_cfg_idx]; |
de6eae1f YR |
7441 | |
7442 | params->phy[actual_phy_idx].req_line_speed = | |
a22f0788 | 7443 | params->req_line_speed[link_cfg_idx]; |
de6eae1f YR |
7444 | |
7445 | params->phy[actual_phy_idx].speed_cap_mask = | |
a22f0788 | 7446 | params->speed_cap_mask[link_cfg_idx]; |
de6eae1f YR |
7447 | |
7448 | params->phy[actual_phy_idx].req_duplex = | |
a22f0788 | 7449 | params->req_duplex[link_cfg_idx]; |
de6eae1f YR |
7450 | |
7451 | DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x," | |
7452 | " speed_cap_mask %x\n", | |
7453 | params->phy[actual_phy_idx].req_flow_ctrl, | |
7454 | params->phy[actual_phy_idx].req_line_speed, | |
7455 | params->phy[actual_phy_idx].speed_cap_mask); | |
7456 | } | |
7457 | } | |
7458 | ||
7459 | u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars) | |
7460 | { | |
7461 | struct bnx2x *bp = params->bp; | |
de6eae1f | 7462 | DP(NETIF_MSG_LINK, "Phy Initialization started\n"); |
a22f0788 YR |
7463 | DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n", |
7464 | params->req_line_speed[0], params->req_flow_ctrl[0]); | |
7465 | DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n", | |
7466 | params->req_line_speed[1], params->req_flow_ctrl[1]); | |
de6eae1f YR |
7467 | vars->link_status = 0; |
7468 | vars->phy_link_up = 0; | |
7469 | vars->link_up = 0; | |
7470 | vars->line_speed = 0; | |
7471 | vars->duplex = DUPLEX_FULL; | |
7472 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7473 | vars->mac_type = MAC_TYPE_NONE; | |
7474 | vars->phy_flags = 0; | |
7475 | ||
7476 | /* disable attentions */ | |
7477 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, | |
7478 | (NIG_MASK_XGXS0_LINK_STATUS | | |
7479 | NIG_MASK_XGXS0_LINK10G | | |
7480 | NIG_MASK_SERDES0_LINK_STATUS | | |
7481 | NIG_MASK_MI_INT)); | |
7482 | ||
7483 | bnx2x_emac_init(params, vars); | |
7484 | ||
7485 | if (params->num_phys == 0) { | |
7486 | DP(NETIF_MSG_LINK, "No phy found for initialization !!\n"); | |
7487 | return -EINVAL; | |
7488 | } | |
7489 | set_phy_vars(params); | |
7490 | ||
7491 | DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); | |
7492 | if (CHIP_REV_IS_FPGA(bp)) { | |
7493 | ||
7494 | vars->link_up = 1; | |
7495 | vars->line_speed = SPEED_10000; | |
7496 | vars->duplex = DUPLEX_FULL; | |
7497 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7498 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | |
7499 | /* enable on E1.5 FPGA */ | |
7500 | if (CHIP_IS_E1H(bp)) { | |
7501 | vars->flow_ctrl |= | |
7502 | (BNX2X_FLOW_CTRL_TX | | |
7503 | BNX2X_FLOW_CTRL_RX); | |
7504 | vars->link_status |= | |
7505 | (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | | |
7506 | LINK_STATUS_RX_FLOW_CONTROL_ENABLED); | |
7507 | } | |
7508 | ||
7509 | bnx2x_emac_enable(params, vars, 0); | |
f2e0899f DK |
7510 | if (!(CHIP_IS_E2(bp))) |
7511 | bnx2x_pbf_update(params, vars->flow_ctrl, | |
7512 | vars->line_speed); | |
de6eae1f YR |
7513 | /* disable drain */ |
7514 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); | |
7515 | ||
7516 | /* update shared memory */ | |
7517 | bnx2x_update_mng(params, vars->link_status); | |
7518 | ||
7519 | return 0; | |
7520 | ||
7521 | } else | |
7522 | if (CHIP_REV_IS_EMUL(bp)) { | |
7523 | ||
7524 | vars->link_up = 1; | |
7525 | vars->line_speed = SPEED_10000; | |
7526 | vars->duplex = DUPLEX_FULL; | |
7527 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7528 | vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD); | |
7529 | ||
7530 | bnx2x_bmac_enable(params, vars, 0); | |
7531 | ||
7532 | bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed); | |
7533 | /* Disable drain */ | |
7534 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE | |
7535 | + params->port*4, 0); | |
7536 | ||
7537 | /* update shared memory */ | |
7538 | bnx2x_update_mng(params, vars->link_status); | |
7539 | ||
7540 | return 0; | |
7541 | ||
7542 | } else | |
7543 | if (params->loopback_mode == LOOPBACK_BMAC) { | |
7544 | ||
7545 | vars->link_up = 1; | |
7546 | vars->line_speed = SPEED_10000; | |
7547 | vars->duplex = DUPLEX_FULL; | |
7548 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7549 | vars->mac_type = MAC_TYPE_BMAC; | |
b7737c9b | 7550 | |
de6eae1f | 7551 | vars->phy_flags = PHY_XGXS_FLAG; |
b7737c9b | 7552 | |
de6eae1f | 7553 | bnx2x_xgxs_deassert(params); |
b7737c9b | 7554 | |
de6eae1f YR |
7555 | /* set bmac loopback */ |
7556 | bnx2x_bmac_enable(params, vars, 1); | |
b7737c9b | 7557 | |
cd88ccee | 7558 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
b7737c9b | 7559 | |
de6eae1f | 7560 | } else if (params->loopback_mode == LOOPBACK_EMAC) { |
b7737c9b | 7561 | |
de6eae1f YR |
7562 | vars->link_up = 1; |
7563 | vars->line_speed = SPEED_1000; | |
7564 | vars->duplex = DUPLEX_FULL; | |
7565 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; | |
7566 | vars->mac_type = MAC_TYPE_EMAC; | |
b7737c9b | 7567 | |
de6eae1f | 7568 | vars->phy_flags = PHY_XGXS_FLAG; |
e10bc84d | 7569 | |
de6eae1f YR |
7570 | bnx2x_xgxs_deassert(params); |
7571 | /* set bmac loopback */ | |
7572 | bnx2x_emac_enable(params, vars, 1); | |
7573 | bnx2x_emac_program(params, vars); | |
cd88ccee | 7574 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
b7737c9b | 7575 | |
de6eae1f YR |
7576 | } else if ((params->loopback_mode == LOOPBACK_XGXS) || |
7577 | (params->loopback_mode == LOOPBACK_EXT_PHY)) { | |
b7737c9b | 7578 | |
de6eae1f | 7579 | vars->link_up = 1; |
de6eae1f | 7580 | vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; |
a22f0788 YR |
7581 | vars->duplex = DUPLEX_FULL; |
7582 | if (params->req_line_speed[0] == SPEED_1000) { | |
7583 | vars->line_speed = SPEED_1000; | |
7584 | vars->mac_type = MAC_TYPE_EMAC; | |
7585 | } else { | |
7586 | vars->line_speed = SPEED_10000; | |
7587 | vars->mac_type = MAC_TYPE_BMAC; | |
7588 | } | |
62b29a5d | 7589 | |
de6eae1f YR |
7590 | bnx2x_xgxs_deassert(params); |
7591 | bnx2x_link_initialize(params, vars); | |
c18aa15d | 7592 | |
a22f0788 YR |
7593 | if (params->req_line_speed[0] == SPEED_1000) { |
7594 | bnx2x_emac_program(params, vars); | |
7595 | bnx2x_emac_enable(params, vars, 0); | |
7596 | } else | |
cd88ccee | 7597 | bnx2x_bmac_enable(params, vars, 0); |
de6eae1f YR |
7598 | if (params->loopback_mode == LOOPBACK_XGXS) { |
7599 | /* set 10G XGXS loopback */ | |
7600 | params->phy[INT_PHY].config_loopback( | |
7601 | ¶ms->phy[INT_PHY], | |
7602 | params); | |
c18aa15d | 7603 | |
de6eae1f YR |
7604 | } else { |
7605 | /* set external phy loopback */ | |
7606 | u8 phy_index; | |
7607 | for (phy_index = EXT_PHY1; | |
7608 | phy_index < params->num_phys; phy_index++) { | |
7609 | if (params->phy[phy_index].config_loopback) | |
7610 | params->phy[phy_index].config_loopback( | |
7611 | ¶ms->phy[phy_index], | |
7612 | params); | |
7613 | } | |
7614 | } | |
cd88ccee | 7615 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); |
de6eae1f | 7616 | |
7f02c4ad YR |
7617 | bnx2x_set_led(params, vars, |
7618 | LED_MODE_OPER, vars->line_speed); | |
de6eae1f YR |
7619 | } else |
7620 | /* No loopback */ | |
7621 | { | |
7622 | if (params->switch_cfg == SWITCH_CFG_10G) | |
7623 | bnx2x_xgxs_deassert(params); | |
7624 | else | |
7625 | bnx2x_serdes_deassert(bp, params->port); | |
7f02c4ad | 7626 | |
de6eae1f YR |
7627 | bnx2x_link_initialize(params, vars); |
7628 | msleep(30); | |
7629 | bnx2x_link_int_enable(params); | |
7630 | } | |
e10bc84d YR |
7631 | return 0; |
7632 | } | |
de6eae1f | 7633 | u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars, |
cd88ccee | 7634 | u8 reset_ext_phy) |
b7737c9b YR |
7635 | { |
7636 | struct bnx2x *bp = params->bp; | |
cf1d972c | 7637 | u8 phy_index, port = params->port, clear_latch_ind = 0; |
de6eae1f YR |
7638 | DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port); |
7639 | /* disable attentions */ | |
7640 | vars->link_status = 0; | |
7641 | bnx2x_update_mng(params, vars->link_status); | |
7642 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | |
cd88ccee YR |
7643 | (NIG_MASK_XGXS0_LINK_STATUS | |
7644 | NIG_MASK_XGXS0_LINK10G | | |
7645 | NIG_MASK_SERDES0_LINK_STATUS | | |
7646 | NIG_MASK_MI_INT)); | |
b7737c9b | 7647 | |
de6eae1f YR |
7648 | /* activate nig drain */ |
7649 | REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | |
b7737c9b | 7650 | |
de6eae1f YR |
7651 | /* disable nig egress interface */ |
7652 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
7653 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
b7737c9b | 7654 | |
de6eae1f YR |
7655 | /* Stop BigMac rx */ |
7656 | bnx2x_bmac_rx_disable(bp, port); | |
b7737c9b | 7657 | |
de6eae1f YR |
7658 | /* disable emac */ |
7659 | REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); | |
b7737c9b | 7660 | |
de6eae1f YR |
7661 | msleep(10); |
7662 | /* The PHY reset is controled by GPIO 1 | |
7663 | * Hold it as vars low | |
7664 | */ | |
7665 | /* clear link led */ | |
7f02c4ad YR |
7666 | bnx2x_set_led(params, vars, LED_MODE_OFF, 0); |
7667 | ||
de6eae1f YR |
7668 | if (reset_ext_phy) { |
7669 | for (phy_index = EXT_PHY1; phy_index < params->num_phys; | |
7670 | phy_index++) { | |
7671 | if (params->phy[phy_index].link_reset) | |
7672 | params->phy[phy_index].link_reset( | |
7673 | ¶ms->phy[phy_index], | |
7674 | params); | |
cf1d972c YR |
7675 | if (params->phy[phy_index].flags & |
7676 | FLAGS_REARM_LATCH_SIGNAL) | |
7677 | clear_latch_ind = 1; | |
b7737c9b | 7678 | } |
b7737c9b YR |
7679 | } |
7680 | ||
cf1d972c YR |
7681 | if (clear_latch_ind) { |
7682 | /* Clear latching indication */ | |
7683 | bnx2x_rearm_latch_signal(bp, port, 0); | |
7684 | bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, | |
7685 | 1 << NIG_LATCH_BC_ENABLE_MI_INT); | |
7686 | } | |
de6eae1f YR |
7687 | if (params->phy[INT_PHY].link_reset) |
7688 | params->phy[INT_PHY].link_reset( | |
7689 | ¶ms->phy[INT_PHY], params); | |
7690 | /* reset BigMac */ | |
7691 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | |
7692 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | |
b7737c9b | 7693 | |
de6eae1f YR |
7694 | /* disable nig ingress interface */ |
7695 | REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); | |
7696 | REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); | |
7697 | REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); | |
7698 | REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | |
7699 | vars->link_up = 0; | |
b7737c9b YR |
7700 | return 0; |
7701 | } | |
7702 | ||
de6eae1f YR |
7703 | /****************************************************************************/ |
7704 | /* Common function */ | |
7705 | /****************************************************************************/ | |
f2e0899f DK |
7706 | static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, |
7707 | u32 shmem_base_path[], | |
7708 | u32 shmem2_base_path[], u8 phy_index, | |
7709 | u32 chip_id) | |
6bbca910 | 7710 | { |
e10bc84d YR |
7711 | struct bnx2x_phy phy[PORT_MAX]; |
7712 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
6bbca910 | 7713 | u16 val; |
c8e64df4 | 7714 | s8 port = 0; |
f2e0899f | 7715 | s8 port_of_path = 0; |
c8e64df4 YR |
7716 | u32 swap_val, swap_override; |
7717 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); | |
7718 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
7719 | port ^= (swap_val && swap_override); | |
7720 | bnx2x_ext_phy_hw_reset(bp, port); | |
6bbca910 YR |
7721 | /* PART1 - Reset both phys */ |
7722 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
7723 | u32 shmem_base, shmem2_base; |
7724 | /* In E2, same phy is using for port0 of the two paths */ | |
7725 | if (CHIP_IS_E2(bp)) { | |
7726 | shmem_base = shmem_base_path[port]; | |
7727 | shmem2_base = shmem2_base_path[port]; | |
7728 | port_of_path = 0; | |
7729 | } else { | |
7730 | shmem_base = shmem_base_path[0]; | |
7731 | shmem2_base = shmem2_base_path[0]; | |
7732 | port_of_path = port; | |
7733 | } | |
7734 | ||
6bbca910 | 7735 | /* Extract the ext phy address for the port */ |
a22f0788 | 7736 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 7737 | port_of_path, &phy[port]) != |
e10bc84d YR |
7738 | 0) { |
7739 | DP(NETIF_MSG_LINK, "populate_phy failed\n"); | |
7740 | return -EINVAL; | |
7741 | } | |
6bbca910 | 7742 | /* disable attentions */ |
6a71bbe0 YR |
7743 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
7744 | port_of_path*4, | |
cd88ccee YR |
7745 | (NIG_MASK_XGXS0_LINK_STATUS | |
7746 | NIG_MASK_XGXS0_LINK10G | | |
7747 | NIG_MASK_SERDES0_LINK_STATUS | | |
7748 | NIG_MASK_MI_INT)); | |
6bbca910 | 7749 | |
6bbca910 YR |
7750 | /* Need to take the phy out of low power mode in order |
7751 | to write to access its registers */ | |
7752 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee YR |
7753 | MISC_REGISTERS_GPIO_OUTPUT_HIGH, |
7754 | port); | |
6bbca910 YR |
7755 | |
7756 | /* Reset the phy */ | |
e10bc84d | 7757 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee YR |
7758 | MDIO_PMA_DEVAD, |
7759 | MDIO_PMA_REG_CTRL, | |
7760 | 1<<15); | |
6bbca910 YR |
7761 | } |
7762 | ||
7763 | /* Add delay of 150ms after reset */ | |
7764 | msleep(150); | |
7765 | ||
e10bc84d YR |
7766 | if (phy[PORT_0].addr & 0x1) { |
7767 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
7768 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
7769 | } else { | |
7770 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
7771 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
7772 | } | |
7773 | ||
6bbca910 YR |
7774 | /* PART2 - Download firmware to both phys */ |
7775 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f2e0899f DK |
7776 | if (CHIP_IS_E2(bp)) |
7777 | port_of_path = 0; | |
7778 | else | |
7779 | port_of_path = port; | |
6bbca910 | 7780 | |
f2e0899f DK |
7781 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", |
7782 | phy_blk[port]->addr); | |
5c99274b YR |
7783 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
7784 | port_of_path)) | |
6bbca910 | 7785 | return -EINVAL; |
6bbca910 YR |
7786 | |
7787 | /* Only set bit 10 = 1 (Tx power down) */ | |
e10bc84d | 7788 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
7789 | MDIO_PMA_DEVAD, |
7790 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 YR |
7791 | |
7792 | /* Phase1 of TX_POWER_DOWN reset */ | |
e10bc84d | 7793 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
7794 | MDIO_PMA_DEVAD, |
7795 | MDIO_PMA_REG_TX_POWER_DOWN, | |
7796 | (val | 1<<10)); | |
6bbca910 YR |
7797 | } |
7798 | ||
2cf7acf9 YR |
7799 | /* |
7800 | * Toggle Transmitter: Power down and then up with 600ms delay | |
7801 | * between | |
7802 | */ | |
6bbca910 YR |
7803 | msleep(600); |
7804 | ||
7805 | /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ | |
7806 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { | |
f5372251 | 7807 | /* Phase2 of POWER_DOWN_RESET */ |
6bbca910 | 7808 | /* Release bit 10 (Release Tx power down) */ |
e10bc84d | 7809 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
7810 | MDIO_PMA_DEVAD, |
7811 | MDIO_PMA_REG_TX_POWER_DOWN, &val); | |
6bbca910 | 7812 | |
e10bc84d | 7813 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
7814 | MDIO_PMA_DEVAD, |
7815 | MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); | |
6bbca910 YR |
7816 | msleep(15); |
7817 | ||
7818 | /* Read modify write the SPI-ROM version select register */ | |
e10bc84d | 7819 | bnx2x_cl45_read(bp, phy_blk[port], |
cd88ccee YR |
7820 | MDIO_PMA_DEVAD, |
7821 | MDIO_PMA_REG_EDC_FFE_MAIN, &val); | |
e10bc84d | 7822 | bnx2x_cl45_write(bp, phy_blk[port], |
cd88ccee YR |
7823 | MDIO_PMA_DEVAD, |
7824 | MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); | |
6bbca910 YR |
7825 | |
7826 | /* set GPIO2 back to LOW */ | |
7827 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | |
cd88ccee | 7828 | MISC_REGISTERS_GPIO_OUTPUT_LOW, port); |
6bbca910 YR |
7829 | } |
7830 | return 0; | |
6bbca910 | 7831 | } |
f2e0899f DK |
7832 | static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, |
7833 | u32 shmem_base_path[], | |
7834 | u32 shmem2_base_path[], u8 phy_index, | |
7835 | u32 chip_id) | |
de6eae1f YR |
7836 | { |
7837 | u32 val; | |
7838 | s8 port; | |
7839 | struct bnx2x_phy phy; | |
7840 | /* Use port1 because of the static port-swap */ | |
7841 | /* Enable the module detection interrupt */ | |
7842 | val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); | |
7843 | val |= ((1<<MISC_REGISTERS_GPIO_3)| | |
7844 | (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); | |
7845 | REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); | |
7846 | ||
650154bf | 7847 | bnx2x_ext_phy_hw_reset(bp, 0); |
de6eae1f YR |
7848 | msleep(5); |
7849 | for (port = 0; port < PORT_MAX; port++) { | |
f2e0899f DK |
7850 | u32 shmem_base, shmem2_base; |
7851 | ||
7852 | /* In E2, same phy is using for port0 of the two paths */ | |
7853 | if (CHIP_IS_E2(bp)) { | |
7854 | shmem_base = shmem_base_path[port]; | |
7855 | shmem2_base = shmem2_base_path[port]; | |
7856 | } else { | |
7857 | shmem_base = shmem_base_path[0]; | |
7858 | shmem2_base = shmem2_base_path[0]; | |
7859 | } | |
de6eae1f | 7860 | /* Extract the ext phy address for the port */ |
a22f0788 | 7861 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
de6eae1f YR |
7862 | port, &phy) != |
7863 | 0) { | |
7864 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7865 | return -EINVAL; | |
7866 | } | |
7867 | ||
7868 | /* Reset phy*/ | |
7869 | bnx2x_cl45_write(bp, &phy, | |
7870 | MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); | |
7871 | ||
7872 | ||
7873 | /* Set fault module detected LED on */ | |
7874 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, | |
cd88ccee YR |
7875 | MISC_REGISTERS_GPIO_HIGH, |
7876 | port); | |
de6eae1f YR |
7877 | } |
7878 | ||
7879 | return 0; | |
7880 | } | |
f2e0899f DK |
7881 | static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, |
7882 | u32 shmem_base_path[], | |
7883 | u32 shmem2_base_path[], u8 phy_index, | |
7884 | u32 chip_id) | |
4d295db0 | 7885 | { |
a22f0788 | 7886 | s8 port; |
4d295db0 | 7887 | u32 swap_val, swap_override; |
e10bc84d YR |
7888 | struct bnx2x_phy phy[PORT_MAX]; |
7889 | struct bnx2x_phy *phy_blk[PORT_MAX]; | |
f2e0899f | 7890 | s8 port_of_path; |
cd88ccee YR |
7891 | swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); |
7892 | swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); | |
4d295db0 | 7893 | |
a22f0788 | 7894 | port = 1; |
4d295db0 | 7895 | |
a22f0788 YR |
7896 | bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override)); |
7897 | ||
7898 | /* Calculate the port based on port swap */ | |
7899 | port ^= (swap_val && swap_override); | |
7900 | ||
7901 | msleep(5); | |
bc7f0a05 | 7902 | |
4d295db0 | 7903 | /* PART1 - Reset both phys */ |
a22f0788 | 7904 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
f2e0899f DK |
7905 | u32 shmem_base, shmem2_base; |
7906 | ||
7907 | /* In E2, same phy is using for port0 of the two paths */ | |
7908 | if (CHIP_IS_E2(bp)) { | |
7909 | shmem_base = shmem_base_path[port]; | |
7910 | shmem2_base = shmem2_base_path[port]; | |
7911 | port_of_path = 0; | |
7912 | } else { | |
7913 | shmem_base = shmem_base_path[0]; | |
7914 | shmem2_base = shmem2_base_path[0]; | |
7915 | port_of_path = port; | |
7916 | } | |
7917 | ||
4d295db0 | 7918 | /* Extract the ext phy address for the port */ |
a22f0788 | 7919 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
f2e0899f | 7920 | port_of_path, &phy[port]) != |
e10bc84d YR |
7921 | 0) { |
7922 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
7923 | return -EINVAL; | |
7924 | } | |
4d295db0 | 7925 | /* disable attentions */ |
f2e0899f DK |
7926 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + |
7927 | port_of_path*4, | |
7928 | (NIG_MASK_XGXS0_LINK_STATUS | | |
7929 | NIG_MASK_XGXS0_LINK10G | | |
7930 | NIG_MASK_SERDES0_LINK_STATUS | | |
7931 | NIG_MASK_MI_INT)); | |
4d295db0 | 7932 | |
4d295db0 EG |
7933 | |
7934 | /* Reset the phy */ | |
e10bc84d | 7935 | bnx2x_cl45_write(bp, &phy[port], |
cd88ccee | 7936 | MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); |
4d295db0 EG |
7937 | } |
7938 | ||
7939 | /* Add delay of 150ms after reset */ | |
7940 | msleep(150); | |
e10bc84d YR |
7941 | if (phy[PORT_0].addr & 0x1) { |
7942 | phy_blk[PORT_0] = &(phy[PORT_1]); | |
7943 | phy_blk[PORT_1] = &(phy[PORT_0]); | |
7944 | } else { | |
7945 | phy_blk[PORT_0] = &(phy[PORT_0]); | |
7946 | phy_blk[PORT_1] = &(phy[PORT_1]); | |
7947 | } | |
4d295db0 | 7948 | /* PART2 - Download firmware to both phys */ |
e10bc84d | 7949 | for (port = PORT_MAX - 1; port >= PORT_0; port--) { |
cd88ccee | 7950 | if (CHIP_IS_E2(bp)) |
f2e0899f DK |
7951 | port_of_path = 0; |
7952 | else | |
7953 | port_of_path = port; | |
7954 | DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", | |
7955 | phy_blk[port]->addr); | |
5c99274b YR |
7956 | if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], |
7957 | port_of_path)) | |
4d295db0 | 7958 | return -EINVAL; |
4d295db0 | 7959 | |
5c99274b | 7960 | } |
4d295db0 EG |
7961 | return 0; |
7962 | } | |
7963 | ||
f2e0899f DK |
7964 | static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], |
7965 | u32 shmem2_base_path[], u8 phy_index, | |
7966 | u32 ext_phy_type, u32 chip_id) | |
6bbca910 YR |
7967 | { |
7968 | u8 rc = 0; | |
6bbca910 YR |
7969 | |
7970 | switch (ext_phy_type) { | |
7971 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: | |
f2e0899f DK |
7972 | rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, |
7973 | shmem2_base_path, | |
7974 | phy_index, chip_id); | |
6bbca910 | 7975 | break; |
4d295db0 EG |
7976 | |
7977 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | |
7978 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | |
f2e0899f DK |
7979 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |
7980 | shmem2_base_path, | |
7981 | phy_index, chip_id); | |
4d295db0 EG |
7982 | break; |
7983 | ||
589abe3a | 7984 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
2cf7acf9 YR |
7985 | /* |
7986 | * GPIO1 affects both ports, so there's need to pull | |
7987 | * it for single port alone | |
7988 | */ | |
f2e0899f DK |
7989 | rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, |
7990 | shmem2_base_path, | |
7991 | phy_index, chip_id); | |
a22f0788 YR |
7992 | break; |
7993 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: | |
7994 | rc = -EINVAL; | |
4f60dab1 | 7995 | break; |
6bbca910 YR |
7996 | default: |
7997 | DP(NETIF_MSG_LINK, | |
2cf7acf9 YR |
7998 | "ext_phy 0x%x common init not required\n", |
7999 | ext_phy_type); | |
6bbca910 YR |
8000 | break; |
8001 | } | |
8002 | ||
8003 | return rc; | |
8004 | } | |
8005 | ||
f2e0899f DK |
8006 | u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], |
8007 | u32 shmem2_base_path[], u32 chip_id) | |
a22f0788 YR |
8008 | { |
8009 | u8 rc = 0; | |
b21a3424 | 8010 | u32 phy_ver; |
a22f0788 YR |
8011 | u8 phy_index; |
8012 | u32 ext_phy_type, ext_phy_config; | |
8013 | DP(NETIF_MSG_LINK, "Begin common phy init\n"); | |
8014 | ||
8015 | if (CHIP_REV_IS_EMUL(bp)) | |
8016 | return 0; | |
8017 | ||
b21a3424 YR |
8018 | /* Check if common init was already done */ |
8019 | phy_ver = REG_RD(bp, shmem_base_path[0] + | |
8020 | offsetof(struct shmem_region, | |
8021 | port_mb[PORT_0].ext_phy_fw_version)); | |
8022 | if (phy_ver) { | |
8023 | DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", | |
8024 | phy_ver); | |
8025 | return 0; | |
8026 | } | |
8027 | ||
a22f0788 YR |
8028 | /* Read the ext_phy_type for arbitrary port(0) */ |
8029 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
8030 | phy_index++) { | |
8031 | ext_phy_config = bnx2x_get_ext_phy_config(bp, | |
f2e0899f | 8032 | shmem_base_path[0], |
a22f0788 YR |
8033 | phy_index, 0); |
8034 | ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); | |
f2e0899f DK |
8035 | rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, |
8036 | shmem2_base_path, | |
8037 | phy_index, ext_phy_type, | |
8038 | chip_id); | |
a22f0788 YR |
8039 | } |
8040 | return rc; | |
8041 | } | |
d90d96ba | 8042 | |
a22f0788 | 8043 | u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) |
d90d96ba YR |
8044 | { |
8045 | u8 phy_index; | |
8046 | struct bnx2x_phy phy; | |
8047 | for (phy_index = INT_PHY; phy_index < MAX_PHYS; | |
8048 | phy_index++) { | |
a22f0788 | 8049 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
8050 | 0, &phy) != 0) { |
8051 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
8052 | return 0; | |
8053 | } | |
8054 | ||
8055 | if (phy.flags & FLAGS_HW_LOCK_REQUIRED) | |
8056 | return 1; | |
8057 | } | |
8058 | return 0; | |
8059 | } | |
8060 | ||
8061 | u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, | |
8062 | u32 shmem_base, | |
a22f0788 | 8063 | u32 shmem2_base, |
d90d96ba YR |
8064 | u8 port) |
8065 | { | |
8066 | u8 phy_index, fan_failure_det_req = 0; | |
8067 | struct bnx2x_phy phy; | |
8068 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
8069 | phy_index++) { | |
a22f0788 | 8070 | if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, |
d90d96ba YR |
8071 | port, &phy) |
8072 | != 0) { | |
8073 | DP(NETIF_MSG_LINK, "populate phy failed\n"); | |
8074 | return 0; | |
8075 | } | |
8076 | fan_failure_det_req |= (phy.flags & | |
8077 | FLAGS_FAN_FAILURE_DET_REQ); | |
8078 | } | |
8079 | return fan_failure_det_req; | |
8080 | } | |
8081 | ||
8082 | void bnx2x_hw_reset_phy(struct link_params *params) | |
8083 | { | |
8084 | u8 phy_index; | |
8085 | for (phy_index = EXT_PHY1; phy_index < MAX_PHYS; | |
8086 | phy_index++) { | |
8087 | if (params->phy[phy_index].hw_reset) { | |
8088 | params->phy[phy_index].hw_reset( | |
8089 | ¶ms->phy[phy_index], | |
8090 | params); | |
8091 | params->phy[phy_index] = phy_null; | |
8092 | } | |
8093 | } | |
8094 | } |