Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
5de92408 | 3 | * Copyright (c) 2007-2011 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
ec6ba945 VZ |
16 | #include <linux/netdevice.h> |
17 | #include <linux/types.h> | |
a2fbb9ea | 18 | |
34f80b04 EG |
19 | /* compilation time flags */ |
20 | ||
21 | /* define this to make the driver freeze on error to allow getting debug info | |
22 | * (you will need to reboot afterwards) */ | |
23 | /* #define BNX2X_STOP_ON_ERROR */ | |
24 | ||
5de92408 DK |
25 | #define DRV_MODULE_VERSION "1.62.12-0" |
26 | #define DRV_MODULE_RELDATE "2011/03/20" | |
de0c62db DK |
27 | #define BNX2X_BC_VER 0x040200 |
28 | ||
1ac218c8 VZ |
29 | #define BNX2X_MULTI_QUEUE |
30 | ||
31 | #define BNX2X_NEW_NAPI | |
32 | ||
785b9b1a | 33 | #if defined(CONFIG_DCB) |
98507672 | 34 | #define BCM_DCBNL |
785b9b1a | 35 | #endif |
993ac7b5 MC |
36 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
37 | #define BCM_CNIC 1 | |
5d1e859c | 38 | #include "../cnic_if.h" |
993ac7b5 | 39 | #endif |
0c6671b0 | 40 | |
1ac218c8 VZ |
41 | #ifdef BCM_CNIC |
42 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
43 | #define BNX2X_MSIX_VEC_FP_START 2 | |
44 | #else | |
45 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
46 | #define BNX2X_MSIX_VEC_FP_START 1 | |
47 | #endif | |
01cd4528 EG |
48 | |
49 | #include <linux/mdio.h> | |
9f6c9258 | 50 | #include <linux/pci.h> |
359d8b15 EG |
51 | #include "bnx2x_reg.h" |
52 | #include "bnx2x_fw_defs.h" | |
53 | #include "bnx2x_hsi.h" | |
54 | #include "bnx2x_link.h" | |
e4901dde | 55 | #include "bnx2x_dcb.h" |
6c719d00 | 56 | #include "bnx2x_stats.h" |
359d8b15 | 57 | |
a2fbb9ea ET |
58 | /* error/debug prints */ |
59 | ||
34f80b04 | 60 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
61 | |
62 | /* for messages that are currently off */ | |
34f80b04 EG |
63 | #define BNX2X_MSG_OFF 0 |
64 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
65 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
66 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
67 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
68 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
69 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 70 | |
34f80b04 | 71 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
72 | |
73 | /* regular debug print */ | |
7995c64e JP |
74 | #define DP(__mask, __fmt, __args...) \ |
75 | do { \ | |
76 | if (bp->msg_enable & (__mask)) \ | |
77 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ | |
78 | __func__, __LINE__, \ | |
79 | bp->dev ? (bp->dev->name) : "?", \ | |
80 | ##__args); \ | |
81 | } while (0) | |
a2fbb9ea | 82 | |
34f80b04 | 83 | /* errors debug print */ |
7995c64e JP |
84 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
85 | do { \ | |
86 | if (netif_msg_probe(bp)) \ | |
87 | pr_err("[%s:%d(%s)]" __fmt, \ | |
88 | __func__, __LINE__, \ | |
89 | bp->dev ? (bp->dev->name) : "?", \ | |
90 | ##__args); \ | |
91 | } while (0) | |
a2fbb9ea | 92 | |
34f80b04 | 93 | /* for errors (never masked) */ |
7995c64e JP |
94 | #define BNX2X_ERR(__fmt, __args...) \ |
95 | do { \ | |
96 | pr_err("[%s:%d(%s)]" __fmt, \ | |
97 | __func__, __LINE__, \ | |
98 | bp->dev ? (bp->dev->name) : "?", \ | |
99 | ##__args); \ | |
cdaa7cb8 VZ |
100 | } while (0) |
101 | ||
102 | #define BNX2X_ERROR(__fmt, __args...) do { \ | |
103 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ | |
104 | } while (0) | |
105 | ||
f1410647 | 106 | |
a2fbb9ea | 107 | /* before we have a dev->name use dev_info() */ |
7995c64e JP |
108 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
109 | do { \ | |
110 | if (netif_msg_probe(bp)) \ | |
111 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
112 | } while (0) | |
a2fbb9ea | 113 | |
6c719d00 | 114 | void bnx2x_panic_dump(struct bnx2x *bp); |
a2fbb9ea ET |
115 | |
116 | #ifdef BNX2X_STOP_ON_ERROR | |
117 | #define bnx2x_panic() do { \ | |
118 | bp->panic = 1; \ | |
119 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 120 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
121 | bnx2x_panic_dump(bp); \ |
122 | } while (0) | |
123 | #else | |
124 | #define bnx2x_panic() do { \ | |
e3553b29 | 125 | bp->panic = 1; \ |
a2fbb9ea ET |
126 | BNX2X_ERR("driver assert\n"); \ |
127 | bnx2x_panic_dump(bp); \ | |
128 | } while (0) | |
129 | #endif | |
130 | ||
523224a3 | 131 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
6e30dd4e | 132 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
a2fbb9ea | 133 | |
34f80b04 EG |
134 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
135 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
136 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 137 | |
a2fbb9ea | 138 | |
523224a3 | 139 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 140 | |
34f80b04 EG |
141 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
142 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 143 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
144 | |
145 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 146 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 147 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 148 | |
34f80b04 EG |
149 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
150 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 151 | |
c18487ee YR |
152 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
153 | do { \ | |
154 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 155 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
156 | } while (0) |
157 | ||
34f80b04 | 158 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 159 | do { \ |
573f2035 | 160 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
161 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
162 | offset, len32); \ | |
163 | } while (0) | |
164 | ||
523224a3 DK |
165 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
166 | REG_WR_DMAE(bp, offset, valp, len32) | |
167 | ||
3359fced | 168 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
169 | do { \ |
170 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
171 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
172 | } while (0) | |
173 | ||
34f80b04 EG |
174 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
175 | offsetof(struct shmem_region, field)) | |
176 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
177 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 178 | |
2691d51d EG |
179 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
180 | offsetof(struct shmem2_region, field)) | |
181 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
182 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
183 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
184 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 185 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 186 | offsetof(struct mf2_cfg, field)) |
2691d51d | 187 | |
523224a3 DK |
188 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
189 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
190 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 191 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 192 | |
f2e0899f DK |
193 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
194 | (SHMEM2_RD((bp), size) > \ | |
195 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 196 | |
345b5d52 | 197 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 198 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 199 | |
523224a3 DK |
200 | /* SP SB indices */ |
201 | ||
202 | /* General SP events - stats query, cfc delete, etc */ | |
203 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
204 | ||
205 | /* EQ completions */ | |
206 | #define HC_SP_INDEX_EQ_CONS 7 | |
207 | ||
ec6ba945 VZ |
208 | /* FCoE L2 connection completions */ |
209 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
210 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
211 | /* iSCSI L2 */ |
212 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
213 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
214 | ||
ec6ba945 VZ |
215 | /* Special clients parameters */ |
216 | ||
217 | /* SB indices */ | |
218 | /* FCoE L2 */ | |
219 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
220 | (&bp->def_status_blk->sp_sb.\ | |
221 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
222 | ||
223 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
224 | (&bp->def_status_blk->sp_sb.\ | |
225 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
226 | ||
523224a3 DK |
227 | /** |
228 | * CIDs and CLIDs: | |
229 | * CLIDs below is a CLID for func 0, then the CLID for other | |
230 | * functions will be calculated by the formula: | |
231 | * | |
232 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
233 | * | |
234 | */ | |
235 | /* iSCSI L2 */ | |
236 | #define BNX2X_ISCSI_ETH_CL_ID 17 | |
237 | #define BNX2X_ISCSI_ETH_CID 17 | |
238 | ||
ec6ba945 VZ |
239 | /* FCoE L2 */ |
240 | #define BNX2X_FCOE_ETH_CL_ID 18 | |
241 | #define BNX2X_FCOE_ETH_CID 18 | |
242 | ||
523224a3 DK |
243 | /** Additional rings budgeting */ |
244 | #ifdef BCM_CNIC | |
245 | #define CNIC_CONTEXT_USE 1 | |
ec6ba945 | 246 | #define FCOE_CONTEXT_USE 1 |
523224a3 DK |
247 | #else |
248 | #define CNIC_CONTEXT_USE 0 | |
ec6ba945 | 249 | #define FCOE_CONTEXT_USE 0 |
523224a3 | 250 | #endif /* BCM_CNIC */ |
ec6ba945 | 251 | #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE) |
523224a3 | 252 | |
72fd0718 VZ |
253 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
254 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
255 | ||
523224a3 DK |
256 | #define SM_RX_ID 0 |
257 | #define SM_TX_ID 1 | |
a2fbb9ea | 258 | |
7a9b2557 | 259 | /* fast path */ |
a2fbb9ea | 260 | |
a2fbb9ea | 261 | struct sw_rx_bd { |
34f80b04 | 262 | struct sk_buff *skb; |
1a983142 | 263 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
264 | }; |
265 | ||
266 | struct sw_tx_bd { | |
34f80b04 EG |
267 | struct sk_buff *skb; |
268 | u16 first_bd; | |
ca00392c EG |
269 | u8 flags; |
270 | /* Set on the first BD descriptor when there is a split BD */ | |
271 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
272 | }; |
273 | ||
7a9b2557 VZ |
274 | struct sw_rx_page { |
275 | struct page *page; | |
1a983142 | 276 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
277 | }; |
278 | ||
ca00392c EG |
279 | union db_prod { |
280 | struct doorbell_set_prod data; | |
281 | u32 raw; | |
282 | }; | |
283 | ||
7a9b2557 VZ |
284 | |
285 | /* MC hsi */ | |
286 | #define BCM_PAGE_SHIFT 12 | |
287 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
288 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
289 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
290 | ||
291 | #define PAGES_PER_SGE_SHIFT 0 | |
292 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
4f40f2cb EG |
293 | #define SGE_PAGE_SIZE PAGE_SIZE |
294 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
5b6402d1 | 295 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
7a9b2557 VZ |
296 | |
297 | /* SGE ring related macros */ | |
298 | #define NUM_RX_SGE_PAGES 2 | |
299 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
300 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
33471629 | 301 | /* RX_SGE_CNT is promised to be a power of 2 */ |
7a9b2557 VZ |
302 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
303 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
304 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
305 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
306 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
307 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
308 | ||
309 | /* SGE producer mask related macros */ | |
310 | /* Number of bits in one sge_mask array element */ | |
311 | #define RX_SGE_MASK_ELEM_SZ 64 | |
312 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
313 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
314 | ||
315 | /* Creates a bitmask of all ones in less significant bits. | |
316 | idx - index of the most significant bit in the created mask */ | |
317 | #define RX_SGE_ONES_MASK(idx) \ | |
318 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
319 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
320 | ||
321 | /* Number of u64 elements in SGE mask array */ | |
322 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
323 | RX_SGE_MASK_ELEM_SZ) | |
324 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
325 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
326 | ||
523224a3 DK |
327 | union host_hc_status_block { |
328 | /* pointer to fp status block e1x */ | |
329 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
330 | /* pointer to fp status block e2 */ |
331 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 332 | }; |
7a9b2557 | 333 | |
a2fbb9ea ET |
334 | struct bnx2x_fastpath { |
335 | ||
d6214d7a | 336 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 337 | struct napi_struct napi; |
f85582f8 | 338 | union host_hc_status_block status_blk; |
523224a3 DK |
339 | /* chip independed shortcuts into sb structure */ |
340 | __le16 *sb_index_values; | |
341 | __le16 *sb_running_index; | |
342 | /* chip independed shortcut into rx_prods_offset memory */ | |
343 | u32 ustorm_rx_prods_offset; | |
344 | ||
a8c94b91 VZ |
345 | u32 rx_buf_size; |
346 | ||
34f80b04 | 347 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 348 | |
34f80b04 | 349 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea | 350 | |
ca00392c | 351 | union eth_tx_bd_types *tx_desc_ring; |
34f80b04 | 352 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 353 | |
7a9b2557 VZ |
354 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
355 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
356 | |
357 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 358 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
359 | |
360 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
361 | dma_addr_t rx_comp_mapping; |
362 | ||
7a9b2557 VZ |
363 | /* SGE ring */ |
364 | struct eth_rx_sge *rx_sge_ring; | |
365 | dma_addr_t rx_sge_mapping; | |
366 | ||
367 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
368 | ||
34f80b04 EG |
369 | int state; |
370 | #define BNX2X_FP_STATE_CLOSED 0 | |
371 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
372 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
373 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
374 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
375 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
523224a3 DK |
376 | #define BNX2X_FP_STATE_TERMINATING 0xd0000 |
377 | #define BNX2X_FP_STATE_TERMINATED 0xe0000 | |
34f80b04 | 378 | |
f85582f8 DK |
379 | u8 index; /* number in fp array */ |
380 | u8 cl_id; /* eth client id */ | |
523224a3 DK |
381 | u8 cl_qzone_id; |
382 | u8 fw_sb_id; /* status block number in FW */ | |
383 | u8 igu_sb_id; /* status block number in HW */ | |
384 | u32 cid; | |
34f80b04 | 385 | |
ca00392c EG |
386 | union db_prod tx_db; |
387 | ||
34f80b04 EG |
388 | u16 tx_pkt_prod; |
389 | u16 tx_pkt_cons; | |
390 | u16 tx_bd_prod; | |
391 | u16 tx_bd_cons; | |
4781bfad | 392 | __le16 *tx_cons_sb; |
34f80b04 | 393 | |
523224a3 | 394 | __le16 fp_hc_idx; |
34f80b04 EG |
395 | |
396 | u16 rx_bd_prod; | |
397 | u16 rx_bd_cons; | |
398 | u16 rx_comp_prod; | |
399 | u16 rx_comp_cons; | |
7a9b2557 VZ |
400 | u16 rx_sge_prod; |
401 | /* The last maximal completed SGE */ | |
402 | u16 last_max_sge; | |
4781bfad | 403 | __le16 *rx_cons_sb; |
523224a3 | 404 | |
34f80b04 | 405 | unsigned long tx_pkt, |
a2fbb9ea | 406 | rx_pkt, |
66e855f3 | 407 | rx_calls; |
ab6ad5a4 | 408 | |
7a9b2557 VZ |
409 | /* TPA related */ |
410 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
411 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
412 | #define BNX2X_TPA_START 1 | |
413 | #define BNX2X_TPA_STOP 2 | |
414 | u8 disable_tpa; | |
415 | #ifdef BNX2X_STOP_ON_ERROR | |
416 | u64 tpa_queue_used; | |
417 | #endif | |
a2fbb9ea | 418 | |
de832a55 EG |
419 | struct tstorm_per_client_stats old_tclient; |
420 | struct ustorm_per_client_stats old_uclient; | |
421 | struct xstorm_per_client_stats old_xclient; | |
422 | struct bnx2x_eth_q_stats eth_q_stats; | |
423 | ||
ca00392c EG |
424 | /* The size is calculated using the following: |
425 | sizeof name field from netdev structure + | |
426 | 4 ('-Xx-' string) + | |
427 | 4 (for the digits and to make it DWORD aligned) */ | |
428 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
429 | char name[FP_NAME_SIZE]; | |
34f80b04 | 430 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
431 | }; |
432 | ||
34f80b04 | 433 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
a8c94b91 VZ |
434 | |
435 | /* Use 2500 as a mini-jumbo MTU for FCoE */ | |
436 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 | |
437 | ||
ec6ba945 VZ |
438 | #ifdef BCM_CNIC |
439 | /* FCoE L2 `fastpath' is right after the eth entries */ | |
440 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) | |
441 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) | |
442 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
443 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) | |
444 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) | |
445 | #else | |
446 | #define IS_FCOE_FP(fp) false | |
447 | #define IS_FCOE_IDX(idx) false | |
448 | #endif | |
7a9b2557 VZ |
449 | |
450 | ||
451 | /* MC hsi */ | |
452 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
453 | #define RX_COPY_THRESH 92 | |
454 | ||
455 | #define NUM_TX_RINGS 16 | |
ca00392c | 456 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
7a9b2557 VZ |
457 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
458 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
459 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
460 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
523224a3 DK |
461 | #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL |
462 | #define INIT_TX_RING_SIZE MAX_TX_AVAIL | |
7a9b2557 VZ |
463 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
464 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
465 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
466 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
467 | ||
468 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
469 | #define NUM_RX_RINGS 8 | |
470 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
471 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
472 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
473 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
474 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
475 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
b3b83c3f DK |
476 | #define MIN_RX_SIZE_TPA 72 |
477 | #define MIN_RX_SIZE_NONTPA 10 | |
523224a3 DK |
478 | #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL |
479 | #define INIT_RX_RING_SIZE MAX_RX_AVAIL | |
7a9b2557 VZ |
480 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
481 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
482 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
483 | ||
484 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
485 | 4 times more pages for CQ ring in order to keep it balanced with | |
486 | BD ring */ | |
487 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
488 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
489 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
490 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
491 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
492 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
493 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
494 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
495 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
496 | ||
497 | ||
33471629 | 498 | /* This is needed for determining of last_max */ |
34f80b04 | 499 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
a2fbb9ea | 500 | |
7a9b2557 VZ |
501 | #define __SGE_MASK_SET_BIT(el, bit) \ |
502 | do { \ | |
503 | el = ((el) | ((u64)0x1 << (bit))); \ | |
504 | } while (0) | |
505 | ||
506 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
507 | do { \ | |
508 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
509 | } while (0) | |
510 | ||
511 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
512 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
513 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
514 | ||
515 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
516 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
517 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
518 | ||
519 | ||
520 | /* used on a CID received from the HW */ | |
521 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
522 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
523 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
524 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
525 | ||
bb2a0f7a YG |
526 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
527 | le32_to_cpu((bd)->addr_lo)) | |
528 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
529 | ||
523224a3 DK |
530 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
531 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
7a9b2557 VZ |
532 | #define DPM_TRIGER_TYPE 0x40 |
533 | #define DOORBELL(bp, cid, val) \ | |
534 | do { \ | |
523224a3 | 535 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
536 | DPM_TRIGER_TYPE); \ |
537 | } while (0) | |
538 | ||
539 | ||
540 | /* TX CSUM helpers */ | |
541 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
542 | skb->csum_offset) | |
543 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
544 | skb->csum_offset)) | |
545 | ||
546 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
547 | ||
548 | #define XMIT_PLAIN 0 | |
549 | #define XMIT_CSUM_V4 0x1 | |
550 | #define XMIT_CSUM_V6 0x2 | |
551 | #define XMIT_CSUM_TCP 0x4 | |
552 | #define XMIT_GSO_V4 0x8 | |
553 | #define XMIT_GSO_V6 0x10 | |
554 | ||
555 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
556 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
557 | ||
558 | ||
34f80b04 | 559 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 560 | |
34f80b04 | 561 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 562 | |
7a9b2557 VZ |
563 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
564 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
565 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
566 | (TPA_TYPE_START | TPA_TYPE_END)) | |
567 | ||
1adcd8be EG |
568 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
569 | ||
570 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
571 | (!((cqe)->fast_path_cqe.status_flags & \ | |
572 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
573 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
574 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
575 | ||
576 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
577 | (!((cqe)->fast_path_cqe.status_flags & \ | |
578 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
579 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
580 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
581 | ||
582 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
583 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 584 | |
052a38e0 EG |
585 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
586 | (((le16_to_cpu(flags) & \ | |
587 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
588 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
589 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 590 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 591 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 592 | |
523224a3 DK |
593 | #define U_SB_ETH_RX_CQ_INDEX 1 |
594 | #define U_SB_ETH_RX_BD_INDEX 2 | |
595 | #define C_SB_ETH_TX_CQ_INDEX 5 | |
a2fbb9ea | 596 | |
34f80b04 | 597 | #define BNX2X_RX_SB_INDEX \ |
523224a3 | 598 | (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX]) |
a2fbb9ea | 599 | |
34f80b04 | 600 | #define BNX2X_TX_SB_INDEX \ |
523224a3 | 601 | (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX]) |
7a9b2557 VZ |
602 | |
603 | /* end of fast path */ | |
604 | ||
34f80b04 | 605 | /* common */ |
a2fbb9ea | 606 | |
34f80b04 | 607 | struct bnx2x_common { |
a2fbb9ea | 608 | |
ad8d3948 | 609 | u32 chip_id; |
a2fbb9ea | 610 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 611 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 612 | |
34f80b04 | 613 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
614 | #define CHIP_NUM_57710 0x164e |
615 | #define CHIP_NUM_57711 0x164f | |
616 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f DK |
617 | #define CHIP_NUM_57712 0x1662 |
618 | #define CHIP_NUM_57712E 0x1663 | |
ad8d3948 EG |
619 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
620 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
621 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f DK |
622 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
623 | #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E) | |
ad8d3948 EG |
624 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
625 | CHIP_IS_57711E(bp)) | |
f2e0899f DK |
626 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
627 | CHIP_IS_57712E(bp)) | |
628 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) | |
629 | #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp)) | |
ad8d3948 | 630 | |
34f80b04 | 631 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
632 | #define CHIP_REV_Ax 0x00000000 |
633 | /* assume maximum 5 revisions */ | |
634 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
635 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
636 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
637 | !(CHIP_REV(bp) & 0x00001000)) | |
638 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
639 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
640 | (CHIP_REV(bp) & 0x00001000)) | |
641 | ||
642 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
643 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
644 | ||
34f80b04 EG |
645 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
646 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
4a33bc03 | 647 | #define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) |
a2fbb9ea | 648 | |
34f80b04 EG |
649 | int flash_size; |
650 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
651 | #define NVRAM_TIMEOUT_COUNT 30000 | |
652 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 653 | |
34f80b04 | 654 | u32 shmem_base; |
2691d51d | 655 | u32 shmem2_base; |
523224a3 | 656 | u32 mf_cfg_base; |
f2e0899f | 657 | u32 mf2_cfg_base; |
34f80b04 EG |
658 | |
659 | u32 hw_config; | |
c18487ee | 660 | |
34f80b04 | 661 | u32 bc_ver; |
523224a3 DK |
662 | |
663 | u8 int_block; | |
664 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
665 | #define INT_BLOCK_IGU 1 |
666 | #define INT_BLOCK_MODE_NORMAL 0 | |
667 | #define INT_BLOCK_MODE_BW_COMP 2 | |
668 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
669 | (CHIP_IS_E2(bp) && \ | |
670 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) | |
671 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
672 | ||
523224a3 | 673 | u8 chip_port_mode; |
f2e0899f DK |
674 | #define CHIP_4_PORT_MODE 0x0 |
675 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 676 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
677 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
678 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
34f80b04 | 679 | }; |
c18487ee | 680 | |
f2e0899f DK |
681 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
682 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
683 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
684 | |
685 | /* end of common */ | |
686 | ||
687 | /* port */ | |
688 | ||
689 | struct bnx2x_port { | |
690 | u32 pmf; | |
c18487ee | 691 | |
a22f0788 | 692 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 693 | |
a22f0788 | 694 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
695 | /* link settings - missing defines */ |
696 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
697 | ||
a22f0788 | 698 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 699 | /* link settings - missing defines */ |
34f80b04 | 700 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 701 | |
34f80b04 | 702 | u32 phy_addr; |
c18487ee YR |
703 | |
704 | /* used to synchronize phy accesses */ | |
705 | struct mutex phy_mutex; | |
46c6a674 | 706 | int need_hw_lock; |
c18487ee | 707 | |
34f80b04 | 708 | u32 port_stx; |
a2fbb9ea | 709 | |
34f80b04 EG |
710 | struct nig_stats old_nig_stats; |
711 | }; | |
a2fbb9ea | 712 | |
34f80b04 EG |
713 | /* end of port */ |
714 | ||
523224a3 DK |
715 | /* e1h Classification CAM line allocations */ |
716 | enum { | |
717 | CAM_ETH_LINE = 0, | |
718 | CAM_ISCSI_ETH_LINE, | |
ec6ba945 VZ |
719 | CAM_FIP_ETH_LINE, |
720 | CAM_FIP_MCAST_LINE, | |
721 | CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE | |
523224a3 | 722 | }; |
0793f83f DK |
723 | /* number of MACs per function in NIG memory - used for SI mode */ |
724 | #define NIG_LLH_FUNC_MEM_SIZE 16 | |
725 | /* number of entries in NIG_REG_LLHX_FUNC_MEM */ | |
726 | #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8 | |
bb2a0f7a | 727 | |
523224a3 | 728 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 729 | |
523224a3 DK |
730 | /* |
731 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
732 | * control by the number of fast-path status blocks supported by the | |
733 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
734 | * status block represents an independent interrupts context that can | |
735 | * serve a regular L2 networking queue. However special L2 queues such | |
736 | * as the FCoE queue do not require a FP-SB and other components like | |
737 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
738 | * | |
739 | * If the maximum number of FP-SB available is X then: | |
740 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
741 | * regular L2 queues is Y=X-1 | |
742 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
743 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
744 | * is Y+1 | |
745 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
746 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
747 | * FP interrupt context for the CNIC). | |
748 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
749 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
750 | */ | |
751 | ||
752 | #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */ | |
f2e0899f | 753 | #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */ |
523224a3 DK |
754 | |
755 | /* | |
756 | * cid_cnt paramter below refers to the value returned by | |
757 | * 'bnx2x_get_l2_cid_count()' routine | |
758 | */ | |
759 | ||
760 | /* | |
761 | * The number of FP context allocated by the driver == max number of regular | |
762 | * L2 queues + 1 for the FCoE L2 queue | |
763 | */ | |
764 | #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE) | |
34f80b04 | 765 | |
ec6ba945 VZ |
766 | /* |
767 | * The number of FP-SB allocated by the driver == max number of regular L2 | |
768 | * queues + 1 for the CNIC which also consumes an FP-SB | |
769 | */ | |
770 | #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE) | |
771 | #define NUM_IGU_SB_REQUIRED(cid_cnt) \ | |
772 | (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE) | |
773 | ||
34f80b04 EG |
774 | union cdu_context { |
775 | struct eth_context eth; | |
776 | char pad[1024]; | |
777 | }; | |
778 | ||
523224a3 DK |
779 | /* CDU host DB constants */ |
780 | #define CDU_ILT_PAGE_SZ_HW 3 | |
781 | #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */ | |
782 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) | |
783 | ||
784 | #ifdef BCM_CNIC | |
785 | #define CNIC_ISCSI_CID_MAX 256 | |
ec6ba945 VZ |
786 | #define CNIC_FCOE_CID_MAX 2048 |
787 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 DK |
788 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
789 | #endif | |
790 | ||
791 | #define QM_ILT_PAGE_SZ_HW 3 | |
792 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */ | |
793 | #define QM_CID_ROUND 1024 | |
794 | ||
795 | #ifdef BCM_CNIC | |
796 | /* TM (timers) host DB constants */ | |
797 | #define TM_ILT_PAGE_SZ_HW 2 | |
798 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */ | |
799 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ | |
800 | #define TM_CONN_NUM 1024 | |
801 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
802 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
803 | ||
804 | /* SRC (Searcher) host DB constants */ | |
805 | #define SRC_ILT_PAGE_SZ_HW 3 | |
806 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */ | |
807 | #define SRC_HASH_BITS 10 | |
808 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
809 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
810 | #define SRC_T2_SZ SRC_ILT_SZ | |
811 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
812 | #endif | |
813 | ||
bb2a0f7a | 814 | #define MAX_DMAE_C 8 |
34f80b04 EG |
815 | |
816 | /* DMA memory not used in fastpath */ | |
817 | struct bnx2x_slowpath { | |
34f80b04 EG |
818 | struct eth_stats_query fw_stats; |
819 | struct mac_configuration_cmd mac_config; | |
820 | struct mac_configuration_cmd mcast_config; | |
6e30dd4e | 821 | struct mac_configuration_cmd uc_mac_config; |
523224a3 | 822 | struct client_init_ramrod_data client_init_data; |
34f80b04 EG |
823 | |
824 | /* used by dmae command executer */ | |
825 | struct dmae_command dmae[MAX_DMAE_C]; | |
826 | ||
bb2a0f7a YG |
827 | u32 stats_comp; |
828 | union mac_stats mac_stats; | |
829 | struct nig_stats nig_stats; | |
830 | struct host_port_stats port_stats; | |
831 | struct host_func_stats func_stats; | |
6fe49bb9 | 832 | struct host_func_stats func_stats_base; |
34f80b04 EG |
833 | |
834 | u32 wb_comp; | |
34f80b04 | 835 | u32 wb_data[4]; |
e4901dde VZ |
836 | /* pfc configuration for DCBX ramrod */ |
837 | struct flow_control_configuration pfc_config; | |
34f80b04 EG |
838 | }; |
839 | ||
840 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
841 | #define bnx2x_sp_mapping(bp, var) \ | |
842 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
843 | ||
844 | ||
845 | /* attn group wiring */ | |
846 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
847 | ||
848 | struct attn_route { | |
f2e0899f | 849 | u32 sig[5]; |
34f80b04 EG |
850 | }; |
851 | ||
523224a3 DK |
852 | struct iro { |
853 | u32 base; | |
854 | u16 m1; | |
855 | u16 m2; | |
856 | u16 m3; | |
857 | u16 size; | |
858 | }; | |
859 | ||
860 | struct hw_context { | |
861 | union cdu_context *vcxt; | |
862 | dma_addr_t cxt_mapping; | |
863 | size_t size; | |
864 | }; | |
865 | ||
866 | /* forward */ | |
867 | struct bnx2x_ilt; | |
868 | ||
72fd0718 VZ |
869 | typedef enum { |
870 | BNX2X_RECOVERY_DONE, | |
871 | BNX2X_RECOVERY_INIT, | |
872 | BNX2X_RECOVERY_WAIT, | |
873 | } bnx2x_recovery_state_t; | |
874 | ||
523224a3 DK |
875 | /** |
876 | * Event queue (EQ or event ring) MC hsi | |
877 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
878 | */ | |
879 | #define NUM_EQ_PAGES 1 | |
880 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
881 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
882 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
883 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
884 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
885 | ||
886 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
887 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
888 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
889 | ||
890 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
891 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
892 | ||
893 | #define BNX2X_EQ_INDEX \ | |
894 | (&bp->def_status_blk->sp_sb.\ | |
895 | index_values[HC_SP_INDEX_EQ_CONS]) | |
896 | ||
2ae17f66 VZ |
897 | /* This is a data that will be used to create a link report message. |
898 | * We will keep the data used for the last link report in order | |
899 | * to prevent reporting the same link parameters twice. | |
900 | */ | |
901 | struct bnx2x_link_report_data { | |
902 | u16 line_speed; /* Effective line speed */ | |
903 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ | |
904 | }; | |
905 | ||
906 | enum { | |
907 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ | |
908 | BNX2X_LINK_REPORT_LINK_DOWN, | |
909 | BNX2X_LINK_REPORT_RX_FC_ON, | |
910 | BNX2X_LINK_REPORT_TX_FC_ON, | |
911 | }; | |
912 | ||
34f80b04 EG |
913 | struct bnx2x { |
914 | /* Fields used in the tx and intr/napi performance paths | |
915 | * are grouped together in the beginning of the structure | |
916 | */ | |
523224a3 | 917 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
918 | void __iomem *regview; |
919 | void __iomem *doorbells; | |
523224a3 | 920 | u16 db_size; |
34f80b04 EG |
921 | |
922 | struct net_device *dev; | |
923 | struct pci_dev *pdev; | |
924 | ||
523224a3 DK |
925 | struct iro *iro_arr; |
926 | #define IRO (bp->iro_arr) | |
927 | ||
72fd0718 VZ |
928 | bnx2x_recovery_state_t recovery_state; |
929 | int is_leader; | |
523224a3 | 930 | struct msix_entry *msix_table; |
8badd27a EG |
931 | #define INT_MODE_INTx 1 |
932 | #define INT_MODE_MSI 2 | |
34f80b04 EG |
933 | |
934 | int tx_ring_size; | |
935 | ||
523224a3 DK |
936 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
937 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
938 | #define ETH_MIN_PACKET_SIZE 60 |
939 | #define ETH_MAX_PACKET_SIZE 1500 | |
940 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 941 | |
0f00846d EG |
942 | /* Max supported alignment is 256 (8 shift) */ |
943 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
944 | L1_CACHE_SHIFT : 8) | |
945 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) | |
523224a3 | 946 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 947 | |
523224a3 DK |
948 | struct host_sp_status_block *def_status_blk; |
949 | #define DEF_SB_IGU_ID 16 | |
950 | #define DEF_SB_ID HC_SP_SB_ID | |
951 | __le16 def_idx; | |
4781bfad | 952 | __le16 def_att_idx; |
34f80b04 EG |
953 | u32 attn_state; |
954 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
955 | |
956 | /* slow path ring */ | |
957 | struct eth_spe *spq; | |
958 | dma_addr_t spq_mapping; | |
959 | u16 spq_prod_idx; | |
960 | struct eth_spe *spq_prod_bd; | |
961 | struct eth_spe *spq_last_bd; | |
4781bfad | 962 | __le16 *dsb_sp_prod; |
6e30dd4e | 963 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
34f80b04 EG |
964 | /* used to synchronize spq accesses */ |
965 | spinlock_t spq_lock; | |
966 | ||
523224a3 DK |
967 | /* event queue */ |
968 | union event_ring_elem *eq_ring; | |
969 | dma_addr_t eq_mapping; | |
970 | u16 eq_prod; | |
971 | u16 eq_cons; | |
972 | __le16 *eq_cons_sb; | |
6e30dd4e | 973 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
523224a3 | 974 | |
bb2a0f7a YG |
975 | /* Flags for marking that there is a STAT_QUERY or |
976 | SET_MAC ramrod pending */ | |
e665bfda MC |
977 | int stats_pending; |
978 | int set_mac_pending; | |
34f80b04 | 979 | |
33471629 | 980 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
981 | |
982 | int panic; | |
7995c64e | 983 | int msg_enable; |
34f80b04 EG |
984 | |
985 | u32 flags; | |
986 | #define PCIX_FLAG 1 | |
987 | #define PCI_32BIT_FLAG 2 | |
1c06328c | 988 | #define ONE_PORT_FLAG 4 |
34f80b04 EG |
989 | #define NO_WOL_FLAG 8 |
990 | #define USING_DAC_FLAG 0x10 | |
991 | #define USING_MSIX_FLAG 0x20 | |
8badd27a | 992 | #define USING_MSI_FLAG 0x40 |
d6214d7a | 993 | |
7a9b2557 | 994 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 | 995 | #define NO_MCP_FLAG 0x100 |
d6214d7a | 996 | #define DISABLE_MSI_FLAG 0x200 |
34f80b04 | 997 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
f34d28ea | 998 | #define MF_FUNC_DIS 0x1000 |
ec6ba945 VZ |
999 | #define FCOE_MACS_SET 0x2000 |
1000 | #define NO_FCOE_FLAG 0x4000 | |
2ba45142 VZ |
1001 | #define NO_ISCSI_OOO_FLAG 0x8000 |
1002 | #define NO_ISCSI_FLAG 0x10000 | |
ec6ba945 VZ |
1003 | |
1004 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) | |
2ba45142 VZ |
1005 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
1006 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) | |
34f80b04 | 1007 | |
f2e0899f DK |
1008 | int pf_num; /* absolute PF number */ |
1009 | int pfid; /* per-path PF number */ | |
523224a3 | 1010 | int base_fw_ndsb; |
f2e0899f DK |
1011 | #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \ |
1012 | 0 : (bp->pf_num & 1)) | |
1013 | #define BP_PORT(bp) (bp->pfid & 1) | |
1014 | #define BP_FUNC(bp) (bp->pfid) | |
1015 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
1016 | #define BP_E1HVN(bp) (bp->pfid >> 1) | |
1017 | #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \ | |
1018 | 0 : BP_E1HVN(bp)) | |
34f80b04 | 1019 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) |
f2e0899f DK |
1020 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ |
1021 | BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1)) | |
34f80b04 | 1022 | |
37b091ba MC |
1023 | #ifdef BCM_CNIC |
1024 | #define BCM_CNIC_CID_START 16 | |
1025 | #define BCM_ISCSI_ETH_CL_ID 17 | |
1026 | #endif | |
1027 | ||
34f80b04 EG |
1028 | int pm_cap; |
1029 | int pcie_cap; | |
8d5726c4 | 1030 | int mrrs; |
34f80b04 | 1031 | |
1cf167f2 | 1032 | struct delayed_work sp_task; |
72fd0718 | 1033 | struct delayed_work reset_task; |
34f80b04 | 1034 | struct timer_list timer; |
34f80b04 EG |
1035 | int current_interval; |
1036 | ||
1037 | u16 fw_seq; | |
1038 | u16 fw_drv_pulse_wr_seq; | |
1039 | u32 func_stx; | |
1040 | ||
1041 | struct link_params link_params; | |
1042 | struct link_vars link_vars; | |
2ae17f66 VZ |
1043 | u32 link_cnt; |
1044 | struct bnx2x_link_report_data last_reported_link; | |
1045 | ||
01cd4528 | 1046 | struct mdio_if_info mdio; |
a2fbb9ea | 1047 | |
34f80b04 EG |
1048 | struct bnx2x_common common; |
1049 | struct bnx2x_port port; | |
1050 | ||
8a1c38d1 EG |
1051 | struct cmng_struct_per_port cmng; |
1052 | u32 vn_weight_sum; | |
1053 | ||
f2e0899f DK |
1054 | u32 mf_config[E1HVN_MAX]; |
1055 | u32 mf2_config[E2_FUNC_MAX]; | |
fb3bff17 DK |
1056 | u16 mf_ov; |
1057 | u8 mf_mode; | |
f85582f8 | 1058 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1059 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1060 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 1061 | |
f1410647 ET |
1062 | u8 wol; |
1063 | ||
34f80b04 | 1064 | int rx_ring_size; |
a2fbb9ea | 1065 | |
34f80b04 EG |
1066 | u16 tx_quick_cons_trip_int; |
1067 | u16 tx_quick_cons_trip; | |
1068 | u16 tx_ticks_int; | |
1069 | u16 tx_ticks; | |
a2fbb9ea | 1070 | |
34f80b04 EG |
1071 | u16 rx_quick_cons_trip_int; |
1072 | u16 rx_quick_cons_trip; | |
1073 | u16 rx_ticks_int; | |
1074 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1075 | /* Maximal coalescing timeout in us */ |
1076 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1077 | |
34f80b04 | 1078 | u32 lin_cnt; |
a2fbb9ea | 1079 | |
34f80b04 | 1080 | int state; |
356e2385 | 1081 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1082 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1083 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1084 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1085 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
1086 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
1087 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
523224a3 | 1088 | #define BNX2X_STATE_FUNC_STARTED 0x7000 |
34f80b04 EG |
1089 | #define BNX2X_STATE_DIAG 0xe000 |
1090 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1091 | |
555f6c78 | 1092 | int multi_mode; |
54b9ddaa | 1093 | int num_queues; |
5d7cd496 DK |
1094 | int disable_tpa; |
1095 | int int_mode; | |
ab532cf3 | 1096 | u32 *rx_indir_table; |
a2fbb9ea | 1097 | |
523224a3 DK |
1098 | struct tstorm_eth_mac_filter_config mac_filters; |
1099 | #define BNX2X_ACCEPT_NONE 0x0000 | |
1100 | #define BNX2X_ACCEPT_UNICAST 0x0001 | |
1101 | #define BNX2X_ACCEPT_MULTICAST 0x0002 | |
1102 | #define BNX2X_ACCEPT_ALL_UNICAST 0x0004 | |
1103 | #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008 | |
1104 | #define BNX2X_ACCEPT_BROADCAST 0x0010 | |
0793f83f | 1105 | #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020 |
523224a3 DK |
1106 | #define BNX2X_PROMISCUOUS_MODE 0x10000 |
1107 | ||
34f80b04 EG |
1108 | u32 rx_mode; |
1109 | #define BNX2X_RX_MODE_NONE 0 | |
1110 | #define BNX2X_RX_MODE_NORMAL 1 | |
1111 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1112 | #define BNX2X_RX_MODE_PROMISC 3 | |
1113 | #define BNX2X_MAX_MULTICAST 64 | |
1114 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 1115 | |
523224a3 DK |
1116 | u8 igu_dsb_id; |
1117 | u8 igu_base_sb; | |
1118 | u8 igu_sb_cnt; | |
34f80b04 | 1119 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1120 | |
34f80b04 EG |
1121 | struct bnx2x_slowpath *slowpath; |
1122 | dma_addr_t slowpath_mapping; | |
523224a3 DK |
1123 | struct hw_context context; |
1124 | ||
1125 | struct bnx2x_ilt *ilt; | |
1126 | #define BP_ILT(bp) ((bp)->ilt) | |
1127 | #define ILT_MAX_LINES 128 | |
1128 | ||
1129 | int l2_cid_count; | |
1130 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \ | |
1131 | ILT_PAGE_CIDS)) | |
1132 | #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT)) | |
1133 | ||
1134 | int qm_cid_count; | |
a2fbb9ea | 1135 | |
a18f5128 EG |
1136 | int dropless_fc; |
1137 | ||
37b091ba MC |
1138 | #ifdef BCM_CNIC |
1139 | u32 cnic_flags; | |
1140 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1141 | void *t2; |
1142 | dma_addr_t t2_mapping; | |
13707f9e | 1143 | struct cnic_ops __rcu *cnic_ops; |
37b091ba MC |
1144 | void *cnic_data; |
1145 | u32 cnic_tag; | |
1146 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1147 | union host_hc_status_block cnic_sb; |
37b091ba | 1148 | dma_addr_t cnic_sb_mapping; |
523224a3 DK |
1149 | #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp)) |
1150 | #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb) | |
37b091ba MC |
1151 | struct eth_spe *cnic_kwq; |
1152 | struct eth_spe *cnic_kwq_prod; | |
1153 | struct eth_spe *cnic_kwq_cons; | |
1154 | struct eth_spe *cnic_kwq_last; | |
1155 | u16 cnic_kwq_pending; | |
1156 | u16 cnic_spq_pending; | |
1157 | struct mutex cnic_mutex; | |
ec6ba945 | 1158 | u8 fip_mac[ETH_ALEN]; |
37b091ba MC |
1159 | #endif |
1160 | ||
ad8d3948 EG |
1161 | int dmae_ready; |
1162 | /* used to synchronize dmae accesses */ | |
6e30dd4e | 1163 | spinlock_t dmae_lock; |
ad8d3948 | 1164 | |
c4ff7cbf EG |
1165 | /* used to protect the FW mail box */ |
1166 | struct mutex fw_mb_mutex; | |
1167 | ||
bb2a0f7a YG |
1168 | /* used to synchronize stats collecting */ |
1169 | int stats_state; | |
a13773a5 VZ |
1170 | |
1171 | /* used for synchronization of concurrent threads statistics handling */ | |
1172 | spinlock_t stats_lock; | |
1173 | ||
bb2a0f7a YG |
1174 | /* used by dmae command loader */ |
1175 | struct dmae_command stats_dmae; | |
1176 | int executer_idx; | |
ad8d3948 | 1177 | |
bb2a0f7a | 1178 | u16 stats_counter; |
bb2a0f7a YG |
1179 | struct bnx2x_eth_stats eth_stats; |
1180 | ||
1181 | struct z_stream_s *strm; | |
1182 | void *gunzip_buf; | |
1183 | dma_addr_t gunzip_mapping; | |
1184 | int gunzip_outlen; | |
ad8d3948 | 1185 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1186 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1187 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1188 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1189 | |
ab6ad5a4 | 1190 | struct raw_op *init_ops; |
94a78b79 | 1191 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1192 | u16 *init_ops_offsets; |
94a78b79 | 1193 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1194 | u32 *init_data; |
94a78b79 | 1195 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1196 | const u8 *tsem_int_table_data; |
1197 | const u8 *tsem_pram_data; | |
1198 | const u8 *usem_int_table_data; | |
1199 | const u8 *usem_pram_data; | |
1200 | const u8 *xsem_int_table_data; | |
1201 | const u8 *xsem_pram_data; | |
1202 | const u8 *csem_int_table_data; | |
1203 | const u8 *csem_pram_data; | |
573f2035 EG |
1204 | #define INIT_OPS(bp) (bp->init_ops) |
1205 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1206 | #define INIT_DATA(bp) (bp->init_data) | |
1207 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1208 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1209 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1210 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1211 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1212 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1213 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1214 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1215 | ||
34f24c7f | 1216 | char fw_ver[32]; |
ab6ad5a4 | 1217 | const struct firmware *firmware; |
e4901dde VZ |
1218 | /* LLDP params */ |
1219 | struct bnx2x_config_lldp_params lldp_config_params; | |
1220 | ||
785b9b1a SR |
1221 | /* DCB support on/off */ |
1222 | u16 dcb_state; | |
1223 | #define BNX2X_DCB_STATE_OFF 0 | |
1224 | #define BNX2X_DCB_STATE_ON 1 | |
1225 | ||
1226 | /* DCBX engine mode */ | |
1227 | int dcbx_enabled; | |
1228 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1229 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1230 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1231 | #define BNX2X_DCBX_ENABLED_INVALID (-1) | |
1232 | ||
1233 | bool dcbx_mode_uset; | |
1234 | ||
e4901dde VZ |
1235 | struct bnx2x_config_dcbx_params dcbx_config_params; |
1236 | ||
1237 | struct bnx2x_dcbx_port_params dcbx_port_params; | |
1238 | int dcb_version; | |
1239 | ||
25985edc | 1240 | /* DCBX Negotiation results */ |
e4901dde VZ |
1241 | struct dcbx_features dcbx_local_feat; |
1242 | u32 dcbx_error; | |
0be6bc62 SR |
1243 | #ifdef BCM_DCBNL |
1244 | struct dcbx_features dcbx_remote_feat; | |
1245 | u32 dcbx_remote_flags; | |
1246 | #endif | |
e3835b99 | 1247 | u32 pending_max; |
a2fbb9ea ET |
1248 | }; |
1249 | ||
523224a3 DK |
1250 | /** |
1251 | * Init queue/func interface | |
1252 | */ | |
1253 | /* queue init flags */ | |
1254 | #define QUEUE_FLG_TPA 0x0001 | |
1255 | #define QUEUE_FLG_CACHE_ALIGN 0x0002 | |
1256 | #define QUEUE_FLG_STATS 0x0004 | |
1257 | #define QUEUE_FLG_OV 0x0008 | |
1258 | #define QUEUE_FLG_VLAN 0x0010 | |
1259 | #define QUEUE_FLG_COS 0x0020 | |
1260 | #define QUEUE_FLG_HC 0x0040 | |
1261 | #define QUEUE_FLG_DHC 0x0080 | |
1262 | #define QUEUE_FLG_OOO 0x0100 | |
1263 | ||
1264 | #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR | |
1265 | #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR | |
1266 | #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 | |
1267 | #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR | |
1268 | ||
1269 | ||
1270 | ||
1271 | /* rss capabilities */ | |
1272 | #define RSS_IPV4_CAP 0x0001 | |
1273 | #define RSS_IPV4_TCP_CAP 0x0002 | |
1274 | #define RSS_IPV6_CAP 0x0004 | |
1275 | #define RSS_IPV6_TCP_CAP 0x0008 | |
a2fbb9ea | 1276 | |
54b9ddaa | 1277 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
ec6ba945 VZ |
1278 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE) |
1279 | ||
1280 | /* ethtool statistics are displayed for all regular ethernet queues and the | |
1281 | * fcoe L2 queue if not disabled | |
1282 | */ | |
1283 | #define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \ | |
1284 | (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE)) | |
1285 | ||
54b9ddaa | 1286 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1287 | |
f2e0899f | 1288 | #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE) |
523224a3 DK |
1289 | |
1290 | #define RSS_IPV4_CAP_MASK \ | |
1291 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1292 | ||
1293 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1294 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1295 | ||
1296 | #define RSS_IPV6_CAP_MASK \ | |
1297 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1298 | ||
1299 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1300 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1301 | ||
1302 | /* func init flags */ | |
030f3356 DK |
1303 | #define FUNC_FLG_STATS 0x0001 |
1304 | #define FUNC_FLG_TPA 0x0002 | |
1305 | #define FUNC_FLG_SPQ 0x0004 | |
1306 | #define FUNC_FLG_LEADING 0x0008 /* PF only */ | |
523224a3 DK |
1307 | |
1308 | struct rxq_pause_params { | |
1309 | u16 bd_th_lo; | |
1310 | u16 bd_th_hi; | |
1311 | u16 rcq_th_lo; | |
1312 | u16 rcq_th_hi; | |
1313 | u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */ | |
1314 | u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */ | |
1315 | u16 pri_map; | |
1316 | }; | |
1317 | ||
1318 | struct bnx2x_rxq_init_params { | |
1319 | /* cxt*/ | |
1320 | struct eth_context *cxt; | |
1321 | ||
1322 | /* dma */ | |
1323 | dma_addr_t dscr_map; | |
1324 | dma_addr_t sge_map; | |
1325 | dma_addr_t rcq_map; | |
1326 | dma_addr_t rcq_np_map; | |
1327 | ||
1328 | u16 flags; | |
1329 | u16 drop_flags; | |
1330 | u16 mtu; | |
1331 | u16 buf_sz; | |
1332 | u16 fw_sb_id; | |
1333 | u16 cl_id; | |
1334 | u16 spcl_id; | |
1335 | u16 cl_qzone_id; | |
1336 | ||
1337 | /* valid iff QUEUE_FLG_STATS */ | |
1338 | u16 stat_id; | |
1339 | ||
1340 | /* valid iff QUEUE_FLG_TPA */ | |
1341 | u16 tpa_agg_sz; | |
1342 | u16 sge_buf_sz; | |
1343 | u16 max_sges_pkt; | |
1344 | ||
1345 | /* valid iff QUEUE_FLG_CACHE_ALIGN */ | |
1346 | u8 cache_line_log; | |
1347 | ||
1348 | u8 sb_cq_index; | |
1349 | u32 cid; | |
1350 | ||
1351 | /* desired interrupts per sec. valid iff QUEUE_FLG_HC */ | |
1352 | u32 hc_rate; | |
1353 | }; | |
1354 | ||
1355 | struct bnx2x_txq_init_params { | |
1356 | /* cxt*/ | |
1357 | struct eth_context *cxt; | |
1358 | ||
1359 | /* dma */ | |
1360 | dma_addr_t dscr_map; | |
1361 | ||
1362 | u16 flags; | |
1363 | u16 fw_sb_id; | |
1364 | u8 sb_cq_index; | |
1365 | u8 cos; /* valid iff QUEUE_FLG_COS */ | |
1366 | u16 stat_id; /* valid iff QUEUE_FLG_STATS */ | |
1367 | u16 traffic_type; | |
1368 | u32 cid; | |
1369 | u16 hc_rate; /* desired interrupts per sec.*/ | |
1370 | /* valid iff QUEUE_FLG_HC */ | |
1371 | ||
1372 | }; | |
1373 | ||
1374 | struct bnx2x_client_ramrod_params { | |
1375 | int *pstate; | |
1376 | int state; | |
1377 | u16 index; | |
1378 | u16 cl_id; | |
1379 | u32 cid; | |
1380 | u8 poll; | |
ec6ba945 | 1381 | #define CLIENT_IS_FCOE 0x01 |
523224a3 DK |
1382 | #define CLIENT_IS_LEADING_RSS 0x02 |
1383 | u8 flags; | |
1384 | }; | |
1385 | ||
1386 | struct bnx2x_client_init_params { | |
1387 | struct rxq_pause_params pause; | |
1388 | struct bnx2x_rxq_init_params rxq_params; | |
1389 | struct bnx2x_txq_init_params txq_params; | |
1390 | struct bnx2x_client_ramrod_params ramrod_params; | |
1391 | }; | |
1392 | ||
1393 | struct bnx2x_rss_params { | |
1394 | int mode; | |
1395 | u16 cap; | |
1396 | u16 result_mask; | |
1397 | }; | |
1398 | ||
1399 | struct bnx2x_func_init_params { | |
1400 | ||
1401 | /* rss */ | |
1402 | struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */ | |
1403 | ||
1404 | /* dma */ | |
1405 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1406 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1407 | ||
1408 | u16 func_flgs; | |
1409 | u16 func_id; /* abs fid */ | |
1410 | u16 pf_id; | |
1411 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1412 | }; | |
1413 | ||
ec6ba945 VZ |
1414 | #define for_each_eth_queue(bp, var) \ |
1415 | for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++) | |
1416 | ||
1417 | #define for_each_nondefault_eth_queue(bp, var) \ | |
1418 | for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++) | |
1419 | ||
1420 | #define for_each_napi_queue(bp, var) \ | |
1421 | for (var = 0; \ | |
1422 | var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \ | |
1423 | if (skip_queue(bp, var)) \ | |
1424 | continue; \ | |
1425 | else | |
1426 | ||
555f6c78 | 1427 | #define for_each_queue(bp, var) \ |
ec6ba945 VZ |
1428 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ |
1429 | if (skip_queue(bp, var)) \ | |
1430 | continue; \ | |
1431 | else | |
1432 | ||
1433 | #define for_each_rx_queue(bp, var) \ | |
1434 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ | |
1435 | if (skip_rx_queue(bp, var)) \ | |
1436 | continue; \ | |
1437 | else | |
1438 | ||
1439 | #define for_each_tx_queue(bp, var) \ | |
1440 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ | |
1441 | if (skip_tx_queue(bp, var)) \ | |
1442 | continue; \ | |
1443 | else | |
1444 | ||
3196a88a | 1445 | #define for_each_nondefault_queue(bp, var) \ |
ec6ba945 VZ |
1446 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \ |
1447 | if (skip_queue(bp, var)) \ | |
1448 | continue; \ | |
1449 | else | |
3196a88a | 1450 | |
ec6ba945 | 1451 | /* skip rx queue |
008d23e4 | 1452 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1453 | */ |
1454 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1455 | ||
1456 | /* skip tx queue | |
008d23e4 | 1457 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1458 | */ |
1459 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1460 | ||
1461 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1462 | |
f85582f8 DK |
1463 | #define WAIT_RAMROD_POLL 0x01 |
1464 | #define WAIT_RAMROD_COMMON 0x02 | |
f85582f8 | 1465 | |
2ae17f66 VZ |
1466 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
1467 | ||
f85582f8 | 1468 | /* dmae */ |
c18487ee YR |
1469 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1470 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1471 | u32 len32); | |
f85582f8 DK |
1472 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1473 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1474 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1475 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1476 | bool with_comp, u8 comp_type); | |
1477 | ||
4acac6a5 | 1478 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
17de50b7 | 1479 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
4acac6a5 | 1480 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
a22f0788 | 1481 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); |
f85582f8 | 1482 | |
de0c62db DK |
1483 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1484 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
1485 | u32 data_hi, u32 data_lo, int common); | |
6e30dd4e VZ |
1486 | |
1487 | /* Clears multicast and unicast list configuration in the chip. */ | |
1488 | void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp); | |
1489 | void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp); | |
1490 | void bnx2x_invalidate_uc_list(struct bnx2x *bp); | |
1491 | ||
de0c62db | 1492 | void bnx2x_update_coalesce(struct bnx2x *bp); |
1ac9e428 | 1493 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp); |
f85582f8 | 1494 | |
34f80b04 EG |
1495 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1496 | int wait) | |
1497 | { | |
1498 | u32 val; | |
1499 | ||
1500 | do { | |
1501 | val = REG_RD(bp, reg); | |
1502 | if (val == expected) | |
1503 | break; | |
1504 | ms -= wait; | |
1505 | msleep(wait); | |
1506 | ||
1507 | } while (ms > 0); | |
1508 | ||
1509 | return val; | |
1510 | } | |
f85582f8 | 1511 | |
523224a3 DK |
1512 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1513 | do { \ | |
d245a111 | 1514 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
523224a3 DK |
1515 | if (x) \ |
1516 | memset(x, 0, size); \ | |
1517 | } while (0) | |
1518 | ||
1519 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1520 | do { \ | |
1521 | if (x) { \ | |
d245a111 | 1522 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1523 | x = NULL; \ |
1524 | y = 0; \ | |
1525 | } \ | |
1526 | } while (0) | |
1527 | ||
1528 | #define ILOG2(x) (ilog2((x))) | |
1529 | ||
1530 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1531 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1532 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1533 | * the table in use | |
523224a3 DK |
1534 | */ |
1535 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1536 | ||
1537 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1538 | /* | |
1539 | * the phys address is shifted right 12 bits and has an added | |
1540 | * 1=valid bit added to the 53rd bit | |
1541 | * then since this is a wide register(TM) | |
1542 | * we split it into two 32 bit writes | |
1543 | */ | |
1544 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1545 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1546 | |
34f80b04 EG |
1547 | /* load/unload mode */ |
1548 | #define LOAD_NORMAL 0 | |
1549 | #define LOAD_OPEN 1 | |
1550 | #define LOAD_DIAG 2 | |
1551 | #define UNLOAD_NORMAL 0 | |
1552 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1553 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1554 | |
bb2a0f7a | 1555 | |
ad8d3948 | 1556 | /* DMAE command defines */ |
f2e0899f DK |
1557 | #define DMAE_TIMEOUT -1 |
1558 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1559 | #define DMAE_NOT_RDY -3 | |
1560 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1561 | ||
1562 | #define DMAE_SRC_PCI 0 | |
1563 | #define DMAE_SRC_GRC 1 | |
1564 | ||
1565 | #define DMAE_DST_NONE 0 | |
1566 | #define DMAE_DST_PCI 1 | |
1567 | #define DMAE_DST_GRC 2 | |
1568 | ||
1569 | #define DMAE_COMP_PCI 0 | |
1570 | #define DMAE_COMP_GRC 1 | |
1571 | ||
1572 | /* E2 and onward - PCI error handling in the completion */ | |
1573 | ||
1574 | #define DMAE_COMP_REGULAR 0 | |
1575 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1576 | |
f2e0899f DK |
1577 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1578 | DMAE_COMMAND_SRC_SHIFT) | |
1579 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1580 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1581 | |
f2e0899f DK |
1582 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1583 | DMAE_COMMAND_DST_SHIFT) | |
1584 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1585 | DMAE_COMMAND_DST_SHIFT) | |
1586 | ||
1587 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1588 | DMAE_COMMAND_C_DST_SHIFT) | |
1589 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1590 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1591 | |
1592 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1593 | ||
1594 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1595 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1596 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1597 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1598 | ||
1599 | #define DMAE_CMD_PORT_0 0 | |
1600 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1601 | ||
1602 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1603 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1604 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1605 | ||
f2e0899f DK |
1606 | #define DMAE_SRC_PF 0 |
1607 | #define DMAE_SRC_VF 1 | |
1608 | ||
1609 | #define DMAE_DST_PF 0 | |
1610 | #define DMAE_DST_VF 1 | |
1611 | ||
1612 | #define DMAE_C_SRC 0 | |
1613 | #define DMAE_C_DST 1 | |
1614 | ||
ad8d3948 | 1615 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1616 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1617 | |
f2e0899f DK |
1618 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1619 | indicates eror */ | |
ad8d3948 EG |
1620 | |
1621 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1622 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 | 1623 | BP_E1HVN(bp)) |
ab6ad5a4 | 1624 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1625 | E1HVN_MAX) |
1626 | ||
25047950 ET |
1627 | /* PCIE link and speed */ |
1628 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1629 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1630 | #define PCICFG_LINK_SPEED 0xf0000 | |
1631 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1632 | |
bb2a0f7a | 1633 | |
d3d4f495 | 1634 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1635 | |
b5bf9068 EG |
1636 | #define BNX2X_PHY_LOOPBACK 0 |
1637 | #define BNX2X_MAC_LOOPBACK 1 | |
1638 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1639 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1640 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1641 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1642 | |
7a9b2557 VZ |
1643 | |
1644 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1645 | ||
96fc1784 | 1646 | |
34f80b04 | 1647 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 EG |
1648 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
1649 | (BP_E1HVN(bp) << 17) | (x)) | |
7a9b2557 VZ |
1650 | |
1651 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1652 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1653 | ||
1654 | ||
523224a3 | 1655 | #define BNX2X_BTR 4 |
7a9b2557 | 1656 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1657 | |
ff80ee02 DK |
1658 | /* CMNG constants, as derived from system spec calculations */ |
1659 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
1660 | #define DEF_MIN_RATE 100 | |
9b3de1ef DK |
1661 | /* resolution of the rate shaping timer - 400 usec */ |
1662 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
34f80b04 | 1663 | /* number of bytes in single QM arbitration cycle - |
ff80ee02 DK |
1664 | * coefficient for calculating the fairness timer */ |
1665 | #define QM_ARB_BYTES 160000 | |
1666 | /* resolution of Min algorithm 1:100 */ | |
1667 | #define MIN_RES 100 | |
1668 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
1669 | #define MIN_ABOVE_THRESH 32768 | |
1670 | /* Fairness algorithm integration time coefficient - | |
1671 | * for calculating the actual Tfair */ | |
1672 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
1673 | /* Memory of fairness algorithm . 2 cycles */ | |
1674 | #define FAIR_MEM 2 | |
34f80b04 EG |
1675 | |
1676 | ||
1677 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1678 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1679 | #define GPIO_2_FUNC (1L << 10) | |
1680 | #define GPIO_3_FUNC (1L << 11) | |
1681 | #define GPIO_4_FUNC (1L << 12) | |
1682 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1683 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1684 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1685 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1686 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1687 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1688 | ||
1689 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1690 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1691 | |
1692 | ||
34f80b04 EG |
1693 | /* stuff added to make the code fit 80Col */ |
1694 | ||
1695 | #define BNX2X_PMF_LINK_ASSERT \ | |
1696 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1697 | ||
a2fbb9ea ET |
1698 | #define BNX2X_MC_ASSERT_BITS \ |
1699 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1700 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1701 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1702 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1703 | ||
1704 | #define BNX2X_MCP_ASSERT \ | |
1705 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1706 | ||
34f80b04 EG |
1707 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1708 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1709 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1710 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1711 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1712 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1713 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1714 | ||
a2fbb9ea ET |
1715 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1716 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1717 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1718 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1719 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1720 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1721 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1722 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1723 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1724 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1725 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1726 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1727 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1728 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1729 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1730 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1731 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1732 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1733 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1734 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1735 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1736 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1737 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1738 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1739 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1740 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
ab6ad5a4 EG |
1741 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
1742 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
a2fbb9ea ET |
1743 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1744 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1745 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1746 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1747 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1748 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1749 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1750 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1751 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1752 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1753 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1754 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1755 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1756 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1757 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1758 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1759 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1760 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1761 | ||
72fd0718 VZ |
1762 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1763 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1764 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1765 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 1766 | |
c68ed255 | 1767 | #define RSS_FLAGS(bp) \ |
34f80b04 EG |
1768 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1769 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1770 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1771 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1772 | (bp->multi_mode << \ |
1773 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
34f80b04 | 1774 | #define MULTI_MASK 0x7f |
a2fbb9ea | 1775 | |
a2fbb9ea | 1776 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
1777 | (&bp->def_status_blk->sp_sb.\ |
1778 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 1779 | |
523224a3 DK |
1780 | #define SET_FLAG(value, mask, flag) \ |
1781 | do {\ | |
1782 | (value) &= ~(mask);\ | |
1783 | (value) |= ((flag) << (mask##_SHIFT));\ | |
1784 | } while (0) | |
a2fbb9ea | 1785 | |
523224a3 DK |
1786 | #define GET_FLAG(value, mask) \ |
1787 | (((value) &= (mask)) >> (mask##_SHIFT)) | |
a2fbb9ea | 1788 | |
f2e0899f DK |
1789 | #define GET_FIELD(value, fname) \ |
1790 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
1791 | ||
a2fbb9ea | 1792 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
1793 | (GET_FLAG(x.flags, \ |
1794 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
1795 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 1796 | |
34f80b04 EG |
1797 | /* Number of u32 elements in MC hash array */ |
1798 | #define MC_HASH_SIZE 8 | |
1799 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1800 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1801 | |
1802 | ||
34f80b04 EG |
1803 | #ifndef PXP2_REG_PXP2_INT_STS |
1804 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1805 | #endif | |
1806 | ||
f2e0899f DK |
1807 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
1808 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
1809 | #endif | |
f85582f8 | 1810 | |
34f24c7f VZ |
1811 | #define BNX2X_VPD_LEN 128 |
1812 | #define VENDOR_ID_LEN 4 | |
1813 | ||
523224a3 DK |
1814 | /* Congestion management fairness mode */ |
1815 | #define CMNG_FNS_NONE 0 | |
1816 | #define CMNG_FNS_MINMAX 1 | |
1817 | ||
1818 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
1819 | #define HC_SEG_ACCESS_ATTN 4 | |
1820 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
1821 | ||
b0efbb99 DK |
1822 | #ifdef BNX2X_MAIN |
1823 | #define BNX2X_EXTERN | |
1824 | #else | |
1825 | #define BNX2X_EXTERN extern | |
1826 | #endif | |
1827 | ||
f2e0899f | 1828 | BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */ |
b0efbb99 | 1829 | |
de0c62db | 1830 | extern void bnx2x_set_ethtool_ops(struct net_device *netdev); |
ab532cf3 | 1831 | void bnx2x_push_indir_table(struct bnx2x *bp); |
de0c62db | 1832 | |
a2fbb9ea | 1833 | #endif /* bnx2x.h */ |