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6b7c5b94 SP |
1 | /* |
2 | * Copyright (C) 2005 - 2009 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | ||
18 | #ifndef BE_H | |
19 | #define BE_H | |
20 | ||
21 | #include <linux/pci.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/version.h> | |
24 | #include <linux/delay.h> | |
25 | #include <net/tcp.h> | |
26 | #include <net/ip.h> | |
27 | #include <net/ipv6.h> | |
28 | #include <linux/if_vlan.h> | |
29 | #include <linux/workqueue.h> | |
30 | #include <linux/interrupt.h> | |
84517482 | 31 | #include <linux/firmware.h> |
6b7c5b94 SP |
32 | |
33 | #include "be_hw.h" | |
34 | ||
3454f835 | 35 | #define DRV_VER "2.101.346u" |
6b7c5b94 SP |
36 | #define DRV_NAME "be2net" |
37 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | |
12d7ea2c | 38 | #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" |
c4ca2374 | 39 | #define OC_NAME "Emulex OneConnect 10Gbps NIC" |
12d7ea2c | 40 | #define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)" |
6b7c5b94 SP |
41 | #define DRV_DESC BE_NAME "Driver" |
42 | ||
c4ca2374 AK |
43 | #define BE_VENDOR_ID 0x19a2 |
44 | #define BE_DEVICE_ID1 0x211 | |
12d7ea2c | 45 | #define BE_DEVICE_ID2 0x221 |
c4ca2374 AK |
46 | #define OC_DEVICE_ID1 0x700 |
47 | #define OC_DEVICE_ID2 0x701 | |
12d7ea2c | 48 | #define OC_DEVICE_ID3 0x710 |
c4ca2374 AK |
49 | |
50 | static inline char *nic_name(struct pci_dev *pdev) | |
51 | { | |
12d7ea2c AK |
52 | switch (pdev->device) { |
53 | case OC_DEVICE_ID1: | |
54 | case OC_DEVICE_ID2: | |
c4ca2374 | 55 | return OC_NAME; |
12d7ea2c AK |
56 | case OC_DEVICE_ID3: |
57 | return OC_NAME1; | |
58 | case BE_DEVICE_ID2: | |
59 | return BE3_NAME; | |
60 | default: | |
c4ca2374 | 61 | return BE_NAME; |
12d7ea2c | 62 | } |
c4ca2374 AK |
63 | } |
64 | ||
6b7c5b94 SP |
65 | /* Number of bytes of an RX frame that are copied to skb->data */ |
66 | #define BE_HDR_LEN 64 | |
67 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 | |
68 | #define BE_MIN_MTU 256 | |
69 | ||
70 | #define BE_NUM_VLANS_SUPPORTED 64 | |
71 | #define BE_MAX_EQD 96 | |
72 | #define BE_MAX_TX_FRAG_COUNT 30 | |
73 | ||
74 | #define EVNT_Q_LEN 1024 | |
75 | #define TX_Q_LEN 2048 | |
76 | #define TX_CQ_LEN 1024 | |
77 | #define RX_Q_LEN 1024 /* Does not support any other value */ | |
78 | #define RX_CQ_LEN 1024 | |
5fb379ee | 79 | #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ |
6b7c5b94 SP |
80 | #define MCC_CQ_LEN 256 |
81 | ||
82 | #define BE_NAPI_WEIGHT 64 | |
83 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ | |
84 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) | |
85 | ||
8788fdc2 SP |
86 | #define FW_VER_LEN 32 |
87 | ||
6b7c5b94 SP |
88 | struct be_dma_mem { |
89 | void *va; | |
90 | dma_addr_t dma; | |
91 | u32 size; | |
92 | }; | |
93 | ||
94 | struct be_queue_info { | |
95 | struct be_dma_mem dma_mem; | |
96 | u16 len; | |
97 | u16 entry_size; /* Size of an element in the queue */ | |
98 | u16 id; | |
99 | u16 tail, head; | |
100 | bool created; | |
101 | atomic_t used; /* Number of valid elements in the queue */ | |
102 | }; | |
103 | ||
5fb379ee SP |
104 | static inline u32 MODULO(u16 val, u16 limit) |
105 | { | |
106 | BUG_ON(limit & (limit - 1)); | |
107 | return val & (limit - 1); | |
108 | } | |
109 | ||
110 | static inline void index_adv(u16 *index, u16 val, u16 limit) | |
111 | { | |
112 | *index = MODULO((*index + val), limit); | |
113 | } | |
114 | ||
115 | static inline void index_inc(u16 *index, u16 limit) | |
116 | { | |
117 | *index = MODULO((*index + 1), limit); | |
118 | } | |
119 | ||
120 | static inline void *queue_head_node(struct be_queue_info *q) | |
121 | { | |
122 | return q->dma_mem.va + q->head * q->entry_size; | |
123 | } | |
124 | ||
125 | static inline void *queue_tail_node(struct be_queue_info *q) | |
126 | { | |
127 | return q->dma_mem.va + q->tail * q->entry_size; | |
128 | } | |
129 | ||
130 | static inline void queue_head_inc(struct be_queue_info *q) | |
131 | { | |
132 | index_inc(&q->head, q->len); | |
133 | } | |
134 | ||
135 | static inline void queue_tail_inc(struct be_queue_info *q) | |
136 | { | |
137 | index_inc(&q->tail, q->len); | |
138 | } | |
139 | ||
5fb379ee SP |
140 | struct be_eq_obj { |
141 | struct be_queue_info q; | |
142 | char desc[32]; | |
143 | ||
144 | /* Adaptive interrupt coalescing (AIC) info */ | |
145 | bool enable_aic; | |
146 | u16 min_eqd; /* in usecs */ | |
147 | u16 max_eqd; /* in usecs */ | |
148 | u16 cur_eqd; /* in usecs */ | |
149 | ||
150 | struct napi_struct napi; | |
151 | }; | |
152 | ||
153 | struct be_mcc_obj { | |
154 | struct be_queue_info q; | |
155 | struct be_queue_info cq; | |
156 | }; | |
157 | ||
6b7c5b94 SP |
158 | struct be_drvr_stats { |
159 | u32 be_tx_reqs; /* number of TX requests initiated */ | |
160 | u32 be_tx_stops; /* number of times TX Q was stopped */ | |
161 | u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */ | |
162 | u32 be_tx_wrbs; /* number of tx WRBs used */ | |
163 | u32 be_tx_events; /* number of tx completion events */ | |
164 | u32 be_tx_compl; /* number of tx completion entries processed */ | |
4097f663 SP |
165 | ulong be_tx_jiffies; |
166 | u64 be_tx_bytes; | |
167 | u64 be_tx_bytes_prev; | |
6b7c5b94 SP |
168 | u32 be_tx_rate; |
169 | ||
170 | u32 cache_barrier[16]; | |
171 | ||
172 | u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */ | |
b7b83ac3 | 173 | u32 be_rx_polls; /* number of times NAPI called poll function */ |
6b7c5b94 SP |
174 | u32 be_rx_events; /* number of ucast rx completion events */ |
175 | u32 be_rx_compl; /* number of rx completion entries processed */ | |
4097f663 SP |
176 | ulong be_rx_jiffies; |
177 | u64 be_rx_bytes; | |
178 | u64 be_rx_bytes_prev; | |
6b7c5b94 SP |
179 | u32 be_rx_rate; |
180 | /* number of non ether type II frames dropped where | |
181 | * frame len > length field of Mac Hdr */ | |
182 | u32 be_802_3_dropped_frames; | |
183 | /* number of non ether type II frames malformed where | |
184 | * in frame len < length field of Mac Hdr */ | |
185 | u32 be_802_3_malformed_frames; | |
186 | u32 be_rxcp_err; /* Num rx completion entries w/ err set. */ | |
187 | ulong rx_fps_jiffies; /* jiffies at last FPS calc */ | |
188 | u32 be_rx_frags; | |
189 | u32 be_prev_rx_frags; | |
190 | u32 be_rx_fps; /* Rx frags per second */ | |
191 | }; | |
192 | ||
193 | struct be_stats_obj { | |
194 | struct be_drvr_stats drvr_stats; | |
6b7c5b94 SP |
195 | struct be_dma_mem cmd; |
196 | }; | |
197 | ||
6b7c5b94 SP |
198 | struct be_tx_obj { |
199 | struct be_queue_info q; | |
200 | struct be_queue_info cq; | |
201 | /* Remember the skbs that were transmitted */ | |
202 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | |
203 | }; | |
204 | ||
205 | /* Struct to remember the pages posted for rx frags */ | |
206 | struct be_rx_page_info { | |
207 | struct page *page; | |
208 | dma_addr_t bus; | |
209 | u16 page_offset; | |
210 | bool last_page_user; | |
211 | }; | |
212 | ||
213 | struct be_rx_obj { | |
214 | struct be_queue_info q; | |
215 | struct be_queue_info cq; | |
216 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; | |
6b7c5b94 SP |
217 | }; |
218 | ||
219 | #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */ | |
220 | struct be_adapter { | |
221 | struct pci_dev *pdev; | |
222 | struct net_device *netdev; | |
223 | ||
8788fdc2 SP |
224 | u8 __iomem *csr; |
225 | u8 __iomem *db; /* Door Bell */ | |
226 | u8 __iomem *pcicfg; /* PCI config space */ | |
8788fdc2 SP |
227 | |
228 | spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */ | |
229 | struct be_dma_mem mbox_mem; | |
230 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | |
231 | * is stored for freeing purpose */ | |
232 | struct be_dma_mem mbox_mem_alloced; | |
233 | ||
234 | struct be_mcc_obj mcc_obj; | |
235 | spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ | |
236 | spinlock_t mcc_cq_lock; | |
6b7c5b94 SP |
237 | |
238 | struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS]; | |
239 | bool msix_enabled; | |
240 | bool isr_registered; | |
241 | ||
242 | /* TX Rings */ | |
243 | struct be_eq_obj tx_eq; | |
244 | struct be_tx_obj tx_obj; | |
245 | ||
246 | u32 cache_line_break[8]; | |
247 | ||
248 | /* Rx rings */ | |
249 | struct be_eq_obj rx_eq; | |
250 | struct be_rx_obj rx_obj; | |
251 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ | |
ea1dae11 | 252 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ |
6b7c5b94 SP |
253 | |
254 | struct vlan_group *vlan_grp; | |
255 | u16 num_vlans; | |
256 | u8 vlan_tag[VLAN_GROUP_ARRAY_LEN]; | |
e7b909a6 | 257 | struct be_dma_mem mc_cmd_mem; |
6b7c5b94 SP |
258 | |
259 | struct be_stats_obj stats; | |
260 | /* Work queue used to perform periodic tasks like getting statistics */ | |
261 | struct delayed_work work; | |
262 | ||
263 | /* Ethtool knobs and info */ | |
264 | bool rx_csum; /* BE card must perform rx-checksumming */ | |
6b7c5b94 SP |
265 | char fw_ver[FW_VER_LEN]; |
266 | u32 if_handle; /* Used to configure filtering */ | |
267 | u32 pmac_id; /* MAC addr handle used by BE card */ | |
268 | ||
a8f447bd | 269 | bool link_up; |
6b7c5b94 | 270 | u32 port_num; |
24307eef | 271 | bool promiscuous; |
71d8d1b5 | 272 | bool wol; |
dcb9b564 | 273 | u32 cap; |
9e90c961 AK |
274 | u32 rx_fc; /* Rx flow control */ |
275 | u32 tx_fc; /* Tx flow control */ | |
0dffc83e AK |
276 | int link_speed; |
277 | u8 port_type; | |
16c02145 | 278 | u8 transceiver; |
7b139c83 | 279 | u8 generation; /* BladeEngine ASIC generation */ |
6b7c5b94 SP |
280 | }; |
281 | ||
7b139c83 AK |
282 | /* BladeEngine Generation numbers */ |
283 | #define BE_GEN2 2 | |
284 | #define BE_GEN3 3 | |
285 | ||
0fc0b732 | 286 | extern const struct ethtool_ops be_ethtool_ops; |
6b7c5b94 SP |
287 | |
288 | #define drvr_stats(adapter) (&adapter->stats.drvr_stats) | |
289 | ||
eec368fb SP |
290 | static inline unsigned int be_pci_func(struct be_adapter *adapter) |
291 | { | |
292 | return PCI_FUNC(adapter->pdev->devfn); | |
293 | } | |
294 | ||
6b7c5b94 SP |
295 | #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) |
296 | ||
6b7c5b94 SP |
297 | #define PAGE_SHIFT_4K 12 |
298 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | |
299 | ||
300 | /* Returns number of pages spanned by the data starting at the given addr */ | |
301 | #define PAGES_4K_SPANNED(_address, size) \ | |
302 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | |
303 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | |
304 | ||
305 | /* Byte offset into the page corresponding to given address */ | |
306 | #define OFFSET_IN_PAGE(addr) \ | |
307 | ((size_t)(addr) & (PAGE_SIZE_4K-1)) | |
308 | ||
309 | /* Returns bit offset within a DWORD of a bitfield */ | |
310 | #define AMAP_BIT_OFFSET(_struct, field) \ | |
311 | (((size_t)&(((_struct *)0)->field))%32) | |
312 | ||
313 | /* Returns the bit mask of the field that is NOT shifted into location. */ | |
314 | static inline u32 amap_mask(u32 bitsize) | |
315 | { | |
316 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | |
317 | } | |
318 | ||
319 | static inline void | |
320 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | |
321 | { | |
322 | u32 *dw = (u32 *) ptr + dw_offset; | |
323 | *dw &= ~(mask << offset); | |
324 | *dw |= (mask & value) << offset; | |
325 | } | |
326 | ||
327 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | |
328 | amap_set(ptr, \ | |
329 | offsetof(_struct, field)/32, \ | |
330 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
331 | AMAP_BIT_OFFSET(_struct, field), \ | |
332 | val) | |
333 | ||
334 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | |
335 | { | |
336 | u32 *dw = (u32 *) ptr; | |
337 | return mask & (*(dw + dw_offset) >> offset); | |
338 | } | |
339 | ||
340 | #define AMAP_GET_BITS(_struct, field, ptr) \ | |
341 | amap_get(ptr, \ | |
342 | offsetof(_struct, field)/32, \ | |
343 | amap_mask(sizeof(((_struct *)0)->field)), \ | |
344 | AMAP_BIT_OFFSET(_struct, field)) | |
345 | ||
346 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | |
347 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | |
348 | static inline void swap_dws(void *wrb, int len) | |
349 | { | |
350 | #ifdef __BIG_ENDIAN | |
351 | u32 *dw = wrb; | |
352 | BUG_ON(len % 4); | |
353 | do { | |
354 | *dw = cpu_to_le32(*dw); | |
355 | dw++; | |
356 | len -= 4; | |
357 | } while (len); | |
358 | #endif /* __BIG_ENDIAN */ | |
359 | } | |
360 | ||
361 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | |
362 | { | |
363 | u8 val = 0; | |
364 | ||
365 | if (ip_hdr(skb)->version == 4) | |
366 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | |
367 | else if (ip_hdr(skb)->version == 6) | |
368 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | |
369 | ||
370 | return val; | |
371 | } | |
372 | ||
373 | static inline u8 is_udp_pkt(struct sk_buff *skb) | |
374 | { | |
375 | u8 val = 0; | |
376 | ||
377 | if (ip_hdr(skb)->version == 4) | |
378 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | |
379 | else if (ip_hdr(skb)->version == 6) | |
380 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | |
381 | ||
382 | return val; | |
383 | } | |
384 | ||
8788fdc2 | 385 | extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, |
5fb379ee | 386 | u16 num_popped); |
8788fdc2 | 387 | extern void be_link_status_update(struct be_adapter *adapter, bool link_up); |
b31c50a7 | 388 | extern void netdev_stats_update(struct be_adapter *adapter); |
84517482 | 389 | extern int be_load_fw(struct be_adapter *adapter, u8 *func); |
6b7c5b94 | 390 | #endif /* BE_H */ |