projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] changing CONFIG_LOCALVERSION rebuilds too much, for no good reason
[linux-2.6-block.git] / drivers / net / b44.c
CommitLineData
1da177e4
LT		 1/* b44.c: Broadcom 4400 device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
5 *
6 * Distribute under GPL.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/types.h>
13#include <linux/netdevice.h>
14#include <linux/ethtool.h>
15#include <linux/mii.h>
16#include <linux/if_ether.h>
17#include <linux/etherdevice.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/init.h>
89358f90 21#include <linux/dma-mapping.h>
1da177e4
LT		 22
23#include <asm/uaccess.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include "b44.h"
28
29#define DRV_MODULE_NAME "b44"
30#define PFX DRV_MODULE_NAME ": "
31#define DRV_MODULE_VERSION "0.95"
32#define DRV_MODULE_RELDATE "Aug 3, 2004"
33
34#define B44_DEF_MSG_ENABLE \
35 (NETIF_MSG_DRV | \
36 NETIF_MSG_PROBE | \
37 NETIF_MSG_LINK | \
38 NETIF_MSG_TIMER | \
39 NETIF_MSG_IFDOWN | \
40 NETIF_MSG_IFUP | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR)
43
44/* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
46 */
47#define B44_TX_TIMEOUT (5 * HZ)
48
49/* hardware minimum and maximum for a single frame's data payload */
50#define B44_MIN_MTU 60
51#define B44_MAX_MTU 1500
52
53#define B44_RX_RING_SIZE 512
54#define B44_DEF_RX_RING_PENDING 200
55#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
56 B44_RX_RING_SIZE)
57#define B44_TX_RING_SIZE 512
58#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
60 B44_TX_RING_SIZE)
61#define B44_DMA_MASK 0x3fffffff
62
63#define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65#define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
70
71#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72#define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
73
74/* minimum number of free TX descriptors required to wake up TX process */
75#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
76
77static char version[] __devinitdata =
78 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79
80MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
84
85static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86module_param(b44_debug, int, 0);
87MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
88
89static struct pci_device_id b44_pci_tbl[] = {
90 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
94 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
96 { } /* terminate list with empty entry */
97};
98
99MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
100
101static void b44_halt(struct b44 *);
102static void b44_init_rings(struct b44 *);
103static void b44_init_hw(struct b44 *);
104static int b44_poll(struct net_device *dev, int *budget);
105#ifdef CONFIG_NET_POLL_CONTROLLER
106static void b44_poll_controller(struct net_device *dev);
107#endif
108
9f38c636
JL		 109static int dma_desc_align_mask;
110static int dma_desc_sync_size;
111
112static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
113 dma_addr_t dma_base,
114 unsigned long offset,
115 enum dma_data_direction dir)
116{
117 dma_sync_single_range_for_device(&pdev->dev, dma_base,
118 offset & dma_desc_align_mask,
119 dma_desc_sync_size, dir);
120}
121
122static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
123 dma_addr_t dma_base,
124 unsigned long offset,
125 enum dma_data_direction dir)
126{
127 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
128 offset & dma_desc_align_mask,
129 dma_desc_sync_size, dir);
130}
131
1da177e4
LT		 132static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
133{
134 return readl(bp->regs + reg);
135}
136
137static inline void bw32(const struct b44 *bp,
138 unsigned long reg, unsigned long val)
139{
140 writel(val, bp->regs + reg);
141}
142
143static int b44_wait_bit(struct b44 *bp, unsigned long reg,
144 u32 bit, unsigned long timeout, const int clear)
145{
146 unsigned long i;
147
148 for (i = 0; i < timeout; i++) {
149 u32 val = br32(bp, reg);
150
151 if (clear && !(val & bit))
152 break;
153 if (!clear && (val & bit))
154 break;
155 udelay(10);
156 }
157 if (i == timeout) {
158 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
159 "%lx to %s.\n",
160 bp->dev->name,
161 bit, reg,
162 (clear ? "clear" : "set"));
163 return -ENODEV;
164 }
165 return 0;
166}
167
168/* Sonics SiliconBackplane support routines. ROFL, you should see all the
169 * buzz words used on this company's website :-)
170 *
171 * All of these routines must be invoked with bp->lock held and
172 * interrupts disabled.
173 */
174
175#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
176#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
177
178static u32 ssb_get_core_rev(struct b44 *bp)
179{
180 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
181}
182
183static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
184{
185 u32 bar_orig, pci_rev, val;
186
187 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
188 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
189 pci_rev = ssb_get_core_rev(bp);
190
191 val = br32(bp, B44_SBINTVEC);
192 val |= cores;
193 bw32(bp, B44_SBINTVEC, val);
194
195 val = br32(bp, SSB_PCI_TRANS_2);
196 val |= SSB_PCI_PREF | SSB_PCI_BURST;
197 bw32(bp, SSB_PCI_TRANS_2, val);
198
199 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
200
201 return pci_rev;
202}
203
204static void ssb_core_disable(struct b44 *bp)
205{
206 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
207 return;
208
209 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
210 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
211 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
212 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
213 SBTMSLOW_REJECT | SBTMSLOW_RESET));
214 br32(bp, B44_SBTMSLOW);
215 udelay(1);
216 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
217 br32(bp, B44_SBTMSLOW);
218 udelay(1);
219}
220
221static void ssb_core_reset(struct b44 *bp)
222{
223 u32 val;
224
225 ssb_core_disable(bp);
226 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
227 br32(bp, B44_SBTMSLOW);
228 udelay(1);
229
230 /* Clear SERR if set, this is a hw bug workaround. */
231 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
232 bw32(bp, B44_SBTMSHIGH, 0);
233
234 val = br32(bp, B44_SBIMSTATE);
235 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
236 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
237
238 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
239 br32(bp, B44_SBTMSLOW);
240 udelay(1);
241
242 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
243 br32(bp, B44_SBTMSLOW);
244 udelay(1);
245}
246
247static int ssb_core_unit(struct b44 *bp)
248{
249#if 0
250 u32 val = br32(bp, B44_SBADMATCH0);
251 u32 base;
252
253 type = val & SBADMATCH0_TYPE_MASK;
254 switch (type) {
255 case 0:
256 base = val & SBADMATCH0_BS0_MASK;
257 break;
258
259 case 1:
260 base = val & SBADMATCH0_BS1_MASK;
261 break;
262
263 case 2:
264 default:
265 base = val & SBADMATCH0_BS2_MASK;
266 break;
267 };
268#endif
269 return 0;
270}
271
272static int ssb_is_core_up(struct b44 *bp)
273{
274 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
275 == SBTMSLOW_CLOCK);
276}
277
278static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
279{
280 u32 val;
281
282 val = ((u32) data[2]) << 24;
283 val |= ((u32) data[3]) << 16;
284 val |= ((u32) data[4]) << 8;
285 val |= ((u32) data[5]) << 0;
286 bw32(bp, B44_CAM_DATA_LO, val);
287 val = (CAM_DATA_HI_VALID |
288 (((u32) data[0]) << 8) |
289 (((u32) data[1]) << 0));
290 bw32(bp, B44_CAM_DATA_HI, val);
291 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
292 (index << CAM_CTRL_INDEX_SHIFT)));
293 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
294}
295
296static inline void __b44_disable_ints(struct b44 *bp)
297{
298 bw32(bp, B44_IMASK, 0);
299}
300
301static void b44_disable_ints(struct b44 *bp)
302{
303 __b44_disable_ints(bp);
304
305 /* Flush posted writes. */
306 br32(bp, B44_IMASK);
307}
308
309static void b44_enable_ints(struct b44 *bp)
310{
311 bw32(bp, B44_IMASK, bp->imask);
312}
313
314static int b44_readphy(struct b44 *bp, int reg, u32 *val)
315{
316 int err;
317
318 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
319 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
320 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
321 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
322 (reg << MDIO_DATA_RA_SHIFT) |
323 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
324 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
325 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
326
327 return err;
328}
329
330static int b44_writephy(struct b44 *bp, int reg, u32 val)
331{
332 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
333 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
334 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
335 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
336 (reg << MDIO_DATA_RA_SHIFT) |
337 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
338 (val & MDIO_DATA_DATA)));
339 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
340}
341
342/* miilib interface */
343/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
344 * due to code existing before miilib use was added to this driver.
345 * Someone should remove this artificial driver limitation in
346 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
347 */
348static int b44_mii_read(struct net_device *dev, int phy_id, int location)
349{
350 u32 val;
351 struct b44 *bp = netdev_priv(dev);
352 int rc = b44_readphy(bp, location, &val);
353 if (rc)
354 return 0xffffffff;
355 return val;
356}
357
358static void b44_mii_write(struct net_device *dev, int phy_id, int location,
359 int val)
360{
361 struct b44 *bp = netdev_priv(dev);
362 b44_writephy(bp, location, val);
363}
364
365static int b44_phy_reset(struct b44 *bp)
366{
367 u32 val;
368 int err;
369
370 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
371 if (err)
372 return err;
373 udelay(100);
374 err = b44_readphy(bp, MII_BMCR, &val);
375 if (!err) {
376 if (val & BMCR_RESET) {
377 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
378 bp->dev->name);
379 err = -ENODEV;
380 }
381 }
382
383 return 0;
384}
385
386static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
387{
388 u32 val;
389
390 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
391 bp->flags |= pause_flags;
392
393 val = br32(bp, B44_RXCONFIG);
394 if (pause_flags & B44_FLAG_RX_PAUSE)
395 val |= RXCONFIG_FLOW;
396 else
397 val &= ~RXCONFIG_FLOW;
398 bw32(bp, B44_RXCONFIG, val);
399
400 val = br32(bp, B44_MAC_FLOW);
401 if (pause_flags & B44_FLAG_TX_PAUSE)
402 val |= (MAC_FLOW_PAUSE_ENAB |
403 (0xc0 & MAC_FLOW_RX_HI_WATER));
404 else
405 val &= ~MAC_FLOW_PAUSE_ENAB;
406 bw32(bp, B44_MAC_FLOW, val);
407}
408
409static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
410{
411 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
412 B44_FLAG_RX_PAUSE);
413
414 if (local & ADVERTISE_PAUSE_CAP) {
415 if (local & ADVERTISE_PAUSE_ASYM) {
416 if (remote & LPA_PAUSE_CAP)
417 pause_enab |= (B44_FLAG_TX_PAUSE |
418 B44_FLAG_RX_PAUSE);
419 else if (remote & LPA_PAUSE_ASYM)
420 pause_enab |= B44_FLAG_RX_PAUSE;
421 } else {
422 if (remote & LPA_PAUSE_CAP)
423 pause_enab |= (B44_FLAG_TX_PAUSE |
424 B44_FLAG_RX_PAUSE);
425 }
426 } else if (local & ADVERTISE_PAUSE_ASYM) {
427 if ((remote & LPA_PAUSE_CAP) &&
428 (remote & LPA_PAUSE_ASYM))
429 pause_enab |= B44_FLAG_TX_PAUSE;
430 }
431
432 __b44_set_flow_ctrl(bp, pause_enab);
433}
434
435static int b44_setup_phy(struct b44 *bp)
436{
437 u32 val;
438 int err;
439
440 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
441 goto out;
442 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
443 val & MII_ALEDCTRL_ALLMSK)) != 0)
444 goto out;
445 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
446 goto out;
447 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
448 val | MII_TLEDCTRL_ENABLE)) != 0)
449 goto out;
450
451 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
452 u32 adv = ADVERTISE_CSMA;
453
454 if (bp->flags & B44_FLAG_ADV_10HALF)
455 adv |= ADVERTISE_10HALF;
456 if (bp->flags & B44_FLAG_ADV_10FULL)
457 adv |= ADVERTISE_10FULL;
458 if (bp->flags & B44_FLAG_ADV_100HALF)
459 adv |= ADVERTISE_100HALF;
460 if (bp->flags & B44_FLAG_ADV_100FULL)
461 adv |= ADVERTISE_100FULL;
462
463 if (bp->flags & B44_FLAG_PAUSE_AUTO)
464 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
465
466 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
467 goto out;
468 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
469 BMCR_ANRESTART))) != 0)
470 goto out;
471 } else {
472 u32 bmcr;
473
474 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
475 goto out;
476 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
477 if (bp->flags & B44_FLAG_100_BASE_T)
478 bmcr |= BMCR_SPEED100;
479 if (bp->flags & B44_FLAG_FULL_DUPLEX)
480 bmcr |= BMCR_FULLDPLX;
481 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
482 goto out;
483
484 /* Since we will not be negotiating there is no safe way
485 * to determine if the link partner supports flow control
486 * or not. So just disable it completely in this case.
487 */
488 b44_set_flow_ctrl(bp, 0, 0);
489 }
490
491out:
492 return err;
493}
494
495static void b44_stats_update(struct b44 *bp)
496{
497 unsigned long reg;
498 u32 *val;
499
500 val = &bp->hw_stats.tx_good_octets;
501 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504 val = &bp->hw_stats.rx_good_octets;
505 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
506 *val++ += br32(bp, reg);
507 }
508}
509
510static void b44_link_report(struct b44 *bp)
511{
512 if (!netif_carrier_ok(bp->dev)) {
513 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
514 } else {
515 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
516 bp->dev->name,
517 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
518 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
519
520 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
521 "%s for RX.\n",
522 bp->dev->name,
523 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
524 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
525 }
526}
527
528static void b44_check_phy(struct b44 *bp)
529{
530 u32 bmsr, aux;
531
532 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
533 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
534 (bmsr != 0xffff)) {
535 if (aux & MII_AUXCTRL_SPEED)
536 bp->flags |= B44_FLAG_100_BASE_T;
537 else
538 bp->flags &= ~B44_FLAG_100_BASE_T;
539 if (aux & MII_AUXCTRL_DUPLEX)
540 bp->flags |= B44_FLAG_FULL_DUPLEX;
541 else
542 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
543
544 if (!netif_carrier_ok(bp->dev) &&
545 (bmsr & BMSR_LSTATUS)) {
546 u32 val = br32(bp, B44_TX_CTRL);
547 u32 local_adv, remote_adv;
548
549 if (bp->flags & B44_FLAG_FULL_DUPLEX)
550 val |= TX_CTRL_DUPLEX;
551 else
552 val &= ~TX_CTRL_DUPLEX;
553 bw32(bp, B44_TX_CTRL, val);
554
555 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
556 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
557 !b44_readphy(bp, MII_LPA, &remote_adv))
558 b44_set_flow_ctrl(bp, local_adv, remote_adv);
559
560 /* Link now up */
561 netif_carrier_on(bp->dev);
562 b44_link_report(bp);
563 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
564 /* Link now down */
565 netif_carrier_off(bp->dev);
566 b44_link_report(bp);
567 }
568
569 if (bmsr & BMSR_RFAULT)
570 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
571 bp->dev->name);
572 if (bmsr & BMSR_JCD)
573 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
574 bp->dev->name);
575 }
576}
577
578static void b44_timer(unsigned long __opaque)
579{
580 struct b44 *bp = (struct b44 *) __opaque;
581
582 spin_lock_irq(&bp->lock);
583
584 b44_check_phy(bp);
585
586 b44_stats_update(bp);
587
588 spin_unlock_irq(&bp->lock);
589
590 bp->timer.expires = jiffies + HZ;
591 add_timer(&bp->timer);
592}
593
594static void b44_tx(struct b44 *bp)
595{
596 u32 cur, cons;
597
598 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
599 cur /= sizeof(struct dma_desc);
600
601 /* XXX needs updating when NETIF_F_SG is supported */
602 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
603 struct ring_info *rp = &bp->tx_buffers[cons];
604 struct sk_buff *skb = rp->skb;
605
606 if (unlikely(skb == NULL))
607 BUG();
608
609 pci_unmap_single(bp->pdev,
610 pci_unmap_addr(rp, mapping),
611 skb->len,
612 PCI_DMA_TODEVICE);
613 rp->skb = NULL;
614 dev_kfree_skb_irq(skb);
615 }
616
617 bp->tx_cons = cons;
618 if (netif_queue_stopped(bp->dev) &&
619 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
620 netif_wake_queue(bp->dev);
621
622 bw32(bp, B44_GPTIMER, 0);
623}
624
625/* Works like this. This chip writes a 'struct rx_header" 30 bytes
626 * before the DMA address you give it. So we allocate 30 more bytes
627 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
628 * point the chip at 30 bytes past where the rx_header will go.
629 */
630static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
631{
632 struct dma_desc *dp;
633 struct ring_info *src_map, *map;
634 struct rx_header *rh;
635 struct sk_buff *skb;
636 dma_addr_t mapping;
637 int dest_idx;
638 u32 ctrl;
639
640 src_map = NULL;
641 if (src_idx >= 0)
642 src_map = &bp->rx_buffers[src_idx];
643 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
644 map = &bp->rx_buffers[dest_idx];
645 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
646 if (skb == NULL)
647 return -ENOMEM;
648
649 mapping = pci_map_single(bp->pdev, skb->data,
650 RX_PKT_BUF_SZ,
651 PCI_DMA_FROMDEVICE);
652
653 /* Hardware bug work-around, the chip is unable to do PCI DMA
654 to/from anything above 1GB :-( */
655 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
656 /* Sigh... */
657 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
658 dev_kfree_skb_any(skb);
659 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
660 if (skb == NULL)
661 return -ENOMEM;
662 mapping = pci_map_single(bp->pdev, skb->data,
663 RX_PKT_BUF_SZ,
664 PCI_DMA_FROMDEVICE);
665 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
666 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
667 dev_kfree_skb_any(skb);
668 return -ENOMEM;
669 }
670 }
671
672 skb->dev = bp->dev;
673 skb_reserve(skb, bp->rx_offset);
674
675 rh = (struct rx_header *)
676 (skb->data - bp->rx_offset);
677 rh->len = 0;
678 rh->flags = 0;
679
680 map->skb = skb;
681 pci_unmap_addr_set(map, mapping, mapping);
682
683 if (src_map != NULL)
684 src_map->skb = NULL;
685
686 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
687 if (dest_idx == (B44_RX_RING_SIZE - 1))
688 ctrl |= DESC_CTRL_EOT;
689
690 dp = &bp->rx_ring[dest_idx];
691 dp->ctrl = cpu_to_le32(ctrl);
692 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
693
9f38c636
JL		 694 if (bp->flags & B44_FLAG_RX_RING_HACK)
695 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
696 dest_idx * sizeof(dp),
697 DMA_BIDIRECTIONAL);
698
1da177e4
LT		 699 return RX_PKT_BUF_SZ;
700}
701
702static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
703{
704 struct dma_desc *src_desc, *dest_desc;
705 struct ring_info *src_map, *dest_map;
706 struct rx_header *rh;
707 int dest_idx;
708 u32 ctrl;
709
710 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
711 dest_desc = &bp->rx_ring[dest_idx];
712 dest_map = &bp->rx_buffers[dest_idx];
713 src_desc = &bp->rx_ring[src_idx];
714 src_map = &bp->rx_buffers[src_idx];
715
716 dest_map->skb = src_map->skb;
717 rh = (struct rx_header *) src_map->skb->data;
718 rh->len = 0;
719 rh->flags = 0;
720 pci_unmap_addr_set(dest_map, mapping,
721 pci_unmap_addr(src_map, mapping));
722
9f38c636
JL		 723 if (bp->flags & B44_FLAG_RX_RING_HACK)
724 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
725 src_idx * sizeof(src_desc),
726 DMA_BIDIRECTIONAL);
727
1da177e4
LT		 728 ctrl = src_desc->ctrl;
729 if (dest_idx == (B44_RX_RING_SIZE - 1))
730 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
731 else
732 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
733
734 dest_desc->ctrl = ctrl;
735 dest_desc->addr = src_desc->addr;
9f38c636 736
1da177e4
LT		 737 src_map->skb = NULL;
738
9f38c636
JL		 739 if (bp->flags & B44_FLAG_RX_RING_HACK)
740 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
741 dest_idx * sizeof(dest_desc),
742 DMA_BIDIRECTIONAL);
743
1da177e4
LT		 744 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
745 RX_PKT_BUF_SZ,
746 PCI_DMA_FROMDEVICE);
747}
748
749static int b44_rx(struct b44 *bp, int budget)
750{
751 int received;
752 u32 cons, prod;
753
754 received = 0;
755 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
756 prod /= sizeof(struct dma_desc);
757 cons = bp->rx_cons;
758
759 while (cons != prod && budget > 0) {
760 struct ring_info *rp = &bp->rx_buffers[cons];
761 struct sk_buff *skb = rp->skb;
762 dma_addr_t map = pci_unmap_addr(rp, mapping);
763 struct rx_header *rh;
764 u16 len;
765
766 pci_dma_sync_single_for_cpu(bp->pdev, map,
767 RX_PKT_BUF_SZ,
768 PCI_DMA_FROMDEVICE);
769 rh = (struct rx_header *) skb->data;
770 len = cpu_to_le16(rh->len);
771 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
772 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
773 drop_it:
774 b44_recycle_rx(bp, cons, bp->rx_prod);
775 drop_it_no_recycle:
776 bp->stats.rx_dropped++;
777 goto next_pkt;
778 }
779
780 if (len == 0) {
781 int i = 0;
782
783 do {
784 udelay(2);
785 barrier();
786 len = cpu_to_le16(rh->len);
787 } while (len == 0 && i++ < 5);
788 if (len == 0)
789 goto drop_it;
790 }
791
792 /* Omit CRC. */
793 len -= 4;
794
795 if (len > RX_COPY_THRESHOLD) {
796 int skb_size;
797 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
798 if (skb_size < 0)
799 goto drop_it;
800 pci_unmap_single(bp->pdev, map,
801 skb_size, PCI_DMA_FROMDEVICE);
802 /* Leave out rx_header */
803 skb_put(skb, len+bp->rx_offset);
804 skb_pull(skb,bp->rx_offset);
805 } else {
806 struct sk_buff *copy_skb;
807
808 b44_recycle_rx(bp, cons, bp->rx_prod);
809 copy_skb = dev_alloc_skb(len + 2);
810 if (copy_skb == NULL)
811 goto drop_it_no_recycle;
812
813 copy_skb->dev = bp->dev;
814 skb_reserve(copy_skb, 2);
815 skb_put(copy_skb, len);
816 /* DMA sync done above, copy just the actual packet */
817 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
818
819 skb = copy_skb;
820 }
821 skb->ip_summed = CHECKSUM_NONE;
822 skb->protocol = eth_type_trans(skb, bp->dev);
823 netif_receive_skb(skb);
824 bp->dev->last_rx = jiffies;
825 received++;
826 budget--;
827 next_pkt:
828 bp->rx_prod = (bp->rx_prod + 1) &
829 (B44_RX_RING_SIZE - 1);
830 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
831 }
832
833 bp->rx_cons = cons;
834 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
835
836 return received;
837}
838
839static int b44_poll(struct net_device *netdev, int *budget)
840{
841 struct b44 *bp = netdev_priv(netdev);
842 int done;
843
844 spin_lock_irq(&bp->lock);
845
846 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
847 /* spin_lock(&bp->tx_lock); */
848 b44_tx(bp);
849 /* spin_unlock(&bp->tx_lock); */
850 }
851 spin_unlock_irq(&bp->lock);
852
853 done = 1;
854 if (bp->istat & ISTAT_RX) {
855 int orig_budget = *budget;
856 int work_done;
857
858 if (orig_budget > netdev->quota)
859 orig_budget = netdev->quota;
860
861 work_done = b44_rx(bp, orig_budget);
862
863 *budget -= work_done;
864 netdev->quota -= work_done;
865
866 if (work_done >= orig_budget)
867 done = 0;
868 }
869
870 if (bp->istat & ISTAT_ERRORS) {
871 spin_lock_irq(&bp->lock);
872 b44_halt(bp);
873 b44_init_rings(bp);
874 b44_init_hw(bp);
875 netif_wake_queue(bp->dev);
876 spin_unlock_irq(&bp->lock);
877 done = 1;
878 }
879
880 if (done) {
881 netif_rx_complete(netdev);
882 b44_enable_ints(bp);
883 }
884
885 return (done ? 0 : 1);
886}
887
888static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
889{
890 struct net_device *dev = dev_id;
891 struct b44 *bp = netdev_priv(dev);
892 unsigned long flags;
893 u32 istat, imask;
894 int handled = 0;
895
896 spin_lock_irqsave(&bp->lock, flags);
897
898 istat = br32(bp, B44_ISTAT);
899 imask = br32(bp, B44_IMASK);
900
901 /* ??? What the fuck is the purpose of the interrupt mask
902 * ??? register if we have to mask it out by hand anyways?
903 */
904 istat &= imask;
905 if (istat) {
906 handled = 1;
907 if (netif_rx_schedule_prep(dev)) {
908 /* NOTE: These writes are posted by the readback of
909 * the ISTAT register below.
910 */
911 bp->istat = istat;
912 __b44_disable_ints(bp);
913 __netif_rx_schedule(dev);
914 } else {
915 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
916 dev->name);
917 }
918
919 bw32(bp, B44_ISTAT, istat);
920 br32(bp, B44_ISTAT);
921 }
922 spin_unlock_irqrestore(&bp->lock, flags);
923 return IRQ_RETVAL(handled);
924}
925
926static void b44_tx_timeout(struct net_device *dev)
927{
928 struct b44 *bp = netdev_priv(dev);
929
930 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
931 dev->name);
932
933 spin_lock_irq(&bp->lock);
934
935 b44_halt(bp);
936 b44_init_rings(bp);
937 b44_init_hw(bp);
938
939 spin_unlock_irq(&bp->lock);
940
941 b44_enable_ints(bp);
942
943 netif_wake_queue(dev);
944}
945
946static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
947{
948 struct b44 *bp = netdev_priv(dev);
949 struct sk_buff *bounce_skb;
950 dma_addr_t mapping;
951 u32 len, entry, ctrl;
952
953 len = skb->len;
954 spin_lock_irq(&bp->lock);
955
956 /* This is a hard error, log it. */
957 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
958 netif_stop_queue(dev);
959 spin_unlock_irq(&bp->lock);
960 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
961 dev->name);
962 return 1;
963 }
964
965 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
966 if(mapping+len > B44_DMA_MASK) {
967 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
968 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
969
970 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
971 GFP_ATOMIC|GFP_DMA);
972 if (!bounce_skb)
973 return NETDEV_TX_BUSY;
974
975 mapping = pci_map_single(bp->pdev, bounce_skb->data,
976 len, PCI_DMA_TODEVICE);
977 if(mapping+len > B44_DMA_MASK) {
978 pci_unmap_single(bp->pdev, mapping,
979 len, PCI_DMA_TODEVICE);
980 dev_kfree_skb_any(bounce_skb);
981 return NETDEV_TX_BUSY;
982 }
983
984 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
985 dev_kfree_skb_any(skb);
986 skb = bounce_skb;
987 }
988
989 entry = bp->tx_prod;
990 bp->tx_buffers[entry].skb = skb;
991 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
992
993 ctrl = (len & DESC_CTRL_LEN);
994 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
995 if (entry == (B44_TX_RING_SIZE - 1))
996 ctrl |= DESC_CTRL_EOT;
997
998 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
999 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1000
9f38c636
JL		 1001 if (bp->flags & B44_FLAG_TX_RING_HACK)
1002 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1003 entry * sizeof(bp->tx_ring[0]),
1004 DMA_TO_DEVICE);
1005
1da177e4
LT		 1006 entry = NEXT_TX(entry);
1007
1008 bp->tx_prod = entry;
1009
1010 wmb();
1011
1012 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1013 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1014 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1015 if (bp->flags & B44_FLAG_REORDER_BUG)
1016 br32(bp, B44_DMATX_PTR);
1017
1018 if (TX_BUFFS_AVAIL(bp) < 1)
1019 netif_stop_queue(dev);
1020
1021 spin_unlock_irq(&bp->lock);
1022
1023 dev->trans_start = jiffies;
1024
1025 return 0;
1026}
1027
1028static int b44_change_mtu(struct net_device *dev, int new_mtu)
1029{
1030 struct b44 *bp = netdev_priv(dev);
1031
1032 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1033 return -EINVAL;
1034
1035 if (!netif_running(dev)) {
1036 /* We'll just catch it later when the
1037 * device is up'd.
1038 */
1039 dev->mtu = new_mtu;
1040 return 0;
1041 }
1042
1043 spin_lock_irq(&bp->lock);
1044 b44_halt(bp);
1045 dev->mtu = new_mtu;
1046 b44_init_rings(bp);
1047 b44_init_hw(bp);
1048 spin_unlock_irq(&bp->lock);
1049
1050 b44_enable_ints(bp);
1051
1052 return 0;
1053}
1054
1055/* Free up pending packets in all rx/tx rings.
1056 *
1057 * The chip has been shut down and the driver detached from
1058 * the networking, so no interrupts or new tx packets will
1059 * end up in the driver. bp->lock is not held and we are not
1060 * in an interrupt context and thus may sleep.
1061 */
1062static void b44_free_rings(struct b44 *bp)
1063{
1064 struct ring_info *rp;
1065 int i;
1066
1067 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1068 rp = &bp->rx_buffers[i];
1069
1070 if (rp->skb == NULL)
1071 continue;
1072 pci_unmap_single(bp->pdev,
1073 pci_unmap_addr(rp, mapping),
1074 RX_PKT_BUF_SZ,
1075 PCI_DMA_FROMDEVICE);
1076 dev_kfree_skb_any(rp->skb);
1077 rp->skb = NULL;
1078 }
1079
1080 /* XXX needs changes once NETIF_F_SG is set... */
1081 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1082 rp = &bp->tx_buffers[i];
1083
1084 if (rp->skb == NULL)
1085 continue;
1086 pci_unmap_single(bp->pdev,
1087 pci_unmap_addr(rp, mapping),
1088 rp->skb->len,
1089 PCI_DMA_TODEVICE);
1090 dev_kfree_skb_any(rp->skb);
1091 rp->skb = NULL;
1092 }
1093}
1094
1095/* Initialize tx/rx rings for packet processing.
1096 *
1097 * The chip has been shut down and the driver detached from
1098 * the networking, so no interrupts or new tx packets will
1099 * end up in the driver. bp->lock is not held and we are not
1100 * in an interrupt context and thus may sleep.
1101 */
1102static void b44_init_rings(struct b44 *bp)
1103{
1104 int i;
1105
1106 b44_free_rings(bp);
1107
1108 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1109 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1110
9f38c636
JL		 1111 if (bp->flags & B44_FLAG_RX_RING_HACK)
1112 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1113 DMA_TABLE_BYTES,
1114 PCI_DMA_BIDIRECTIONAL);
1115
1116 if (bp->flags & B44_FLAG_TX_RING_HACK)
1117 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1118 DMA_TABLE_BYTES,
1119 PCI_DMA_TODEVICE);
1120
1da177e4
LT		 1121 for (i = 0; i < bp->rx_pending; i++) {
1122 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1123 break;
1124 }
1125}
1126
1127/*
1128 * Must not be invoked with interrupt sources disabled and
1129 * the hardware shutdown down.
1130 */
1131static void b44_free_consistent(struct b44 *bp)
1132{
b4558ea9
JJ		 1133 kfree(bp->rx_buffers);
1134 bp->rx_buffers = NULL;
1135 kfree(bp->tx_buffers);
1136 bp->tx_buffers = NULL;
1da177e4 1137 if (bp->rx_ring) {
9f38c636
JL		 1138 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1139 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1140 DMA_TABLE_BYTES,
1141 DMA_BIDIRECTIONAL);
1142 kfree(bp->rx_ring);
1143 } else
1144 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1145 bp->rx_ring, bp->rx_ring_dma);
1da177e4 1146 bp->rx_ring = NULL;
9f38c636 1147 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1148 }
1149 if (bp->tx_ring) {
9f38c636
JL		 1150 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1151 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1152 DMA_TABLE_BYTES,
1153 DMA_TO_DEVICE);
1154 kfree(bp->tx_ring);
1155 } else
1156 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1157 bp->tx_ring, bp->tx_ring_dma);
1da177e4 1158 bp->tx_ring = NULL;
9f38c636 1159 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1160 }
1161}
1162
1163/*
1164 * Must not be invoked with interrupt sources disabled and
1165 * the hardware shutdown down. Can sleep.
1166 */
1167static int b44_alloc_consistent(struct b44 *bp)
1168{
1169 int size;
1170
1171 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1172 bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1173 if (!bp->rx_buffers)
1174 goto out_err;
1175 memset(bp->rx_buffers, 0, size);
1176
1177 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1178 bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1179 if (!bp->tx_buffers)
1180 goto out_err;
1181 memset(bp->tx_buffers, 0, size);
1182
1183 size = DMA_TABLE_BYTES;
1184 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
9f38c636
JL		 1185 if (!bp->rx_ring) {
1186 /* Allocation may have failed due to pci_alloc_consistent
1187 insisting on use of GFP_DMA, which is more restrictive
1188 than necessary... */
1189 struct dma_desc *rx_ring;
1190 dma_addr_t rx_ring_dma;
1191
1192 if (!(rx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1193 goto out_err;
1194
1195 memset(rx_ring, 0, size);
1196 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1197 DMA_TABLE_BYTES,
1198 DMA_BIDIRECTIONAL);
1199
1200 if (rx_ring_dma + size > B44_DMA_MASK) {
1201 kfree(rx_ring);
1202 goto out_err;
1203 }
1204
1205 bp->rx_ring = rx_ring;
1206 bp->rx_ring_dma = rx_ring_dma;
1207 bp->flags |= B44_FLAG_RX_RING_HACK;
1208 }
1da177e4
LT		 1209
1210 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
9f38c636
JL		 1211 if (!bp->tx_ring) {
1212 /* Allocation may have failed due to pci_alloc_consistent
1213 insisting on use of GFP_DMA, which is more restrictive
1214 than necessary... */
1215 struct dma_desc *tx_ring;
1216 dma_addr_t tx_ring_dma;
1217
1218 if (!(tx_ring = (struct dma_desc *)kmalloc(size, GFP_KERNEL)))
1219 goto out_err;
1220
1221 memset(tx_ring, 0, size);
1222 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1223 DMA_TABLE_BYTES,
1224 DMA_TO_DEVICE);
1225
1226 if (tx_ring_dma + size > B44_DMA_MASK) {
1227 kfree(tx_ring);
1228 goto out_err;
1229 }
1230
1231 bp->tx_ring = tx_ring;
1232 bp->tx_ring_dma = tx_ring_dma;
1233 bp->flags |= B44_FLAG_TX_RING_HACK;
1234 }
1da177e4
LT		 1235
1236 return 0;
1237
1238out_err:
1239 b44_free_consistent(bp);
1240 return -ENOMEM;
1241}
1242
1243/* bp->lock is held. */
1244static void b44_clear_stats(struct b44 *bp)
1245{
1246 unsigned long reg;
1247
1248 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1249 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1250 br32(bp, reg);
1251 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1252 br32(bp, reg);
1253}
1254
1255/* bp->lock is held. */
1256static void b44_chip_reset(struct b44 *bp)
1257{
1258 if (ssb_is_core_up(bp)) {
1259 bw32(bp, B44_RCV_LAZY, 0);
1260 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1261 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1262 bw32(bp, B44_DMATX_CTRL, 0);
1263 bp->tx_prod = bp->tx_cons = 0;
1264 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1265 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1266 100, 0);
1267 }
1268 bw32(bp, B44_DMARX_CTRL, 0);
1269 bp->rx_prod = bp->rx_cons = 0;
1270 } else {
1271 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1272 SBINTVEC_ENET0 :
1273 SBINTVEC_ENET1));
1274 }
1275
1276 ssb_core_reset(bp);
1277
1278 b44_clear_stats(bp);
1279
1280 /* Make PHY accessible. */
1281 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1282 (0x0d & MDIO_CTRL_MAXF_MASK)));
1283 br32(bp, B44_MDIO_CTRL);
1284
1285 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1286 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1287 br32(bp, B44_ENET_CTRL);
1288 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1289 } else {
1290 u32 val = br32(bp, B44_DEVCTRL);
1291
1292 if (val & DEVCTRL_EPR) {
1293 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1294 br32(bp, B44_DEVCTRL);
1295 udelay(100);
1296 }
1297 bp->flags |= B44_FLAG_INTERNAL_PHY;
1298 }
1299}
1300
1301/* bp->lock is held. */
1302static void b44_halt(struct b44 *bp)
1303{
1304 b44_disable_ints(bp);
1305 b44_chip_reset(bp);
1306}
1307
1308/* bp->lock is held. */
1309static void __b44_set_mac_addr(struct b44 *bp)
1310{
1311 bw32(bp, B44_CAM_CTRL, 0);
1312 if (!(bp->dev->flags & IFF_PROMISC)) {
1313 u32 val;
1314
1315 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1316 val = br32(bp, B44_CAM_CTRL);
1317 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1318 }
1319}
1320
1321static int b44_set_mac_addr(struct net_device *dev, void *p)
1322{
1323 struct b44 *bp = netdev_priv(dev);
1324 struct sockaddr *addr = p;
1325
1326 if (netif_running(dev))
1327 return -EBUSY;
1328
1329 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1330
1331 spin_lock_irq(&bp->lock);
1332 __b44_set_mac_addr(bp);
1333 spin_unlock_irq(&bp->lock);
1334
1335 return 0;
1336}
1337
1338/* Called at device open time to get the chip ready for
1339 * packet processing. Invoked with bp->lock held.
1340 */
1341static void __b44_set_rx_mode(struct net_device *);
1342static void b44_init_hw(struct b44 *bp)
1343{
1344 u32 val;
1345
1346 b44_chip_reset(bp);
1347 b44_phy_reset(bp);
1348 b44_setup_phy(bp);
1349
1350 /* Enable CRC32, set proper LED modes and power on PHY */
1351 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1352 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1353
1354 /* This sets the MAC address too. */
1355 __b44_set_rx_mode(bp->dev);
1356
1357 /* MTU + eth header + possible VLAN tag + struct rx_header */
1358 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1359 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1360
1361 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1362 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1363 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1364 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1365 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1366 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1367
1368 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1369 bp->rx_prod = bp->rx_pending;
1370
1371 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1372
1373 val = br32(bp, B44_ENET_CTRL);
1374 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1375}
1376
1377static int b44_open(struct net_device *dev)
1378{
1379 struct b44 *bp = netdev_priv(dev);
1380 int err;
1381
1382 err = b44_alloc_consistent(bp);
1383 if (err)
1384 return err;
1385
1386 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1387 if (err)
1388 goto err_out_free;
1389
1390 spin_lock_irq(&bp->lock);
1391
1392 b44_init_rings(bp);
1393 b44_init_hw(bp);
1394 bp->flags |= B44_FLAG_INIT_COMPLETE;
1395
e254e9bf
JL		 1396 netif_carrier_off(dev);
1397 b44_check_phy(bp);
1398
1da177e4
LT		 1399 spin_unlock_irq(&bp->lock);
1400
1401 init_timer(&bp->timer);
1402 bp->timer.expires = jiffies + HZ;
1403 bp->timer.data = (unsigned long) bp;
1404 bp->timer.function = b44_timer;
1405 add_timer(&bp->timer);
1406
1407 b44_enable_ints(bp);
1408
1409 return 0;
1410
1411err_out_free:
1412 b44_free_consistent(bp);
1413 return err;
1414}
1415
1416#if 0
1417/*static*/ void b44_dump_state(struct b44 *bp)
1418{
1419 u32 val32, val32_2, val32_3, val32_4, val32_5;
1420 u16 val16;
1421
1422 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1423 printk("DEBUG: PCI status [%04x] \n", val16);
1424
1425}
1426#endif
1427
1428#ifdef CONFIG_NET_POLL_CONTROLLER
1429/*
1430 * Polling receive - used by netconsole and other diagnostic tools
1431 * to allow network i/o with interrupts disabled.
1432 */
1433static void b44_poll_controller(struct net_device *dev)
1434{
1435 disable_irq(dev->irq);
1436 b44_interrupt(dev->irq, dev, NULL);
1437 enable_irq(dev->irq);
1438}
1439#endif
1440
1441static int b44_close(struct net_device *dev)
1442{
1443 struct b44 *bp = netdev_priv(dev);
1444
1445 netif_stop_queue(dev);
1446
1447 del_timer_sync(&bp->timer);
1448
1449 spin_lock_irq(&bp->lock);
1450
1451#if 0
1452 b44_dump_state(bp);
1453#endif
1454 b44_halt(bp);
1455 b44_free_rings(bp);
1456 bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1457 netif_carrier_off(bp->dev);
1458
1459 spin_unlock_irq(&bp->lock);
1460
1461 free_irq(dev->irq, dev);
1462
1463 b44_free_consistent(bp);
1464
1465 return 0;
1466}
1467
1468static struct net_device_stats *b44_get_stats(struct net_device *dev)
1469{
1470 struct b44 *bp = netdev_priv(dev);
1471 struct net_device_stats *nstat = &bp->stats;
1472 struct b44_hw_stats *hwstat = &bp->hw_stats;
1473
1474 /* Convert HW stats into netdevice stats. */
1475 nstat->rx_packets = hwstat->rx_pkts;
1476 nstat->tx_packets = hwstat->tx_pkts;
1477 nstat->rx_bytes = hwstat->rx_octets;
1478 nstat->tx_bytes = hwstat->tx_octets;
1479 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1480 hwstat->tx_oversize_pkts +
1481 hwstat->tx_underruns +
1482 hwstat->tx_excessive_cols +
1483 hwstat->tx_late_cols);
1484 nstat->multicast = hwstat->tx_multicast_pkts;
1485 nstat->collisions = hwstat->tx_total_cols;
1486
1487 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1488 hwstat->rx_undersize);
1489 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1490 nstat->rx_frame_errors = hwstat->rx_align_errs;
1491 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1492 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1493 hwstat->rx_oversize_pkts +
1494 hwstat->rx_missed_pkts +
1495 hwstat->rx_crc_align_errs +
1496 hwstat->rx_undersize +
1497 hwstat->rx_crc_errs +
1498 hwstat->rx_align_errs +
1499 hwstat->rx_symbol_errs);
1500
1501 nstat->tx_aborted_errors = hwstat->tx_underruns;
1502#if 0
1503 /* Carrier lost counter seems to be broken for some devices */
1504 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1505#endif
1506
1507 return nstat;
1508}
1509
1510static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1511{
1512 struct dev_mc_list *mclist;
1513 int i, num_ents;
1514
1515 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1516 mclist = dev->mc_list;
1517 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1518 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1519 }
1520 return i+1;
1521}
1522
1523static void __b44_set_rx_mode(struct net_device *dev)
1524{
1525 struct b44 *bp = netdev_priv(dev);
1526 u32 val;
1527 int i=0;
1528 unsigned char zero[6] = {0,0,0,0,0,0};
1529
1530 val = br32(bp, B44_RXCONFIG);
1531 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1532 if (dev->flags & IFF_PROMISC) {
1533 val |= RXCONFIG_PROMISC;
1534 bw32(bp, B44_RXCONFIG, val);
1535 } else {
1536 __b44_set_mac_addr(bp);
1537
1538 if (dev->flags & IFF_ALLMULTI)
1539 val |= RXCONFIG_ALLMULTI;
1540 else
1541 i=__b44_load_mcast(bp, dev);
1542
1543 for(;i<64;i++) {
1544 __b44_cam_write(bp, zero, i);
1545 }
1546 bw32(bp, B44_RXCONFIG, val);
1547 val = br32(bp, B44_CAM_CTRL);
1548 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1549 }
1550}
1551
1552static void b44_set_rx_mode(struct net_device *dev)
1553{
1554 struct b44 *bp = netdev_priv(dev);
1555
1556 spin_lock_irq(&bp->lock);
1557 __b44_set_rx_mode(dev);
1558 spin_unlock_irq(&bp->lock);
1559}
1560
1561static u32 b44_get_msglevel(struct net_device *dev)
1562{
1563 struct b44 *bp = netdev_priv(dev);
1564 return bp->msg_enable;
1565}
1566
1567static void b44_set_msglevel(struct net_device *dev, u32 value)
1568{
1569 struct b44 *bp = netdev_priv(dev);
1570 bp->msg_enable = value;
1571}
1572
1573static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1574{
1575 struct b44 *bp = netdev_priv(dev);
1576 struct pci_dev *pci_dev = bp->pdev;
1577
1578 strcpy (info->driver, DRV_MODULE_NAME);
1579 strcpy (info->version, DRV_MODULE_VERSION);
1580 strcpy (info->bus_info, pci_name(pci_dev));
1581}
1582
1583static int b44_nway_reset(struct net_device *dev)
1584{
1585 struct b44 *bp = netdev_priv(dev);
1586 u32 bmcr;
1587 int r;
1588
1589 spin_lock_irq(&bp->lock);
1590 b44_readphy(bp, MII_BMCR, &bmcr);
1591 b44_readphy(bp, MII_BMCR, &bmcr);
1592 r = -EINVAL;
1593 if (bmcr & BMCR_ANENABLE) {
1594 b44_writephy(bp, MII_BMCR,
1595 bmcr | BMCR_ANRESTART);
1596 r = 0;
1597 }
1598 spin_unlock_irq(&bp->lock);
1599
1600 return r;
1601}
1602
1603static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1604{
1605 struct b44 *bp = netdev_priv(dev);
1606
1607 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1608 return -EAGAIN;
1609 cmd->supported = (SUPPORTED_Autoneg);
1610 cmd->supported |= (SUPPORTED_100baseT_Half |
1611 SUPPORTED_100baseT_Full |
1612 SUPPORTED_10baseT_Half |
1613 SUPPORTED_10baseT_Full |
1614 SUPPORTED_MII);
1615
1616 cmd->advertising = 0;
1617 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1618 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1619 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1620 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1621 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1622 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1623 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1624 cmd->advertising |= ADVERTISED_100baseT_Full;
1625 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1626 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1627 SPEED_100 : SPEED_10;
1628 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1629 DUPLEX_FULL : DUPLEX_HALF;
1630 cmd->port = 0;
1631 cmd->phy_address = bp->phy_addr;
1632 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1633 XCVR_INTERNAL : XCVR_EXTERNAL;
1634 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1635 AUTONEG_DISABLE : AUTONEG_ENABLE;
1636 cmd->maxtxpkt = 0;
1637 cmd->maxrxpkt = 0;
1638 return 0;
1639}
1640
1641static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1642{
1643 struct b44 *bp = netdev_priv(dev);
1644
1645 if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1646 return -EAGAIN;
1647
1648 /* We do not support gigabit. */
1649 if (cmd->autoneg == AUTONEG_ENABLE) {
1650 if (cmd->advertising &
1651 (ADVERTISED_1000baseT_Half |
1652 ADVERTISED_1000baseT_Full))
1653 return -EINVAL;
1654 } else if ((cmd->speed != SPEED_100 &&
1655 cmd->speed != SPEED_10) ||
1656 (cmd->duplex != DUPLEX_HALF &&
1657 cmd->duplex != DUPLEX_FULL)) {
1658 return -EINVAL;
1659 }
1660
1661 spin_lock_irq(&bp->lock);
1662
1663 if (cmd->autoneg == AUTONEG_ENABLE) {
1664 bp->flags &= ~B44_FLAG_FORCE_LINK;
1665 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1666 B44_FLAG_ADV_10FULL |
1667 B44_FLAG_ADV_100HALF |
1668 B44_FLAG_ADV_100FULL);
1669 if (cmd->advertising & ADVERTISE_10HALF)
1670 bp->flags |= B44_FLAG_ADV_10HALF;
1671 if (cmd->advertising & ADVERTISE_10FULL)
1672 bp->flags |= B44_FLAG_ADV_10FULL;
1673 if (cmd->advertising & ADVERTISE_100HALF)
1674 bp->flags |= B44_FLAG_ADV_100HALF;
1675 if (cmd->advertising & ADVERTISE_100FULL)
1676 bp->flags |= B44_FLAG_ADV_100FULL;
1677 } else {
1678 bp->flags |= B44_FLAG_FORCE_LINK;
1679 if (cmd->speed == SPEED_100)
1680 bp->flags |= B44_FLAG_100_BASE_T;
1681 if (cmd->duplex == DUPLEX_FULL)
1682 bp->flags |= B44_FLAG_FULL_DUPLEX;
1683 }
1684
1685 b44_setup_phy(bp);
1686
1687 spin_unlock_irq(&bp->lock);
1688
1689 return 0;
1690}
1691
1692static void b44_get_ringparam(struct net_device *dev,
1693 struct ethtool_ringparam *ering)
1694{
1695 struct b44 *bp = netdev_priv(dev);
1696
1697 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1698 ering->rx_pending = bp->rx_pending;
1699
1700 /* XXX ethtool lacks a tx_max_pending, oops... */
1701}
1702
1703static int b44_set_ringparam(struct net_device *dev,
1704 struct ethtool_ringparam *ering)
1705{
1706 struct b44 *bp = netdev_priv(dev);
1707
1708 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1709 (ering->rx_mini_pending != 0) ||
1710 (ering->rx_jumbo_pending != 0) ||
1711 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1712 return -EINVAL;
1713
1714 spin_lock_irq(&bp->lock);
1715
1716 bp->rx_pending = ering->rx_pending;
1717 bp->tx_pending = ering->tx_pending;
1718
1719 b44_halt(bp);
1720 b44_init_rings(bp);
1721 b44_init_hw(bp);
1722 netif_wake_queue(bp->dev);
1723 spin_unlock_irq(&bp->lock);
1724
1725 b44_enable_ints(bp);
1726
1727 return 0;
1728}
1729
1730static void b44_get_pauseparam(struct net_device *dev,
1731 struct ethtool_pauseparam *epause)
1732{
1733 struct b44 *bp = netdev_priv(dev);
1734
1735 epause->autoneg =
1736 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1737 epause->rx_pause =
1738 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1739 epause->tx_pause =
1740 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1741}
1742
1743static int b44_set_pauseparam(struct net_device *dev,
1744 struct ethtool_pauseparam *epause)
1745{
1746 struct b44 *bp = netdev_priv(dev);
1747
1748 spin_lock_irq(&bp->lock);
1749 if (epause->autoneg)
1750 bp->flags |= B44_FLAG_PAUSE_AUTO;
1751 else
1752 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1753 if (epause->rx_pause)
1754 bp->flags |= B44_FLAG_RX_PAUSE;
1755 else
1756 bp->flags &= ~B44_FLAG_RX_PAUSE;
1757 if (epause->tx_pause)
1758 bp->flags |= B44_FLAG_TX_PAUSE;
1759 else
1760 bp->flags &= ~B44_FLAG_TX_PAUSE;
1761 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1762 b44_halt(bp);
1763 b44_init_rings(bp);
1764 b44_init_hw(bp);
1765 } else {
1766 __b44_set_flow_ctrl(bp, bp->flags);
1767 }
1768 spin_unlock_irq(&bp->lock);
1769
1770 b44_enable_ints(bp);
1771
1772 return 0;
1773}
1774
1775static struct ethtool_ops b44_ethtool_ops = {
1776 .get_drvinfo = b44_get_drvinfo,
1777 .get_settings = b44_get_settings,
1778 .set_settings = b44_set_settings,
1779 .nway_reset = b44_nway_reset,
1780 .get_link = ethtool_op_get_link,
1781 .get_ringparam = b44_get_ringparam,
1782 .set_ringparam = b44_set_ringparam,
1783 .get_pauseparam = b44_get_pauseparam,
1784 .set_pauseparam = b44_set_pauseparam,
1785 .get_msglevel = b44_get_msglevel,
1786 .set_msglevel = b44_set_msglevel,
2160de53 1787 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1788};
1789
1790static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1791{
1792 struct mii_ioctl_data *data = if_mii(ifr);
1793 struct b44 *bp = netdev_priv(dev);
1794 int err;
1795
1796 spin_lock_irq(&bp->lock);
1797 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1798 spin_unlock_irq(&bp->lock);
1799
1800 return err;
1801}
1802
1803/* Read 128-bytes of EEPROM. */
1804static int b44_read_eeprom(struct b44 *bp, u8 *data)
1805{
1806 long i;
1807 u16 *ptr = (u16 *) data;
1808
1809 for (i = 0; i < 128; i += 2)
1810 ptr[i / 2] = readw(bp->regs + 4096 + i);
1811
1812 return 0;
1813}
1814
1815static int __devinit b44_get_invariants(struct b44 *bp)
1816{
1817 u8 eeprom[128];
1818 int err;
1819
1820 err = b44_read_eeprom(bp, &eeprom[0]);
1821 if (err)
1822 goto out;
1823
1824 bp->dev->dev_addr[0] = eeprom[79];
1825 bp->dev->dev_addr[1] = eeprom[78];
1826 bp->dev->dev_addr[2] = eeprom[81];
1827 bp->dev->dev_addr[3] = eeprom[80];
1828 bp->dev->dev_addr[4] = eeprom[83];
1829 bp->dev->dev_addr[5] = eeprom[82];
2160de53 1830 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4
LT		 1831
1832 bp->phy_addr = eeprom[90] & 0x1f;
1833
1834 /* With this, plus the rx_header prepended to the data by the
1835 * hardware, we'll land the ethernet header on a 2-byte boundary.
1836 */
1837 bp->rx_offset = 30;
1838
1839 bp->imask = IMASK_DEF;
1840
1841 bp->core_unit = ssb_core_unit(bp);
1842 bp->dma_offset = SB_PCI_DMA;
1843
1844 /* XXX - really required?
1845 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1846 */
1847out:
1848 return err;
1849}
1850
1851static int __devinit b44_init_one(struct pci_dev *pdev,
1852 const struct pci_device_id *ent)
1853{
1854 static int b44_version_printed = 0;
1855 unsigned long b44reg_base, b44reg_len;
1856 struct net_device *dev;
1857 struct b44 *bp;
1858 int err, i;
1859
1860 if (b44_version_printed++ == 0)
1861 printk(KERN_INFO "%s", version);
1862
1863 err = pci_enable_device(pdev);
1864 if (err) {
1865 printk(KERN_ERR PFX "Cannot enable PCI device, "
1866 "aborting.\n");
1867 return err;
1868 }
1869
1870 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1871 printk(KERN_ERR PFX "Cannot find proper PCI device "
1872 "base address, aborting.\n");
1873 err = -ENODEV;
1874 goto err_out_disable_pdev;
1875 }
1876
1877 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1878 if (err) {
1879 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1880 "aborting.\n");
1881 goto err_out_disable_pdev;
1882 }
1883
1884 pci_set_master(pdev);
1885
1886 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1887 if (err) {
1888 printk(KERN_ERR PFX "No usable DMA configuration, "
1889 "aborting.\n");
1890 goto err_out_free_res;
1891 }
1892
1893 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1894 if (err) {
1895 printk(KERN_ERR PFX "No usable DMA configuration, "
1896 "aborting.\n");
1897 goto err_out_free_res;
1898 }
1899
1900 b44reg_base = pci_resource_start(pdev, 0);
1901 b44reg_len = pci_resource_len(pdev, 0);
1902
1903 dev = alloc_etherdev(sizeof(*bp));
1904 if (!dev) {
1905 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1906 err = -ENOMEM;
1907 goto err_out_free_res;
1908 }
1909
1910 SET_MODULE_OWNER(dev);
1911 SET_NETDEV_DEV(dev,&pdev->dev);
1912
1913 /* No interesting netdevice features in this card... */
1914 dev->features |= 0;
1915
1916 bp = netdev_priv(dev);
1917 bp->pdev = pdev;
1918 bp->dev = dev;
1919 if (b44_debug >= 0)
1920 bp->msg_enable = (1 << b44_debug) - 1;
1921 else
1922 bp->msg_enable = B44_DEF_MSG_ENABLE;
1923
1924 spin_lock_init(&bp->lock);
1925
1926 bp->regs = ioremap(b44reg_base, b44reg_len);
1927 if (bp->regs == 0UL) {
1928 printk(KERN_ERR PFX "Cannot map device registers, "
1929 "aborting.\n");
1930 err = -ENOMEM;
1931 goto err_out_free_dev;
1932 }
1933
1934 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1935 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1936
1937 dev->open = b44_open;
1938 dev->stop = b44_close;
1939 dev->hard_start_xmit = b44_start_xmit;
1940 dev->get_stats = b44_get_stats;
1941 dev->set_multicast_list = b44_set_rx_mode;
1942 dev->set_mac_address = b44_set_mac_addr;
1943 dev->do_ioctl = b44_ioctl;
1944 dev->tx_timeout = b44_tx_timeout;
1945 dev->poll = b44_poll;
1946 dev->weight = 64;
1947 dev->watchdog_timeo = B44_TX_TIMEOUT;
1948#ifdef CONFIG_NET_POLL_CONTROLLER
1949 dev->poll_controller = b44_poll_controller;
1950#endif
1951 dev->change_mtu = b44_change_mtu;
1952 dev->irq = pdev->irq;
1953 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1954
1955 err = b44_get_invariants(bp);
1956 if (err) {
1957 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1958 "aborting.\n");
1959 goto err_out_iounmap;
1960 }
1961
1962 bp->mii_if.dev = dev;
1963 bp->mii_if.mdio_read = b44_mii_read;
1964 bp->mii_if.mdio_write = b44_mii_write;
1965 bp->mii_if.phy_id = bp->phy_addr;
1966 bp->mii_if.phy_id_mask = 0x1f;
1967 bp->mii_if.reg_num_mask = 0x1f;
1968
1969 /* By default, advertise all speed/duplex settings. */
1970 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1971 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1972
1973 /* By default, auto-negotiate PAUSE. */
1974 bp->flags |= B44_FLAG_PAUSE_AUTO;
1975
1976 err = register_netdev(dev);
1977 if (err) {
1978 printk(KERN_ERR PFX "Cannot register net device, "
1979 "aborting.\n");
1980 goto err_out_iounmap;
1981 }
1982
1983 pci_set_drvdata(pdev, dev);
1984
1985 pci_save_state(bp->pdev);
1986
1987 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1988 for (i = 0; i < 6; i++)
1989 printk("%2.2x%c", dev->dev_addr[i],
1990 i == 5 ? '\n' : ':');
1991
1992 return 0;
1993
1994err_out_iounmap:
1995 iounmap(bp->regs);
1996
1997err_out_free_dev:
1998 free_netdev(dev);
1999
2000err_out_free_res:
2001 pci_release_regions(pdev);
2002
2003err_out_disable_pdev:
2004 pci_disable_device(pdev);
2005 pci_set_drvdata(pdev, NULL);
2006 return err;
2007}
2008
2009static void __devexit b44_remove_one(struct pci_dev *pdev)
2010{
2011 struct net_device *dev = pci_get_drvdata(pdev);
2012
2013 if (dev) {
2014 struct b44 *bp = netdev_priv(dev);
2015
2016 unregister_netdev(dev);
2017 iounmap(bp->regs);
2018 free_netdev(dev);
2019 pci_release_regions(pdev);
2020 pci_disable_device(pdev);
2021 pci_set_drvdata(pdev, NULL);
2022 }
2023}
2024
2025static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2026{
2027 struct net_device *dev = pci_get_drvdata(pdev);
2028 struct b44 *bp = netdev_priv(dev);
2029
2030 if (!netif_running(dev))
2031 return 0;
2032
2033 del_timer_sync(&bp->timer);
2034
2035 spin_lock_irq(&bp->lock);
2036
2037 b44_halt(bp);
2038 netif_carrier_off(bp->dev);
2039 netif_device_detach(bp->dev);
2040 b44_free_rings(bp);
2041
2042 spin_unlock_irq(&bp->lock);
46e17853
PM		 2043
2044 free_irq(dev->irq, dev);
d58da590 2045 pci_disable_device(pdev);
1da177e4
LT		 2046 return 0;
2047}
2048
2049static int b44_resume(struct pci_dev *pdev)
2050{
2051 struct net_device *dev = pci_get_drvdata(pdev);
2052 struct b44 *bp = netdev_priv(dev);
2053
2054 pci_restore_state(pdev);
d58da590
DSL		 2055 pci_enable_device(pdev);
2056 pci_set_master(pdev);
1da177e4
LT		 2057
2058 if (!netif_running(dev))
2059 return 0;
2060
46e17853
PM		 2061 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2062 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2063
1da177e4
LT		 2064 spin_lock_irq(&bp->lock);
2065
2066 b44_init_rings(bp);
2067 b44_init_hw(bp);
2068 netif_device_attach(bp->dev);
2069 spin_unlock_irq(&bp->lock);
2070
2071 bp->timer.expires = jiffies + HZ;
2072 add_timer(&bp->timer);
2073
2074 b44_enable_ints(bp);
2075 return 0;
2076}
2077
2078static struct pci_driver b44_driver = {
2079 .name = DRV_MODULE_NAME,
2080 .id_table = b44_pci_tbl,
2081 .probe = b44_init_one,
2082 .remove = __devexit_p(b44_remove_one),
2083 .suspend = b44_suspend,
2084 .resume = b44_resume,
2085};
2086
2087static int __init b44_init(void)
2088{
9f38c636
JL		 2089 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2090
2091 /* Setup paramaters for syncing RX/TX DMA descriptors */
2092 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2093 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2094
1da177e4
LT		 2095 return pci_module_init(&b44_driver);
2096}
2097
2098static void __exit b44_cleanup(void)
2099{
2100 pci_unregister_driver(&b44_driver);
2101}
2102
2103module_init(b44_init);
2104module_exit(b44_cleanup);
2105
Linux 6.x block layer and io_uring tree(s)