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socket: use percpu_add() while updating sockets_in_use
[linux-2.6-block.git] / drivers / net / b44.c
CommitLineData
753f4920 1/* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
1da177e4
LT		 2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
753f4920
MB		 4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
8056bfaf 7 * Copyright (C) 2006 Broadcom Corporation.
753f4920 8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
1da177e4
LT		 9 *
10 * Distribute under GPL.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/types.h>
17#include <linux/netdevice.h>
18#include <linux/ethtool.h>
19#include <linux/mii.h>
20#include <linux/if_ether.h>
72f4861e 21#include <linux/if_vlan.h>
1da177e4
LT		 22#include <linux/etherdevice.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/init.h>
89358f90 26#include <linux/dma-mapping.h>
753f4920 27#include <linux/ssb/ssb.h>
1da177e4
LT		 28
29#include <asm/uaccess.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32
753f4920 33
1da177e4
LT		 34#include "b44.h"
35
36#define DRV_MODULE_NAME "b44"
37#define PFX DRV_MODULE_NAME ": "
753f4920 38#define DRV_MODULE_VERSION "2.0"
1da177e4
LT		 39
40#define B44_DEF_MSG_ENABLE \
41 (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49
50/* length of time before we decide the hardware is borked,
51 * and dev->tx_timeout() should be called to fix the problem
52 */
53#define B44_TX_TIMEOUT (5 * HZ)
54
55/* hardware minimum and maximum for a single frame's data payload */
56#define B44_MIN_MTU 60
57#define B44_MAX_MTU 1500
58
59#define B44_RX_RING_SIZE 512
60#define B44_DEF_RX_RING_PENDING 200
61#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
62 B44_RX_RING_SIZE)
63#define B44_TX_RING_SIZE 512
64#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
66 B44_TX_RING_SIZE)
1da177e4
LT		 67
68#define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70#define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
75
4ca85795
FF		 76#define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
77#define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
1da177e4
LT		 78
79/* minimum number of free TX descriptors required to wake up TX process */
80#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
81
725ad800
GZ		 82/* b44 internal pattern match filter info */
83#define B44_PATTERN_BASE 0x400
84#define B44_PATTERN_SIZE 0x80
85#define B44_PMASK_BASE 0x600
86#define B44_PMASK_SIZE 0x10
87#define B44_MAX_PATTERNS 16
88#define B44_ETHIPV6UDP_HLEN 62
89#define B44_ETHIPV4UDP_HLEN 42
90
1da177e4 91static char version[] __devinitdata =
753f4920 92 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
1da177e4 93
753f4920
MB		 94MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
1da177e4
LT		 96MODULE_LICENSE("GPL");
97MODULE_VERSION(DRV_MODULE_VERSION);
98
99static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
100module_param(b44_debug, int, 0);
101MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
102
1da177e4 103
753f4920
MB		 104#ifdef CONFIG_B44_PCI
105static const struct pci_device_id b44_pci_tbl[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109 { 0 } /* terminate list with empty entry */
110};
1da177e4
LT		 111MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
112
753f4920
MB		 113static struct pci_driver b44_pci_driver = {
114 .name = DRV_MODULE_NAME,
115 .id_table = b44_pci_tbl,
116};
117#endif /* CONFIG_B44_PCI */
118
119static const struct ssb_device_id b44_ssb_tbl[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
121 SSB_DEVTABLE_END
122};
123MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
124
1da177e4
LT		 125static void b44_halt(struct b44 *);
126static void b44_init_rings(struct b44 *);
5fc7d61a
MC		 127
128#define B44_FULL_RESET 1
129#define B44_FULL_RESET_SKIP_PHY 2
130#define B44_PARTIAL_RESET 3
fedb0eef
MB		 131#define B44_CHIP_RESET_FULL 4
132#define B44_CHIP_RESET_PARTIAL 5
5fc7d61a 133
00e8b3aa 134static void b44_init_hw(struct b44 *, int);
1da177e4 135
9f38c636
JL		 136static int dma_desc_align_mask;
137static int dma_desc_sync_size;
753f4920 138static int instance;
9f38c636 139
3353930d
FR		 140static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141#define _B44(x...) # x,
142B44_STAT_REG_DECLARE
143#undef _B44
144};
145
753f4920
MB		 146static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
147 dma_addr_t dma_base,
148 unsigned long offset,
149 enum dma_data_direction dir)
9f38c636 150{
f225763a
MB		 151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir);
9f38c636
JL		 154}
155
753f4920
MB		 156static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
9f38c636 160{
f225763a
MB		 161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir);
9f38c636
JL		 164}
165
1da177e4
LT		 166static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
167{
753f4920 168 return ssb_read32(bp->sdev, reg);
1da177e4
LT		 169}
170
10badc21 171static inline void bw32(const struct b44 *bp,
1da177e4
LT		 172 unsigned long reg, unsigned long val)
173{
753f4920 174 ssb_write32(bp->sdev, reg, val);
1da177e4
LT		 175}
176
177static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
179{
180 unsigned long i;
181
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
184
185 if (clear && !(val & bit))
186 break;
187 if (!clear && (val & bit))
188 break;
189 udelay(10);
190 }
191 if (i == timeout) {
192 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
193 "%lx to %s.\n",
194 bp->dev->name,
195 bit, reg,
196 (clear ? "clear" : "set"));
197 return -ENODEV;
198 }
199 return 0;
200}
201
753f4920 202static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 203{
204 u32 val;
205
753f4920
MB		 206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
1da177e4 208
753f4920 209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4 210
753f4920 211 val = br32(bp, B44_CAM_DATA_LO);
1da177e4 212
753f4920
MB		 213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
1da177e4 217
753f4920 218 val = br32(bp, B44_CAM_DATA_HI);
1da177e4 219
753f4920
MB		 220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
1da177e4
LT		 222}
223
753f4920 224static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
1da177e4
LT		 225{
226 u32 val;
227
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
10badc21 233 val = (CAM_DATA_HI_VALID |
1da177e4
LT		 234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
10badc21 239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
1da177e4
LT		 240}
241
242static inline void __b44_disable_ints(struct b44 *bp)
243{
244 bw32(bp, B44_IMASK, 0);
245}
246
247static void b44_disable_ints(struct b44 *bp)
248{
249 __b44_disable_ints(bp);
250
251 /* Flush posted writes. */
252 br32(bp, B44_IMASK);
253}
254
255static void b44_enable_ints(struct b44 *bp)
256{
257 bw32(bp, B44_IMASK, bp->imask);
258}
259
753f4920 260static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
1da177e4
LT		 261{
262 int err;
263
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
753f4920 267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
272
273 return err;
274}
275
753f4920 276static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
1da177e4
LT		 277{
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
753f4920 281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
1da177e4
LT		 282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286}
287
753f4920
MB		 288static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289{
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
291 return 0;
292
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
294}
295
296static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297{
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
299 return 0;
300
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
302}
303
1da177e4 304/* miilib interface */
1da177e4
LT		 305static int b44_mii_read(struct net_device *dev, int phy_id, int location)
306{
307 u32 val;
308 struct b44 *bp = netdev_priv(dev);
753f4920 309 int rc = __b44_readphy(bp, phy_id, location, &val);
1da177e4
LT		 310 if (rc)
311 return 0xffffffff;
312 return val;
313}
314
315static void b44_mii_write(struct net_device *dev, int phy_id, int location,
316 int val)
317{
318 struct b44 *bp = netdev_priv(dev);
753f4920 319 __b44_writephy(bp, phy_id, location, val);
1da177e4
LT		 320}
321
322static int b44_phy_reset(struct b44 *bp)
323{
324 u32 val;
325 int err;
326
753f4920
MB		 327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
328 return 0;
1da177e4
LT		 329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330 if (err)
331 return err;
332 udelay(100);
333 err = b44_readphy(bp, MII_BMCR, &val);
334 if (!err) {
335 if (val & BMCR_RESET) {
336 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
337 bp->dev->name);
338 err = -ENODEV;
339 }
340 }
341
342 return 0;
343}
344
345static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346{
347 u32 val;
348
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
351
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
355 else
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
358
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 else
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
366}
367
368static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369{
10badc21 370 u32 pause_enab = 0;
2b474cf5
GZ		 371
372 /* The driver supports only rx pause by default because
10badc21
JG		 373 the b44 mac tx pause mechanism generates excessive
374 pause frames.
2b474cf5
GZ		 375 Use ethtool to turn on b44 tx pause if necessary.
376 */
377 if ((local & ADVERTISE_PAUSE_CAP) &&
10badc21 378 (local & ADVERTISE_PAUSE_ASYM)){
2b474cf5
GZ		 379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
1da177e4
LT		 382 }
383
384 __b44_set_flow_ctrl(bp, pause_enab);
385}
386
753f4920
MB		 387#ifdef SSB_DRIVER_MIPS
388extern char *nvram_get(char *name);
389static void b44_wap54g10_workaround(struct b44 *bp)
390{
391 const char *str;
392 u32 val;
393 int err;
394
395 /*
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
399 */
400 str = nvram_get("boardnum");
401 if (!str)
402 return;
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405 if (err)
406 goto error;
407 if (!(val & BMCR_ISOLATE))
408 return;
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 if (err)
412 goto error;
413 }
414 return;
415error:
416 printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
417}
418#else
419static inline void b44_wap54g10_workaround(struct b44 *bp)
420{
421}
422#endif
423
1da177e4
LT		 424static int b44_setup_phy(struct b44 *bp)
425{
426 u32 val;
427 int err;
428
753f4920
MB		 429 b44_wap54g10_workaround(bp);
430
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 return 0;
1da177e4
LT		 433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 goto out;
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 goto out;
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 goto out;
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
442 goto out;
443
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
446
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
455
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 goto out;
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
463 goto out;
464 } else {
465 u32 bmcr;
466
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 goto out;
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475 goto out;
476
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
480 */
481 b44_set_flow_ctrl(bp, 0, 0);
482 }
483
484out:
485 return err;
486}
487
488static void b44_stats_update(struct b44 *bp)
489{
490 unsigned long reg;
491 u32 *val;
492
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
496 }
3353930d
FR		 497
498 /* Pad */
499 reg += 8*4UL;
500
1da177e4
LT		 501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504}
505
506static void b44_link_report(struct b44 *bp)
507{
508 if (!netif_carrier_ok(bp->dev)) {
509 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
510 } else {
511 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
512 bp->dev->name,
513 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
515
516 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
517 "%s for RX.\n",
518 bp->dev->name,
519 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
521 }
522}
523
524static void b44_check_phy(struct b44 *bp)
525{
526 u32 bmsr, aux;
527
753f4920
MB		 528 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529 bp->flags |= B44_FLAG_100_BASE_T;
530 bp->flags |= B44_FLAG_FULL_DUPLEX;
531 if (!netif_carrier_ok(bp->dev)) {
532 u32 val = br32(bp, B44_TX_CTRL);
533 val |= TX_CTRL_DUPLEX;
534 bw32(bp, B44_TX_CTRL, val);
535 netif_carrier_on(bp->dev);
536 b44_link_report(bp);
537 }
538 return;
539 }
540
1da177e4
LT		 541 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
543 (bmsr != 0xffff)) {
544 if (aux & MII_AUXCTRL_SPEED)
545 bp->flags |= B44_FLAG_100_BASE_T;
546 else
547 bp->flags &= ~B44_FLAG_100_BASE_T;
548 if (aux & MII_AUXCTRL_DUPLEX)
549 bp->flags |= B44_FLAG_FULL_DUPLEX;
550 else
551 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
552
553 if (!netif_carrier_ok(bp->dev) &&
554 (bmsr & BMSR_LSTATUS)) {
555 u32 val = br32(bp, B44_TX_CTRL);
556 u32 local_adv, remote_adv;
557
558 if (bp->flags & B44_FLAG_FULL_DUPLEX)
559 val |= TX_CTRL_DUPLEX;
560 else
561 val &= ~TX_CTRL_DUPLEX;
562 bw32(bp, B44_TX_CTRL, val);
563
564 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566 !b44_readphy(bp, MII_LPA, &remote_adv))
567 b44_set_flow_ctrl(bp, local_adv, remote_adv);
568
569 /* Link now up */
570 netif_carrier_on(bp->dev);
571 b44_link_report(bp);
572 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
573 /* Link now down */
574 netif_carrier_off(bp->dev);
575 b44_link_report(bp);
576 }
577
578 if (bmsr & BMSR_RFAULT)
579 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
580 bp->dev->name);
581 if (bmsr & BMSR_JCD)
582 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
583 bp->dev->name);
584 }
585}
586
587static void b44_timer(unsigned long __opaque)
588{
589 struct b44 *bp = (struct b44 *) __opaque;
590
591 spin_lock_irq(&bp->lock);
592
593 b44_check_phy(bp);
594
595 b44_stats_update(bp);
596
597 spin_unlock_irq(&bp->lock);
598
a72a8179 599 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
1da177e4
LT		 600}
601
602static void b44_tx(struct b44 *bp)
603{
604 u32 cur, cons;
605
606 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607 cur /= sizeof(struct dma_desc);
608
609 /* XXX needs updating when NETIF_F_SG is supported */
610 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611 struct ring_info *rp = &bp->tx_buffers[cons];
612 struct sk_buff *skb = rp->skb;
613
5d9428de 614 BUG_ON(skb == NULL);
1da177e4 615
f225763a
MB		 616 ssb_dma_unmap_single(bp->sdev,
617 rp->mapping,
618 skb->len,
619 DMA_TO_DEVICE);
1da177e4
LT		 620 rp->skb = NULL;
621 dev_kfree_skb_irq(skb);
622 }
623
624 bp->tx_cons = cons;
625 if (netif_queue_stopped(bp->dev) &&
626 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627 netif_wake_queue(bp->dev);
628
629 bw32(bp, B44_GPTIMER, 0);
630}
631
632/* Works like this. This chip writes a 'struct rx_header" 30 bytes
633 * before the DMA address you give it. So we allocate 30 more bytes
634 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635 * point the chip at 30 bytes past where the rx_header will go.
636 */
637static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
638{
639 struct dma_desc *dp;
640 struct ring_info *src_map, *map;
641 struct rx_header *rh;
642 struct sk_buff *skb;
643 dma_addr_t mapping;
644 int dest_idx;
645 u32 ctrl;
646
647 src_map = NULL;
648 if (src_idx >= 0)
649 src_map = &bp->rx_buffers[src_idx];
650 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651 map = &bp->rx_buffers[dest_idx];
bf0dcbd9 652 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
1da177e4
LT		 653 if (skb == NULL)
654 return -ENOMEM;
655
f225763a
MB		 656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
657 RX_PKT_BUF_SZ,
658 DMA_FROM_DEVICE);
1da177e4
LT		 659
660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */
f225763a 662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
97db9ee7 663 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
1da177e4 664 /* Sigh... */
f225763a
MB		 665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
1da177e4 668 dev_kfree_skb_any(skb);
bf0dcbd9 669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
1da177e4
LT		 670 if (skb == NULL)
671 return -ENOMEM;
f225763a
MB		 672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
673 RX_PKT_BUF_SZ,
674 DMA_FROM_DEVICE);
675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
97db9ee7 676 mapping + RX_PKT_BUF_SZ > DMA_30BIT_MASK) {
f225763a
MB		 677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
1da177e4
LT		 679 dev_kfree_skb_any(skb);
680 return -ENOMEM;
681 }
a58c891a 682 bp->force_copybreak = 1;
1da177e4
LT		 683 }
684
72f4861e 685 rh = (struct rx_header *) skb->data;
1da177e4 686
1da177e4
LT		 687 rh->len = 0;
688 rh->flags = 0;
689
690 map->skb = skb;
753f4920 691 map->mapping = mapping;
1da177e4
LT		 692
693 if (src_map != NULL)
694 src_map->skb = NULL;
695
4ca85795 696 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
1da177e4
LT		 697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= DESC_CTRL_EOT;
699
700 dp = &bp->rx_ring[dest_idx];
701 dp->ctrl = cpu_to_le32(ctrl);
4ca85795 702 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
1da177e4 703
9f38c636 704 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 705 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706 dest_idx * sizeof(dp),
707 DMA_BIDIRECTIONAL);
9f38c636 708
1da177e4
LT		 709 return RX_PKT_BUF_SZ;
710}
711
712static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
713{
714 struct dma_desc *src_desc, *dest_desc;
715 struct ring_info *src_map, *dest_map;
716 struct rx_header *rh;
717 int dest_idx;
a7bed27d 718 __le32 ctrl;
1da177e4
LT		 719
720 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721 dest_desc = &bp->rx_ring[dest_idx];
722 dest_map = &bp->rx_buffers[dest_idx];
723 src_desc = &bp->rx_ring[src_idx];
724 src_map = &bp->rx_buffers[src_idx];
725
726 dest_map->skb = src_map->skb;
727 rh = (struct rx_header *) src_map->skb->data;
728 rh->len = 0;
729 rh->flags = 0;
753f4920 730 dest_map->mapping = src_map->mapping;
1da177e4 731
9f38c636 732 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 733 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734 src_idx * sizeof(src_desc),
735 DMA_BIDIRECTIONAL);
9f38c636 736
1da177e4
LT		 737 ctrl = src_desc->ctrl;
738 if (dest_idx == (B44_RX_RING_SIZE - 1))
739 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
740 else
741 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
742
743 dest_desc->ctrl = ctrl;
744 dest_desc->addr = src_desc->addr;
9f38c636 745
1da177e4
LT		 746 src_map->skb = NULL;
747
9f38c636 748 if (bp->flags & B44_FLAG_RX_RING_HACK)
753f4920
MB		 749 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750 dest_idx * sizeof(dest_desc),
751 DMA_BIDIRECTIONAL);
9f38c636 752
f225763a
MB		 753 ssb_dma_sync_single_for_device(bp->sdev, le32_to_cpu(src_desc->addr),
754 RX_PKT_BUF_SZ,
755 DMA_FROM_DEVICE);
1da177e4
LT		 756}
757
758static int b44_rx(struct b44 *bp, int budget)
759{
760 int received;
761 u32 cons, prod;
762
763 received = 0;
764 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765 prod /= sizeof(struct dma_desc);
766 cons = bp->rx_cons;
767
768 while (cons != prod && budget > 0) {
769 struct ring_info *rp = &bp->rx_buffers[cons];
770 struct sk_buff *skb = rp->skb;
753f4920 771 dma_addr_t map = rp->mapping;
1da177e4
LT		 772 struct rx_header *rh;
773 u16 len;
774
f225763a 775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
1da177e4 776 RX_PKT_BUF_SZ,
753f4920 777 DMA_FROM_DEVICE);
1da177e4 778 rh = (struct rx_header *) skb->data;
a7bed27d 779 len = le16_to_cpu(rh->len);
72f4861e 780 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
1da177e4
LT		 781 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
782 drop_it:
783 b44_recycle_rx(bp, cons, bp->rx_prod);
784 drop_it_no_recycle:
785 bp->stats.rx_dropped++;
786 goto next_pkt;
787 }
788
789 if (len == 0) {
790 int i = 0;
791
792 do {
793 udelay(2);
794 barrier();
a7bed27d 795 len = le16_to_cpu(rh->len);
1da177e4
LT		 796 } while (len == 0 && i++ < 5);
797 if (len == 0)
798 goto drop_it;
799 }
800
801 /* Omit CRC. */
802 len -= 4;
803
a58c891a 804 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
1da177e4
LT		 805 int skb_size;
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807 if (skb_size < 0)
808 goto drop_it;
f225763a
MB		 809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE);
1da177e4 811 /* Leave out rx_header */
4ca85795
FF		 812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET);
1da177e4
LT		 814 } else {
815 struct sk_buff *copy_skb;
816
817 b44_recycle_rx(bp, cons, bp->rx_prod);
818 copy_skb = dev_alloc_skb(len + 2);
819 if (copy_skb == NULL)
820 goto drop_it_no_recycle;
821
1da177e4
LT		 822 skb_reserve(copy_skb, 2);
823 skb_put(copy_skb, len);
824 /* DMA sync done above, copy just the actual packet */
72f4861e 825 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
d626f62b 826 copy_skb->data, len);
1da177e4
LT		 827 skb = copy_skb;
828 }
829 skb->ip_summed = CHECKSUM_NONE;
830 skb->protocol = eth_type_trans(skb, bp->dev);
831 netif_receive_skb(skb);
1da177e4
LT		 832 received++;
833 budget--;
834 next_pkt:
835 bp->rx_prod = (bp->rx_prod + 1) &
836 (B44_RX_RING_SIZE - 1);
837 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
838 }
839
840 bp->rx_cons = cons;
841 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
842
843 return received;
844}
845
bea3348e 846static int b44_poll(struct napi_struct *napi, int budget)
1da177e4 847{
bea3348e 848 struct b44 *bp = container_of(napi, struct b44, napi);
bea3348e 849 int work_done;
1da177e4
LT		 850
851 spin_lock_irq(&bp->lock);
852
853 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
854 /* spin_lock(&bp->tx_lock); */
855 b44_tx(bp);
856 /* spin_unlock(&bp->tx_lock); */
857 }
858 spin_unlock_irq(&bp->lock);
859
bea3348e
SH		 860 work_done = 0;
861 if (bp->istat & ISTAT_RX)
862 work_done += b44_rx(bp, budget);
1da177e4
LT		 863
864 if (bp->istat & ISTAT_ERRORS) {
d15e9c4d
FR		 865 unsigned long flags;
866
867 spin_lock_irqsave(&bp->lock, flags);
1da177e4
LT		 868 b44_halt(bp);
869 b44_init_rings(bp);
5fc7d61a 870 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
1da177e4 871 netif_wake_queue(bp->dev);
d15e9c4d 872 spin_unlock_irqrestore(&bp->lock, flags);
bea3348e 873 work_done = 0;
1da177e4
LT		 874 }
875
bea3348e 876 if (work_done < budget) {
288379f0 877 napi_complete(napi);
1da177e4
LT		 878 b44_enable_ints(bp);
879 }
880
bea3348e 881 return work_done;
1da177e4
LT		 882}
883
7d12e780 884static irqreturn_t b44_interrupt(int irq, void *dev_id)
1da177e4
LT		 885{
886 struct net_device *dev = dev_id;
887 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 888 u32 istat, imask;
889 int handled = 0;
890
65b984f2 891 spin_lock(&bp->lock);
1da177e4
LT		 892
893 istat = br32(bp, B44_ISTAT);
894 imask = br32(bp, B44_IMASK);
895
e78181fe
JB		 896 /* The interrupt mask register controls which interrupt bits
897 * will actually raise an interrupt to the CPU when set by hw/firmware,
898 * but doesn't mask off the bits.
1da177e4
LT		 899 */
900 istat &= imask;
901 if (istat) {
902 handled = 1;
ba5eec9c
FR		 903
904 if (unlikely(!netif_running(dev))) {
905 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
906 goto irq_ack;
907 }
908
288379f0 909 if (napi_schedule_prep(&bp->napi)) {
1da177e4
LT		 910 /* NOTE: These writes are posted by the readback of
911 * the ISTAT register below.
912 */
913 bp->istat = istat;
914 __b44_disable_ints(bp);
288379f0 915 __napi_schedule(&bp->napi);
1da177e4
LT		 916 } else {
917 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
918 dev->name);
919 }
920
ba5eec9c 921irq_ack:
1da177e4
LT		 922 bw32(bp, B44_ISTAT, istat);
923 br32(bp, B44_ISTAT);
924 }
65b984f2 925 spin_unlock(&bp->lock);
1da177e4
LT		 926 return IRQ_RETVAL(handled);
927}
928
929static void b44_tx_timeout(struct net_device *dev)
930{
931 struct b44 *bp = netdev_priv(dev);
932
933 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
934 dev->name);
935
936 spin_lock_irq(&bp->lock);
937
938 b44_halt(bp);
939 b44_init_rings(bp);
5fc7d61a 940 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 941
942 spin_unlock_irq(&bp->lock);
943
944 b44_enable_ints(bp);
945
946 netif_wake_queue(dev);
947}
948
949static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
950{
951 struct b44 *bp = netdev_priv(dev);
c7193693 952 int rc = NETDEV_TX_OK;
1da177e4
LT		 953 dma_addr_t mapping;
954 u32 len, entry, ctrl;
955
956 len = skb->len;
957 spin_lock_irq(&bp->lock);
958
959 /* This is a hard error, log it. */
960 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
961 netif_stop_queue(dev);
1da177e4
LT		 962 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
963 dev->name);
c7193693 964 goto err_out;
1da177e4
LT		 965 }
966
f225763a
MB		 967 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
968 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
f65a7177
SH		 969 struct sk_buff *bounce_skb;
970
1da177e4 971 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
f225763a
MB		 972 if (!ssb_dma_mapping_error(bp->sdev, mapping))
973 ssb_dma_unmap_single(bp->sdev, mapping, len,
974 DMA_TO_DEVICE);
1da177e4 975
9034f77b 976 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
1da177e4 977 if (!bounce_skb)
c7193693 978 goto err_out;
1da177e4 979
f225763a
MB		 980 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
981 len, DMA_TO_DEVICE);
982 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_30BIT_MASK) {
983 if (!ssb_dma_mapping_error(bp->sdev, mapping))
984 ssb_dma_unmap_single(bp->sdev, mapping,
985 len, DMA_TO_DEVICE);
1da177e4 986 dev_kfree_skb_any(bounce_skb);
c7193693 987 goto err_out;
1da177e4
LT		 988 }
989
f65a7177 990 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
1da177e4
LT		 991 dev_kfree_skb_any(skb);
992 skb = bounce_skb;
993 }
994
995 entry = bp->tx_prod;
996 bp->tx_buffers[entry].skb = skb;
753f4920 997 bp->tx_buffers[entry].mapping = mapping;
1da177e4
LT		 998
999 ctrl = (len & DESC_CTRL_LEN);
1000 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1001 if (entry == (B44_TX_RING_SIZE - 1))
1002 ctrl |= DESC_CTRL_EOT;
1003
1004 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1005 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1006
9f38c636 1007 if (bp->flags & B44_FLAG_TX_RING_HACK)
753f4920
MB		 1008 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1009 entry * sizeof(bp->tx_ring[0]),
1010 DMA_TO_DEVICE);
9f38c636 1011
1da177e4
LT		 1012 entry = NEXT_TX(entry);
1013
1014 bp->tx_prod = entry;
1015
1016 wmb();
1017
1018 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1019 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_REORDER_BUG)
1022 br32(bp, B44_DMATX_PTR);
1023
1024 if (TX_BUFFS_AVAIL(bp) < 1)
1025 netif_stop_queue(dev);
1026
c7193693
FR		 1027 dev->trans_start = jiffies;
1028
1029out_unlock:
1da177e4
LT		 1030 spin_unlock_irq(&bp->lock);
1031
c7193693 1032 return rc;
1da177e4 1033
c7193693
FR		 1034err_out:
1035 rc = NETDEV_TX_BUSY;
1036 goto out_unlock;
1da177e4
LT		 1037}
1038
1039static int b44_change_mtu(struct net_device *dev, int new_mtu)
1040{
1041 struct b44 *bp = netdev_priv(dev);
1042
1043 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1044 return -EINVAL;
1045
1046 if (!netif_running(dev)) {
1047 /* We'll just catch it later when the
1048 * device is up'd.
1049 */
1050 dev->mtu = new_mtu;
1051 return 0;
1052 }
1053
1054 spin_lock_irq(&bp->lock);
1055 b44_halt(bp);
1056 dev->mtu = new_mtu;
1057 b44_init_rings(bp);
5fc7d61a 1058 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1059 spin_unlock_irq(&bp->lock);
1060
1061 b44_enable_ints(bp);
10badc21 1062
1da177e4
LT		 1063 return 0;
1064}
1065
1066/* Free up pending packets in all rx/tx rings.
1067 *
1068 * The chip has been shut down and the driver detached from
1069 * the networking, so no interrupts or new tx packets will
1070 * end up in the driver. bp->lock is not held and we are not
1071 * in an interrupt context and thus may sleep.
1072 */
1073static void b44_free_rings(struct b44 *bp)
1074{
1075 struct ring_info *rp;
1076 int i;
1077
1078 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1079 rp = &bp->rx_buffers[i];
1080
1081 if (rp->skb == NULL)
1082 continue;
f225763a
MB		 1083 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1084 DMA_FROM_DEVICE);
1da177e4
LT		 1085 dev_kfree_skb_any(rp->skb);
1086 rp->skb = NULL;
1087 }
1088
1089 /* XXX needs changes once NETIF_F_SG is set... */
1090 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1091 rp = &bp->tx_buffers[i];
1092
1093 if (rp->skb == NULL)
1094 continue;
f225763a
MB		 1095 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1096 DMA_TO_DEVICE);
1da177e4
LT		 1097 dev_kfree_skb_any(rp->skb);
1098 rp->skb = NULL;
1099 }
1100}
1101
1102/* Initialize tx/rx rings for packet processing.
1103 *
1104 * The chip has been shut down and the driver detached from
1105 * the networking, so no interrupts or new tx packets will
874a6214 1106 * end up in the driver.
1da177e4
LT		 1107 */
1108static void b44_init_rings(struct b44 *bp)
1109{
1110 int i;
1111
1112 b44_free_rings(bp);
1113
1114 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1115 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1116
9f38c636 1117 if (bp->flags & B44_FLAG_RX_RING_HACK)
f225763a
MB		 1118 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1119 DMA_TABLE_BYTES,
1120 DMA_BIDIRECTIONAL);
9f38c636
JL		 1121
1122 if (bp->flags & B44_FLAG_TX_RING_HACK)
f225763a
MB		 1123 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1124 DMA_TABLE_BYTES,
1125 DMA_TO_DEVICE);
9f38c636 1126
1da177e4
LT		 1127 for (i = 0; i < bp->rx_pending; i++) {
1128 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1129 break;
1130 }
1131}
1132
1133/*
1134 * Must not be invoked with interrupt sources disabled and
1135 * the hardware shutdown down.
1136 */
1137static void b44_free_consistent(struct b44 *bp)
1138{
b4558ea9
JJ		 1139 kfree(bp->rx_buffers);
1140 bp->rx_buffers = NULL;
1141 kfree(bp->tx_buffers);
1142 bp->tx_buffers = NULL;
1da177e4 1143 if (bp->rx_ring) {
9f38c636 1144 if (bp->flags & B44_FLAG_RX_RING_HACK) {
f225763a
MB		 1145 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1146 DMA_TABLE_BYTES,
1147 DMA_BIDIRECTIONAL);
9f38c636
JL		 1148 kfree(bp->rx_ring);
1149 } else
f225763a
MB		 1150 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1151 bp->rx_ring, bp->rx_ring_dma,
1152 GFP_KERNEL);
1da177e4 1153 bp->rx_ring = NULL;
9f38c636 1154 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1155 }
1156 if (bp->tx_ring) {
9f38c636 1157 if (bp->flags & B44_FLAG_TX_RING_HACK) {
f225763a
MB		 1158 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1159 DMA_TABLE_BYTES,
1160 DMA_TO_DEVICE);
9f38c636
JL		 1161 kfree(bp->tx_ring);
1162 } else
f225763a
MB		 1163 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1164 bp->tx_ring, bp->tx_ring_dma,
1165 GFP_KERNEL);
1da177e4 1166 bp->tx_ring = NULL;
9f38c636 1167 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1168 }
1169}
1170
1171/*
1172 * Must not be invoked with interrupt sources disabled and
1173 * the hardware shutdown down. Can sleep.
1174 */
753f4920 1175static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1da177e4
LT		 1176{
1177 int size;
1178
1179 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
753f4920 1180 bp->rx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1181 if (!bp->rx_buffers)
1182 goto out_err;
1da177e4
LT		 1183
1184 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
753f4920 1185 bp->tx_buffers = kzalloc(size, gfp);
1da177e4
LT		 1186 if (!bp->tx_buffers)
1187 goto out_err;
1da177e4
LT		 1188
1189 size = DMA_TABLE_BYTES;
f225763a 1190 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
9f38c636
JL		 1191 if (!bp->rx_ring) {
1192 /* Allocation may have failed due to pci_alloc_consistent
1193 insisting on use of GFP_DMA, which is more restrictive
1194 than necessary... */
1195 struct dma_desc *rx_ring;
1196 dma_addr_t rx_ring_dma;
1197
753f4920 1198 rx_ring = kzalloc(size, gfp);
874a6214 1199 if (!rx_ring)
9f38c636
JL		 1200 goto out_err;
1201
f225763a
MB		 1202 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1203 DMA_TABLE_BYTES,
1204 DMA_BIDIRECTIONAL);
9f38c636 1205
f225763a 1206 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
97db9ee7 1207 rx_ring_dma + size > DMA_30BIT_MASK) {
9f38c636
JL		 1208 kfree(rx_ring);
1209 goto out_err;
1210 }
1211
1212 bp->rx_ring = rx_ring;
1213 bp->rx_ring_dma = rx_ring_dma;
1214 bp->flags |= B44_FLAG_RX_RING_HACK;
1215 }
1da177e4 1216
f225763a 1217 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
9f38c636 1218 if (!bp->tx_ring) {
f225763a 1219 /* Allocation may have failed due to ssb_dma_alloc_consistent
9f38c636
JL		 1220 insisting on use of GFP_DMA, which is more restrictive
1221 than necessary... */
1222 struct dma_desc *tx_ring;
1223 dma_addr_t tx_ring_dma;
1224
753f4920 1225 tx_ring = kzalloc(size, gfp);
874a6214 1226 if (!tx_ring)
9f38c636
JL		 1227 goto out_err;
1228
f225763a 1229 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
753f4920
MB		 1230 DMA_TABLE_BYTES,
1231 DMA_TO_DEVICE);
9f38c636 1232
f225763a 1233 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
97db9ee7 1234 tx_ring_dma + size > DMA_30BIT_MASK) {
9f38c636
JL		 1235 kfree(tx_ring);
1236 goto out_err;
1237 }
1238
1239 bp->tx_ring = tx_ring;
1240 bp->tx_ring_dma = tx_ring_dma;
1241 bp->flags |= B44_FLAG_TX_RING_HACK;
1242 }
1da177e4
LT		 1243
1244 return 0;
1245
1246out_err:
1247 b44_free_consistent(bp);
1248 return -ENOMEM;
1249}
1250
1251/* bp->lock is held. */
1252static void b44_clear_stats(struct b44 *bp)
1253{
1254 unsigned long reg;
1255
1256 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1257 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1258 br32(bp, reg);
1259 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1260 br32(bp, reg);
1261}
1262
1263/* bp->lock is held. */
fedb0eef 1264static void b44_chip_reset(struct b44 *bp, int reset_kind)
1da177e4 1265{
753f4920 1266 struct ssb_device *sdev = bp->sdev;
f8af11af 1267 bool was_enabled;
753f4920 1268
f8af11af
MB		 1269 was_enabled = ssb_device_is_enabled(bp->sdev);
1270
1271 ssb_device_enable(bp->sdev, 0);
1272 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1273
1274 if (was_enabled) {
1da177e4
LT		 1275 bw32(bp, B44_RCV_LAZY, 0);
1276 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
40ee8c76 1277 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1da177e4
LT		 1278 bw32(bp, B44_DMATX_CTRL, 0);
1279 bp->tx_prod = bp->tx_cons = 0;
1280 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1281 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1282 100, 0);
1283 }
1284 bw32(bp, B44_DMARX_CTRL, 0);
1285 bp->rx_prod = bp->rx_cons = 0;
f8af11af 1286 }
1da177e4
LT		 1287
1288 b44_clear_stats(bp);
1289
fedb0eef
MB		 1290 /*
1291 * Don't enable PHY if we are doing a partial reset
1292 * we are probably going to power down
1293 */
1294 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1295 return;
1296
753f4920
MB		 1297 switch (sdev->bus->bustype) {
1298 case SSB_BUSTYPE_SSB:
1299 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1300 (((ssb_clockspeed(sdev->bus) + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
1301 & MDIO_CTRL_MAXF_MASK)));
1302 break;
1303 case SSB_BUSTYPE_PCI:
1304 case SSB_BUSTYPE_PCMCIA:
1305 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1306 (0x0d & MDIO_CTRL_MAXF_MASK)));
1307 break;
1308 }
1309
1da177e4
LT		 1310 br32(bp, B44_MDIO_CTRL);
1311
1312 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1313 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1314 br32(bp, B44_ENET_CTRL);
1315 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1316 } else {
1317 u32 val = br32(bp, B44_DEVCTRL);
1318
1319 if (val & DEVCTRL_EPR) {
1320 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1321 br32(bp, B44_DEVCTRL);
1322 udelay(100);
1323 }
1324 bp->flags |= B44_FLAG_INTERNAL_PHY;
1325 }
1326}
1327
1328/* bp->lock is held. */
1329static void b44_halt(struct b44 *bp)
1330{
1331 b44_disable_ints(bp);
fedb0eef
MB		 1332 /* reset PHY */
1333 b44_phy_reset(bp);
1334 /* power down PHY */
1335 printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1336 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1337 /* now reset the chip, but without enabling the MAC&PHY
1338 * part of it. This has to be done _after_ we shut down the PHY */
1339 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1da177e4
LT		 1340}
1341
1342/* bp->lock is held. */
1343static void __b44_set_mac_addr(struct b44 *bp)
1344{
1345 bw32(bp, B44_CAM_CTRL, 0);
1346 if (!(bp->dev->flags & IFF_PROMISC)) {
1347 u32 val;
1348
1349 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1350 val = br32(bp, B44_CAM_CTRL);
1351 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1352 }
1353}
1354
1355static int b44_set_mac_addr(struct net_device *dev, void *p)
1356{
1357 struct b44 *bp = netdev_priv(dev);
1358 struct sockaddr *addr = p;
753f4920 1359 u32 val;
1da177e4
LT		 1360
1361 if (netif_running(dev))
1362 return -EBUSY;
1363
391fc09a
GZ		 1364 if (!is_valid_ether_addr(addr->sa_data))
1365 return -EINVAL;
1366
1da177e4
LT		 1367 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1368
1369 spin_lock_irq(&bp->lock);
753f4920
MB		 1370
1371 val = br32(bp, B44_RXCONFIG);
1372 if (!(val & RXCONFIG_CAM_ABSENT))
1373 __b44_set_mac_addr(bp);
1374
1da177e4
LT		 1375 spin_unlock_irq(&bp->lock);
1376
1377 return 0;
1378}
1379
1380/* Called at device open time to get the chip ready for
1381 * packet processing. Invoked with bp->lock held.
1382 */
1383static void __b44_set_rx_mode(struct net_device *);
5fc7d61a 1384static void b44_init_hw(struct b44 *bp, int reset_kind)
1da177e4
LT		 1385{
1386 u32 val;
1387
fedb0eef 1388 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5fc7d61a 1389 if (reset_kind == B44_FULL_RESET) {
00e8b3aa
GZ		 1390 b44_phy_reset(bp);
1391 b44_setup_phy(bp);
1392 }
1da177e4
LT		 1393
1394 /* Enable CRC32, set proper LED modes and power on PHY */
1395 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1396 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1397
1398 /* This sets the MAC address too. */
1399 __b44_set_rx_mode(bp->dev);
1400
1401 /* MTU + eth header + possible VLAN tag + struct rx_header */
1402 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1403 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1404
1405 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
5fc7d61a
MC		 1406 if (reset_kind == B44_PARTIAL_RESET) {
1407 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1408 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
5fc7d61a 1409 } else {
00e8b3aa
GZ		 1410 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1411 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1412 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
72f4861e 1413 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
00e8b3aa 1414 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1da177e4 1415
00e8b3aa
GZ		 1416 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1417 bp->rx_prod = bp->rx_pending;
1da177e4 1418
00e8b3aa 1419 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
00e8b3aa 1420 }
1da177e4
LT		 1421
1422 val = br32(bp, B44_ENET_CTRL);
1423 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1424}
1425
1426static int b44_open(struct net_device *dev)
1427{
1428 struct b44 *bp = netdev_priv(dev);
1429 int err;
1430
753f4920 1431 err = b44_alloc_consistent(bp, GFP_KERNEL);
1da177e4 1432 if (err)
6c2f4267 1433 goto out;
1da177e4 1434
bea3348e
SH		 1435 napi_enable(&bp->napi);
1436
1da177e4 1437 b44_init_rings(bp);
5fc7d61a 1438 b44_init_hw(bp, B44_FULL_RESET);
1da177e4 1439
e254e9bf
JL		 1440 b44_check_phy(bp);
1441
1fb9df5d 1442 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
6c2f4267 1443 if (unlikely(err < 0)) {
bea3348e 1444 napi_disable(&bp->napi);
fedb0eef 1445 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
6c2f4267
FR		 1446 b44_free_rings(bp);
1447 b44_free_consistent(bp);
1448 goto out;
1449 }
1da177e4
LT		 1450
1451 init_timer(&bp->timer);
1452 bp->timer.expires = jiffies + HZ;
1453 bp->timer.data = (unsigned long) bp;
1454 bp->timer.function = b44_timer;
1455 add_timer(&bp->timer);
1456
1457 b44_enable_ints(bp);
d9e2d185 1458 netif_start_queue(dev);
6c2f4267 1459out:
1da177e4
LT		 1460 return err;
1461}
1462
1da177e4
LT		 1463#ifdef CONFIG_NET_POLL_CONTROLLER
1464/*
1465 * Polling receive - used by netconsole and other diagnostic tools
1466 * to allow network i/o with interrupts disabled.
1467 */
1468static void b44_poll_controller(struct net_device *dev)
1469{
1470 disable_irq(dev->irq);
7d12e780 1471 b44_interrupt(dev->irq, dev);
1da177e4
LT		 1472 enable_irq(dev->irq);
1473}
1474#endif
1475
725ad800
GZ		 1476static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1477{
1478 u32 i;
1479 u32 *pattern = (u32 *) pp;
1480
1481 for (i = 0; i < bytes; i += sizeof(u32)) {
1482 bw32(bp, B44_FILT_ADDR, table_offset + i);
1483 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1484 }
1485}
1486
1487static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1488{
1489 int magicsync = 6;
1490 int k, j, len = offset;
1491 int ethaddr_bytes = ETH_ALEN;
1492
1493 memset(ppattern + offset, 0xff, magicsync);
1494 for (j = 0; j < magicsync; j++)
1495 set_bit(len++, (unsigned long *) pmask);
1496
1497 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1498 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1499 ethaddr_bytes = ETH_ALEN;
1500 else
1501 ethaddr_bytes = B44_PATTERN_SIZE - len;
1502 if (ethaddr_bytes <=0)
1503 break;
1504 for (k = 0; k< ethaddr_bytes; k++) {
1505 ppattern[offset + magicsync +
1506 (j * ETH_ALEN) + k] = macaddr[k];
1507 len++;
1508 set_bit(len, (unsigned long *) pmask);
1509 }
1510 }
1511 return len - 1;
1512}
1513
1514/* Setup magic packet patterns in the b44 WOL
1515 * pattern matching filter.
1516 */
1517static void b44_setup_pseudo_magicp(struct b44 *bp)
1518{
1519
1520 u32 val;
1521 int plen0, plen1, plen2;
1522 u8 *pwol_pattern;
1523 u8 pwol_mask[B44_PMASK_SIZE];
1524
dd00cc48 1525 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
725ad800
GZ		 1526 if (!pwol_pattern) {
1527 printk(KERN_ERR PFX "Memory not available for WOL\n");
1528 return;
1529 }
1530
1531 /* Ipv4 magic packet pattern - pattern 0.*/
725ad800
GZ		 1532 memset(pwol_mask, 0, B44_PMASK_SIZE);
1533 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1534 B44_ETHIPV4UDP_HLEN);
1535
1536 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1537 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1538
1539 /* Raw ethernet II magic packet pattern - pattern 1 */
1540 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1541 memset(pwol_mask, 0, B44_PMASK_SIZE);
1542 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1543 ETH_HLEN);
1544
1545 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1546 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1547 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1548 B44_PMASK_BASE + B44_PMASK_SIZE);
1549
1550 /* Ipv6 magic packet pattern - pattern 2 */
1551 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1552 memset(pwol_mask, 0, B44_PMASK_SIZE);
1553 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1554 B44_ETHIPV6UDP_HLEN);
1555
1556 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1557 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1558 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1559 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1560
1561 kfree(pwol_pattern);
1562
1563 /* set these pattern's lengths: one less than each real length */
1564 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1565 bw32(bp, B44_WKUP_LEN, val);
1566
1567 /* enable wakeup pattern matching */
1568 val = br32(bp, B44_DEVCTRL);
1569 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1570
1571}
52cafd96 1572
753f4920
MB		 1573#ifdef CONFIG_B44_PCI
1574static void b44_setup_wol_pci(struct b44 *bp)
1575{
1576 u16 val;
1577
1578 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1579 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1580 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1581 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1582 }
1583}
1584#else
1585static inline void b44_setup_wol_pci(struct b44 *bp) { }
1586#endif /* CONFIG_B44_PCI */
1587
52cafd96
GZ		 1588static void b44_setup_wol(struct b44 *bp)
1589{
1590 u32 val;
52cafd96
GZ		 1591
1592 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1593
1594 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1595
1596 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1597
1598 val = bp->dev->dev_addr[2] << 24 |
1599 bp->dev->dev_addr[3] << 16 |
1600 bp->dev->dev_addr[4] << 8 |
1601 bp->dev->dev_addr[5];
1602 bw32(bp, B44_ADDR_LO, val);
1603
1604 val = bp->dev->dev_addr[0] << 8 |
1605 bp->dev->dev_addr[1];
1606 bw32(bp, B44_ADDR_HI, val);
1607
1608 val = br32(bp, B44_DEVCTRL);
1609 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1610
725ad800
GZ		 1611 } else {
1612 b44_setup_pseudo_magicp(bp);
1613 }
753f4920 1614 b44_setup_wol_pci(bp);
52cafd96
GZ		 1615}
1616
1da177e4
LT		 1617static int b44_close(struct net_device *dev)
1618{
1619 struct b44 *bp = netdev_priv(dev);
1620
1621 netif_stop_queue(dev);
1622
bea3348e 1623 napi_disable(&bp->napi);
ba5eec9c 1624
1da177e4
LT		 1625 del_timer_sync(&bp->timer);
1626
1627 spin_lock_irq(&bp->lock);
1628
1da177e4
LT		 1629 b44_halt(bp);
1630 b44_free_rings(bp);
c35ca399 1631 netif_carrier_off(dev);
1da177e4
LT		 1632
1633 spin_unlock_irq(&bp->lock);
1634
1635 free_irq(dev->irq, dev);
1636
52cafd96 1637 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 1638 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 1639 b44_setup_wol(bp);
1640 }
1641
1da177e4
LT		 1642 b44_free_consistent(bp);
1643
1644 return 0;
1645}
1646
1647static struct net_device_stats *b44_get_stats(struct net_device *dev)
1648{
1649 struct b44 *bp = netdev_priv(dev);
1650 struct net_device_stats *nstat = &bp->stats;
1651 struct b44_hw_stats *hwstat = &bp->hw_stats;
1652
1653 /* Convert HW stats into netdevice stats. */
1654 nstat->rx_packets = hwstat->rx_pkts;
1655 nstat->tx_packets = hwstat->tx_pkts;
1656 nstat->rx_bytes = hwstat->rx_octets;
1657 nstat->tx_bytes = hwstat->tx_octets;
1658 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1659 hwstat->tx_oversize_pkts +
1660 hwstat->tx_underruns +
1661 hwstat->tx_excessive_cols +
1662 hwstat->tx_late_cols);
1663 nstat->multicast = hwstat->tx_multicast_pkts;
1664 nstat->collisions = hwstat->tx_total_cols;
1665
1666 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1667 hwstat->rx_undersize);
1668 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1669 nstat->rx_frame_errors = hwstat->rx_align_errs;
1670 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1671 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1672 hwstat->rx_oversize_pkts +
1673 hwstat->rx_missed_pkts +
1674 hwstat->rx_crc_align_errs +
1675 hwstat->rx_undersize +
1676 hwstat->rx_crc_errs +
1677 hwstat->rx_align_errs +
1678 hwstat->rx_symbol_errs);
1679
1680 nstat->tx_aborted_errors = hwstat->tx_underruns;
1681#if 0
1682 /* Carrier lost counter seems to be broken for some devices */
1683 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1684#endif
1685
1686 return nstat;
1687}
1688
1689static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1690{
1691 struct dev_mc_list *mclist;
1692 int i, num_ents;
1693
1694 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1695 mclist = dev->mc_list;
1696 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1697 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1698 }
1699 return i+1;
1700}
1701
1702static void __b44_set_rx_mode(struct net_device *dev)
1703{
1704 struct b44 *bp = netdev_priv(dev);
1705 u32 val;
1da177e4
LT		 1706
1707 val = br32(bp, B44_RXCONFIG);
1708 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
753f4920 1709 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1da177e4
LT		 1710 val |= RXCONFIG_PROMISC;
1711 bw32(bp, B44_RXCONFIG, val);
1712 } else {
874a6214 1713 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
cda22aa9 1714 int i = 1;
874a6214 1715
1da177e4
LT		 1716 __b44_set_mac_addr(bp);
1717
2f614fe0
JG		 1718 if ((dev->flags & IFF_ALLMULTI) ||
1719 (dev->mc_count > B44_MCAST_TABLE_SIZE))
1da177e4
LT		 1720 val |= RXCONFIG_ALLMULTI;
1721 else
874a6214 1722 i = __b44_load_mcast(bp, dev);
10badc21 1723
2f614fe0 1724 for (; i < 64; i++)
10badc21 1725 __b44_cam_write(bp, zero, i);
2f614fe0 1726
1da177e4
LT		 1727 bw32(bp, B44_RXCONFIG, val);
1728 val = br32(bp, B44_CAM_CTRL);
1729 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1730 }
1731}
1732
1733static void b44_set_rx_mode(struct net_device *dev)
1734{
1735 struct b44 *bp = netdev_priv(dev);
1736
1737 spin_lock_irq(&bp->lock);
1738 __b44_set_rx_mode(dev);
1739 spin_unlock_irq(&bp->lock);
1740}
1741
1742static u32 b44_get_msglevel(struct net_device *dev)
1743{
1744 struct b44 *bp = netdev_priv(dev);
1745 return bp->msg_enable;
1746}
1747
1748static void b44_set_msglevel(struct net_device *dev, u32 value)
1749{
1750 struct b44 *bp = netdev_priv(dev);
1751 bp->msg_enable = value;
1752}
1753
1754static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1755{
1756 struct b44 *bp = netdev_priv(dev);
753f4920 1757 struct ssb_bus *bus = bp->sdev->bus;
1da177e4 1758
753f4920
MB		 1759 strncpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1760 strncpy(info->version, DRV_MODULE_VERSION, sizeof(info->driver));
1761 switch (bus->bustype) {
1762 case SSB_BUSTYPE_PCI:
1763 strncpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1764 break;
1765 case SSB_BUSTYPE_PCMCIA:
1766 case SSB_BUSTYPE_SSB:
1767 strncpy(info->bus_info, "SSB", sizeof(info->bus_info));
1768 break;
1769 }
1da177e4
LT		 1770}
1771
1772static int b44_nway_reset(struct net_device *dev)
1773{
1774 struct b44 *bp = netdev_priv(dev);
1775 u32 bmcr;
1776 int r;
1777
1778 spin_lock_irq(&bp->lock);
1779 b44_readphy(bp, MII_BMCR, &bmcr);
1780 b44_readphy(bp, MII_BMCR, &bmcr);
1781 r = -EINVAL;
1782 if (bmcr & BMCR_ANENABLE) {
1783 b44_writephy(bp, MII_BMCR,
1784 bmcr | BMCR_ANRESTART);
1785 r = 0;
1786 }
1787 spin_unlock_irq(&bp->lock);
1788
1789 return r;
1790}
1791
1792static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1793{
1794 struct b44 *bp = netdev_priv(dev);
1795
1da177e4
LT		 1796 cmd->supported = (SUPPORTED_Autoneg);
1797 cmd->supported |= (SUPPORTED_100baseT_Half |
1798 SUPPORTED_100baseT_Full |
1799 SUPPORTED_10baseT_Half |
1800 SUPPORTED_10baseT_Full |
1801 SUPPORTED_MII);
1802
1803 cmd->advertising = 0;
1804 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1805 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1806 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1807 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1808 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1809 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1810 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1811 cmd->advertising |= ADVERTISED_100baseT_Full;
1812 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1813 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1814 SPEED_100 : SPEED_10;
1815 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1816 DUPLEX_FULL : DUPLEX_HALF;
1817 cmd->port = 0;
1818 cmd->phy_address = bp->phy_addr;
1819 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1820 XCVR_INTERNAL : XCVR_EXTERNAL;
1821 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1822 AUTONEG_DISABLE : AUTONEG_ENABLE;
47b9c3b1
GZ		 1823 if (cmd->autoneg == AUTONEG_ENABLE)
1824 cmd->advertising |= ADVERTISED_Autoneg;
1825 if (!netif_running(dev)){
1826 cmd->speed = 0;
1827 cmd->duplex = 0xff;
1828 }
1da177e4
LT		 1829 cmd->maxtxpkt = 0;
1830 cmd->maxrxpkt = 0;
1831 return 0;
1832}
1833
1834static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1835{
1836 struct b44 *bp = netdev_priv(dev);
1837
1da177e4
LT		 1838 /* We do not support gigabit. */
1839 if (cmd->autoneg == AUTONEG_ENABLE) {
1840 if (cmd->advertising &
1841 (ADVERTISED_1000baseT_Half |
1842 ADVERTISED_1000baseT_Full))
1843 return -EINVAL;
1844 } else if ((cmd->speed != SPEED_100 &&
1845 cmd->speed != SPEED_10) ||
1846 (cmd->duplex != DUPLEX_HALF &&
1847 cmd->duplex != DUPLEX_FULL)) {
1848 return -EINVAL;
1849 }
1850
1851 spin_lock_irq(&bp->lock);
1852
1853 if (cmd->autoneg == AUTONEG_ENABLE) {
47b9c3b1
GZ		 1854 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1855 B44_FLAG_100_BASE_T |
1856 B44_FLAG_FULL_DUPLEX |
1857 B44_FLAG_ADV_10HALF |
1da177e4
LT		 1858 B44_FLAG_ADV_10FULL |
1859 B44_FLAG_ADV_100HALF |
1860 B44_FLAG_ADV_100FULL);
47b9c3b1
GZ		 1861 if (cmd->advertising == 0) {
1862 bp->flags |= (B44_FLAG_ADV_10HALF |
1863 B44_FLAG_ADV_10FULL |
1864 B44_FLAG_ADV_100HALF |
1865 B44_FLAG_ADV_100FULL);
1866 } else {
1867 if (cmd->advertising & ADVERTISED_10baseT_Half)
1868 bp->flags |= B44_FLAG_ADV_10HALF;
1869 if (cmd->advertising & ADVERTISED_10baseT_Full)
1870 bp->flags |= B44_FLAG_ADV_10FULL;
1871 if (cmd->advertising & ADVERTISED_100baseT_Half)
1872 bp->flags |= B44_FLAG_ADV_100HALF;
1873 if (cmd->advertising & ADVERTISED_100baseT_Full)
1874 bp->flags |= B44_FLAG_ADV_100FULL;
1875 }
1da177e4
LT		 1876 } else {
1877 bp->flags |= B44_FLAG_FORCE_LINK;
47b9c3b1 1878 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1da177e4
LT		 1879 if (cmd->speed == SPEED_100)
1880 bp->flags |= B44_FLAG_100_BASE_T;
1881 if (cmd->duplex == DUPLEX_FULL)
1882 bp->flags |= B44_FLAG_FULL_DUPLEX;
1883 }
1884
47b9c3b1
GZ		 1885 if (netif_running(dev))
1886 b44_setup_phy(bp);
1da177e4
LT		 1887
1888 spin_unlock_irq(&bp->lock);
1889
1890 return 0;
1891}
1892
1893static void b44_get_ringparam(struct net_device *dev,
1894 struct ethtool_ringparam *ering)
1895{
1896 struct b44 *bp = netdev_priv(dev);
1897
1898 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1899 ering->rx_pending = bp->rx_pending;
1900
1901 /* XXX ethtool lacks a tx_max_pending, oops... */
1902}
1903
1904static int b44_set_ringparam(struct net_device *dev,
1905 struct ethtool_ringparam *ering)
1906{
1907 struct b44 *bp = netdev_priv(dev);
1908
1909 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1910 (ering->rx_mini_pending != 0) ||
1911 (ering->rx_jumbo_pending != 0) ||
1912 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1913 return -EINVAL;
1914
1915 spin_lock_irq(&bp->lock);
1916
1917 bp->rx_pending = ering->rx_pending;
1918 bp->tx_pending = ering->tx_pending;
1919
1920 b44_halt(bp);
1921 b44_init_rings(bp);
5fc7d61a 1922 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1923 netif_wake_queue(bp->dev);
1924 spin_unlock_irq(&bp->lock);
1925
1926 b44_enable_ints(bp);
10badc21 1927
1da177e4
LT		 1928 return 0;
1929}
1930
1931static void b44_get_pauseparam(struct net_device *dev,
1932 struct ethtool_pauseparam *epause)
1933{
1934 struct b44 *bp = netdev_priv(dev);
1935
1936 epause->autoneg =
1937 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1938 epause->rx_pause =
1939 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1940 epause->tx_pause =
1941 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1942}
1943
1944static int b44_set_pauseparam(struct net_device *dev,
1945 struct ethtool_pauseparam *epause)
1946{
1947 struct b44 *bp = netdev_priv(dev);
1948
1949 spin_lock_irq(&bp->lock);
1950 if (epause->autoneg)
1951 bp->flags |= B44_FLAG_PAUSE_AUTO;
1952 else
1953 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1954 if (epause->rx_pause)
1955 bp->flags |= B44_FLAG_RX_PAUSE;
1956 else
1957 bp->flags &= ~B44_FLAG_RX_PAUSE;
1958 if (epause->tx_pause)
1959 bp->flags |= B44_FLAG_TX_PAUSE;
1960 else
1961 bp->flags &= ~B44_FLAG_TX_PAUSE;
1962 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1963 b44_halt(bp);
1964 b44_init_rings(bp);
5fc7d61a 1965 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 1966 } else {
1967 __b44_set_flow_ctrl(bp, bp->flags);
1968 }
1969 spin_unlock_irq(&bp->lock);
1970
1971 b44_enable_ints(bp);
10badc21 1972
1da177e4
LT		 1973 return 0;
1974}
1975
3353930d
FR		 1976static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1977{
1978 switch(stringset) {
1979 case ETH_SS_STATS:
1980 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1981 break;
1982 }
1983}
1984
b9f2c044 1985static int b44_get_sset_count(struct net_device *dev, int sset)
3353930d 1986{
b9f2c044
JG		 1987 switch (sset) {
1988 case ETH_SS_STATS:
1989 return ARRAY_SIZE(b44_gstrings);
1990 default:
1991 return -EOPNOTSUPP;
1992 }
3353930d
FR		 1993}
1994
1995static void b44_get_ethtool_stats(struct net_device *dev,
1996 struct ethtool_stats *stats, u64 *data)
1997{
1998 struct b44 *bp = netdev_priv(dev);
1999 u32 *val = &bp->hw_stats.tx_good_octets;
2000 u32 i;
2001
2002 spin_lock_irq(&bp->lock);
2003
2004 b44_stats_update(bp);
2005
2006 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2007 *data++ = *val++;
2008
2009 spin_unlock_irq(&bp->lock);
2010}
2011
52cafd96
GZ		 2012static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2013{
2014 struct b44 *bp = netdev_priv(dev);
2015
2016 wol->supported = WAKE_MAGIC;
2017 if (bp->flags & B44_FLAG_WOL_ENABLE)
2018 wol->wolopts = WAKE_MAGIC;
2019 else
2020 wol->wolopts = 0;
2021 memset(&wol->sopass, 0, sizeof(wol->sopass));
2022}
2023
2024static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2025{
2026 struct b44 *bp = netdev_priv(dev);
2027
2028 spin_lock_irq(&bp->lock);
2029 if (wol->wolopts & WAKE_MAGIC)
2030 bp->flags |= B44_FLAG_WOL_ENABLE;
2031 else
2032 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2033 spin_unlock_irq(&bp->lock);
2034
2035 return 0;
2036}
2037
7282d491 2038static const struct ethtool_ops b44_ethtool_ops = {
1da177e4
LT		 2039 .get_drvinfo = b44_get_drvinfo,
2040 .get_settings = b44_get_settings,
2041 .set_settings = b44_set_settings,
2042 .nway_reset = b44_nway_reset,
2043 .get_link = ethtool_op_get_link,
52cafd96
GZ		 2044 .get_wol = b44_get_wol,
2045 .set_wol = b44_set_wol,
1da177e4
LT		 2046 .get_ringparam = b44_get_ringparam,
2047 .set_ringparam = b44_set_ringparam,
2048 .get_pauseparam = b44_get_pauseparam,
2049 .set_pauseparam = b44_set_pauseparam,
2050 .get_msglevel = b44_get_msglevel,
2051 .set_msglevel = b44_set_msglevel,
3353930d 2052 .get_strings = b44_get_strings,
b9f2c044 2053 .get_sset_count = b44_get_sset_count,
3353930d 2054 .get_ethtool_stats = b44_get_ethtool_stats,
1da177e4
LT		 2055};
2056
2057static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2058{
2059 struct mii_ioctl_data *data = if_mii(ifr);
2060 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 2061 int err = -EINVAL;
2062
2063 if (!netif_running(dev))
2064 goto out;
1da177e4
LT		 2065
2066 spin_lock_irq(&bp->lock);
2067 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2068 spin_unlock_irq(&bp->lock);
3410572d 2069out:
1da177e4
LT		 2070 return err;
2071}
2072
1da177e4
LT		 2073static int __devinit b44_get_invariants(struct b44 *bp)
2074{
753f4920
MB		 2075 struct ssb_device *sdev = bp->sdev;
2076 int err = 0;
2077 u8 *addr;
1da177e4 2078
753f4920 2079 bp->dma_offset = ssb_dma_translation(sdev);
1da177e4 2080
753f4920
MB		 2081 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2082 instance > 1) {
458414b2
LF		 2083 addr = sdev->bus->sprom.et1mac;
2084 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
753f4920 2085 } else {
458414b2
LF		 2086 addr = sdev->bus->sprom.et0mac;
2087 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
753f4920 2088 }
5ea79631
MB		 2089 /* Some ROMs have buggy PHY addresses with the high
2090 * bits set (sign extension?). Truncate them to a
2091 * valid PHY address. */
2092 bp->phy_addr &= 0x1F;
2093
753f4920 2094 memcpy(bp->dev->dev_addr, addr, 6);
391fc09a
GZ		 2095
2096 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2097 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2098 return -EINVAL;
2099 }
2100
2160de53 2101 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4 2102
1da177e4
LT		 2103 bp->imask = IMASK_DEF;
2104
10badc21 2105 /* XXX - really required?
1da177e4 2106 bp->flags |= B44_FLAG_BUGGY_TXPTR;
753f4920 2107 */
52cafd96 2108
753f4920
MB		 2109 if (bp->sdev->id.revision >= 7)
2110 bp->flags |= B44_FLAG_B0_ANDLATER;
52cafd96 2111
1da177e4
LT		 2112 return err;
2113}
2114
403413e5
SH		 2115static const struct net_device_ops b44_netdev_ops = {
2116 .ndo_open = b44_open,
2117 .ndo_stop = b44_close,
2118 .ndo_start_xmit = b44_start_xmit,
2119 .ndo_get_stats = b44_get_stats,
2120 .ndo_set_multicast_list = b44_set_rx_mode,
2121 .ndo_set_mac_address = b44_set_mac_addr,
2122 .ndo_validate_addr = eth_validate_addr,
2123 .ndo_do_ioctl = b44_ioctl,
2124 .ndo_tx_timeout = b44_tx_timeout,
2125 .ndo_change_mtu = b44_change_mtu,
2126#ifdef CONFIG_NET_POLL_CONTROLLER
2127 .ndo_poll_controller = b44_poll_controller,
2128#endif
2129};
2130
753f4920
MB		 2131static int __devinit b44_init_one(struct ssb_device *sdev,
2132 const struct ssb_device_id *ent)
1da177e4
LT		 2133{
2134 static int b44_version_printed = 0;
1da177e4
LT		 2135 struct net_device *dev;
2136 struct b44 *bp;
0795af57 2137 int err;
1da177e4 2138
753f4920
MB		 2139 instance++;
2140
1da177e4
LT		 2141 if (b44_version_printed++ == 0)
2142 printk(KERN_INFO "%s", version);
2143
1da177e4
LT		 2144
2145 dev = alloc_etherdev(sizeof(*bp));
2146 if (!dev) {
753f4920 2147 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
1da177e4 2148 err = -ENOMEM;
753f4920 2149 goto out;
1da177e4
LT		 2150 }
2151
753f4920 2152 SET_NETDEV_DEV(dev, sdev->dev);
1da177e4
LT		 2153
2154 /* No interesting netdevice features in this card... */
2155 dev->features |= 0;
2156
2157 bp = netdev_priv(dev);
753f4920 2158 bp->sdev = sdev;
1da177e4 2159 bp->dev = dev;
a58c891a 2160 bp->force_copybreak = 0;
874a6214
FR		 2161
2162 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 2163
2164 spin_lock_init(&bp->lock);
2165
1da177e4
LT		 2166 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2167 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2168
403413e5 2169 dev->netdev_ops = &b44_netdev_ops;
bea3348e 2170 netif_napi_add(dev, &bp->napi, b44_poll, 64);
1da177e4 2171 dev->watchdog_timeo = B44_TX_TIMEOUT;
753f4920 2172 dev->irq = sdev->irq;
1da177e4
LT		 2173 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2174
c35ca399
SH		 2175 netif_carrier_off(dev);
2176
753f4920
MB		 2177 err = ssb_bus_powerup(sdev->bus, 0);
2178 if (err) {
2179 dev_err(sdev->dev,
2180 "Failed to powerup the bus\n");
2181 goto err_out_free_dev;
2182 }
2183 err = ssb_dma_set_mask(sdev, DMA_30BIT_MASK);
2184 if (err) {
2185 dev_err(sdev->dev,
2186 "Required 30BIT DMA mask unsupported by the system.\n");
2187 goto err_out_powerdown;
2188 }
1da177e4
LT		 2189 err = b44_get_invariants(bp);
2190 if (err) {
753f4920 2191 dev_err(sdev->dev,
2e8a538d 2192 "Problem fetching invariants of chip, aborting.\n");
753f4920 2193 goto err_out_powerdown;
1da177e4
LT		 2194 }
2195
2196 bp->mii_if.dev = dev;
2197 bp->mii_if.mdio_read = b44_mii_read;
2198 bp->mii_if.mdio_write = b44_mii_write;
2199 bp->mii_if.phy_id = bp->phy_addr;
2200 bp->mii_if.phy_id_mask = 0x1f;
2201 bp->mii_if.reg_num_mask = 0x1f;
2202
2203 /* By default, advertise all speed/duplex settings. */
2204 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2205 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2206
2207 /* By default, auto-negotiate PAUSE. */
2208 bp->flags |= B44_FLAG_PAUSE_AUTO;
2209
2210 err = register_netdev(dev);
2211 if (err) {
753f4920
MB		 2212 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2213 goto err_out_powerdown;
1da177e4
LT		 2214 }
2215
753f4920 2216 ssb_set_drvdata(sdev, dev);
1da177e4 2217
10badc21 2218 /* Chip reset provides power to the b44 MAC & PCI cores, which
5c513129 2219 * is necessary for MAC register access.
10badc21 2220 */
fedb0eef 2221 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
5c513129 2222
e174961c
JB		 2223 printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2224 dev->name, dev->dev_addr);
1da177e4
LT		 2225
2226 return 0;
2227
753f4920
MB		 2228err_out_powerdown:
2229 ssb_bus_may_powerdown(sdev->bus);
1da177e4
LT		 2230
2231err_out_free_dev:
2232 free_netdev(dev);
2233
753f4920 2234out:
1da177e4
LT		 2235 return err;
2236}
2237
753f4920 2238static void __devexit b44_remove_one(struct ssb_device *sdev)
1da177e4 2239{
753f4920 2240 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2241
874a6214 2242 unregister_netdev(dev);
e92aa634 2243 ssb_device_disable(sdev, 0);
753f4920 2244 ssb_bus_may_powerdown(sdev->bus);
874a6214 2245 free_netdev(dev);
fedb0eef 2246 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
753f4920 2247 ssb_set_drvdata(sdev, NULL);
1da177e4
LT		 2248}
2249
753f4920 2250static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
1da177e4 2251{
753f4920 2252 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4
LT		 2253 struct b44 *bp = netdev_priv(dev);
2254
753f4920
MB		 2255 if (!netif_running(dev))
2256 return 0;
1da177e4
LT		 2257
2258 del_timer_sync(&bp->timer);
2259
10badc21 2260 spin_lock_irq(&bp->lock);
1da177e4
LT		 2261
2262 b44_halt(bp);
10badc21 2263 netif_carrier_off(bp->dev);
1da177e4
LT		 2264 netif_device_detach(bp->dev);
2265 b44_free_rings(bp);
2266
2267 spin_unlock_irq(&bp->lock);
46e17853
PM		 2268
2269 free_irq(dev->irq, dev);
52cafd96 2270 if (bp->flags & B44_FLAG_WOL_ENABLE) {
5fc7d61a 2271 b44_init_hw(bp, B44_PARTIAL_RESET);
52cafd96
GZ		 2272 b44_setup_wol(bp);
2273 }
753f4920 2274
fedb0eef 2275 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
1da177e4
LT		 2276 return 0;
2277}
2278
753f4920 2279static int b44_resume(struct ssb_device *sdev)
1da177e4 2280{
753f4920 2281 struct net_device *dev = ssb_get_drvdata(sdev);
1da177e4 2282 struct b44 *bp = netdev_priv(dev);
90afd0e5 2283 int rc = 0;
1da177e4 2284
753f4920 2285 rc = ssb_bus_powerup(sdev->bus, 0);
90afd0e5 2286 if (rc) {
753f4920
MB		 2287 dev_err(sdev->dev,
2288 "Failed to powerup the bus\n");
90afd0e5
DM		 2289 return rc;
2290 }
2291
1da177e4
LT		 2292 if (!netif_running(dev))
2293 return 0;
2294
90afd0e5
DM		 2295 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2296 if (rc) {
46e17853 2297 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
90afd0e5
DM		 2298 return rc;
2299 }
46e17853 2300
1da177e4
LT		 2301 spin_lock_irq(&bp->lock);
2302
2303 b44_init_rings(bp);
5fc7d61a 2304 b44_init_hw(bp, B44_FULL_RESET);
1da177e4
LT		 2305 netif_device_attach(bp->dev);
2306 spin_unlock_irq(&bp->lock);
2307
1da177e4 2308 b44_enable_ints(bp);
d9e2d185 2309 netif_wake_queue(dev);
a72a8179
SH		 2310
2311 mod_timer(&bp->timer, jiffies + 1);
2312
1da177e4
LT		 2313 return 0;
2314}
2315
753f4920 2316static struct ssb_driver b44_ssb_driver = {
1da177e4 2317 .name = DRV_MODULE_NAME,
753f4920 2318 .id_table = b44_ssb_tbl,
1da177e4
LT		 2319 .probe = b44_init_one,
2320 .remove = __devexit_p(b44_remove_one),
753f4920
MB		 2321 .suspend = b44_suspend,
2322 .resume = b44_resume,
1da177e4
LT		 2323};
2324
753f4920
MB		 2325static inline int b44_pci_init(void)
2326{
2327 int err = 0;
2328#ifdef CONFIG_B44_PCI
2329 err = ssb_pcihost_register(&b44_pci_driver);
2330#endif
2331 return err;
2332}
2333
2334static inline void b44_pci_exit(void)
2335{
2336#ifdef CONFIG_B44_PCI
2337 ssb_pcihost_unregister(&b44_pci_driver);
2338#endif
2339}
2340
1da177e4
LT		 2341static int __init b44_init(void)
2342{
9f38c636 2343 unsigned int dma_desc_align_size = dma_get_cache_alignment();
753f4920 2344 int err;
9f38c636
JL		 2345
2346 /* Setup paramaters for syncing RX/TX DMA descriptors */
2347 dma_desc_align_mask = ~(dma_desc_align_size - 1);
22d4d771 2348 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
9f38c636 2349
753f4920
MB		 2350 err = b44_pci_init();
2351 if (err)
2352 return err;
2353 err = ssb_driver_register(&b44_ssb_driver);
2354 if (err)
2355 b44_pci_exit();
2356 return err;
1da177e4
LT		 2357}
2358
2359static void __exit b44_cleanup(void)
2360{
753f4920
MB		 2361 ssb_driver_unregister(&b44_ssb_driver);
2362 b44_pci_exit();
1da177e4
LT		 2363}
2364
2365module_init(b44_init);
2366module_exit(b44_cleanup);
2367
Linux 6.x block layer and io_uring tree(s)