Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 LT |
15 | * Author: MontaVista Software, Inc. |
16 | * ppopov@mvista.com or source@mvista.com | |
17 | * | |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
30 | * with this program; if not, write to the Free Software Foundation, Inc., | |
31 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
32 | * | |
33 | * ######################################################################## | |
34 | * | |
6aa20a22 | 35 | * |
1da177e4 | 36 | */ |
bc36b428 | 37 | #include <linux/capability.h> |
d791c2bd | 38 | #include <linux/dma-mapping.h> |
1da177e4 LT |
39 | #include <linux/module.h> |
40 | #include <linux/kernel.h> | |
1da177e4 LT |
41 | #include <linux/string.h> |
42 | #include <linux/timer.h> | |
43 | #include <linux/errno.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/ioport.h> | |
46 | #include <linux/bitops.h> | |
47 | #include <linux/slab.h> | |
48 | #include <linux/interrupt.h> | |
1da177e4 LT |
49 | #include <linux/init.h> |
50 | #include <linux/netdevice.h> | |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
25b31cb1 YY |
58 | |
59 | #include <asm/cpu.h> | |
1da177e4 LT |
60 | #include <asm/mipsregs.h> |
61 | #include <asm/irq.h> | |
62 | #include <asm/io.h> | |
63 | #include <asm/processor.h> | |
64 | ||
25b31cb1 YY |
65 | #include <au1000.h> |
66 | #include <prom.h> | |
67 | ||
1da177e4 LT |
68 | #include "au1000_eth.h" |
69 | ||
70 | #ifdef AU1000_ETH_DEBUG | |
71 | static int au1000_debug = 5; | |
72 | #else | |
73 | static int au1000_debug = 3; | |
74 | #endif | |
75 | ||
89be0501 | 76 | #define DRV_NAME "au1000_eth" |
d5b20697 | 77 | #define DRV_VERSION "1.6" |
1da177e4 LT |
78 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
79 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
80 | ||
81 | MODULE_AUTHOR(DRV_AUTHOR); | |
82 | MODULE_DESCRIPTION(DRV_DESC); | |
83 | MODULE_LICENSE("GPL"); | |
84 | ||
1da177e4 LT |
85 | /* |
86 | * Theory of operation | |
87 | * | |
6aa20a22 JG |
88 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
89 | * There are four receive and four transmit descriptors. These | |
90 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
91 | * hardware registers. |
92 | * | |
93 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 94 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
95 | * hardware registers, however, are still mapped at KSEG1 to |
96 | * make sure there's no out-of-order writes, and that all writes | |
97 | * complete immediately. | |
98 | */ | |
99 | ||
100 | /* These addresses are only used if yamon doesn't tell us what | |
101 | * the mac address is, and the mac address is not passed on the | |
102 | * command line. | |
103 | */ | |
6aa20a22 | 104 | static unsigned char au1000_mac_addr[6] __devinitdata = { |
1da177e4 LT |
105 | 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00 |
106 | }; | |
107 | ||
1da177e4 LT |
108 | struct au1000_private *au_macs[NUM_ETH_INTERFACES]; |
109 | ||
0638dec0 HVR |
110 | /* |
111 | * board-specific configurations | |
112 | * | |
113 | * PHY detection algorithm | |
114 | * | |
115 | * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is | |
116 | * autodetected: | |
117 | * | |
118 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
119 | * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is | |
120 | * defined) PHY address not already claimed by another netdev. | |
121 | * | |
122 | * If nothing was found that way when searching for the 2nd ethernet | |
123 | * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then | |
124 | * the first MII bus is searched as well for an unclaimed PHY; this is | |
125 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
126 | * bus. | |
127 | * | |
128 | * Finally, if no PHY is found, then the corresponding ethernet | |
129 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
130 | */ |
131 | ||
0638dec0 HVR |
132 | /* autodetection defaults */ |
133 | #undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR | |
134 | #define AU1XXX_PHY1_SEARCH_ON_MAC0 | |
1da177e4 | 135 | |
0638dec0 HVR |
136 | /* static PHY setup |
137 | * | |
138 | * most boards PHY setup should be detectable properly with the | |
139 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
140 | * you have a switch attached, or want to use the PHY's interrupt | |
141 | * notification capabilities) you can provide a static PHY | |
142 | * configuration here | |
143 | * | |
144 | * IRQs may only be set, if a PHY address was configured | |
145 | * If a PHY address is given, also a bus id is required to be set | |
146 | * | |
147 | * ps: make sure the used irqs are configured properly in the board | |
148 | * specific irq-map | |
149 | */ | |
1da177e4 | 150 | |
0638dec0 HVR |
151 | #if defined(CONFIG_MIPS_BOSPORUS) |
152 | /* | |
153 | * Micrel/Kendin 5 port switch attached to MAC0, | |
154 | * MAC0 is associated with PHY address 5 (== WAN port) | |
155 | * MAC1 is not associated with any PHY, since it's connected directly | |
156 | * to the switch. | |
157 | * no interrupts are used | |
158 | */ | |
159 | # define AU1XXX_PHY_STATIC_CONFIG | |
1da177e4 | 160 | |
0638dec0 HVR |
161 | # define AU1XXX_PHY0_ADDR 5 |
162 | # define AU1XXX_PHY0_BUSID 0 | |
163 | # undef AU1XXX_PHY0_IRQ | |
1da177e4 | 164 | |
0638dec0 HVR |
165 | # undef AU1XXX_PHY1_ADDR |
166 | # undef AU1XXX_PHY1_BUSID | |
167 | # undef AU1XXX_PHY1_IRQ | |
1da177e4 LT |
168 | #endif |
169 | ||
0638dec0 HVR |
170 | #if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0) |
171 | # error MAC0-associated PHY attached 2nd MACs MII bus not supported yet | |
1da177e4 | 172 | #endif |
1da177e4 | 173 | |
5ef3041e FF |
174 | static void enable_mac(struct net_device *dev, int force_reset) |
175 | { | |
176 | unsigned long flags; | |
177 | struct au1000_private *aup = netdev_priv(dev); | |
178 | ||
179 | spin_lock_irqsave(&aup->lock, flags); | |
180 | ||
181 | if(force_reset || (!aup->mac_enabled)) { | |
182 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
183 | au_sync_delay(2); | |
184 | *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 | |
185 | | MAC_EN_CLOCK_ENABLE); | |
186 | au_sync_delay(2); | |
187 | ||
188 | aup->mac_enabled = 1; | |
189 | } | |
190 | ||
191 | spin_unlock_irqrestore(&aup->lock, flags); | |
192 | } | |
193 | ||
0638dec0 HVR |
194 | /* |
195 | * MII operations | |
196 | */ | |
1210dde7 | 197 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 198 | { |
454d7c9b | 199 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
200 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
201 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
202 | u32 timedout = 20; |
203 | u32 mii_control; | |
204 | ||
1da177e4 LT |
205 | while (*mii_control_reg & MAC_MII_BUSY) { |
206 | mdelay(1); | |
207 | if (--timedout == 0) { | |
6aa20a22 | 208 | printk(KERN_ERR "%s: read_MII busy timeout!!\n", |
1da177e4 LT |
209 | dev->name); |
210 | return -1; | |
211 | } | |
212 | } | |
213 | ||
6aa20a22 | 214 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 215 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 LT |
216 | |
217 | *mii_control_reg = mii_control; | |
218 | ||
219 | timedout = 20; | |
220 | while (*mii_control_reg & MAC_MII_BUSY) { | |
221 | mdelay(1); | |
222 | if (--timedout == 0) { | |
6aa20a22 | 223 | printk(KERN_ERR "%s: mdio_read busy timeout!!\n", |
1da177e4 LT |
224 | dev->name); |
225 | return -1; | |
226 | } | |
227 | } | |
228 | return (int)*mii_data_reg; | |
229 | } | |
230 | ||
1210dde7 AB |
231 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
232 | int reg, u16 value) | |
1da177e4 | 233 | { |
454d7c9b | 234 | struct au1000_private *aup = netdev_priv(dev); |
0638dec0 HVR |
235 | volatile u32 *const mii_control_reg = &aup->mac->mii_control; |
236 | volatile u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
237 | u32 timedout = 20; |
238 | u32 mii_control; | |
239 | ||
1da177e4 LT |
240 | while (*mii_control_reg & MAC_MII_BUSY) { |
241 | mdelay(1); | |
242 | if (--timedout == 0) { | |
6aa20a22 | 243 | printk(KERN_ERR "%s: mdio_write busy timeout!!\n", |
1da177e4 LT |
244 | dev->name); |
245 | return; | |
246 | } | |
247 | } | |
248 | ||
6aa20a22 | 249 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 250 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 LT |
251 | |
252 | *mii_data_reg = value; | |
253 | *mii_control_reg = mii_control; | |
254 | } | |
255 | ||
1210dde7 | 256 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
257 | { |
258 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
259 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */ | |
260 | struct net_device *const dev = bus->priv; | |
261 | ||
262 | enable_mac(dev, 0); /* make sure the MAC associated with this | |
263 | * mii_bus is enabled */ | |
1210dde7 | 264 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 265 | } |
1da177e4 | 266 | |
1210dde7 AB |
267 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
268 | u16 value) | |
1da177e4 | 269 | { |
0638dec0 | 270 | struct net_device *const dev = bus->priv; |
1da177e4 | 271 | |
0638dec0 HVR |
272 | enable_mac(dev, 0); /* make sure the MAC associated with this |
273 | * mii_bus is enabled */ | |
1210dde7 | 274 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 275 | return 0; |
1da177e4 LT |
276 | } |
277 | ||
1210dde7 | 278 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 279 | { |
0638dec0 | 280 | struct net_device *const dev = bus->priv; |
1da177e4 | 281 | |
0638dec0 HVR |
282 | enable_mac(dev, 0); /* make sure the MAC associated with this |
283 | * mii_bus is enabled */ | |
284 | return 0; | |
285 | } | |
1da177e4 | 286 | |
5ef3041e FF |
287 | static void hard_stop(struct net_device *dev) |
288 | { | |
289 | struct au1000_private *aup = netdev_priv(dev); | |
290 | ||
291 | if (au1000_debug > 4) | |
292 | printk(KERN_INFO "%s: hard stop\n", dev->name); | |
293 | ||
294 | aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
295 | au_sync_delay(10); | |
296 | } | |
297 | ||
298 | static void enable_rx_tx(struct net_device *dev) | |
299 | { | |
300 | struct au1000_private *aup = netdev_priv(dev); | |
301 | ||
302 | if (au1000_debug > 4) | |
303 | printk(KERN_INFO "%s: enable_rx_tx\n", dev->name); | |
304 | ||
305 | aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
306 | au_sync_delay(10); | |
307 | } | |
308 | ||
309 | static void | |
310 | au1000_adjust_link(struct net_device *dev) | |
311 | { | |
312 | struct au1000_private *aup = netdev_priv(dev); | |
313 | struct phy_device *phydev = aup->phy_dev; | |
314 | unsigned long flags; | |
315 | ||
316 | int status_change = 0; | |
317 | ||
318 | BUG_ON(!aup->phy_dev); | |
319 | ||
320 | spin_lock_irqsave(&aup->lock, flags); | |
321 | ||
322 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
323 | // speed changed | |
324 | ||
325 | switch(phydev->speed) { | |
326 | case SPEED_10: | |
327 | case SPEED_100: | |
328 | break; | |
329 | default: | |
330 | printk(KERN_WARNING | |
331 | "%s: Speed (%d) is not 10/100 ???\n", | |
332 | dev->name, phydev->speed); | |
333 | break; | |
334 | } | |
335 | ||
336 | aup->old_speed = phydev->speed; | |
337 | ||
338 | status_change = 1; | |
339 | } | |
340 | ||
341 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
342 | // duplex mode changed | |
343 | ||
344 | /* switching duplex mode requires to disable rx and tx! */ | |
345 | hard_stop(dev); | |
346 | ||
347 | if (DUPLEX_FULL == phydev->duplex) | |
348 | aup->mac->control = ((aup->mac->control | |
349 | | MAC_FULL_DUPLEX) | |
350 | & ~MAC_DISABLE_RX_OWN); | |
351 | else | |
352 | aup->mac->control = ((aup->mac->control | |
353 | & ~MAC_FULL_DUPLEX) | |
354 | | MAC_DISABLE_RX_OWN); | |
355 | au_sync_delay(1); | |
356 | ||
357 | enable_rx_tx(dev); | |
358 | aup->old_duplex = phydev->duplex; | |
359 | ||
360 | status_change = 1; | |
361 | } | |
362 | ||
363 | if(phydev->link != aup->old_link) { | |
364 | // link state changed | |
365 | ||
366 | if (!phydev->link) { | |
367 | /* link went down */ | |
368 | aup->old_speed = 0; | |
369 | aup->old_duplex = -1; | |
370 | } | |
371 | ||
372 | aup->old_link = phydev->link; | |
373 | status_change = 1; | |
374 | } | |
375 | ||
376 | spin_unlock_irqrestore(&aup->lock, flags); | |
377 | ||
378 | if (status_change) { | |
379 | if (phydev->link) | |
380 | printk(KERN_INFO "%s: link up (%d/%s)\n", | |
381 | dev->name, phydev->speed, | |
382 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); | |
383 | else | |
384 | printk(KERN_INFO "%s: link down\n", dev->name); | |
385 | } | |
386 | } | |
387 | ||
0638dec0 HVR |
388 | static int mii_probe (struct net_device *dev) |
389 | { | |
454d7c9b | 390 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
391 | struct phy_device *phydev = NULL; |
392 | ||
393 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
394 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
395 | ||
396 | if(aup->mac_id == 0) { /* get PHY0 */ | |
397 | # if defined(AU1XXX_PHY0_ADDR) | |
298cf9be | 398 | phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR]; |
0638dec0 HVR |
399 | # else |
400 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
401 | dev->name); | |
402 | return 0; | |
403 | # endif /* defined(AU1XXX_PHY0_ADDR) */ | |
404 | } else if (aup->mac_id == 1) { /* get PHY1 */ | |
405 | # if defined(AU1XXX_PHY1_ADDR) | |
298cf9be | 406 | phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR]; |
0638dec0 HVR |
407 | # else |
408 | printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", | |
409 | dev->name); | |
410 | return 0; | |
411 | # endif /* defined(AU1XXX_PHY1_ADDR) */ | |
412 | } | |
413 | ||
414 | #else /* defined(AU1XXX_PHY_STATIC_CONFIG) */ | |
415 | int phy_addr; | |
416 | ||
417 | /* find the first (lowest address) PHY on the current MAC's MII bus */ | |
418 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) | |
298cf9be LB |
419 | if (aup->mii_bus->phy_map[phy_addr]) { |
420 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
0638dec0 HVR |
421 | # if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR) |
422 | break; /* break out with first one found */ | |
423 | # endif | |
1da177e4 | 424 | } |
1da177e4 | 425 | |
0638dec0 HVR |
426 | # if defined(AU1XXX_PHY1_SEARCH_ON_MAC0) |
427 | /* try harder to find a PHY */ | |
428 | if (!phydev && (aup->mac_id == 1)) { | |
429 | /* no PHY found, maybe we have a dual PHY? */ | |
430 | printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, " | |
431 | "let's see if it's attached to MAC0...\n"); | |
432 | ||
433 | BUG_ON(!au_macs[0]); | |
434 | ||
435 | /* find the first (lowest address) non-attached PHY on | |
436 | * the MAC0 MII bus */ | |
437 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
438 | struct phy_device *const tmp_phydev = | |
298cf9be | 439 | au_macs[0]->mii_bus->phy_map[phy_addr]; |
0638dec0 HVR |
440 | |
441 | if (!tmp_phydev) | |
442 | continue; /* no PHY here... */ | |
443 | ||
444 | if (tmp_phydev->attached_dev) | |
445 | continue; /* already claimed by MAC0 */ | |
446 | ||
447 | phydev = tmp_phydev; | |
448 | break; /* found it */ | |
1da177e4 LT |
449 | } |
450 | } | |
0638dec0 | 451 | # endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */ |
1da177e4 | 452 | |
0638dec0 HVR |
453 | #endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */ |
454 | if (!phydev) { | |
455 | printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name); | |
1da177e4 LT |
456 | return -1; |
457 | } | |
458 | ||
0638dec0 | 459 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
460 | BUG_ON(phydev->attached_dev); |
461 | ||
db1d7bf7 KS |
462 | phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link, |
463 | 0, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
464 | |
465 | if (IS_ERR(phydev)) { | |
466 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | |
467 | return PTR_ERR(phydev); | |
468 | } | |
469 | ||
470 | /* mask with MAC supported features */ | |
471 | phydev->supported &= (SUPPORTED_10baseT_Half | |
472 | | SUPPORTED_10baseT_Full | |
473 | | SUPPORTED_100baseT_Half | |
474 | | SUPPORTED_100baseT_Full | |
475 | | SUPPORTED_Autoneg | |
476 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
477 | | SUPPORTED_MII | |
478 | | SUPPORTED_TP); | |
479 | ||
480 | phydev->advertising = phydev->supported; | |
481 | ||
482 | aup->old_link = 0; | |
483 | aup->old_speed = 0; | |
484 | aup->old_duplex = -1; | |
485 | aup->phy_dev = phydev; | |
486 | ||
487 | printk(KERN_INFO "%s: attached PHY driver [%s] " | |
db1d7bf7 KS |
488 | "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, |
489 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | |
1da177e4 LT |
490 | |
491 | return 0; | |
492 | } | |
493 | ||
494 | ||
495 | /* | |
496 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 497 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
498 | * both, receive and transmit operations. |
499 | */ | |
500 | static db_dest_t *GetFreeDB(struct au1000_private *aup) | |
501 | { | |
502 | db_dest_t *pDB; | |
503 | pDB = aup->pDBfree; | |
504 | ||
505 | if (pDB) { | |
506 | aup->pDBfree = pDB->pnext; | |
507 | } | |
508 | return pDB; | |
509 | } | |
510 | ||
511 | void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB) | |
512 | { | |
513 | db_dest_t *pDBfree = aup->pDBfree; | |
514 | if (pDBfree) | |
515 | pDBfree->pnext = pDB; | |
516 | aup->pDBfree = pDB; | |
517 | } | |
518 | ||
0638dec0 HVR |
519 | static void reset_mac_unlocked(struct net_device *dev) |
520 | { | |
454d7c9b | 521 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
522 | int i; |
523 | ||
524 | hard_stop(dev); | |
525 | ||
526 | *aup->enable = MAC_EN_CLOCK_ENABLE; | |
527 | au_sync_delay(2); | |
528 | *aup->enable = 0; | |
529 | au_sync_delay(2); | |
530 | ||
1da177e4 LT |
531 | aup->tx_full = 0; |
532 | for (i = 0; i < NUM_RX_DMA; i++) { | |
533 | /* reset control bits */ | |
534 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
535 | } | |
536 | for (i = 0; i < NUM_TX_DMA; i++) { | |
537 | /* reset control bits */ | |
538 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
539 | } | |
0638dec0 HVR |
540 | |
541 | aup->mac_enabled = 0; | |
542 | ||
1da177e4 LT |
543 | } |
544 | ||
0638dec0 HVR |
545 | static void reset_mac(struct net_device *dev) |
546 | { | |
454d7c9b | 547 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
548 | unsigned long flags; |
549 | ||
550 | if (au1000_debug > 4) | |
551 | printk(KERN_INFO "%s: reset mac, aup %x\n", | |
552 | dev->name, (unsigned)aup); | |
553 | ||
554 | spin_lock_irqsave(&aup->lock, flags); | |
555 | ||
556 | reset_mac_unlocked (dev); | |
557 | ||
558 | spin_unlock_irqrestore(&aup->lock, flags); | |
559 | } | |
1da177e4 | 560 | |
6aa20a22 | 561 | /* |
1da177e4 LT |
562 | * Setup the receive and transmit "rings". These pointers are the addresses |
563 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
564 | * these are not descriptors sitting in memory. | |
565 | */ | |
6aa20a22 | 566 | static void |
1da177e4 LT |
567 | setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) |
568 | { | |
569 | int i; | |
570 | ||
571 | for (i = 0; i < NUM_RX_DMA; i++) { | |
6aa20a22 | 572 | aup->rx_dma_ring[i] = |
1da177e4 LT |
573 | (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i); |
574 | } | |
575 | for (i = 0; i < NUM_TX_DMA; i++) { | |
6aa20a22 | 576 | aup->tx_dma_ring[i] = |
1da177e4 LT |
577 | (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i); |
578 | } | |
579 | } | |
580 | ||
581 | static struct { | |
1da177e4 LT |
582 | u32 base_addr; |
583 | u32 macen_addr; | |
584 | int irq; | |
585 | struct net_device *dev; | |
89be0501 SS |
586 | } iflist[2] = { |
587 | #ifdef CONFIG_SOC_AU1000 | |
588 | {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT}, | |
589 | {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT} | |
590 | #endif | |
591 | #ifdef CONFIG_SOC_AU1100 | |
592 | {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT} | |
593 | #endif | |
594 | #ifdef CONFIG_SOC_AU1500 | |
595 | {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT}, | |
596 | {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT} | |
597 | #endif | |
598 | #ifdef CONFIG_SOC_AU1550 | |
599 | {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT}, | |
600 | {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT} | |
601 | #endif | |
602 | }; | |
1da177e4 LT |
603 | |
604 | static int num_ifs; | |
605 | ||
0638dec0 HVR |
606 | /* |
607 | * ethtool operations | |
608 | */ | |
1da177e4 | 609 | |
0638dec0 | 610 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 611 | { |
454d7c9b | 612 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 613 | |
0638dec0 HVR |
614 | if (aup->phy_dev) |
615 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 616 | |
0638dec0 | 617 | return -EINVAL; |
1da177e4 LT |
618 | } |
619 | ||
0638dec0 | 620 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 621 | { |
454d7c9b | 622 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 623 | |
0638dec0 HVR |
624 | if (!capable(CAP_NET_ADMIN)) |
625 | return -EPERM; | |
1da177e4 | 626 | |
0638dec0 HVR |
627 | if (aup->phy_dev) |
628 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 629 | |
0638dec0 | 630 | return -EINVAL; |
1da177e4 LT |
631 | } |
632 | ||
633 | static void | |
634 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
635 | { | |
454d7c9b | 636 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
637 | |
638 | strcpy(info->driver, DRV_NAME); | |
639 | strcpy(info->version, DRV_VERSION); | |
640 | info->fw_version[0] = '\0'; | |
641 | sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id); | |
642 | info->regdump_len = 0; | |
643 | } | |
644 | ||
7282d491 | 645 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
646 | .get_settings = au1000_get_settings, |
647 | .set_settings = au1000_set_settings, | |
648 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 649 | .get_link = ethtool_op_get_link, |
1da177e4 LT |
650 | }; |
651 | ||
5ef3041e FF |
652 | |
653 | /* | |
654 | * Initialize the interface. | |
655 | * | |
656 | * When the device powers up, the clocks are disabled and the | |
657 | * mac is in reset state. When the interface is closed, we | |
658 | * do the same -- reset the device and disable the clocks to | |
659 | * conserve power. Thus, whenever au1000_init() is called, | |
660 | * the device should already be in reset state. | |
661 | */ | |
662 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 663 | { |
5ef3041e FF |
664 | struct au1000_private *aup = netdev_priv(dev); |
665 | unsigned long flags; | |
666 | int i; | |
667 | u32 control; | |
89be0501 | 668 | |
5ef3041e FF |
669 | if (au1000_debug > 4) |
670 | printk("%s: au1000_init\n", dev->name); | |
1da177e4 | 671 | |
5ef3041e FF |
672 | /* bring the device out of reset */ |
673 | enable_mac(dev, 1); | |
89be0501 | 674 | |
5ef3041e | 675 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 676 | |
5ef3041e FF |
677 | aup->mac->control = 0; |
678 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
679 | aup->tx_tail = aup->tx_head; | |
680 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 681 | |
5ef3041e FF |
682 | aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4]; |
683 | aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
684 | dev->dev_addr[1]<<8 | dev->dev_addr[0]; | |
685 | ||
686 | for (i = 0; i < NUM_RX_DMA; i++) { | |
687 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; | |
1da177e4 | 688 | } |
5ef3041e | 689 | au_sync(); |
1da177e4 | 690 | |
5ef3041e FF |
691 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
692 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
693 | control |= MAC_BIG_ENDIAN; | |
694 | #endif | |
695 | if (aup->phy_dev) { | |
696 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
697 | control |= MAC_FULL_DUPLEX; | |
698 | else | |
699 | control |= MAC_DISABLE_RX_OWN; | |
700 | } else { /* PHY-less op, assume full-duplex */ | |
701 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
702 | } |
703 | ||
5ef3041e FF |
704 | aup->mac->control = control; |
705 | aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ | |
706 | au_sync(); | |
1da177e4 | 707 | |
5ef3041e FF |
708 | spin_unlock_irqrestore(&aup->lock, flags); |
709 | return 0; | |
710 | } | |
1da177e4 | 711 | |
5ef3041e FF |
712 | static inline void update_rx_stats(struct net_device *dev, u32 status) |
713 | { | |
714 | struct au1000_private *aup = netdev_priv(dev); | |
715 | struct net_device_stats *ps = &dev->stats; | |
1da177e4 | 716 | |
5ef3041e FF |
717 | ps->rx_packets++; |
718 | if (status & RX_MCAST_FRAME) | |
719 | ps->multicast++; | |
1da177e4 | 720 | |
5ef3041e FF |
721 | if (status & RX_ERROR) { |
722 | ps->rx_errors++; | |
723 | if (status & RX_MISSED_FRAME) | |
724 | ps->rx_missed_errors++; | |
4989ccb2 | 725 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
726 | ps->rx_length_errors++; |
727 | if (status & RX_CRC_ERROR) | |
728 | ps->rx_crc_errors++; | |
729 | if (status & RX_COLL) | |
730 | ps->collisions++; | |
298cf9be | 731 | } |
5ef3041e FF |
732 | else |
733 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; | |
298cf9be | 734 | |
1da177e4 LT |
735 | } |
736 | ||
6aa20a22 | 737 | /* |
5ef3041e | 738 | * Au1000 receive routine. |
1da177e4 | 739 | */ |
5ef3041e | 740 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 741 | { |
454d7c9b | 742 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e FF |
743 | struct sk_buff *skb; |
744 | volatile rx_dma_t *prxd; | |
745 | u32 buff_stat, status; | |
746 | db_dest_t *pDB; | |
747 | u32 frmlen; | |
1da177e4 | 748 | |
5ef3041e FF |
749 | if (au1000_debug > 5) |
750 | printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head); | |
1da177e4 | 751 | |
5ef3041e FF |
752 | prxd = aup->rx_dma_ring[aup->rx_head]; |
753 | buff_stat = prxd->buff_stat; | |
754 | while (buff_stat & RX_T_DONE) { | |
755 | status = prxd->status; | |
756 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
757 | update_rx_stats(dev, status); | |
758 | if (!(status & RX_ERROR)) { | |
1da177e4 | 759 | |
5ef3041e FF |
760 | /* good frame */ |
761 | frmlen = (status & RX_FRAME_LEN_MASK); | |
762 | frmlen -= 4; /* Remove FCS */ | |
763 | skb = dev_alloc_skb(frmlen + 2); | |
764 | if (skb == NULL) { | |
765 | printk(KERN_ERR | |
766 | "%s: Memory squeeze, dropping packet.\n", | |
767 | dev->name); | |
768 | dev->stats.rx_dropped++; | |
769 | continue; | |
770 | } | |
771 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
772 | skb_copy_to_linear_data(skb, | |
773 | (unsigned char *)pDB->vaddr, frmlen); | |
774 | skb_put(skb, frmlen); | |
775 | skb->protocol = eth_type_trans(skb, dev); | |
776 | netif_rx(skb); /* pass the packet to upper layers */ | |
777 | } | |
778 | else { | |
779 | if (au1000_debug > 4) { | |
780 | if (status & RX_MISSED_FRAME) | |
781 | printk("rx miss\n"); | |
782 | if (status & RX_WDOG_TIMER) | |
783 | printk("rx wdog\n"); | |
784 | if (status & RX_RUNT) | |
785 | printk("rx runt\n"); | |
786 | if (status & RX_OVERLEN) | |
787 | printk("rx overlen\n"); | |
788 | if (status & RX_COLL) | |
789 | printk("rx coll\n"); | |
790 | if (status & RX_MII_ERROR) | |
791 | printk("rx mii error\n"); | |
792 | if (status & RX_CRC_ERROR) | |
793 | printk("rx crc error\n"); | |
794 | if (status & RX_LEN_ERROR) | |
795 | printk("rx len error\n"); | |
796 | if (status & RX_U_CNTRL_FRAME) | |
797 | printk("rx u control frame\n"); | |
5ef3041e FF |
798 | } |
799 | } | |
800 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
801 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
802 | au_sync(); | |
1da177e4 | 803 | |
5ef3041e FF |
804 | /* next descriptor */ |
805 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
806 | buff_stat = prxd->buff_stat; | |
1da177e4 | 807 | } |
1da177e4 LT |
808 | return 0; |
809 | } | |
810 | ||
5ef3041e | 811 | static void update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 812 | { |
454d7c9b | 813 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 814 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 815 | |
5ef3041e FF |
816 | if (status & TX_FRAME_ABORTED) { |
817 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
818 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
819 | /* any other tx errors are only valid | |
820 | * in half duplex mode */ | |
821 | ps->tx_errors++; | |
822 | ps->tx_aborted_errors++; | |
823 | } | |
1da177e4 | 824 | } |
5ef3041e FF |
825 | else { |
826 | ps->tx_errors++; | |
827 | ps->tx_aborted_errors++; | |
828 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
829 | ps->tx_carrier_errors++; | |
830 | } | |
831 | } | |
832 | } | |
0638dec0 | 833 | |
5ef3041e FF |
834 | /* |
835 | * Called from the interrupt service routine to acknowledge | |
836 | * the TX DONE bits. This is a must if the irq is setup as | |
837 | * edge triggered. | |
838 | */ | |
839 | static void au1000_tx_ack(struct net_device *dev) | |
840 | { | |
841 | struct au1000_private *aup = netdev_priv(dev); | |
842 | volatile tx_dma_t *ptxd; | |
0638dec0 | 843 | |
5ef3041e | 844 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 845 | |
5ef3041e FF |
846 | while (ptxd->buff_stat & TX_T_DONE) { |
847 | update_tx_stats(dev, ptxd->status); | |
848 | ptxd->buff_stat &= ~TX_T_DONE; | |
849 | ptxd->len = 0; | |
850 | au_sync(); | |
0638dec0 | 851 | |
5ef3041e FF |
852 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
853 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 854 | |
5ef3041e FF |
855 | if (aup->tx_full) { |
856 | aup->tx_full = 0; | |
857 | netif_wake_queue(dev); | |
858 | } | |
1da177e4 | 859 | } |
5ef3041e | 860 | } |
1da177e4 | 861 | |
5ef3041e FF |
862 | /* |
863 | * Au1000 interrupt service routine. | |
864 | */ | |
865 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
866 | { | |
867 | struct net_device *dev = dev_id; | |
1da177e4 | 868 | |
5ef3041e FF |
869 | /* Handle RX interrupts first to minimize chance of overrun */ |
870 | ||
871 | au1000_rx(dev); | |
872 | au1000_tx_ack(dev); | |
873 | return IRQ_RETVAL(1); | |
1da177e4 LT |
874 | } |
875 | ||
876 | static int au1000_open(struct net_device *dev) | |
877 | { | |
878 | int retval; | |
454d7c9b | 879 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 LT |
880 | |
881 | if (au1000_debug > 4) | |
882 | printk("%s: open: dev=%p\n", dev->name, dev); | |
883 | ||
0638dec0 HVR |
884 | if ((retval = request_irq(dev->irq, &au1000_interrupt, 0, |
885 | dev->name, dev))) { | |
886 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
887 | dev->name, dev->irq); | |
888 | return retval; | |
889 | } | |
890 | ||
1da177e4 LT |
891 | if ((retval = au1000_init(dev))) { |
892 | printk(KERN_ERR "%s: error in au1000_init\n", dev->name); | |
893 | free_irq(dev->irq, dev); | |
894 | return retval; | |
895 | } | |
1da177e4 | 896 | |
0638dec0 HVR |
897 | if (aup->phy_dev) { |
898 | /* cause the PHY state machine to schedule a link state check */ | |
899 | aup->phy_dev->state = PHY_CHANGELINK; | |
900 | phy_start(aup->phy_dev); | |
1da177e4 LT |
901 | } |
902 | ||
0638dec0 | 903 | netif_start_queue(dev); |
1da177e4 LT |
904 | |
905 | if (au1000_debug > 4) | |
906 | printk("%s: open: Initialization done.\n", dev->name); | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | static int au1000_close(struct net_device *dev) | |
912 | { | |
0638dec0 | 913 | unsigned long flags; |
454d7c9b | 914 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 LT |
915 | |
916 | if (au1000_debug > 4) | |
917 | printk("%s: close: dev=%p\n", dev->name, dev); | |
918 | ||
0638dec0 HVR |
919 | if (aup->phy_dev) |
920 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
921 | |
922 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 HVR |
923 | |
924 | reset_mac_unlocked (dev); | |
925 | ||
1da177e4 LT |
926 | /* stop the device */ |
927 | netif_stop_queue(dev); | |
928 | ||
929 | /* disable the interrupt */ | |
930 | free_irq(dev->irq, dev); | |
931 | spin_unlock_irqrestore(&aup->lock, flags); | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
1da177e4 LT |
936 | /* |
937 | * Au1000 transmit routine. | |
938 | */ | |
61357325 | 939 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 940 | { |
454d7c9b | 941 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 942 | struct net_device_stats *ps = &dev->stats; |
1da177e4 LT |
943 | volatile tx_dma_t *ptxd; |
944 | u32 buff_stat; | |
945 | db_dest_t *pDB; | |
946 | int i; | |
947 | ||
948 | if (au1000_debug > 5) | |
6aa20a22 JG |
949 | printk("%s: tx: aup %x len=%d, data=%p, head %d\n", |
950 | dev->name, (unsigned)aup, skb->len, | |
1da177e4 LT |
951 | skb->data, aup->tx_head); |
952 | ||
953 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
954 | buff_stat = ptxd->buff_stat; | |
955 | if (buff_stat & TX_DMA_ENABLE) { | |
956 | /* We've wrapped around and the transmitter is still busy */ | |
957 | netif_stop_queue(dev); | |
958 | aup->tx_full = 1; | |
5b548140 | 959 | return NETDEV_TX_BUSY; |
1da177e4 LT |
960 | } |
961 | else if (buff_stat & TX_T_DONE) { | |
c2d3d4b9 | 962 | update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
963 | ptxd->len = 0; |
964 | } | |
965 | ||
966 | if (aup->tx_full) { | |
967 | aup->tx_full = 0; | |
968 | netif_wake_queue(dev); | |
969 | } | |
970 | ||
971 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
d626f62b | 972 | skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); |
1da177e4 | 973 | if (skb->len < ETH_ZLEN) { |
6aa20a22 | 974 | for (i=skb->len; i<ETH_ZLEN; i++) { |
1da177e4 LT |
975 | ((char *)pDB->vaddr)[i] = 0; |
976 | } | |
977 | ptxd->len = ETH_ZLEN; | |
978 | } | |
979 | else | |
5ef3041e | 980 | ptxd->len = skb->len; |
1da177e4 | 981 | |
5ef3041e FF |
982 | ps->tx_packets++; |
983 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 984 | |
5ef3041e FF |
985 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
986 | au_sync(); | |
987 | dev_kfree_skb(skb); | |
988 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
989 | dev->trans_start = jiffies; | |
6ed10654 | 990 | return NETDEV_TX_OK; |
1da177e4 LT |
991 | } |
992 | ||
1da177e4 LT |
993 | /* |
994 | * The Tx ring has been full longer than the watchdog timeout | |
995 | * value. The transmitter must be hung? | |
996 | */ | |
997 | static void au1000_tx_timeout(struct net_device *dev) | |
998 | { | |
999 | printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev); | |
1000 | reset_mac(dev); | |
1001 | au1000_init(dev); | |
1002 | dev->trans_start = jiffies; | |
1003 | netif_wake_queue(dev); | |
1004 | } | |
1005 | ||
d9a92cee | 1006 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 1007 | { |
454d7c9b | 1008 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1009 | |
6aa20a22 | 1010 | if (au1000_debug > 4) |
d9a92cee | 1011 | printk("%s: au1000_multicast_list: flags=%x\n", dev->name, dev->flags); |
1da177e4 LT |
1012 | |
1013 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1014 | aup->mac->control |= MAC_PROMISCUOUS; | |
1da177e4 LT |
1015 | } else if ((dev->flags & IFF_ALLMULTI) || |
1016 | dev->mc_count > MULTICAST_FILTER_LIMIT) { | |
1017 | aup->mac->control |= MAC_PASS_ALL_MULTI; | |
1018 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1019 | printk(KERN_INFO "%s: Pass all multicast\n", dev->name); | |
1020 | } else { | |
1021 | int i; | |
1022 | struct dev_mc_list *mclist; | |
1023 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1024 | ||
1025 | mc_filter[1] = mc_filter[0] = 0; | |
1026 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1027 | i++, mclist = mclist->next) { | |
6aa20a22 | 1028 | set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26, |
1da177e4 LT |
1029 | (long *)mc_filter); |
1030 | } | |
1031 | aup->mac->multi_hash_high = mc_filter[1]; | |
1032 | aup->mac->multi_hash_low = mc_filter[0]; | |
1033 | aup->mac->control &= ~MAC_PROMISCUOUS; | |
1034 | aup->mac->control |= MAC_HASH_MODE; | |
1035 | } | |
1036 | } | |
1037 | ||
1da177e4 LT |
1038 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1039 | { | |
454d7c9b | 1040 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1041 | |
0638dec0 | 1042 | if (!netif_running(dev)) return -EINVAL; |
1da177e4 | 1043 | |
0638dec0 | 1044 | if (!aup->phy_dev) return -EINVAL; // PHY not controllable |
1da177e4 | 1045 | |
0638dec0 | 1046 | return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd); |
1da177e4 LT |
1047 | } |
1048 | ||
d9a92cee AB |
1049 | static const struct net_device_ops au1000_netdev_ops = { |
1050 | .ndo_open = au1000_open, | |
1051 | .ndo_stop = au1000_close, | |
1052 | .ndo_start_xmit = au1000_tx, | |
1053 | .ndo_set_multicast_list = au1000_multicast_list, | |
1054 | .ndo_do_ioctl = au1000_ioctl, | |
1055 | .ndo_tx_timeout = au1000_tx_timeout, | |
1056 | .ndo_set_mac_address = eth_mac_addr, | |
1057 | .ndo_validate_addr = eth_validate_addr, | |
1058 | .ndo_change_mtu = eth_change_mtu, | |
1059 | }; | |
1060 | ||
5ef3041e FF |
1061 | static struct net_device * au1000_probe(int port_num) |
1062 | { | |
1063 | static unsigned version_printed = 0; | |
1064 | struct au1000_private *aup = NULL; | |
1065 | struct net_device *dev = NULL; | |
1066 | db_dest_t *pDB, *pDBfree; | |
1067 | char ethaddr[6]; | |
1068 | int irq, i, err; | |
1069 | u32 base, macen; | |
1070 | ||
1071 | if (port_num >= NUM_ETH_INTERFACES) | |
1072 | return NULL; | |
1073 | ||
1074 | base = CPHYSADDR(iflist[port_num].base_addr ); | |
1075 | macen = CPHYSADDR(iflist[port_num].macen_addr); | |
1076 | irq = iflist[port_num].irq; | |
1077 | ||
1078 | if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") || | |
1079 | !request_mem_region(macen, 4, "Au1x00 ENET")) | |
1080 | return NULL; | |
1081 | ||
1082 | if (version_printed++ == 0) | |
1083 | printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
1084 | ||
1085 | dev = alloc_etherdev(sizeof(struct au1000_private)); | |
1086 | if (!dev) { | |
1087 | printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME); | |
1088 | return NULL; | |
1089 | } | |
1090 | ||
1091 | if ((err = register_netdev(dev)) != 0) { | |
1092 | printk(KERN_ERR "%s: Cannot register net device, error %d\n", | |
1093 | DRV_NAME, err); | |
1094 | free_netdev(dev); | |
1095 | return NULL; | |
1096 | } | |
1097 | ||
1098 | printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", | |
1099 | dev->name, base, irq); | |
1100 | ||
1101 | aup = netdev_priv(dev); | |
1102 | ||
1103 | spin_lock_init(&aup->lock); | |
1104 | ||
1105 | /* Allocate the data buffers */ | |
1106 | /* Snooping works fine with eth on all au1xxx */ | |
1107 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * | |
1108 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1109 | &aup->dma_addr, 0); | |
1110 | if (!aup->vaddr) { | |
1111 | free_netdev(dev); | |
1112 | release_mem_region( base, MAC_IOSIZE); | |
1113 | release_mem_region(macen, 4); | |
1114 | return NULL; | |
1115 | } | |
1116 | ||
1117 | /* aup->mac is the base address of the MAC's registers */ | |
1118 | aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr; | |
1119 | ||
1120 | /* Setup some variables for quick register address access */ | |
1121 | aup->enable = (volatile u32 *)iflist[port_num].macen_addr; | |
1122 | aup->mac_id = port_num; | |
1123 | au_macs[port_num] = aup; | |
1124 | ||
1125 | if (port_num == 0) { | |
1126 | if (prom_get_ethernet_addr(ethaddr) == 0) | |
1127 | memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr)); | |
1128 | else { | |
1129 | printk(KERN_INFO "%s: No MAC address found\n", | |
1130 | dev->name); | |
1131 | /* Use the hard coded MAC addresses */ | |
1132 | } | |
1133 | ||
1134 | setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); | |
1135 | } else if (port_num == 1) | |
1136 | setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); | |
1137 | ||
1138 | /* | |
1139 | * Assign to the Ethernet ports two consecutive MAC addresses | |
1140 | * to match those that are printed on their stickers | |
1141 | */ | |
1142 | memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr)); | |
1143 | dev->dev_addr[5] += port_num; | |
1144 | ||
1145 | *aup->enable = 0; | |
1146 | aup->mac_enabled = 0; | |
1147 | ||
1148 | aup->mii_bus = mdiobus_alloc(); | |
1149 | if (aup->mii_bus == NULL) | |
1150 | goto err_out; | |
1151 | ||
1152 | aup->mii_bus->priv = dev; | |
1153 | aup->mii_bus->read = au1000_mdiobus_read; | |
1154 | aup->mii_bus->write = au1000_mdiobus_write; | |
1155 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1156 | aup->mii_bus->name = "au1000_eth_mii"; | |
1157 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id); | |
1158 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
dcbfef82 | 1159 | if (aup->mii_bus->irq == NULL) |
1160 | goto err_out; | |
1161 | ||
5ef3041e FF |
1162 | for(i = 0; i < PHY_MAX_ADDR; ++i) |
1163 | aup->mii_bus->irq[i] = PHY_POLL; | |
1164 | ||
1165 | /* if known, set corresponding PHY IRQs */ | |
1166 | #if defined(AU1XXX_PHY_STATIC_CONFIG) | |
1167 | # if defined(AU1XXX_PHY0_IRQ) | |
1168 | if (AU1XXX_PHY0_BUSID == aup->mac_id) | |
1169 | aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ; | |
1170 | # endif | |
1171 | # if defined(AU1XXX_PHY1_IRQ) | |
1172 | if (AU1XXX_PHY1_BUSID == aup->mac_id) | |
1173 | aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ; | |
1174 | # endif | |
1175 | #endif | |
1176 | mdiobus_register(aup->mii_bus); | |
1177 | ||
1178 | if (mii_probe(dev) != 0) { | |
1179 | goto err_out; | |
1180 | } | |
1181 | ||
1182 | pDBfree = NULL; | |
1183 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1184 | pDB = aup->db; | |
1185 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1186 | pDB->pnext = pDBfree; | |
1187 | pDBfree = pDB; | |
1188 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1189 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1190 | pDB++; | |
1191 | } | |
1192 | aup->pDBfree = pDBfree; | |
1193 | ||
1194 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1195 | pDB = GetFreeDB(aup); | |
1196 | if (!pDB) { | |
1197 | goto err_out; | |
1198 | } | |
1199 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1200 | aup->rx_db_inuse[i] = pDB; | |
1201 | } | |
1202 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1203 | pDB = GetFreeDB(aup); | |
1204 | if (!pDB) { | |
1205 | goto err_out; | |
1206 | } | |
1207 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; | |
1208 | aup->tx_dma_ring[i]->len = 0; | |
1209 | aup->tx_db_inuse[i] = pDB; | |
1210 | } | |
1211 | ||
1212 | dev->base_addr = base; | |
1213 | dev->irq = irq; | |
d9a92cee | 1214 | dev->netdev_ops = &au1000_netdev_ops; |
5ef3041e | 1215 | SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); |
5ef3041e FF |
1216 | dev->watchdog_timeo = ETH_TX_TIMEOUT; |
1217 | ||
1218 | /* | |
1219 | * The boot code uses the ethernet controller, so reset it to start | |
1220 | * fresh. au1000_init() expects that the device is in reset state. | |
1221 | */ | |
1222 | reset_mac(dev); | |
1223 | ||
1224 | return dev; | |
1225 | ||
1226 | err_out: | |
1227 | if (aup->mii_bus != NULL) { | |
1228 | mdiobus_unregister(aup->mii_bus); | |
1229 | mdiobus_free(aup->mii_bus); | |
1230 | } | |
1231 | ||
1232 | /* here we should have a valid dev plus aup-> register addresses | |
1233 | * so we can reset the mac properly.*/ | |
1234 | reset_mac(dev); | |
1235 | ||
1236 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1237 | if (aup->rx_db_inuse[i]) | |
1238 | ReleaseDB(aup, aup->rx_db_inuse[i]); | |
1239 | } | |
1240 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1241 | if (aup->tx_db_inuse[i]) | |
1242 | ReleaseDB(aup, aup->tx_db_inuse[i]); | |
1243 | } | |
1244 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1245 | (void *)aup->vaddr, aup->dma_addr); | |
1246 | unregister_netdev(dev); | |
1247 | free_netdev(dev); | |
1248 | release_mem_region( base, MAC_IOSIZE); | |
1249 | release_mem_region(macen, 4); | |
1250 | return NULL; | |
1251 | } | |
1252 | ||
1253 | /* | |
1254 | * Setup the base address and interrupt of the Au1xxx ethernet macs | |
1255 | * based on cpu type and whether the interface is enabled in sys_pinfunc | |
1256 | * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0. | |
1257 | */ | |
1258 | static int __init au1000_init_module(void) | |
1259 | { | |
1260 | int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); | |
1261 | struct net_device *dev; | |
1262 | int i, found_one = 0; | |
1263 | ||
1264 | num_ifs = NUM_ETH_INTERFACES - ni; | |
1265 | ||
1266 | for(i = 0; i < num_ifs; i++) { | |
1267 | dev = au1000_probe(i); | |
1268 | iflist[i].dev = dev; | |
1269 | if (dev) | |
1270 | found_one++; | |
1271 | } | |
1272 | if (!found_one) | |
1273 | return -ENODEV; | |
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | static void __exit au1000_cleanup_module(void) | |
1278 | { | |
1279 | int i, j; | |
1280 | struct net_device *dev; | |
1281 | struct au1000_private *aup; | |
1282 | ||
1283 | for (i = 0; i < num_ifs; i++) { | |
1284 | dev = iflist[i].dev; | |
1285 | if (dev) { | |
1286 | aup = netdev_priv(dev); | |
1287 | unregister_netdev(dev); | |
1288 | mdiobus_unregister(aup->mii_bus); | |
1289 | mdiobus_free(aup->mii_bus); | |
1290 | for (j = 0; j < NUM_RX_DMA; j++) | |
1291 | if (aup->rx_db_inuse[j]) | |
1292 | ReleaseDB(aup, aup->rx_db_inuse[j]); | |
1293 | for (j = 0; j < NUM_TX_DMA; j++) | |
1294 | if (aup->tx_db_inuse[j]) | |
1295 | ReleaseDB(aup, aup->tx_db_inuse[j]); | |
1296 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1297 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1298 | (void *)aup->vaddr, aup->dma_addr); | |
1299 | release_mem_region(dev->base_addr, MAC_IOSIZE); | |
1300 | release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4); | |
1301 | free_netdev(dev); | |
1302 | } | |
1303 | } | |
1304 | } | |
1305 | ||
1da177e4 LT |
1306 | module_init(au1000_init_module); |
1307 | module_exit(au1000_cleanup_module); |