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ibm_newemac: Fix EMAC soft reset on 460EX/GT
[linux-2.6-block.git] / drivers / net / atlx / atl2.c
CommitLineData
452c1ce2
CS		 1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119 spin_lock_init(&adapter->tx_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct dev_mc_list *mc_ptr;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
162 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337/*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342}
343
344/*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349{
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352}
353
354/*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359{
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363}
364
365#ifdef NETIF_F_HW_VLAN_TX
366static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368{
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393}
394#endif
395
396static void atl2_intr_rx(struct atl2_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
413 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
422 adapter->net_stats.rx_dropped++;
423 break;
424 }
425 skb_reserve(skb, NET_IP_ALIGN);
426 skb->dev = netdev;
427 memcpy(skb->data, rxd->packet, rx_size);
428 skb_put(skb, rx_size);
429 skb->protocol = eth_type_trans(skb, netdev);
430#ifdef NETIF_F_HW_VLAN_TX
431 if (adapter->vlgrp && (rxd->status.vlan)) {
432 u16 vlan_tag = (rxd->status.vtag>>4) |
433 ((rxd->status.vtag&7) << 13) |
434 ((rxd->status.vtag&8) << 9);
435 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
436 } else
437#endif
438 netif_rx(skb);
439 adapter->net_stats.rx_bytes += rx_size;
440 adapter->net_stats.rx_packets++;
441 netdev->last_rx = jiffies;
442 } else {
443 adapter->net_stats.rx_errors++;
444
445 if (rxd->status.ok && rxd->status.pkt_size <= 60)
446 adapter->net_stats.rx_length_errors++;
447 if (rxd->status.mcast)
448 adapter->net_stats.multicast++;
449 if (rxd->status.crc)
450 adapter->net_stats.rx_crc_errors++;
451 if (rxd->status.align)
452 adapter->net_stats.rx_frame_errors++;
453 }
454
455 /* advance write ptr */
456 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
457 adapter->rxd_write_ptr = 0;
458 } while (1);
459
460 /* update mailbox? */
461 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
462 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
463}
464
465static void atl2_intr_tx(struct atl2_adapter *adapter)
466{
467 u32 txd_read_ptr;
468 u32 txs_write_ptr;
469 struct tx_pkt_status *txs;
470 struct tx_pkt_header *txph;
471 int free_hole = 0;
472
473 do {
474 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
475 txs = adapter->txs_ring + txs_write_ptr;
476 if (!txs->update)
477 break; /* tx stop here */
478
479 free_hole = 1;
480 txs->update = 0;
481
482 if (++txs_write_ptr == adapter->txs_ring_size)
483 txs_write_ptr = 0;
484 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
485
486 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
487 txph = (struct tx_pkt_header *)
488 (((u8 *)adapter->txd_ring) + txd_read_ptr);
489
490 if (txph->pkt_size != txs->pkt_size) {
491 struct tx_pkt_status *old_txs = txs;
492 printk(KERN_WARNING
493 "%s: txs packet size not consistent with txd"
494 " txd_:0x%08x, txs_:0x%08x!\n",
495 adapter->netdev->name,
496 *(u32 *)txph, *(u32 *)txs);
497 printk(KERN_WARNING
498 "txd read ptr: 0x%x\n",
499 txd_read_ptr);
500 txs = adapter->txs_ring + txs_write_ptr;
501 printk(KERN_WARNING
502 "txs-behind:0x%08x\n",
503 *(u32 *)txs);
504 if (txs_write_ptr < 2) {
505 txs = adapter->txs_ring +
506 (adapter->txs_ring_size +
507 txs_write_ptr - 2);
508 } else {
509 txs = adapter->txs_ring + (txs_write_ptr - 2);
510 }
511 printk(KERN_WARNING
512 "txs-before:0x%08x\n",
513 *(u32 *)txs);
514 txs = old_txs;
515 }
516
517 /* 4for TPH */
518 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
519 if (txd_read_ptr >= adapter->txd_ring_size)
520 txd_read_ptr -= adapter->txd_ring_size;
521
522 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
523
524 /* tx statistics: */
e2f092ff
JC		 525 if (txs->ok) {
526 adapter->net_stats.tx_bytes += txs->pkt_size;
452c1ce2 527 adapter->net_stats.tx_packets++;
e2f092ff 528 }
452c1ce2
CS		 529 else
530 adapter->net_stats.tx_errors++;
531
532 if (txs->defer)
533 adapter->net_stats.collisions++;
534 if (txs->abort_col)
535 adapter->net_stats.tx_aborted_errors++;
536 if (txs->late_col)
537 adapter->net_stats.tx_window_errors++;
538 if (txs->underun)
539 adapter->net_stats.tx_fifo_errors++;
540 } while (1);
541
542 if (free_hole) {
543 if (netif_queue_stopped(adapter->netdev) &&
544 netif_carrier_ok(adapter->netdev))
545 netif_wake_queue(adapter->netdev);
546 }
547}
548
549static void atl2_check_for_link(struct atl2_adapter *adapter)
550{
551 struct net_device *netdev = adapter->netdev;
552 u16 phy_data = 0;
553
554 spin_lock(&adapter->stats_lock);
555 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
556 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
557 spin_unlock(&adapter->stats_lock);
558
559 /* notify upper layer link down ASAP */
560 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
561 if (netif_carrier_ok(netdev)) { /* old link state: Up */
562 printk(KERN_INFO "%s: %s NIC Link is Down\n",
563 atl2_driver_name, netdev->name);
564 adapter->link_speed = SPEED_0;
565 netif_carrier_off(netdev);
566 netif_stop_queue(netdev);
567 }
568 }
569 schedule_work(&adapter->link_chg_task);
570}
571
572static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
573{
574 u16 phy_data;
575 spin_lock(&adapter->stats_lock);
576 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
577 spin_unlock(&adapter->stats_lock);
578}
579
580/*
581 * atl2_intr - Interrupt Handler
582 * @irq: interrupt number
583 * @data: pointer to a network interface device structure
584 * @pt_regs: CPU registers structure
585 */
586static irqreturn_t atl2_intr(int irq, void *data)
587{
588 struct atl2_adapter *adapter = netdev_priv(data);
589 struct atl2_hw *hw = &adapter->hw;
590 u32 status;
591
592 status = ATL2_READ_REG(hw, REG_ISR);
593 if (0 == status)
594 return IRQ_NONE;
595
596 /* link event */
597 if (status & ISR_PHY)
598 atl2_clear_phy_int(adapter);
599
600 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
601 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
602
603 /* check if PCIE PHY Link down */
604 if (status & ISR_PHY_LINKDOWN) {
605 if (netif_running(adapter->netdev)) { /* reset MAC */
606 ATL2_WRITE_REG(hw, REG_ISR, 0);
607 ATL2_WRITE_REG(hw, REG_IMR, 0);
608 ATL2_WRITE_FLUSH(hw);
609 schedule_work(&adapter->reset_task);
610 return IRQ_HANDLED;
611 }
612 }
613
614 /* check if DMA read/write error? */
615 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
616 ATL2_WRITE_REG(hw, REG_ISR, 0);
617 ATL2_WRITE_REG(hw, REG_IMR, 0);
618 ATL2_WRITE_FLUSH(hw);
619 schedule_work(&adapter->reset_task);
620 return IRQ_HANDLED;
621 }
622
623 /* link event */
624 if (status & (ISR_PHY | ISR_MANUAL)) {
625 adapter->net_stats.tx_carrier_errors++;
626 atl2_check_for_link(adapter);
627 }
628
629 /* transmit event */
630 if (status & ISR_TX_EVENT)
631 atl2_intr_tx(adapter);
632
633 /* rx exception */
634 if (status & ISR_RX_EVENT)
635 atl2_intr_rx(adapter);
636
637 /* re-enable Interrupt */
638 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
639 return IRQ_HANDLED;
640}
641
642static int atl2_request_irq(struct atl2_adapter *adapter)
643{
644 struct net_device *netdev = adapter->netdev;
645 int flags, err = 0;
646
647 flags = IRQF_SHARED;
648#ifdef CONFIG_PCI_MSI
649 adapter->have_msi = true;
650 err = pci_enable_msi(adapter->pdev);
651 if (err)
652 adapter->have_msi = false;
653
654 if (adapter->have_msi)
655 flags &= ~IRQF_SHARED;
656#endif
657
658 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
659 netdev);
660}
661
662/*
663 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
664 * @adapter: board private structure
665 *
666 * Free all transmit software resources
667 */
668static void atl2_free_ring_resources(struct atl2_adapter *adapter)
669{
670 struct pci_dev *pdev = adapter->pdev;
671 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
672 adapter->ring_dma);
673}
674
675/*
676 * atl2_open - Called when a network interface is made active
677 * @netdev: network interface device structure
678 *
679 * Returns 0 on success, negative value on failure
680 *
681 * The open entry point is called when a network interface is made
682 * active by the system (IFF_UP). At this point all resources needed
683 * for transmit and receive operations are allocated, the interrupt
684 * handler is registered with the OS, the watchdog timer is started,
685 * and the stack is notified that the interface is ready.
686 */
687static int atl2_open(struct net_device *netdev)
688{
689 struct atl2_adapter *adapter = netdev_priv(netdev);
690 int err;
691 u32 val;
692
693 /* disallow open during test */
694 if (test_bit(__ATL2_TESTING, &adapter->flags))
695 return -EBUSY;
696
697 /* allocate transmit descriptors */
698 err = atl2_setup_ring_resources(adapter);
699 if (err)
700 return err;
701
702 err = atl2_init_hw(&adapter->hw);
703 if (err) {
704 err = -EIO;
705 goto err_init_hw;
706 }
707
708 /* hardware has been reset, we need to reload some things */
709 atl2_set_multi(netdev);
710 init_ring_ptrs(adapter);
711
712#ifdef NETIF_F_HW_VLAN_TX
713 atl2_restore_vlan(adapter);
714#endif
715
716 if (atl2_configure(adapter)) {
717 err = -EIO;
718 goto err_config;
719 }
720
721 err = atl2_request_irq(adapter);
722 if (err)
723 goto err_req_irq;
724
725 clear_bit(__ATL2_DOWN, &adapter->flags);
726
727 mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
728
729 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
730 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
731 val | MASTER_CTRL_MANUAL_INT);
732
733 atl2_irq_enable(adapter);
734
735 return 0;
736
737err_init_hw:
738err_req_irq:
739err_config:
740 atl2_free_ring_resources(adapter);
741 atl2_reset_hw(&adapter->hw);
742
743 return err;
744}
745
746static void atl2_down(struct atl2_adapter *adapter)
747{
748 struct net_device *netdev = adapter->netdev;
749
750 /* signal that we're down so the interrupt handler does not
751 * reschedule our watchdog timer */
752 set_bit(__ATL2_DOWN, &adapter->flags);
753
754#ifdef NETIF_F_LLTX
755 netif_stop_queue(netdev);
756#else
757 netif_tx_disable(netdev);
758#endif
759
760 /* reset MAC to disable all RX/TX */
761 atl2_reset_hw(&adapter->hw);
762 msleep(1);
763
764 atl2_irq_disable(adapter);
765
766 del_timer_sync(&adapter->watchdog_timer);
767 del_timer_sync(&adapter->phy_config_timer);
768 clear_bit(0, &adapter->cfg_phy);
769
770 netif_carrier_off(netdev);
771 adapter->link_speed = SPEED_0;
772 adapter->link_duplex = -1;
773}
774
775static void atl2_free_irq(struct atl2_adapter *adapter)
776{
777 struct net_device *netdev = adapter->netdev;
778
779 free_irq(adapter->pdev->irq, netdev);
780
781#ifdef CONFIG_PCI_MSI
782 if (adapter->have_msi)
783 pci_disable_msi(adapter->pdev);
784#endif
785}
786
787/*
788 * atl2_close - Disables a network interface
789 * @netdev: network interface device structure
790 *
791 * Returns 0, this is not allowed to fail
792 *
793 * The close entry point is called when an interface is de-activated
794 * by the OS. The hardware is still under the drivers control, but
795 * needs to be disabled. A global MAC reset is issued to stop the
796 * hardware, and all transmit and receive resources are freed.
797 */
798static int atl2_close(struct net_device *netdev)
799{
800 struct atl2_adapter *adapter = netdev_priv(netdev);
801
802 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
803
804 atl2_down(adapter);
805 atl2_free_irq(adapter);
806 atl2_free_ring_resources(adapter);
807
808 return 0;
809}
810
811static inline int TxsFreeUnit(struct atl2_adapter *adapter)
812{
813 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
814
815 return (adapter->txs_next_clear >= txs_write_ptr) ?
816 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
817 txs_write_ptr - 1) :
818 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
819}
820
821static inline int TxdFreeBytes(struct atl2_adapter *adapter)
822{
823 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
824
825 return (adapter->txd_write_ptr >= txd_read_ptr) ?
826 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
827 txd_read_ptr - 1) :
828 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
829}
830
831static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
832{
833 struct atl2_adapter *adapter = netdev_priv(netdev);
834 unsigned long flags;
835 struct tx_pkt_header *txph;
836 u32 offset, copy_len;
837 int txs_unused;
838 int txbuf_unused;
839
840 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
841 dev_kfree_skb_any(skb);
842 return NETDEV_TX_OK;
843 }
844
845 if (unlikely(skb->len <= 0)) {
846 dev_kfree_skb_any(skb);
847 return NETDEV_TX_OK;
848 }
849
850#ifdef NETIF_F_LLTX
851 local_irq_save(flags);
852 if (!spin_trylock(&adapter->tx_lock)) {
853 /* Collision - tell upper layer to requeue */
854 local_irq_restore(flags);
855 return NETDEV_TX_LOCKED;
856 }
857#else
858 spin_lock_irqsave(&adapter->tx_lock, flags);
859#endif
860 txs_unused = TxsFreeUnit(adapter);
861 txbuf_unused = TxdFreeBytes(adapter);
862
863 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
864 txs_unused < 1) {
865 /* not enough resources */
866 netif_stop_queue(netdev);
867 spin_unlock_irqrestore(&adapter->tx_lock, flags);
868 return NETDEV_TX_BUSY;
869 }
870
871 offset = adapter->txd_write_ptr;
872
873 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
874
875 *(u32 *)txph = 0;
876 txph->pkt_size = skb->len;
877
878 offset += 4;
879 if (offset >= adapter->txd_ring_size)
880 offset -= adapter->txd_ring_size;
881 copy_len = adapter->txd_ring_size - offset;
882 if (copy_len >= skb->len) {
883 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
884 offset += ((u32)(skb->len + 3) & ~3);
885 } else {
886 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
887 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
888 skb->len-copy_len);
889 offset = ((u32)(skb->len-copy_len + 3) & ~3);
890 }
891#ifdef NETIF_F_HW_VLAN_TX
892 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
893 u16 vlan_tag = vlan_tx_tag_get(skb);
894 vlan_tag = (vlan_tag << 4) |
895 (vlan_tag >> 13) |
896 ((vlan_tag >> 9) & 0x8);
897 txph->ins_vlan = 1;
898 txph->vlan = vlan_tag;
899 }
900#endif
901 if (offset >= adapter->txd_ring_size)
902 offset -= adapter->txd_ring_size;
903 adapter->txd_write_ptr = offset;
904
905 /* clear txs before send */
906 adapter->txs_ring[adapter->txs_next_clear].update = 0;
907 if (++adapter->txs_next_clear == adapter->txs_ring_size)
908 adapter->txs_next_clear = 0;
909
910 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
911 (adapter->txd_write_ptr >> 2));
912
913 spin_unlock_irqrestore(&adapter->tx_lock, flags);
914
915 netdev->trans_start = jiffies;
916 dev_kfree_skb_any(skb);
917 return NETDEV_TX_OK;
918}
919
920/*
921 * atl2_get_stats - Get System Network Statistics
922 * @netdev: network interface device structure
923 *
924 * Returns the address of the device statistics structure.
925 * The statistics are actually updated from the timer callback.
926 */
927static struct net_device_stats *atl2_get_stats(struct net_device *netdev)
928{
929 struct atl2_adapter *adapter = netdev_priv(netdev);
930 return &adapter->net_stats;
931}
932
933/*
934 * atl2_change_mtu - Change the Maximum Transfer Unit
935 * @netdev: network interface device structure
936 * @new_mtu: new value for maximum frame size
937 *
938 * Returns 0 on success, negative on failure
939 */
940static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
941{
942 struct atl2_adapter *adapter = netdev_priv(netdev);
943 struct atl2_hw *hw = &adapter->hw;
944
945 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
946 return -EINVAL;
947
948 /* set MTU */
949 if (hw->max_frame_size != new_mtu) {
950 netdev->mtu = new_mtu;
951 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
952 VLAN_SIZE + ETHERNET_FCS_SIZE);
953 }
954
955 return 0;
956}
957
958/*
959 * atl2_set_mac - Change the Ethernet Address of the NIC
960 * @netdev: network interface device structure
961 * @p: pointer to an address structure
962 *
963 * Returns 0 on success, negative on failure
964 */
965static int atl2_set_mac(struct net_device *netdev, void *p)
966{
967 struct atl2_adapter *adapter = netdev_priv(netdev);
968 struct sockaddr *addr = p;
969
970 if (!is_valid_ether_addr(addr->sa_data))
971 return -EADDRNOTAVAIL;
972
973 if (netif_running(netdev))
974 return -EBUSY;
975
976 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
977 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
978
979 atl2_set_mac_addr(&adapter->hw);
980
981 return 0;
982}
983
984/*
985 * atl2_mii_ioctl -
986 * @netdev:
987 * @ifreq:
988 * @cmd:
989 */
990static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
991{
992 struct atl2_adapter *adapter = netdev_priv(netdev);
993 struct mii_ioctl_data *data = if_mii(ifr);
994 unsigned long flags;
995
996 switch (cmd) {
997 case SIOCGMIIPHY:
998 data->phy_id = 0;
999 break;
1000 case SIOCGMIIREG:
1001 if (!capable(CAP_NET_ADMIN))
1002 return -EPERM;
1003 spin_lock_irqsave(&adapter->stats_lock, flags);
1004 if (atl2_read_phy_reg(&adapter->hw,
1005 data->reg_num & 0x1F, &data->val_out)) {
1006 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1007 return -EIO;
1008 }
1009 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1010 break;
1011 case SIOCSMIIREG:
1012 if (!capable(CAP_NET_ADMIN))
1013 return -EPERM;
1014 if (data->reg_num & ~(0x1F))
1015 return -EFAULT;
1016 spin_lock_irqsave(&adapter->stats_lock, flags);
1017 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
1018 data->val_in)) {
1019 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1020 return -EIO;
1021 }
1022 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1023 break;
1024 default:
1025 return -EOPNOTSUPP;
1026 }
1027 return 0;
1028}
1029
1030/*
1031 * atl2_ioctl -
1032 * @netdev:
1033 * @ifreq:
1034 * @cmd:
1035 */
1036static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1037{
1038 switch (cmd) {
1039 case SIOCGMIIPHY:
1040 case SIOCGMIIREG:
1041 case SIOCSMIIREG:
1042 return atl2_mii_ioctl(netdev, ifr, cmd);
1043#ifdef ETHTOOL_OPS_COMPAT
1044 case SIOCETHTOOL:
1045 return ethtool_ioctl(ifr);
1046#endif
1047 default:
1048 return -EOPNOTSUPP;
1049 }
1050}
1051
1052/*
1053 * atl2_tx_timeout - Respond to a Tx Hang
1054 * @netdev: network interface device structure
1055 */
1056static void atl2_tx_timeout(struct net_device *netdev)
1057{
1058 struct atl2_adapter *adapter = netdev_priv(netdev);
1059
1060 /* Do the reset outside of interrupt context */
1061 schedule_work(&adapter->reset_task);
1062}
1063
1064/*
1065 * atl2_watchdog - Timer Call-back
1066 * @data: pointer to netdev cast into an unsigned long
1067 */
1068static void atl2_watchdog(unsigned long data)
1069{
1070 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1071 u32 drop_rxd, drop_rxs;
1072 unsigned long flags;
1073
1074 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1075 spin_lock_irqsave(&adapter->stats_lock, flags);
1076 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1077 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1078 adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs);
1079 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1080
1081 /* Reset the timer */
1082 mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1083 }
1084}
1085
1086/*
1087 * atl2_phy_config - Timer Call-back
1088 * @data: pointer to netdev cast into an unsigned long
1089 */
1090static void atl2_phy_config(unsigned long data)
1091{
1092 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1093 struct atl2_hw *hw = &adapter->hw;
1094 unsigned long flags;
1095
1096 spin_lock_irqsave(&adapter->stats_lock, flags);
1097 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1098 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1099 MII_CR_RESTART_AUTO_NEG);
1100 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1101 clear_bit(0, &adapter->cfg_phy);
1102}
1103
1104static int atl2_up(struct atl2_adapter *adapter)
1105{
1106 struct net_device *netdev = adapter->netdev;
1107 int err = 0;
1108 u32 val;
1109
1110 /* hardware has been reset, we need to reload some things */
1111
1112 err = atl2_init_hw(&adapter->hw);
1113 if (err) {
1114 err = -EIO;
1115 return err;
1116 }
1117
1118 atl2_set_multi(netdev);
1119 init_ring_ptrs(adapter);
1120
1121#ifdef NETIF_F_HW_VLAN_TX
1122 atl2_restore_vlan(adapter);
1123#endif
1124
1125 if (atl2_configure(adapter)) {
1126 err = -EIO;
1127 goto err_up;
1128 }
1129
1130 clear_bit(__ATL2_DOWN, &adapter->flags);
1131
1132 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1133 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1134 MASTER_CTRL_MANUAL_INT);
1135
1136 atl2_irq_enable(adapter);
1137
1138err_up:
1139 return err;
1140}
1141
1142static void atl2_reinit_locked(struct atl2_adapter *adapter)
1143{
1144 WARN_ON(in_interrupt());
1145 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1146 msleep(1);
1147 atl2_down(adapter);
1148 atl2_up(adapter);
1149 clear_bit(__ATL2_RESETTING, &adapter->flags);
1150}
1151
1152static void atl2_reset_task(struct work_struct *work)
1153{
1154 struct atl2_adapter *adapter;
1155 adapter = container_of(work, struct atl2_adapter, reset_task);
1156
1157 atl2_reinit_locked(adapter);
1158}
1159
1160static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1161{
1162 u32 value;
1163 struct atl2_hw *hw = &adapter->hw;
1164 struct net_device *netdev = adapter->netdev;
1165
1166 /* Config MAC CTRL Register */
1167 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1168
1169 /* duplex */
1170 if (FULL_DUPLEX == adapter->link_duplex)
1171 value |= MAC_CTRL_DUPLX;
1172
1173 /* flow control */
1174 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1175
1176 /* PAD & CRC */
1177 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1178
1179 /* preamble length */
1180 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1181 MAC_CTRL_PRMLEN_SHIFT);
1182
1183 /* vlan */
1184 if (adapter->vlgrp)
1185 value |= MAC_CTRL_RMV_VLAN;
1186
1187 /* filter mode */
1188 value |= MAC_CTRL_BC_EN;
1189 if (netdev->flags & IFF_PROMISC)
1190 value |= MAC_CTRL_PROMIS_EN;
1191 else if (netdev->flags & IFF_ALLMULTI)
1192 value |= MAC_CTRL_MC_ALL_EN;
1193
1194 /* half retry buffer */
1195 value |= (((u32)(adapter->hw.retry_buf &
1196 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1197
1198 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1199}
1200
1201static int atl2_check_link(struct atl2_adapter *adapter)
1202{
1203 struct atl2_hw *hw = &adapter->hw;
1204 struct net_device *netdev = adapter->netdev;
1205 int ret_val;
1206 u16 speed, duplex, phy_data;
1207 int reconfig = 0;
1208
1209 /* MII_BMSR must read twise */
1210 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1211 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1212 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1213 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1214 u32 value;
1215 /* disable rx */
1216 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1217 value &= ~MAC_CTRL_RX_EN;
1218 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1219 adapter->link_speed = SPEED_0;
1220 netif_carrier_off(netdev);
1221 netif_stop_queue(netdev);
1222 }
1223 return 0;
1224 }
1225
1226 /* Link Up */
1227 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1228 if (ret_val)
1229 return ret_val;
1230 switch (hw->MediaType) {
1231 case MEDIA_TYPE_100M_FULL:
1232 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1233 reconfig = 1;
1234 break;
1235 case MEDIA_TYPE_100M_HALF:
1236 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1237 reconfig = 1;
1238 break;
1239 case MEDIA_TYPE_10M_FULL:
1240 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1241 reconfig = 1;
1242 break;
1243 case MEDIA_TYPE_10M_HALF:
1244 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1245 reconfig = 1;
1246 break;
1247 }
1248 /* link result is our setting */
1249 if (reconfig == 0) {
1250 if (adapter->link_speed != speed ||
1251 adapter->link_duplex != duplex) {
1252 adapter->link_speed = speed;
1253 adapter->link_duplex = duplex;
1254 atl2_setup_mac_ctrl(adapter);
1255 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1256 atl2_driver_name, netdev->name,
1257 adapter->link_speed,
1258 adapter->link_duplex == FULL_DUPLEX ?
1259 "Full Duplex" : "Half Duplex");
1260 }
1261
1262 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1263 netif_carrier_on(netdev);
1264 netif_wake_queue(netdev);
1265 }
1266 return 0;
1267 }
1268
1269 /* change original link status */
1270 if (netif_carrier_ok(netdev)) {
1271 u32 value;
1272 /* disable rx */
1273 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1274 value &= ~MAC_CTRL_RX_EN;
1275 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1276
1277 adapter->link_speed = SPEED_0;
1278 netif_carrier_off(netdev);
1279 netif_stop_queue(netdev);
1280 }
1281
1282 /* auto-neg, insert timer to re-config phy
1283 * (if interval smaller than 5 seconds, something strange) */
1284 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1285 if (!test_and_set_bit(0, &adapter->cfg_phy))
1286 mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1287 }
1288
1289 return 0;
1290}
1291
1292/*
1293 * atl2_link_chg_task - deal with link change event Out of interrupt context
1294 * @netdev: network interface device structure
1295 */
1296static void atl2_link_chg_task(struct work_struct *work)
1297{
1298 struct atl2_adapter *adapter;
1299 unsigned long flags;
1300
1301 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1302
1303 spin_lock_irqsave(&adapter->stats_lock, flags);
1304 atl2_check_link(adapter);
1305 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1306}
1307
1308static void atl2_setup_pcicmd(struct pci_dev *pdev)
1309{
1310 u16 cmd;
1311
1312 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1313
1314 if (cmd & PCI_COMMAND_INTX_DISABLE)
1315 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1316 if (cmd & PCI_COMMAND_IO)
1317 cmd &= ~PCI_COMMAND_IO;
1318 if (0 == (cmd & PCI_COMMAND_MEMORY))
1319 cmd |= PCI_COMMAND_MEMORY;
1320 if (0 == (cmd & PCI_COMMAND_MASTER))
1321 cmd |= PCI_COMMAND_MASTER;
1322 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1323
1324 /*
1325 * some motherboards BIOS(PXE/EFI) driver may set PME
1326 * while they transfer control to OS (Windows/Linux)
1327 * so we should clear this bit before NIC work normally
1328 */
1329 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1330}
1331
1332/*
1333 * atl2_probe - Device Initialization Routine
1334 * @pdev: PCI device information struct
1335 * @ent: entry in atl2_pci_tbl
1336 *
1337 * Returns 0 on success, negative on failure
1338 *
1339 * atl2_probe initializes an adapter identified by a pci_dev structure.
1340 * The OS initialization, configuring of the adapter private structure,
1341 * and a hardware reset occur.
1342 */
1343static int __devinit atl2_probe(struct pci_dev *pdev,
1344 const struct pci_device_id *ent)
1345{
1346 struct net_device *netdev;
1347 struct atl2_adapter *adapter;
1348 static int cards_found;
1349 unsigned long mmio_start;
1350 int mmio_len;
1351 int err;
1352
1353 cards_found = 0;
1354
1355 err = pci_enable_device(pdev);
1356 if (err)
1357 return err;
1358
1359 /*
1360 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1361 * until the kernel has the proper infrastructure to support 64-bit DMA
1362 * on these devices.
1363 */
1364 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1365 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1366 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1367 goto err_dma;
1368 }
1369
1370 /* Mark all PCI regions associated with PCI device
1371 * pdev as being reserved by owner atl2_driver_name */
1372 err = pci_request_regions(pdev, atl2_driver_name);
1373 if (err)
1374 goto err_pci_reg;
1375
1376 /* Enables bus-mastering on the device and calls
1377 * pcibios_set_master to do the needed arch specific settings */
1378 pci_set_master(pdev);
1379
1380 err = -ENOMEM;
1381 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1382 if (!netdev)
1383 goto err_alloc_etherdev;
1384
1385 SET_NETDEV_DEV(netdev, &pdev->dev);
1386
1387 pci_set_drvdata(pdev, netdev);
1388 adapter = netdev_priv(netdev);
1389 adapter->netdev = netdev;
1390 adapter->pdev = pdev;
1391 adapter->hw.back = adapter;
1392
1393 mmio_start = pci_resource_start(pdev, 0x0);
1394 mmio_len = pci_resource_len(pdev, 0x0);
1395
1396 adapter->hw.mem_rang = (u32)mmio_len;
1397 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1398 if (!adapter->hw.hw_addr) {
1399 err = -EIO;
1400 goto err_ioremap;
1401 }
1402
1403 atl2_setup_pcicmd(pdev);
1404
1405 netdev->open = &atl2_open;
1406 netdev->stop = &atl2_close;
1407 netdev->hard_start_xmit = &atl2_xmit_frame;
1408 netdev->get_stats = &atl2_get_stats;
1409 netdev->set_multicast_list = &atl2_set_multi;
1410 netdev->set_mac_address = &atl2_set_mac;
1411 netdev->change_mtu = &atl2_change_mtu;
1412 netdev->do_ioctl = &atl2_ioctl;
1413 atl2_set_ethtool_ops(netdev);
1414
1415#ifdef HAVE_TX_TIMEOUT
1416 netdev->tx_timeout = &atl2_tx_timeout;
1417 netdev->watchdog_timeo = 5 * HZ;
1418#endif
1419#ifdef NETIF_F_HW_VLAN_TX
1420 netdev->vlan_rx_register = atl2_vlan_rx_register;
1421#endif
1422 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1423
1424 netdev->mem_start = mmio_start;
1425 netdev->mem_end = mmio_start + mmio_len;
1426 adapter->bd_number = cards_found;
1427 adapter->pci_using_64 = false;
1428
1429 /* setup the private structure */
1430 err = atl2_sw_init(adapter);
1431 if (err)
1432 goto err_sw_init;
1433
1434 err = -EIO;
1435
1436#ifdef NETIF_F_HW_VLAN_TX
1437 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1438#endif
1439
1440#ifdef NETIF_F_LLTX
1441 netdev->features |= NETIF_F_LLTX;
1442#endif
1443
1444 /* Init PHY as early as possible due to power saving issue */
1445 atl2_phy_init(&adapter->hw);
1446
1447 /* reset the controller to
1448 * put the device in a known good starting state */
1449
1450 if (atl2_reset_hw(&adapter->hw)) {
1451 err = -EIO;
1452 goto err_reset;
1453 }
1454
1455 /* copy the MAC address out of the EEPROM */
1456 atl2_read_mac_addr(&adapter->hw);
1457 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1458/* FIXME: do we still need this? */
1459#ifdef ETHTOOL_GPERMADDR
1460 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1461
1462 if (!is_valid_ether_addr(netdev->perm_addr)) {
1463#else
1464 if (!is_valid_ether_addr(netdev->dev_addr)) {
1465#endif
1466 err = -EIO;
1467 goto err_eeprom;
1468 }
1469
1470 atl2_check_options(adapter);
1471
1472 init_timer(&adapter->watchdog_timer);
1473 adapter->watchdog_timer.function = &atl2_watchdog;
1474 adapter->watchdog_timer.data = (unsigned long) adapter;
1475
1476 init_timer(&adapter->phy_config_timer);
1477 adapter->phy_config_timer.function = &atl2_phy_config;
1478 adapter->phy_config_timer.data = (unsigned long) adapter;
1479
1480 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1481 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1482
1483 strcpy(netdev->name, "eth%d"); /* ?? */
1484 err = register_netdev(netdev);
1485 if (err)
1486 goto err_register;
1487
1488 /* assume we have no link for now */
1489 netif_carrier_off(netdev);
1490 netif_stop_queue(netdev);
1491
1492 cards_found++;
1493
1494 return 0;
1495
1496err_reset:
1497err_register:
1498err_sw_init:
1499err_eeprom:
1500 iounmap(adapter->hw.hw_addr);
1501err_ioremap:
1502 free_netdev(netdev);
1503err_alloc_etherdev:
1504 pci_release_regions(pdev);
1505err_pci_reg:
1506err_dma:
1507 pci_disable_device(pdev);
1508 return err;
1509}
1510
1511/*
1512 * atl2_remove - Device Removal Routine
1513 * @pdev: PCI device information struct
1514 *
1515 * atl2_remove is called by the PCI subsystem to alert the driver
1516 * that it should release a PCI device. The could be caused by a
1517 * Hot-Plug event, or because the driver is going to be removed from
1518 * memory.
1519 */
1520/* FIXME: write the original MAC address back in case it was changed from a
1521 * BIOS-set value, as in atl1 -- CHS */
1522static void __devexit atl2_remove(struct pci_dev *pdev)
1523{
1524 struct net_device *netdev = pci_get_drvdata(pdev);
1525 struct atl2_adapter *adapter = netdev_priv(netdev);
1526
1527 /* flush_scheduled work may reschedule our watchdog task, so
1528 * explicitly disable watchdog tasks from being rescheduled */
1529 set_bit(__ATL2_DOWN, &adapter->flags);
1530
1531 del_timer_sync(&adapter->watchdog_timer);
1532 del_timer_sync(&adapter->phy_config_timer);
1533
1534 flush_scheduled_work();
1535
1536 unregister_netdev(netdev);
1537
1538 atl2_force_ps(&adapter->hw);
1539
1540 iounmap(adapter->hw.hw_addr);
1541 pci_release_regions(pdev);
1542
1543 free_netdev(netdev);
1544
1545 pci_disable_device(pdev);
1546}
1547
1548static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1549{
1550 struct net_device *netdev = pci_get_drvdata(pdev);
1551 struct atl2_adapter *adapter = netdev_priv(netdev);
1552 struct atl2_hw *hw = &adapter->hw;
1553 u16 speed, duplex;
1554 u32 ctrl = 0;
1555 u32 wufc = adapter->wol;
1556
1557#ifdef CONFIG_PM
1558 int retval = 0;
1559#endif
1560
1561 netif_device_detach(netdev);
1562
1563 if (netif_running(netdev)) {
1564 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1565 atl2_down(adapter);
1566 }
1567
1568#ifdef CONFIG_PM
1569 retval = pci_save_state(pdev);
1570 if (retval)
1571 return retval;
1572#endif
1573
1574 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1575 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1576 if (ctrl & BMSR_LSTATUS)
1577 wufc &= ~ATLX_WUFC_LNKC;
1578
1579 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1580 u32 ret_val;
1581 /* get current link speed & duplex */
1582 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1583 if (ret_val) {
1584 printk(KERN_DEBUG
1585 "%s: get speed&duplex error while suspend\n",
1586 atl2_driver_name);
1587 goto wol_dis;
1588 }
1589
1590 ctrl = 0;
1591
1592 /* turn on magic packet wol */
1593 if (wufc & ATLX_WUFC_MAG)
1594 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1595
1596 /* ignore Link Chg event when Link is up */
1597 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1598
1599 /* Config MAC CTRL Register */
1600 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1601 if (FULL_DUPLEX == adapter->link_duplex)
1602 ctrl |= MAC_CTRL_DUPLX;
1603 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1604 ctrl |= (((u32)adapter->hw.preamble_len &
1605 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1606 ctrl |= (((u32)(adapter->hw.retry_buf &
1607 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1608 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1609 if (wufc & ATLX_WUFC_MAG) {
1610 /* magic packet maybe Broadcast&multicast&Unicast */
1611 ctrl |= MAC_CTRL_BC_EN;
1612 }
1613
1614 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1615
1616 /* pcie patch */
1617 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1618 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1619 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1620 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1621 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1622 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1623
1624 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1625 goto suspend_exit;
1626 }
1627
1628 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1629 /* link is down, so only LINK CHG WOL event enable */
1630 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1631 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1632 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1633
1634 /* pcie patch */
1635 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1636 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1637 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1638 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1639 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1640 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1641
1642 hw->phy_configured = false; /* re-init PHY when resume */
1643
1644 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1645
1646 goto suspend_exit;
1647 }
1648
1649wol_dis:
1650 /* WOL disabled */
1651 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1652
1653 /* pcie patch */
1654 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1655 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1656 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1657 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1658 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1659 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1660
1661 atl2_force_ps(hw);
1662 hw->phy_configured = false; /* re-init PHY when resume */
1663
1664 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1665
1666suspend_exit:
1667 if (netif_running(netdev))
1668 atl2_free_irq(adapter);
1669
1670 pci_disable_device(pdev);
1671
1672 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1673
1674 return 0;
1675}
1676
1677#ifdef CONFIG_PM
1678static int atl2_resume(struct pci_dev *pdev)
1679{
1680 struct net_device *netdev = pci_get_drvdata(pdev);
1681 struct atl2_adapter *adapter = netdev_priv(netdev);
1682 u32 err;
1683
1684 pci_set_power_state(pdev, PCI_D0);
1685 pci_restore_state(pdev);
1686
1687 err = pci_enable_device(pdev);
1688 if (err) {
1689 printk(KERN_ERR
1690 "atl2: Cannot enable PCI device from suspend\n");
1691 return err;
1692 }
1693
1694 pci_set_master(pdev);
1695
1696 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1697
1698 pci_enable_wake(pdev, PCI_D3hot, 0);
1699 pci_enable_wake(pdev, PCI_D3cold, 0);
1700
1701 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1702
1703 err = atl2_request_irq(adapter);
1704 if (netif_running(netdev) && err)
1705 return err;
1706
1707 atl2_reset_hw(&adapter->hw);
1708
1709 if (netif_running(netdev))
1710 atl2_up(adapter);
1711
1712 netif_device_attach(netdev);
1713
1714 return 0;
1715}
1716#endif
1717
1718static void atl2_shutdown(struct pci_dev *pdev)
1719{
1720 atl2_suspend(pdev, PMSG_SUSPEND);
1721}
1722
1723static struct pci_driver atl2_driver = {
1724 .name = atl2_driver_name,
1725 .id_table = atl2_pci_tbl,
1726 .probe = atl2_probe,
1727 .remove = __devexit_p(atl2_remove),
1728 /* Power Managment Hooks */
1729 .suspend = atl2_suspend,
1730#ifdef CONFIG_PM
1731 .resume = atl2_resume,
1732#endif
1733 .shutdown = atl2_shutdown,
1734};
1735
1736/*
1737 * atl2_init_module - Driver Registration Routine
1738 *
1739 * atl2_init_module is the first routine called when the driver is
1740 * loaded. All it does is register with the PCI subsystem.
1741 */
1742static int __init atl2_init_module(void)
1743{
1744 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1745 atl2_driver_version);
1746 printk(KERN_INFO "%s\n", atl2_copyright);
1747 return pci_register_driver(&atl2_driver);
1748}
1749module_init(atl2_init_module);
1750
1751/*
1752 * atl2_exit_module - Driver Exit Cleanup Routine
1753 *
1754 * atl2_exit_module is called just before the driver is removed
1755 * from memory.
1756 */
1757static void __exit atl2_exit_module(void)
1758{
1759 pci_unregister_driver(&atl2_driver);
1760}
1761module_exit(atl2_exit_module);
1762
1763static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1764{
1765 struct atl2_adapter *adapter = hw->back;
1766 pci_read_config_word(adapter->pdev, reg, value);
1767}
1768
1769static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1770{
1771 struct atl2_adapter *adapter = hw->back;
1772 pci_write_config_word(adapter->pdev, reg, *value);
1773}
1774
1775static int atl2_get_settings(struct net_device *netdev,
1776 struct ethtool_cmd *ecmd)
1777{
1778 struct atl2_adapter *adapter = netdev_priv(netdev);
1779 struct atl2_hw *hw = &adapter->hw;
1780
1781 ecmd->supported = (SUPPORTED_10baseT_Half |
1782 SUPPORTED_10baseT_Full |
1783 SUPPORTED_100baseT_Half |
1784 SUPPORTED_100baseT_Full |
1785 SUPPORTED_Autoneg |
1786 SUPPORTED_TP);
1787 ecmd->advertising = ADVERTISED_TP;
1788
1789 ecmd->advertising |= ADVERTISED_Autoneg;
1790 ecmd->advertising |= hw->autoneg_advertised;
1791
1792 ecmd->port = PORT_TP;
1793 ecmd->phy_address = 0;
1794 ecmd->transceiver = XCVR_INTERNAL;
1795
1796 if (adapter->link_speed != SPEED_0) {
1797 ecmd->speed = adapter->link_speed;
1798 if (adapter->link_duplex == FULL_DUPLEX)
1799 ecmd->duplex = DUPLEX_FULL;
1800 else
1801 ecmd->duplex = DUPLEX_HALF;
1802 } else {
1803 ecmd->speed = -1;
1804 ecmd->duplex = -1;
1805 }
1806
1807 ecmd->autoneg = AUTONEG_ENABLE;
1808 return 0;
1809}
1810
1811static int atl2_set_settings(struct net_device *netdev,
1812 struct ethtool_cmd *ecmd)
1813{
1814 struct atl2_adapter *adapter = netdev_priv(netdev);
1815 struct atl2_hw *hw = &adapter->hw;
1816
1817 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1818 msleep(1);
1819
1820 if (ecmd->autoneg == AUTONEG_ENABLE) {
1821#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1822 ADVERTISE_10_FULL | \
1823 ADVERTISE_100_HALF| \
1824 ADVERTISE_100_FULL)
1825
1826 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1827 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1828 hw->autoneg_advertised = MY_ADV_MASK;
1829 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1830 ADVERTISE_100_FULL) {
1831 hw->MediaType = MEDIA_TYPE_100M_FULL;
1832 hw->autoneg_advertised = ADVERTISE_100_FULL;
1833 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1834 ADVERTISE_100_HALF) {
1835 hw->MediaType = MEDIA_TYPE_100M_HALF;
1836 hw->autoneg_advertised = ADVERTISE_100_HALF;
1837 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1838 ADVERTISE_10_FULL) {
1839 hw->MediaType = MEDIA_TYPE_10M_FULL;
1840 hw->autoneg_advertised = ADVERTISE_10_FULL;
1841 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1842 ADVERTISE_10_HALF) {
1843 hw->MediaType = MEDIA_TYPE_10M_HALF;
1844 hw->autoneg_advertised = ADVERTISE_10_HALF;
1845 } else {
1846 clear_bit(__ATL2_RESETTING, &adapter->flags);
1847 return -EINVAL;
1848 }
1849 ecmd->advertising = hw->autoneg_advertised |
1850 ADVERTISED_TP | ADVERTISED_Autoneg;
1851 } else {
1852 clear_bit(__ATL2_RESETTING, &adapter->flags);
1853 return -EINVAL;
1854 }
1855
1856 /* reset the link */
1857 if (netif_running(adapter->netdev)) {
1858 atl2_down(adapter);
1859 atl2_up(adapter);
1860 } else
1861 atl2_reset_hw(&adapter->hw);
1862
1863 clear_bit(__ATL2_RESETTING, &adapter->flags);
1864 return 0;
1865}
1866
1867static u32 atl2_get_tx_csum(struct net_device *netdev)
1868{
1869 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1870}
1871
1872static u32 atl2_get_msglevel(struct net_device *netdev)
1873{
1874 return 0;
1875}
1876
1877/*
1878 * It's sane for this to be empty, but we might want to take advantage of this.
1879 */
1880static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1881{
1882}
1883
1884static int atl2_get_regs_len(struct net_device *netdev)
1885{
1886#define ATL2_REGS_LEN 42
1887 return sizeof(u32) * ATL2_REGS_LEN;
1888}
1889
1890static void atl2_get_regs(struct net_device *netdev,
1891 struct ethtool_regs *regs, void *p)
1892{
1893 struct atl2_adapter *adapter = netdev_priv(netdev);
1894 struct atl2_hw *hw = &adapter->hw;
1895 u32 *regs_buff = p;
1896 u16 phy_data;
1897
1898 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1899
1900 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1901
1902 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1903 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1904 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1905 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1906 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1907 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1908 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1909 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1910 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1911 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1912 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1913 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1914 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1915 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1916 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1917 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1918 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1919 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1920 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1921 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1922 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1923 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1924 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1925 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1926 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1927 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1928 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1929 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1930 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1931 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1932 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1933 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1934 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1935 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1936 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1937 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1938 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1939 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1940 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1941
1942 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1943 regs_buff[40] = (u32)phy_data;
1944 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1945 regs_buff[41] = (u32)phy_data;
1946}
1947
1948static int atl2_get_eeprom_len(struct net_device *netdev)
1949{
1950 struct atl2_adapter *adapter = netdev_priv(netdev);
1951
1952 if (!atl2_check_eeprom_exist(&adapter->hw))
1953 return 512;
1954 else
1955 return 0;
1956}
1957
1958static int atl2_get_eeprom(struct net_device *netdev,
1959 struct ethtool_eeprom *eeprom, u8 *bytes)
1960{
1961 struct atl2_adapter *adapter = netdev_priv(netdev);
1962 struct atl2_hw *hw = &adapter->hw;
1963 u32 *eeprom_buff;
1964 int first_dword, last_dword;
1965 int ret_val = 0;
1966 int i;
1967
1968 if (eeprom->len == 0)
1969 return -EINVAL;
1970
1971 if (atl2_check_eeprom_exist(hw))
1972 return -EINVAL;
1973
1974 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1975
1976 first_dword = eeprom->offset >> 2;
1977 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1978
1979 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1980 GFP_KERNEL);
1981 if (!eeprom_buff)
1982 return -ENOMEM;
1983
1984 for (i = first_dword; i < last_dword; i++) {
1985 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1986 return -EIO;
1987 }
1988
1989 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1990 eeprom->len);
1991 kfree(eeprom_buff);
1992
1993 return ret_val;
1994}
1995
1996static int atl2_set_eeprom(struct net_device *netdev,
1997 struct ethtool_eeprom *eeprom, u8 *bytes)
1998{
1999 struct atl2_adapter *adapter = netdev_priv(netdev);
2000 struct atl2_hw *hw = &adapter->hw;
2001 u32 *eeprom_buff;
2002 u32 *ptr;
2003 int max_len, first_dword, last_dword, ret_val = 0;
2004 int i;
2005
2006 if (eeprom->len == 0)
2007 return -EOPNOTSUPP;
2008
2009 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2010 return -EFAULT;
2011
2012 max_len = 512;
2013
2014 first_dword = eeprom->offset >> 2;
2015 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2016 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2017 if (!eeprom_buff)
2018 return -ENOMEM;
2019
2020 ptr = (u32 *)eeprom_buff;
2021
2022 if (eeprom->offset & 3) {
2023 /* need read/modify/write of first changed EEPROM word */
2024 /* only the second byte of the word is being modified */
2025 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2026 return -EIO;
2027 ptr++;
2028 }
2029 if (((eeprom->offset + eeprom->len) & 3)) {
2030 /*
2031 * need read/modify/write of last changed EEPROM word
2032 * only the first byte of the word is being modified
2033 */
2034 if (!atl2_read_eeprom(hw, last_dword * 4,
2035 &(eeprom_buff[last_dword - first_dword])))
2036 return -EIO;
2037 }
2038
2039 /* Device's eeprom is always little-endian, word addressable */
2040 memcpy(ptr, bytes, eeprom->len);
2041
2042 for (i = 0; i < last_dword - first_dword + 1; i++) {
2043 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2044 return -EIO;
2045 }
2046
2047 kfree(eeprom_buff);
2048 return ret_val;
2049}
2050
2051static void atl2_get_drvinfo(struct net_device *netdev,
2052 struct ethtool_drvinfo *drvinfo)
2053{
2054 struct atl2_adapter *adapter = netdev_priv(netdev);
2055
2056 strncpy(drvinfo->driver, atl2_driver_name, 32);
2057 strncpy(drvinfo->version, atl2_driver_version, 32);
2058 strncpy(drvinfo->fw_version, "L2", 32);
2059 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2060 drvinfo->n_stats = 0;
2061 drvinfo->testinfo_len = 0;
2062 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2063 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2064}
2065
2066static void atl2_get_wol(struct net_device *netdev,
2067 struct ethtool_wolinfo *wol)
2068{
2069 struct atl2_adapter *adapter = netdev_priv(netdev);
2070
2071 wol->supported = WAKE_MAGIC;
2072 wol->wolopts = 0;
2073
2074 if (adapter->wol & ATLX_WUFC_EX)
2075 wol->wolopts |= WAKE_UCAST;
2076 if (adapter->wol & ATLX_WUFC_MC)
2077 wol->wolopts |= WAKE_MCAST;
2078 if (adapter->wol & ATLX_WUFC_BC)
2079 wol->wolopts |= WAKE_BCAST;
2080 if (adapter->wol & ATLX_WUFC_MAG)
2081 wol->wolopts |= WAKE_MAGIC;
2082 if (adapter->wol & ATLX_WUFC_LNKC)
2083 wol->wolopts |= WAKE_PHY;
2084}
2085
2086static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2087{
2088 struct atl2_adapter *adapter = netdev_priv(netdev);
2089
2090 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2091 return -EOPNOTSUPP;
2092
2093 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2094 return -EOPNOTSUPP;
2095
2096 /* these settings will always override what we currently have */
2097 adapter->wol = 0;
2098
2099 if (wol->wolopts & WAKE_MAGIC)
2100 adapter->wol |= ATLX_WUFC_MAG;
2101 if (wol->wolopts & WAKE_PHY)
2102 adapter->wol |= ATLX_WUFC_LNKC;
2103
2104 return 0;
2105}
2106
2107static int atl2_nway_reset(struct net_device *netdev)
2108{
2109 struct atl2_adapter *adapter = netdev_priv(netdev);
2110 if (netif_running(netdev))
2111 atl2_reinit_locked(adapter);
2112 return 0;
2113}
2114
2115static struct ethtool_ops atl2_ethtool_ops = {
2116 .get_settings = atl2_get_settings,
2117 .set_settings = atl2_set_settings,
2118 .get_drvinfo = atl2_get_drvinfo,
2119 .get_regs_len = atl2_get_regs_len,
2120 .get_regs = atl2_get_regs,
2121 .get_wol = atl2_get_wol,
2122 .set_wol = atl2_set_wol,
2123 .get_msglevel = atl2_get_msglevel,
2124 .set_msglevel = atl2_set_msglevel,
2125 .nway_reset = atl2_nway_reset,
2126 .get_link = ethtool_op_get_link,
2127 .get_eeprom_len = atl2_get_eeprom_len,
2128 .get_eeprom = atl2_get_eeprom,
2129 .set_eeprom = atl2_set_eeprom,
2130 .get_tx_csum = atl2_get_tx_csum,
2131 .get_sg = ethtool_op_get_sg,
2132 .set_sg = ethtool_op_set_sg,
2133#ifdef NETIF_F_TSO
2134 .get_tso = ethtool_op_get_tso,
2135#endif
2136};
2137
2138static void atl2_set_ethtool_ops(struct net_device *netdev)
2139{
2140 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2141}
2142
2143#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2144 (((a) & 0xff00ff00) >> 8))
2145#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2146#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2147
2148/*
2149 * Reset the transmit and receive units; mask and clear all interrupts.
2150 *
2151 * hw - Struct containing variables accessed by shared code
2152 * return : 0 or idle status (if error)
2153 */
2154static s32 atl2_reset_hw(struct atl2_hw *hw)
2155{
2156 u32 icr;
2157 u16 pci_cfg_cmd_word;
2158 int i;
2159
2160 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2161 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2162 if ((pci_cfg_cmd_word &
2163 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2164 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2165 pci_cfg_cmd_word |=
2166 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2167 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2168 }
2169
2170 /* Clear Interrupt mask to stop board from generating
2171 * interrupts & Clear any pending interrupt events
2172 */
2173 /* FIXME */
2174 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2175 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2176
2177 /* Issue Soft Reset to the MAC. This will reset the chip's
2178 * transmit, receive, DMA. It will not effect
2179 * the current PCI configuration. The global reset bit is self-
2180 * clearing, and should clear within a microsecond.
2181 */
2182 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2183 wmb();
2184 msleep(1); /* delay about 1ms */
2185
2186 /* Wait at least 10ms for All module to be Idle */
2187 for (i = 0; i < 10; i++) {
2188 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2189 if (!icr)
2190 break;
2191 msleep(1); /* delay 1 ms */
2192 cpu_relax();
2193 }
2194
2195 if (icr)
2196 return icr;
2197
2198 return 0;
2199}
2200
2201#define CUSTOM_SPI_CS_SETUP 2
2202#define CUSTOM_SPI_CLK_HI 2
2203#define CUSTOM_SPI_CLK_LO 2
2204#define CUSTOM_SPI_CS_HOLD 2
2205#define CUSTOM_SPI_CS_HI 3
2206
2207static struct atl2_spi_flash_dev flash_table[] =
2208{
2209/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2210{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2211{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2212{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2213};
2214
2215static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2216{
2217 int i;
2218 u32 value;
2219
2220 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2221 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2222
2223 value = SPI_FLASH_CTRL_WAIT_READY |
2224 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2225 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2226 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2227 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2228 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2229 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2230 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2231 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2232 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2233 SPI_FLASH_CTRL_CS_HI_SHIFT |
2234 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2235
2236 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2237
2238 value |= SPI_FLASH_CTRL_START;
2239
2240 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2241
2242 for (i = 0; i < 10; i++) {
2243 msleep(1);
2244 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2245 if (!(value & SPI_FLASH_CTRL_START))
2246 break;
2247 }
2248
2249 if (value & SPI_FLASH_CTRL_START)
2250 return false;
2251
2252 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2253
2254 return true;
2255}
2256
2257/*
2258 * get_permanent_address
2259 * return 0 if get valid mac address,
2260 */
2261static int get_permanent_address(struct atl2_hw *hw)
2262{
2263 u32 Addr[2];
2264 u32 i, Control;
2265 u16 Register;
2266 u8 EthAddr[NODE_ADDRESS_SIZE];
2267 bool KeyValid;
2268
2269 if (is_valid_ether_addr(hw->perm_mac_addr))
2270 return 0;
2271
2272 Addr[0] = 0;
2273 Addr[1] = 0;
2274
2275 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2276 Register = 0;
2277 KeyValid = false;
2278
2279 /* Read out all EEPROM content */
2280 i = 0;
2281 while (1) {
2282 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2283 if (KeyValid) {
2284 if (Register == REG_MAC_STA_ADDR)
2285 Addr[0] = Control;
2286 else if (Register ==
2287 (REG_MAC_STA_ADDR + 4))
2288 Addr[1] = Control;
2289 KeyValid = false;
2290 } else if ((Control & 0xff) == 0x5A) {
2291 KeyValid = true;
2292 Register = (u16) (Control >> 16);
2293 } else {
2294 /* assume data end while encount an invalid KEYWORD */
2295 break;
2296 }
2297 } else {
2298 break; /* read error */
2299 }
2300 i += 4;
2301 }
2302
2303 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2304 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2305
2306 if (is_valid_ether_addr(EthAddr)) {
2307 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2308 return 0;
2309 }
2310 return 1;
2311 }
2312
2313 /* see if SPI flash exists? */
2314 Addr[0] = 0;
2315 Addr[1] = 0;
2316 Register = 0;
2317 KeyValid = false;
2318 i = 0;
2319 while (1) {
2320 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2321 if (KeyValid) {
2322 if (Register == REG_MAC_STA_ADDR)
2323 Addr[0] = Control;
2324 else if (Register == (REG_MAC_STA_ADDR + 4))
2325 Addr[1] = Control;
2326 KeyValid = false;
2327 } else if ((Control & 0xff) == 0x5A) {
2328 KeyValid = true;
2329 Register = (u16) (Control >> 16);
2330 } else {
2331 break; /* data end */
2332 }
2333 } else {
2334 break; /* read error */
2335 }
2336 i += 4;
2337 }
2338
2339 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2340 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2341 if (is_valid_ether_addr(EthAddr)) {
2342 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2343 return 0;
2344 }
2345 /* maybe MAC-address is from BIOS */
2346 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2347 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2348 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2349 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2350
2351 if (is_valid_ether_addr(EthAddr)) {
2352 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2353 return 0;
2354 }
2355
2356 return 1;
2357}
2358
2359/*
2360 * Reads the adapter's MAC address from the EEPROM
2361 *
2362 * hw - Struct containing variables accessed by shared code
2363 */
2364static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2365{
2366 u16 i;
2367
2368 if (get_permanent_address(hw)) {
2369 /* for test */
2370 /* FIXME: shouldn't we use random_ether_addr() here? */
2371 hw->perm_mac_addr[0] = 0x00;
2372 hw->perm_mac_addr[1] = 0x13;
2373 hw->perm_mac_addr[2] = 0x74;
2374 hw->perm_mac_addr[3] = 0x00;
2375 hw->perm_mac_addr[4] = 0x5c;
2376 hw->perm_mac_addr[5] = 0x38;
2377 }
2378
2379 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2380 hw->mac_addr[i] = hw->perm_mac_addr[i];
2381
2382 return 0;
2383}
2384
2385/*
2386 * Hashes an address to determine its location in the multicast table
2387 *
2388 * hw - Struct containing variables accessed by shared code
2389 * mc_addr - the multicast address to hash
2390 *
2391 * atl2_hash_mc_addr
2392 * purpose
2393 * set hash value for a multicast address
2394 * hash calcu processing :
2395 * 1. calcu 32bit CRC for multicast address
2396 * 2. reverse crc with MSB to LSB
2397 */
2398static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2399{
2400 u32 crc32, value;
2401 int i;
2402
2403 value = 0;
2404 crc32 = ether_crc_le(6, mc_addr);
2405
2406 for (i = 0; i < 32; i++)
2407 value |= (((crc32 >> i) & 1) << (31 - i));
2408
2409 return value;
2410}
2411
2412/*
2413 * Sets the bit in the multicast table corresponding to the hash value.
2414 *
2415 * hw - Struct containing variables accessed by shared code
2416 * hash_value - Multicast address hash value
2417 */
2418static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2419{
2420 u32 hash_bit, hash_reg;
2421 u32 mta;
2422
2423 /* The HASH Table is a register array of 2 32-bit registers.
2424 * It is treated like an array of 64 bits. We want to set
2425 * bit BitArray[hash_value]. So we figure out what register
2426 * the bit is in, read it, OR in the new bit, then write
2427 * back the new value. The register is determined by the
2428 * upper 7 bits of the hash value and the bit within that
2429 * register are determined by the lower 5 bits of the value.
2430 */
2431 hash_reg = (hash_value >> 31) & 0x1;
2432 hash_bit = (hash_value >> 26) & 0x1F;
2433
2434 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2435
2436 mta |= (1 << hash_bit);
2437
2438 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2439}
2440
2441/*
2442 * atl2_init_pcie - init PCIE module
2443 */
2444static void atl2_init_pcie(struct atl2_hw *hw)
2445{
2446 u32 value;
2447 value = LTSSM_TEST_MODE_DEF;
2448 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2449
2450 value = PCIE_DLL_TX_CTRL1_DEF;
2451 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2452}
2453
2454static void atl2_init_flash_opcode(struct atl2_hw *hw)
2455{
2456 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2457 hw->flash_vendor = 0; /* ATMEL */
2458
2459 /* Init OP table */
2460 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2461 flash_table[hw->flash_vendor].cmdPROGRAM);
2462 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2463 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2464 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2465 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2466 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2467 flash_table[hw->flash_vendor].cmdRDID);
2468 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2469 flash_table[hw->flash_vendor].cmdWREN);
2470 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2471 flash_table[hw->flash_vendor].cmdRDSR);
2472 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2473 flash_table[hw->flash_vendor].cmdWRSR);
2474 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2475 flash_table[hw->flash_vendor].cmdREAD);
2476}
2477
2478/********************************************************************
2479* Performs basic configuration of the adapter.
2480*
2481* hw - Struct containing variables accessed by shared code
2482* Assumes that the controller has previously been reset and is in a
2483* post-reset uninitialized state. Initializes multicast table,
2484* and Calls routines to setup link
2485* Leaves the transmit and receive units disabled and uninitialized.
2486********************************************************************/
2487static s32 atl2_init_hw(struct atl2_hw *hw)
2488{
2489 u32 ret_val = 0;
2490
2491 atl2_init_pcie(hw);
2492
2493 /* Zero out the Multicast HASH table */
2494 /* clear the old settings from the multicast hash table */
2495 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2496 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2497
2498 atl2_init_flash_opcode(hw);
2499
2500 ret_val = atl2_phy_init(hw);
2501
2502 return ret_val;
2503}
2504
2505/*
2506 * Detects the current speed and duplex settings of the hardware.
2507 *
2508 * hw - Struct containing variables accessed by shared code
2509 * speed - Speed of the connection
2510 * duplex - Duplex setting of the connection
2511 */
2512static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2513 u16 *duplex)
2514{
2515 s32 ret_val;
2516 u16 phy_data;
2517
2518 /* Read PHY Specific Status Register (17) */
2519 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2520 if (ret_val)
2521 return ret_val;
2522
2523 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2524 return ATLX_ERR_PHY_RES;
2525
2526 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2527 case MII_ATLX_PSSR_100MBS:
2528 *speed = SPEED_100;
2529 break;
2530 case MII_ATLX_PSSR_10MBS:
2531 *speed = SPEED_10;
2532 break;
2533 default:
2534 return ATLX_ERR_PHY_SPEED;
2535 break;
2536 }
2537
2538 if (phy_data & MII_ATLX_PSSR_DPLX)
2539 *duplex = FULL_DUPLEX;
2540 else
2541 *duplex = HALF_DUPLEX;
2542
2543 return 0;
2544}
2545
2546/*
2547 * Reads the value from a PHY register
2548 * hw - Struct containing variables accessed by shared code
2549 * reg_addr - address of the PHY register to read
2550 */
2551static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2552{
2553 u32 val;
2554 int i;
2555
2556 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2557 MDIO_START |
2558 MDIO_SUP_PREAMBLE |
2559 MDIO_RW |
2560 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2561 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2562
2563 wmb();
2564
2565 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2566 udelay(2);
2567 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2568 if (!(val & (MDIO_START | MDIO_BUSY)))
2569 break;
2570 wmb();
2571 }
2572 if (!(val & (MDIO_START | MDIO_BUSY))) {
2573 *phy_data = (u16)val;
2574 return 0;
2575 }
2576
2577 return ATLX_ERR_PHY;
2578}
2579
2580/*
2581 * Writes a value to a PHY register
2582 * hw - Struct containing variables accessed by shared code
2583 * reg_addr - address of the PHY register to write
2584 * data - data to write to the PHY
2585 */
2586static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2587{
2588 int i;
2589 u32 val;
2590
2591 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2592 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2593 MDIO_SUP_PREAMBLE |
2594 MDIO_START |
2595 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2596 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2597
2598 wmb();
2599
2600 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2601 udelay(2);
2602 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2603 if (!(val & (MDIO_START | MDIO_BUSY)))
2604 break;
2605
2606 wmb();
2607 }
2608
2609 if (!(val & (MDIO_START | MDIO_BUSY)))
2610 return 0;
2611
2612 return ATLX_ERR_PHY;
2613}
2614
2615/*
2616 * Configures PHY autoneg and flow control advertisement settings
2617 *
2618 * hw - Struct containing variables accessed by shared code
2619 */
2620static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2621{
2622 s32 ret_val;
2623 s16 mii_autoneg_adv_reg;
2624
2625 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2626 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2627
2628 /* Need to parse autoneg_advertised and set up
2629 * the appropriate PHY registers. First we will parse for
2630 * autoneg_advertised software override. Since we can advertise
2631 * a plethora of combinations, we need to check each bit
2632 * individually.
2633 */
2634
2635 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2636 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2637 * the 1000Base-T Control Register (Address 9). */
2638 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2639
2640 /* Need to parse MediaType and setup the
2641 * appropriate PHY registers. */
2642 switch (hw->MediaType) {
2643 case MEDIA_TYPE_AUTO_SENSOR:
2644 mii_autoneg_adv_reg |=
2645 (MII_AR_10T_HD_CAPS |
2646 MII_AR_10T_FD_CAPS |
2647 MII_AR_100TX_HD_CAPS|
2648 MII_AR_100TX_FD_CAPS);
2649 hw->autoneg_advertised =
2650 ADVERTISE_10_HALF |
2651 ADVERTISE_10_FULL |
2652 ADVERTISE_100_HALF|
2653 ADVERTISE_100_FULL;
2654 break;
2655 case MEDIA_TYPE_100M_FULL:
2656 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2657 hw->autoneg_advertised = ADVERTISE_100_FULL;
2658 break;
2659 case MEDIA_TYPE_100M_HALF:
2660 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2661 hw->autoneg_advertised = ADVERTISE_100_HALF;
2662 break;
2663 case MEDIA_TYPE_10M_FULL:
2664 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2665 hw->autoneg_advertised = ADVERTISE_10_FULL;
2666 break;
2667 default:
2668 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2669 hw->autoneg_advertised = ADVERTISE_10_HALF;
2670 break;
2671 }
2672
2673 /* flow control fixed to enable all */
2674 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2675
2676 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2677
2678 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2679
2680 if (ret_val)
2681 return ret_val;
2682
2683 return 0;
2684}
2685
2686/*
2687 * Resets the PHY and make all config validate
2688 *
2689 * hw - Struct containing variables accessed by shared code
2690 *
2691 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2692 */
2693static s32 atl2_phy_commit(struct atl2_hw *hw)
2694{
2695 s32 ret_val;
2696 u16 phy_data;
2697
2698 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2699 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2700 if (ret_val) {
2701 u32 val;
2702 int i;
2703 /* pcie serdes link may be down ! */
2704 for (i = 0; i < 25; i++) {
2705 msleep(1);
2706 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2707 if (!(val & (MDIO_START | MDIO_BUSY)))
2708 break;
2709 }
2710
2711 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2712 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2713 return ret_val;
2714 }
2715 }
2716 return 0;
2717}
2718
2719static s32 atl2_phy_init(struct atl2_hw *hw)
2720{
2721 s32 ret_val;
2722 u16 phy_val;
2723
2724 if (hw->phy_configured)
2725 return 0;
2726
2727 /* Enable PHY */
2728 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2729 ATL2_WRITE_FLUSH(hw);
2730 msleep(1);
2731
2732 /* check if the PHY is in powersaving mode */
2733 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2734 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2735
2736 /* 024E / 124E 0r 0274 / 1274 ? */
2737 if (phy_val & 0x1000) {
2738 phy_val &= ~0x1000;
2739 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2740 }
2741
2742 msleep(1);
2743
2744 /*Enable PHY LinkChange Interrupt */
2745 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2746 if (ret_val)
2747 return ret_val;
2748
2749 /* setup AutoNeg parameters */
2750 ret_val = atl2_phy_setup_autoneg_adv(hw);
2751 if (ret_val)
2752 return ret_val;
2753
2754 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2755 ret_val = atl2_phy_commit(hw);
2756 if (ret_val)
2757 return ret_val;
2758
2759 hw->phy_configured = true;
2760
2761 return ret_val;
2762}
2763
2764static void atl2_set_mac_addr(struct atl2_hw *hw)
2765{
2766 u32 value;
2767 /* 00-0B-6A-F6-00-DC
2768 * 0: 6AF600DC 1: 000B
2769 * low dword */
2770 value = (((u32)hw->mac_addr[2]) << 24) |
2771 (((u32)hw->mac_addr[3]) << 16) |
2772 (((u32)hw->mac_addr[4]) << 8) |
2773 (((u32)hw->mac_addr[5]));
2774 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2775 /* hight dword */
2776 value = (((u32)hw->mac_addr[0]) << 8) |
2777 (((u32)hw->mac_addr[1]));
2778 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2779}
2780
2781/*
2782 * check_eeprom_exist
2783 * return 0 if eeprom exist
2784 */
2785static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2786{
2787 u32 value;
2788
2789 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2790 if (value & SPI_FLASH_CTRL_EN_VPD) {
2791 value &= ~SPI_FLASH_CTRL_EN_VPD;
2792 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2793 }
2794 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2795 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2796}
2797
2798/* FIXME: This doesn't look right. -- CHS */
2799static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2800{
2801 return true;
2802}
2803
2804static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2805{
2806 int i;
2807 u32 Control;
2808
2809 if (Offset & 0x3)
2810 return false; /* address do not align */
2811
2812 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2813 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2814 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2815
2816 for (i = 0; i < 10; i++) {
2817 msleep(2);
2818 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2819 if (Control & VPD_CAP_VPD_FLAG)
2820 break;
2821 }
2822
2823 if (Control & VPD_CAP_VPD_FLAG) {
2824 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2825 return true;
2826 }
2827 return false; /* timeout */
2828}
2829
2830static void atl2_force_ps(struct atl2_hw *hw)
2831{
2832 u16 phy_val;
2833
2834 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2835 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2836 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2837
2838 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2839 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2840 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2841 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2842}
2843
2844/* This is the only thing that needs to be changed to adjust the
2845 * maximum number of ports that the driver can manage.
2846 */
2847#define ATL2_MAX_NIC 4
2848
2849#define OPTION_UNSET -1
2850#define OPTION_DISABLED 0
2851#define OPTION_ENABLED 1
2852
2853/* All parameters are treated the same, as an integer array of values.
2854 * This macro just reduces the need to repeat the same declaration code
2855 * over and over (plus this helps to avoid typo bugs).
2856 */
2857#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2858#ifndef module_param_array
2859/* Module Parameters are always initialized to -1, so that the driver
2860 * can tell the difference between no user specified value or the
2861 * user asking for the default value.
2862 * The true default values are loaded in when atl2_check_options is called.
2863 *
2864 * This is a GCC extension to ANSI C.
2865 * See the item "Labeled Elements in Initializers" in the section
2866 * "Extensions to the C Language Family" of the GCC documentation.
2867 */
2868
2869#define ATL2_PARAM(X, desc) \
2870 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2871 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2872 MODULE_PARM_DESC(X, desc);
2873#else
2874#define ATL2_PARAM(X, desc) \
2875 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2876 static int num_##X = 0; \
2877 module_param_array_named(X, X, int, &num_##X, 0); \
2878 MODULE_PARM_DESC(X, desc);
2879#endif
2880
2881/*
2882 * Transmit Memory Size
2883 * Valid Range: 64-2048
2884 * Default Value: 128
2885 */
2886#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2887#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2888#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2889ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2890
2891/*
2892 * Receive Memory Block Count
2893 * Valid Range: 16-512
2894 * Default Value: 128
2895 */
2896#define ATL2_MIN_RXD_COUNT 16
2897#define ATL2_MAX_RXD_COUNT 512
2898#define ATL2_DEFAULT_RXD_COUNT 64
2899ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2900
2901/*
2902 * User Specified MediaType Override
2903 *
2904 * Valid Range: 0-5
2905 * - 0 - auto-negotiate at all supported speeds
2906 * - 1 - only link at 1000Mbps Full Duplex
2907 * - 2 - only link at 100Mbps Full Duplex
2908 * - 3 - only link at 100Mbps Half Duplex
2909 * - 4 - only link at 10Mbps Full Duplex
2910 * - 5 - only link at 10Mbps Half Duplex
2911 * Default Value: 0
2912 */
2913ATL2_PARAM(MediaType, "MediaType Select");
2914
2915/*
2916 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2917 * Valid Range: 10-65535
2918 * Default Value: 45000(90ms)
2919 */
2920#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2921#define INT_MOD_MAX_CNT 65000
2922#define INT_MOD_MIN_CNT 50
2923ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2924
2925/*
2926 * FlashVendor
2927 * Valid Range: 0-2
2928 * 0 - Atmel
2929 * 1 - SST
2930 * 2 - ST
2931 */
2932ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2933
2934#define AUTONEG_ADV_DEFAULT 0x2F
2935#define AUTONEG_ADV_MASK 0x2F
2936#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2937
2938#define FLASH_VENDOR_DEFAULT 0
2939#define FLASH_VENDOR_MIN 0
2940#define FLASH_VENDOR_MAX 2
2941
2942struct atl2_option {
2943 enum { enable_option, range_option, list_option } type;
2944 char *name;
2945 char *err;
2946 int def;
2947 union {
2948 struct { /* range_option info */
2949 int min;
2950 int max;
2951 } r;
2952 struct { /* list_option info */
2953 int nr;
2954 struct atl2_opt_list { int i; char *str; } *p;
2955 } l;
2956 } arg;
2957};
2958
2959static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2960{
2961 int i;
2962 struct atl2_opt_list *ent;
2963
2964 if (*value == OPTION_UNSET) {
2965 *value = opt->def;
2966 return 0;
2967 }
2968
2969 switch (opt->type) {
2970 case enable_option:
2971 switch (*value) {
2972 case OPTION_ENABLED:
2973 printk(KERN_INFO "%s Enabled\n", opt->name);
2974 return 0;
2975 break;
2976 case OPTION_DISABLED:
2977 printk(KERN_INFO "%s Disabled\n", opt->name);
2978 return 0;
2979 break;
2980 }
2981 break;
2982 case range_option:
2983 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2984 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2985 return 0;
2986 }
2987 break;
2988 case list_option:
2989 for (i = 0; i < opt->arg.l.nr; i++) {
2990 ent = &opt->arg.l.p[i];
2991 if (*value == ent->i) {
2992 if (ent->str[0] != '\0')
2993 printk(KERN_INFO "%s\n", ent->str);
2994 return 0;
2995 }
2996 }
2997 break;
2998 default:
2999 BUG();
3000 }
3001
3002 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
3003 opt->name, *value, opt->err);
3004 *value = opt->def;
3005 return -1;
3006}
3007
3008/*
3009 * atl2_check_options - Range Checking for Command Line Parameters
3010 * @adapter: board private structure
3011 *
3012 * This routine checks all command line parameters for valid user
3013 * input. If an invalid value is given, or if no user specified
3014 * value exists, a default value is used. The final value is stored
3015 * in a variable in the adapter structure.
3016 */
3017static void __devinit atl2_check_options(struct atl2_adapter *adapter)
3018{
3019 int val;
3020 struct atl2_option opt;
3021 int bd = adapter->bd_number;
3022 if (bd >= ATL2_MAX_NIC) {
3023 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3024 bd);
3025 printk(KERN_NOTICE "Using defaults for all values\n");
3026#ifndef module_param_array
3027 bd = ATL2_MAX_NIC;
3028#endif
3029 }
3030
3031 /* Bytes of Transmit Memory */
3032 opt.type = range_option;
3033 opt.name = "Bytes of Transmit Memory";
3034 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3035 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3036 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3037 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3038#ifdef module_param_array
3039 if (num_TxMemSize > bd) {
3040#endif
3041 val = TxMemSize[bd];
3042 atl2_validate_option(&val, &opt);
3043 adapter->txd_ring_size = ((u32) val) * 1024;
3044#ifdef module_param_array
3045 } else
3046 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3047#endif
3048 /* txs ring size: */
3049 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3050 if (adapter->txs_ring_size > 160)
3051 adapter->txs_ring_size = 160;
3052
3053 /* Receive Memory Block Count */
3054 opt.type = range_option;
3055 opt.name = "Number of receive memory block";
3056 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3057 opt.def = ATL2_DEFAULT_RXD_COUNT;
3058 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3059 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3060#ifdef module_param_array
3061 if (num_RxMemBlock > bd) {
3062#endif
3063 val = RxMemBlock[bd];
3064 atl2_validate_option(&val, &opt);
3065 adapter->rxd_ring_size = (u32)val;
3066 /* FIXME */
3067 /* ((u16)val)&~1; */ /* even number */
3068#ifdef module_param_array
3069 } else
3070 adapter->rxd_ring_size = (u32)opt.def;
3071#endif
3072 /* init RXD Flow control value */
3073 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3074 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3075 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3076 (adapter->rxd_ring_size / 12);
3077
3078 /* Interrupt Moderate Timer */
3079 opt.type = range_option;
3080 opt.name = "Interrupt Moderate Timer";
3081 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3082 opt.def = INT_MOD_DEFAULT_CNT;
3083 opt.arg.r.min = INT_MOD_MIN_CNT;
3084 opt.arg.r.max = INT_MOD_MAX_CNT;
3085#ifdef module_param_array
3086 if (num_IntModTimer > bd) {
3087#endif
3088 val = IntModTimer[bd];
3089 atl2_validate_option(&val, &opt);
3090 adapter->imt = (u16) val;
3091#ifdef module_param_array
3092 } else
3093 adapter->imt = (u16)(opt.def);
3094#endif
3095 /* Flash Vendor */
3096 opt.type = range_option;
3097 opt.name = "SPI Flash Vendor";
3098 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3099 opt.def = FLASH_VENDOR_DEFAULT;
3100 opt.arg.r.min = FLASH_VENDOR_MIN;
3101 opt.arg.r.max = FLASH_VENDOR_MAX;
3102#ifdef module_param_array
3103 if (num_FlashVendor > bd) {
3104#endif
3105 val = FlashVendor[bd];
3106 atl2_validate_option(&val, &opt);
3107 adapter->hw.flash_vendor = (u8) val;
3108#ifdef module_param_array
3109 } else
3110 adapter->hw.flash_vendor = (u8)(opt.def);
3111#endif
3112 /* MediaType */
3113 opt.type = range_option;
3114 opt.name = "Speed/Duplex Selection";
3115 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3116 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3117 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3118 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3119#ifdef module_param_array
3120 if (num_MediaType > bd) {
3121#endif
3122 val = MediaType[bd];
3123 atl2_validate_option(&val, &opt);
3124 adapter->hw.MediaType = (u16) val;
3125#ifdef module_param_array
3126 } else
3127 adapter->hw.MediaType = (u16)(opt.def);
3128#endif
3129}
Linux 6.x block layer and io_uring tree(s)