Commit | Line | Data |
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a6a53252 JY |
1 | /* |
2 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. | |
3 | * | |
4 | * Derived from Intel e1000 driver | |
5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the Free | |
9 | * Software Foundation; either version 2 of the License, or (at your option) | |
10 | * any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | #include <linux/pci.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/mii.h> | |
24 | #include <linux/crc32.h> | |
25 | ||
26 | #include "atl1e.h" | |
27 | ||
28 | /* | |
29 | * check_eeprom_exist | |
30 | * return 0 if eeprom exist | |
31 | */ | |
32 | int atl1e_check_eeprom_exist(struct atl1e_hw *hw) | |
33 | { | |
34 | u32 value; | |
35 | ||
36 | value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
37 | if (value & SPI_FLASH_CTRL_EN_VPD) { | |
38 | value &= ~SPI_FLASH_CTRL_EN_VPD; | |
39 | AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
40 | } | |
41 | value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST); | |
42 | return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | |
43 | } | |
44 | ||
45 | void atl1e_hw_set_mac_addr(struct atl1e_hw *hw) | |
46 | { | |
47 | u32 value; | |
48 | /* | |
49 | * 00-0B-6A-F6-00-DC | |
50 | * 0: 6AF600DC 1: 000B | |
51 | * low dword | |
52 | */ | |
53 | value = (((u32)hw->mac_addr[2]) << 24) | | |
54 | (((u32)hw->mac_addr[3]) << 16) | | |
55 | (((u32)hw->mac_addr[4]) << 8) | | |
56 | (((u32)hw->mac_addr[5])) ; | |
57 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); | |
58 | /* hight dword */ | |
59 | value = (((u32)hw->mac_addr[0]) << 8) | | |
60 | (((u32)hw->mac_addr[1])) ; | |
61 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); | |
62 | } | |
63 | ||
64 | /* | |
65 | * atl1e_get_permanent_address | |
66 | * return 0 if get valid mac address, | |
67 | */ | |
68 | static int atl1e_get_permanent_address(struct atl1e_hw *hw) | |
69 | { | |
70 | u32 addr[2]; | |
71 | u32 i; | |
72 | u32 twsi_ctrl_data; | |
73 | u8 eth_addr[ETH_ALEN]; | |
74 | ||
75 | if (is_valid_ether_addr(hw->perm_mac_addr)) | |
76 | return 0; | |
77 | ||
78 | /* init */ | |
79 | addr[0] = addr[1] = 0; | |
80 | ||
81 | if (!atl1e_check_eeprom_exist(hw)) { | |
82 | /* eeprom exist */ | |
83 | twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); | |
84 | twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; | |
85 | AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); | |
86 | for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { | |
87 | msleep(10); | |
88 | twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); | |
89 | if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) | |
90 | break; | |
91 | } | |
92 | if (i >= AT_TWSI_EEPROM_TIMEOUT) | |
93 | return AT_ERR_TIMEOUT; | |
94 | } | |
95 | ||
96 | /* maybe MAC-address is from BIOS */ | |
97 | addr[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR); | |
98 | addr[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4); | |
99 | *(u32 *) ð_addr[2] = swab32(addr[0]); | |
100 | *(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]); | |
101 | ||
102 | if (is_valid_ether_addr(eth_addr)) { | |
103 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
104 | return 0; | |
105 | } | |
106 | ||
107 | return AT_ERR_EEPROM; | |
108 | } | |
109 | ||
110 | bool atl1e_write_eeprom(struct atl1e_hw *hw, u32 offset, u32 value) | |
111 | { | |
112 | return true; | |
113 | } | |
114 | ||
115 | bool atl1e_read_eeprom(struct atl1e_hw *hw, u32 offset, u32 *p_value) | |
116 | { | |
117 | int i; | |
118 | u32 control; | |
119 | ||
120 | if (offset & 3) | |
121 | return false; /* address do not align */ | |
122 | ||
123 | AT_WRITE_REG(hw, REG_VPD_DATA, 0); | |
124 | control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | |
125 | AT_WRITE_REG(hw, REG_VPD_CAP, control); | |
126 | ||
127 | for (i = 0; i < 10; i++) { | |
128 | msleep(2); | |
129 | control = AT_READ_REG(hw, REG_VPD_CAP); | |
130 | if (control & VPD_CAP_VPD_FLAG) | |
131 | break; | |
132 | } | |
133 | if (control & VPD_CAP_VPD_FLAG) { | |
134 | *p_value = AT_READ_REG(hw, REG_VPD_DATA); | |
135 | return true; | |
136 | } | |
137 | return false; /* timeout */ | |
138 | } | |
139 | ||
140 | void atl1e_force_ps(struct atl1e_hw *hw) | |
141 | { | |
142 | AT_WRITE_REGW(hw, REG_GPHY_CTRL, | |
143 | GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET); | |
144 | } | |
145 | ||
146 | /* | |
147 | * Reads the adapter's MAC address from the EEPROM | |
148 | * | |
149 | * hw - Struct containing variables accessed by shared code | |
150 | */ | |
151 | int atl1e_read_mac_addr(struct atl1e_hw *hw) | |
152 | { | |
153 | int err = 0; | |
154 | ||
155 | err = atl1e_get_permanent_address(hw); | |
156 | if (err) | |
157 | return AT_ERR_EEPROM; | |
158 | memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); | |
159 | return 0; | |
160 | } | |
161 | ||
162 | /* | |
163 | * atl1e_hash_mc_addr | |
164 | * purpose | |
165 | * set hash value for a multicast address | |
a6a53252 JY |
166 | */ |
167 | u32 atl1e_hash_mc_addr(struct atl1e_hw *hw, u8 *mc_addr) | |
168 | { | |
169 | u32 crc32; | |
170 | u32 value = 0; | |
171 | int i; | |
172 | ||
173 | crc32 = ether_crc_le(6, mc_addr); | |
a6a53252 JY |
174 | for (i = 0; i < 32; i++) |
175 | value |= (((crc32 >> i) & 1) << (31 - i)); | |
176 | ||
177 | return value; | |
178 | } | |
179 | ||
180 | /* | |
181 | * Sets the bit in the multicast table corresponding to the hash value. | |
182 | * hw - Struct containing variables accessed by shared code | |
183 | * hash_value - Multicast address hash value | |
184 | */ | |
185 | void atl1e_hash_set(struct atl1e_hw *hw, u32 hash_value) | |
186 | { | |
187 | u32 hash_bit, hash_reg; | |
188 | u32 mta; | |
189 | ||
190 | /* | |
191 | * The HASH Table is a register array of 2 32-bit registers. | |
192 | * It is treated like an array of 64 bits. We want to set | |
193 | * bit BitArray[hash_value]. So we figure out what register | |
194 | * the bit is in, read it, OR in the new bit, then write | |
195 | * back the new value. The register is determined by the | |
196 | * upper 7 bits of the hash value and the bit within that | |
197 | * register are determined by the lower 5 bits of the value. | |
198 | */ | |
199 | hash_reg = (hash_value >> 31) & 0x1; | |
200 | hash_bit = (hash_value >> 26) & 0x1F; | |
201 | ||
202 | mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); | |
203 | ||
204 | mta |= (1 << hash_bit); | |
205 | ||
206 | AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); | |
207 | } | |
208 | /* | |
209 | * Reads the value from a PHY register | |
210 | * hw - Struct containing variables accessed by shared code | |
211 | * reg_addr - address of the PHY register to read | |
212 | */ | |
213 | int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data) | |
214 | { | |
215 | u32 val; | |
216 | int i; | |
217 | ||
218 | val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | | |
219 | MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | | |
220 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
221 | ||
222 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
223 | ||
224 | wmb(); | |
225 | ||
226 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
227 | udelay(2); | |
228 | val = AT_READ_REG(hw, REG_MDIO_CTRL); | |
229 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
230 | break; | |
231 | wmb(); | |
232 | } | |
233 | if (!(val & (MDIO_START | MDIO_BUSY))) { | |
234 | *phy_data = (u16)val; | |
235 | return 0; | |
236 | } | |
237 | ||
238 | return AT_ERR_PHY; | |
239 | } | |
240 | ||
241 | /* | |
242 | * Writes a value to a PHY register | |
243 | * hw - Struct containing variables accessed by shared code | |
244 | * reg_addr - address of the PHY register to write | |
245 | * data - data to write to the PHY | |
246 | */ | |
247 | int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data) | |
248 | { | |
249 | int i; | |
250 | u32 val; | |
251 | ||
252 | val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | | |
253 | (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | |
254 | MDIO_SUP_PREAMBLE | | |
255 | MDIO_START | | |
256 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
257 | ||
258 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
259 | wmb(); | |
260 | ||
261 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
262 | udelay(2); | |
263 | val = AT_READ_REG(hw, REG_MDIO_CTRL); | |
264 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
265 | break; | |
266 | wmb(); | |
267 | } | |
268 | ||
269 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
270 | return 0; | |
271 | ||
272 | return AT_ERR_PHY; | |
273 | } | |
274 | ||
275 | /* | |
276 | * atl1e_init_pcie - init PCIE module | |
277 | */ | |
278 | static void atl1e_init_pcie(struct atl1e_hw *hw) | |
279 | { | |
280 | u32 value; | |
281 | /* comment 2lines below to save more power when sususpend | |
282 | value = LTSSM_TEST_MODE_DEF; | |
283 | AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); | |
284 | */ | |
285 | ||
286 | /* pcie flow control mode change */ | |
287 | value = AT_READ_REG(hw, 0x1008); | |
288 | value |= 0x8000; | |
289 | AT_WRITE_REG(hw, 0x1008, value); | |
290 | } | |
291 | /* | |
292 | * Configures PHY autoneg and flow control advertisement settings | |
293 | * | |
294 | * hw - Struct containing variables accessed by shared code | |
295 | */ | |
296 | static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw) | |
297 | { | |
298 | s32 ret_val; | |
299 | u16 mii_autoneg_adv_reg; | |
300 | u16 mii_1000t_ctrl_reg; | |
301 | ||
302 | if (0 != hw->mii_autoneg_adv_reg) | |
303 | return 0; | |
304 | /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */ | |
305 | mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | |
306 | mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK; | |
307 | ||
308 | /* | |
309 | * Need to parse autoneg_advertised and set up | |
310 | * the appropriate PHY registers. First we will parse for | |
311 | * autoneg_advertised software override. Since we can advertise | |
312 | * a plethora of combinations, we need to check each bit | |
313 | * individually. | |
314 | */ | |
315 | ||
316 | /* | |
317 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
318 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
319 | * the 1000Base-T control Register (Address 9). | |
320 | */ | |
321 | mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | |
322 | mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK; | |
323 | ||
324 | /* | |
325 | * Need to parse MediaType and setup the | |
326 | * appropriate PHY registers. | |
327 | */ | |
328 | switch (hw->media_type) { | |
329 | case MEDIA_TYPE_AUTO_SENSOR: | |
330 | mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | | |
331 | MII_AR_10T_FD_CAPS | | |
332 | MII_AR_100TX_HD_CAPS | | |
333 | MII_AR_100TX_FD_CAPS); | |
334 | hw->autoneg_advertised = ADVERTISE_10_HALF | | |
335 | ADVERTISE_10_FULL | | |
336 | ADVERTISE_100_HALF | | |
337 | ADVERTISE_100_FULL; | |
338 | if (hw->nic_type == athr_l1e) { | |
339 | mii_1000t_ctrl_reg |= | |
340 | MII_AT001_CR_1000T_FD_CAPS; | |
341 | hw->autoneg_advertised |= ADVERTISE_1000_FULL; | |
342 | } | |
343 | break; | |
344 | ||
345 | case MEDIA_TYPE_100M_FULL: | |
346 | mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | |
347 | hw->autoneg_advertised = ADVERTISE_100_FULL; | |
348 | break; | |
349 | ||
350 | case MEDIA_TYPE_100M_HALF: | |
351 | mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | |
352 | hw->autoneg_advertised = ADVERTISE_100_HALF; | |
353 | break; | |
354 | ||
355 | case MEDIA_TYPE_10M_FULL: | |
356 | mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | |
357 | hw->autoneg_advertised = ADVERTISE_10_FULL; | |
358 | break; | |
359 | ||
360 | default: | |
361 | mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; | |
362 | hw->autoneg_advertised = ADVERTISE_10_HALF; | |
363 | break; | |
364 | } | |
365 | ||
366 | /* flow control fixed to enable all */ | |
367 | mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | |
368 | ||
369 | hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; | |
370 | hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; | |
371 | ||
372 | ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); | |
373 | if (ret_val) | |
374 | return ret_val; | |
375 | ||
376 | if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { | |
377 | ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR, | |
378 | mii_1000t_ctrl_reg); | |
379 | if (ret_val) | |
380 | return ret_val; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | ||
387 | /* | |
388 | * Resets the PHY and make all config validate | |
389 | * | |
390 | * hw - Struct containing variables accessed by shared code | |
391 | * | |
392 | * Sets bit 15 and 12 of the MII control regiser (for F001 bug) | |
393 | */ | |
394 | int atl1e_phy_commit(struct atl1e_hw *hw) | |
395 | { | |
a4e77d06 | 396 | struct atl1e_adapter *adapter = hw->adapter; |
a6a53252 JY |
397 | struct pci_dev *pdev = adapter->pdev; |
398 | int ret_val; | |
399 | u16 phy_data; | |
400 | ||
401 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; | |
402 | ||
403 | ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); | |
404 | if (ret_val) { | |
405 | u32 val; | |
406 | int i; | |
407 | /************************************** | |
408 | * pcie serdes link may be down ! | |
409 | **************************************/ | |
410 | for (i = 0; i < 25; i++) { | |
411 | msleep(1); | |
412 | val = AT_READ_REG(hw, REG_MDIO_CTRL); | |
413 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
414 | break; | |
415 | } | |
416 | ||
417 | if (0 != (val & (MDIO_START | MDIO_BUSY))) { | |
418 | dev_err(&pdev->dev, | |
419 | "pcie linkdown at least for 25ms\n"); | |
420 | return ret_val; | |
421 | } | |
422 | ||
423 | dev_err(&pdev->dev, "pcie linkup after %d ms\n", i); | |
424 | } | |
425 | return 0; | |
426 | } | |
427 | ||
428 | int atl1e_phy_init(struct atl1e_hw *hw) | |
429 | { | |
a4e77d06 | 430 | struct atl1e_adapter *adapter = hw->adapter; |
a6a53252 JY |
431 | struct pci_dev *pdev = adapter->pdev; |
432 | s32 ret_val; | |
433 | u16 phy_val; | |
434 | ||
435 | if (hw->phy_configured) { | |
436 | if (hw->re_autoneg) { | |
437 | hw->re_autoneg = false; | |
438 | return atl1e_restart_autoneg(hw); | |
439 | } | |
440 | return 0; | |
441 | } | |
442 | ||
443 | /* RESET GPHY Core */ | |
444 | AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); | |
445 | msleep(2); | |
446 | AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT | | |
447 | GPHY_CTRL_EXT_RESET); | |
448 | msleep(2); | |
449 | ||
450 | /* patches */ | |
451 | /* p1. eable hibernation mode */ | |
452 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB); | |
453 | if (ret_val) | |
454 | return ret_val; | |
455 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00); | |
456 | if (ret_val) | |
457 | return ret_val; | |
458 | /* p2. set Class A/B for all modes */ | |
459 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0); | |
460 | if (ret_val) | |
461 | return ret_val; | |
462 | phy_val = 0x02ef; | |
463 | /* remove Class AB */ | |
464 | /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */ | |
465 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val); | |
466 | if (ret_val) | |
467 | return ret_val; | |
468 | /* p3. 10B ??? */ | |
469 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12); | |
470 | if (ret_val) | |
471 | return ret_val; | |
472 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04); | |
473 | if (ret_val) | |
474 | return ret_val; | |
475 | /* p4. 1000T power */ | |
476 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4); | |
477 | if (ret_val) | |
478 | return ret_val; | |
479 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB); | |
480 | if (ret_val) | |
481 | return ret_val; | |
482 | ||
483 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5); | |
484 | if (ret_val) | |
485 | return ret_val; | |
486 | ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46); | |
487 | if (ret_val) | |
488 | return ret_val; | |
489 | ||
490 | msleep(1); | |
491 | ||
492 | /*Enable PHY LinkChange Interrupt */ | |
493 | ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00); | |
494 | if (ret_val) { | |
495 | dev_err(&pdev->dev, "Error enable PHY linkChange Interrupt\n"); | |
496 | return ret_val; | |
497 | } | |
498 | /* setup AutoNeg parameters */ | |
499 | ret_val = atl1e_phy_setup_autoneg_adv(hw); | |
500 | if (ret_val) { | |
501 | dev_err(&pdev->dev, "Error Setting up Auto-Negotiation\n"); | |
502 | return ret_val; | |
503 | } | |
504 | /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/ | |
505 | dev_dbg(&pdev->dev, "Restarting Auto-Neg"); | |
506 | ret_val = atl1e_phy_commit(hw); | |
507 | if (ret_val) { | |
508 | dev_err(&pdev->dev, "Error Resetting the phy"); | |
509 | return ret_val; | |
510 | } | |
511 | ||
512 | hw->phy_configured = true; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | /* | |
518 | * Reset the transmit and receive units; mask and clear all interrupts. | |
519 | * hw - Struct containing variables accessed by shared code | |
520 | * return : 0 or idle status (if error) | |
521 | */ | |
522 | int atl1e_reset_hw(struct atl1e_hw *hw) | |
523 | { | |
a4e77d06 | 524 | struct atl1e_adapter *adapter = hw->adapter; |
a6a53252 JY |
525 | struct pci_dev *pdev = adapter->pdev; |
526 | ||
527 | u32 idle_status_data = 0; | |
528 | u16 pci_cfg_cmd_word = 0; | |
529 | int timeout = 0; | |
530 | ||
531 | /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ | |
532 | pci_read_config_word(pdev, PCI_REG_COMMAND, &pci_cfg_cmd_word); | |
533 | if ((pci_cfg_cmd_word & (CMD_IO_SPACE | | |
534 | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) | |
535 | != (CMD_IO_SPACE | CMD_MEMORY_SPACE | CMD_BUS_MASTER)) { | |
536 | pci_cfg_cmd_word |= (CMD_IO_SPACE | | |
537 | CMD_MEMORY_SPACE | CMD_BUS_MASTER); | |
538 | pci_write_config_word(pdev, PCI_REG_COMMAND, pci_cfg_cmd_word); | |
539 | } | |
540 | ||
541 | /* | |
542 | * Issue Soft Reset to the MAC. This will reset the chip's | |
543 | * transmit, receive, DMA. It will not effect | |
544 | * the current PCI configuration. The global reset bit is self- | |
545 | * clearing, and should clear within a microsecond. | |
546 | */ | |
547 | AT_WRITE_REG(hw, REG_MASTER_CTRL, | |
548 | MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST); | |
549 | wmb(); | |
550 | msleep(1); | |
551 | ||
552 | /* Wait at least 10ms for All module to be Idle */ | |
553 | for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { | |
554 | idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS); | |
555 | if (idle_status_data == 0) | |
556 | break; | |
557 | msleep(1); | |
558 | cpu_relax(); | |
559 | } | |
560 | ||
561 | if (timeout >= AT_HW_MAX_IDLE_DELAY) { | |
562 | dev_err(&pdev->dev, | |
563 | "MAC state machine cann't be idle since" | |
564 | " disabled for 10ms second\n"); | |
565 | return AT_ERR_TIMEOUT; | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | ||
572 | /* | |
573 | * Performs basic configuration of the adapter. | |
574 | * | |
575 | * hw - Struct containing variables accessed by shared code | |
576 | * Assumes that the controller has previously been reset and is in a | |
577 | * post-reset uninitialized state. Initializes multicast table, | |
578 | * and Calls routines to setup link | |
579 | * Leaves the transmit and receive units disabled and uninitialized. | |
580 | */ | |
581 | int atl1e_init_hw(struct atl1e_hw *hw) | |
582 | { | |
583 | s32 ret_val = 0; | |
584 | ||
585 | atl1e_init_pcie(hw); | |
586 | ||
587 | /* Zero out the Multicast HASH table */ | |
588 | /* clear the old settings from the multicast hash table */ | |
589 | AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | |
590 | AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | |
591 | ||
592 | ret_val = atl1e_phy_init(hw); | |
593 | ||
594 | return ret_val; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Detects the current speed and duplex settings of the hardware. | |
599 | * | |
600 | * hw - Struct containing variables accessed by shared code | |
601 | * speed - Speed of the connection | |
602 | * duplex - Duplex setting of the connection | |
603 | */ | |
604 | int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex) | |
605 | { | |
606 | int err; | |
607 | u16 phy_data; | |
608 | ||
609 | /* Read PHY Specific Status Register (17) */ | |
610 | err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); | |
611 | if (err) | |
612 | return err; | |
613 | ||
614 | if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) | |
615 | return AT_ERR_PHY_RES; | |
616 | ||
617 | switch (phy_data & MII_AT001_PSSR_SPEED) { | |
618 | case MII_AT001_PSSR_1000MBS: | |
619 | *speed = SPEED_1000; | |
620 | break; | |
621 | case MII_AT001_PSSR_100MBS: | |
622 | *speed = SPEED_100; | |
623 | break; | |
624 | case MII_AT001_PSSR_10MBS: | |
625 | *speed = SPEED_10; | |
626 | break; | |
627 | default: | |
628 | return AT_ERR_PHY_SPEED; | |
629 | break; | |
630 | } | |
631 | ||
632 | if (phy_data & MII_AT001_PSSR_DPLX) | |
633 | *duplex = FULL_DUPLEX; | |
634 | else | |
635 | *duplex = HALF_DUPLEX; | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | int atl1e_restart_autoneg(struct atl1e_hw *hw) | |
641 | { | |
642 | int err = 0; | |
643 | ||
644 | err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | |
645 | if (err) | |
646 | return err; | |
647 | ||
648 | if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { | |
649 | err = atl1e_write_phy_reg(hw, MII_AT001_CR, | |
650 | hw->mii_1000t_ctrl_reg); | |
651 | if (err) | |
652 | return err; | |
653 | } | |
654 | ||
655 | err = atl1e_write_phy_reg(hw, MII_BMCR, | |
656 | MII_CR_RESET | MII_CR_AUTO_NEG_EN | | |
657 | MII_CR_RESTART_AUTO_NEG); | |
658 | return err; | |
659 | } | |
660 |