Commit | Line | Data |
---|---|---|
1d22e05d LB |
1 | /* |
2 | * EP93xx ethernet network device driver | |
3 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | |
4 | * Dedicated to Marija Kulikova. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
df2f7ec8 HS |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ |
13 | ||
1d22e05d LB |
14 | #include <linux/dma-mapping.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/etherdevice.h> | |
20 | #include <linux/ethtool.h> | |
21 | #include <linux/init.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
1d22e05d LB |
23 | #include <linux/moduleparam.h> |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/delay.h> | |
df2f7ec8 | 26 | #include <linux/io.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
df2f7ec8 HS |
28 | |
29 | #include <mach/hardware.h> | |
1d22e05d LB |
30 | |
31 | #define DRV_MODULE_NAME "ep93xx-eth" | |
32 | #define DRV_MODULE_VERSION "0.1" | |
33 | ||
34 | #define RX_QUEUE_ENTRIES 64 | |
35 | #define TX_QUEUE_ENTRIES 8 | |
36 | ||
37 | #define MAX_PKT_SIZE 2044 | |
38 | #define PKT_BUF_SIZE 2048 | |
39 | ||
40 | #define REG_RXCTL 0x0000 | |
41 | #define REG_RXCTL_DEFAULT 0x00073800 | |
42 | #define REG_TXCTL 0x0004 | |
43 | #define REG_TXCTL_ENABLE 0x00000001 | |
44 | #define REG_MIICMD 0x0010 | |
45 | #define REG_MIICMD_READ 0x00008000 | |
46 | #define REG_MIICMD_WRITE 0x00004000 | |
47 | #define REG_MIIDATA 0x0014 | |
48 | #define REG_MIISTS 0x0018 | |
49 | #define REG_MIISTS_BUSY 0x00000001 | |
50 | #define REG_SELFCTL 0x0020 | |
51 | #define REG_SELFCTL_RESET 0x00000001 | |
52 | #define REG_INTEN 0x0024 | |
53 | #define REG_INTEN_TX 0x00000008 | |
54 | #define REG_INTEN_RX 0x00000007 | |
55 | #define REG_INTSTSP 0x0028 | |
56 | #define REG_INTSTS_TX 0x00000008 | |
57 | #define REG_INTSTS_RX 0x00000004 | |
58 | #define REG_INTSTSC 0x002c | |
59 | #define REG_AFP 0x004c | |
60 | #define REG_INDAD0 0x0050 | |
61 | #define REG_INDAD1 0x0051 | |
62 | #define REG_INDAD2 0x0052 | |
63 | #define REG_INDAD3 0x0053 | |
64 | #define REG_INDAD4 0x0054 | |
65 | #define REG_INDAD5 0x0055 | |
66 | #define REG_GIINTMSK 0x0064 | |
67 | #define REG_GIINTMSK_ENABLE 0x00008000 | |
68 | #define REG_BMCTL 0x0080 | |
69 | #define REG_BMCTL_ENABLE_TX 0x00000100 | |
70 | #define REG_BMCTL_ENABLE_RX 0x00000001 | |
71 | #define REG_BMSTS 0x0084 | |
72 | #define REG_BMSTS_RX_ACTIVE 0x00000008 | |
73 | #define REG_RXDQBADD 0x0090 | |
74 | #define REG_RXDQBLEN 0x0094 | |
75 | #define REG_RXDCURADD 0x0098 | |
76 | #define REG_RXDENQ 0x009c | |
77 | #define REG_RXSTSQBADD 0x00a0 | |
78 | #define REG_RXSTSQBLEN 0x00a4 | |
79 | #define REG_RXSTSQCURADD 0x00a8 | |
80 | #define REG_RXSTSENQ 0x00ac | |
81 | #define REG_TXDQBADD 0x00b0 | |
82 | #define REG_TXDQBLEN 0x00b4 | |
83 | #define REG_TXDQCURADD 0x00b8 | |
84 | #define REG_TXDENQ 0x00bc | |
85 | #define REG_TXSTSQBADD 0x00c0 | |
86 | #define REG_TXSTSQBLEN 0x00c4 | |
87 | #define REG_TXSTSQCURADD 0x00c8 | |
88 | #define REG_MAXFRMLEN 0x00e8 | |
89 | ||
90 | struct ep93xx_rdesc | |
91 | { | |
92 | u32 buf_addr; | |
93 | u32 rdesc1; | |
94 | }; | |
95 | ||
96 | #define RDESC1_NSOF 0x80000000 | |
97 | #define RDESC1_BUFFER_INDEX 0x7fff0000 | |
98 | #define RDESC1_BUFFER_LENGTH 0x0000ffff | |
99 | ||
100 | struct ep93xx_rstat | |
101 | { | |
102 | u32 rstat0; | |
103 | u32 rstat1; | |
104 | }; | |
105 | ||
106 | #define RSTAT0_RFP 0x80000000 | |
107 | #define RSTAT0_RWE 0x40000000 | |
108 | #define RSTAT0_EOF 0x20000000 | |
109 | #define RSTAT0_EOB 0x10000000 | |
110 | #define RSTAT0_AM 0x00c00000 | |
111 | #define RSTAT0_RX_ERR 0x00200000 | |
112 | #define RSTAT0_OE 0x00100000 | |
113 | #define RSTAT0_FE 0x00080000 | |
114 | #define RSTAT0_RUNT 0x00040000 | |
115 | #define RSTAT0_EDATA 0x00020000 | |
116 | #define RSTAT0_CRCE 0x00010000 | |
117 | #define RSTAT0_CRCI 0x00008000 | |
118 | #define RSTAT0_HTI 0x00003f00 | |
119 | #define RSTAT1_RFP 0x80000000 | |
120 | #define RSTAT1_BUFFER_INDEX 0x7fff0000 | |
121 | #define RSTAT1_FRAME_LENGTH 0x0000ffff | |
122 | ||
123 | struct ep93xx_tdesc | |
124 | { | |
125 | u32 buf_addr; | |
126 | u32 tdesc1; | |
127 | }; | |
128 | ||
129 | #define TDESC1_EOF 0x80000000 | |
130 | #define TDESC1_BUFFER_INDEX 0x7fff0000 | |
131 | #define TDESC1_BUFFER_ABORT 0x00008000 | |
132 | #define TDESC1_BUFFER_LENGTH 0x00000fff | |
133 | ||
134 | struct ep93xx_tstat | |
135 | { | |
136 | u32 tstat0; | |
137 | }; | |
138 | ||
139 | #define TSTAT0_TXFP 0x80000000 | |
140 | #define TSTAT0_TXWE 0x40000000 | |
141 | #define TSTAT0_FA 0x20000000 | |
142 | #define TSTAT0_LCRS 0x10000000 | |
143 | #define TSTAT0_OW 0x04000000 | |
144 | #define TSTAT0_TXU 0x02000000 | |
145 | #define TSTAT0_ECOLL 0x01000000 | |
146 | #define TSTAT0_NCOLL 0x001f0000 | |
147 | #define TSTAT0_BUFFER_INDEX 0x00007fff | |
148 | ||
149 | struct ep93xx_descs | |
150 | { | |
151 | struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES]; | |
152 | struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES]; | |
153 | struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES]; | |
154 | struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES]; | |
155 | }; | |
156 | ||
157 | struct ep93xx_priv | |
158 | { | |
159 | struct resource *res; | |
5e075cb5 | 160 | void __iomem *base_addr; |
1d22e05d LB |
161 | int irq; |
162 | ||
163 | struct ep93xx_descs *descs; | |
164 | dma_addr_t descs_dma_addr; | |
165 | ||
166 | void *rx_buf[RX_QUEUE_ENTRIES]; | |
167 | void *tx_buf[TX_QUEUE_ENTRIES]; | |
168 | ||
169 | spinlock_t rx_lock; | |
170 | unsigned int rx_pointer; | |
171 | unsigned int tx_clean_pointer; | |
172 | unsigned int tx_pointer; | |
173 | spinlock_t tx_pending_lock; | |
174 | unsigned int tx_pending; | |
175 | ||
bea3348e SH |
176 | struct net_device *dev; |
177 | struct napi_struct napi; | |
178 | ||
1d22e05d LB |
179 | struct mii_if_info mii; |
180 | u8 mdc_divisor; | |
181 | }; | |
182 | ||
183 | #define rdb(ep, off) __raw_readb((ep)->base_addr + (off)) | |
184 | #define rdw(ep, off) __raw_readw((ep)->base_addr + (off)) | |
185 | #define rdl(ep, off) __raw_readl((ep)->base_addr + (off)) | |
186 | #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off)) | |
187 | #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off)) | |
188 | #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off)) | |
189 | ||
df2f7ec8 HS |
190 | static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg) |
191 | { | |
192 | struct ep93xx_priv *ep = netdev_priv(dev); | |
193 | int data; | |
194 | int i; | |
195 | ||
196 | wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg); | |
197 | ||
198 | for (i = 0; i < 10; i++) { | |
199 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
200 | break; | |
201 | msleep(1); | |
202 | } | |
203 | ||
204 | if (i == 10) { | |
205 | pr_info("mdio read timed out\n"); | |
206 | data = 0xffff; | |
207 | } else { | |
208 | data = rdl(ep, REG_MIIDATA); | |
209 | } | |
210 | ||
211 | return data; | |
212 | } | |
213 | ||
214 | static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data) | |
215 | { | |
216 | struct ep93xx_priv *ep = netdev_priv(dev); | |
217 | int i; | |
218 | ||
219 | wrl(ep, REG_MIIDATA, data); | |
220 | wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg); | |
221 | ||
222 | for (i = 0; i < 10; i++) { | |
223 | if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0) | |
224 | break; | |
225 | msleep(1); | |
226 | } | |
227 | ||
228 | if (i == 10) | |
229 | pr_info("mdio write timed out\n"); | |
230 | } | |
1d22e05d | 231 | |
bea3348e | 232 | static int ep93xx_rx(struct net_device *dev, int processed, int budget) |
1d22e05d LB |
233 | { |
234 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d | 235 | |
bea3348e | 236 | while (processed < budget) { |
1d22e05d LB |
237 | int entry; |
238 | struct ep93xx_rstat *rstat; | |
239 | u32 rstat0; | |
240 | u32 rstat1; | |
241 | int length; | |
242 | struct sk_buff *skb; | |
243 | ||
244 | entry = ep->rx_pointer; | |
245 | rstat = ep->descs->rstat + entry; | |
2d38caba LB |
246 | |
247 | rstat0 = rstat->rstat0; | |
248 | rstat1 = rstat->rstat1; | |
bea3348e | 249 | if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP)) |
1d22e05d | 250 | break; |
1d22e05d | 251 | |
1d22e05d LB |
252 | rstat->rstat0 = 0; |
253 | rstat->rstat1 = 0; | |
254 | ||
1d22e05d | 255 | if (!(rstat0 & RSTAT0_EOF)) |
df2f7ec8 | 256 | pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1); |
1d22e05d | 257 | if (!(rstat0 & RSTAT0_EOB)) |
df2f7ec8 | 258 | pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1); |
1d22e05d | 259 | if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry) |
df2f7ec8 | 260 | pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1); |
1d22e05d LB |
261 | |
262 | if (!(rstat0 & RSTAT0_RWE)) { | |
5dbfbc40 | 263 | dev->stats.rx_errors++; |
1d22e05d | 264 | if (rstat0 & RSTAT0_OE) |
5dbfbc40 | 265 | dev->stats.rx_fifo_errors++; |
1d22e05d | 266 | if (rstat0 & RSTAT0_FE) |
5dbfbc40 | 267 | dev->stats.rx_frame_errors++; |
1d22e05d | 268 | if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA)) |
5dbfbc40 | 269 | dev->stats.rx_length_errors++; |
1d22e05d | 270 | if (rstat0 & RSTAT0_CRCE) |
5dbfbc40 | 271 | dev->stats.rx_crc_errors++; |
1d22e05d LB |
272 | goto err; |
273 | } | |
274 | ||
275 | length = rstat1 & RSTAT1_FRAME_LENGTH; | |
276 | if (length > MAX_PKT_SIZE) { | |
df2f7ec8 | 277 | pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1); |
1d22e05d LB |
278 | goto err; |
279 | } | |
280 | ||
281 | /* Strip FCS. */ | |
282 | if (rstat0 & RSTAT0_CRCI) | |
283 | length -= 4; | |
284 | ||
285 | skb = dev_alloc_skb(length + 2); | |
286 | if (likely(skb != NULL)) { | |
1d22e05d | 287 | skb_reserve(skb, 2); |
5d23a1d2 | 288 | dma_sync_single_for_cpu(NULL, ep->descs->rdesc[entry].buf_addr, |
1d22e05d | 289 | length, DMA_FROM_DEVICE); |
8c7b7faa | 290 | skb_copy_to_linear_data(skb, ep->rx_buf[entry], length); |
1d22e05d LB |
291 | skb_put(skb, length); |
292 | skb->protocol = eth_type_trans(skb, dev); | |
293 | ||
1d22e05d LB |
294 | netif_receive_skb(skb); |
295 | ||
5dbfbc40 TK |
296 | dev->stats.rx_packets++; |
297 | dev->stats.rx_bytes += length; | |
1d22e05d | 298 | } else { |
5dbfbc40 | 299 | dev->stats.rx_dropped++; |
1d22e05d LB |
300 | } |
301 | ||
302 | err: | |
303 | ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1); | |
304 | processed++; | |
1d22e05d LB |
305 | } |
306 | ||
bea3348e | 307 | return processed; |
1d22e05d LB |
308 | } |
309 | ||
310 | static int ep93xx_have_more_rx(struct ep93xx_priv *ep) | |
311 | { | |
2d38caba LB |
312 | struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer; |
313 | return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP)); | |
1d22e05d LB |
314 | } |
315 | ||
bea3348e | 316 | static int ep93xx_poll(struct napi_struct *napi, int budget) |
1d22e05d | 317 | { |
bea3348e SH |
318 | struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi); |
319 | struct net_device *dev = ep->dev; | |
320 | int rx = 0; | |
1d22e05d LB |
321 | |
322 | poll_some_more: | |
bea3348e SH |
323 | rx = ep93xx_rx(dev, rx, budget); |
324 | if (rx < budget) { | |
325 | int more = 0; | |
326 | ||
327 | spin_lock_irq(&ep->rx_lock); | |
288379f0 | 328 | __napi_complete(napi); |
bea3348e SH |
329 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); |
330 | if (ep93xx_have_more_rx(ep)) { | |
331 | wrl(ep, REG_INTEN, REG_INTEN_TX); | |
332 | wrl(ep, REG_INTSTSP, REG_INTSTS_RX); | |
333 | more = 1; | |
334 | } | |
1d22e05d LB |
335 | spin_unlock_irq(&ep->rx_lock); |
336 | ||
288379f0 | 337 | if (more && napi_reschedule(napi)) |
1d22e05d | 338 | goto poll_some_more; |
1d22e05d | 339 | } |
1d22e05d | 340 | |
1827d2e9 DM |
341 | if (rx) { |
342 | wrw(ep, REG_RXDENQ, rx); | |
343 | wrw(ep, REG_RXSTSENQ, rx); | |
344 | } | |
345 | ||
bea3348e | 346 | return rx; |
1d22e05d LB |
347 | } |
348 | ||
349 | static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev) | |
350 | { | |
351 | struct ep93xx_priv *ep = netdev_priv(dev); | |
352 | int entry; | |
353 | ||
79c356f4 | 354 | if (unlikely(skb->len > MAX_PKT_SIZE)) { |
5dbfbc40 | 355 | dev->stats.tx_dropped++; |
1d22e05d LB |
356 | dev_kfree_skb(skb); |
357 | return NETDEV_TX_OK; | |
358 | } | |
359 | ||
360 | entry = ep->tx_pointer; | |
361 | ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1); | |
362 | ||
363 | ep->descs->tdesc[entry].tdesc1 = | |
364 | TDESC1_EOF | (entry << 16) | (skb->len & 0xfff); | |
365 | skb_copy_and_csum_dev(skb, ep->tx_buf[entry]); | |
5d23a1d2 | 366 | dma_sync_single_for_cpu(NULL, ep->descs->tdesc[entry].buf_addr, |
1d22e05d LB |
367 | skb->len, DMA_TO_DEVICE); |
368 | dev_kfree_skb(skb); | |
369 | ||
1d22e05d LB |
370 | spin_lock_irq(&ep->tx_pending_lock); |
371 | ep->tx_pending++; | |
372 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
373 | netif_stop_queue(dev); | |
374 | spin_unlock_irq(&ep->tx_pending_lock); | |
375 | ||
376 | wrl(ep, REG_TXDENQ, 1); | |
377 | ||
378 | return NETDEV_TX_OK; | |
379 | } | |
380 | ||
381 | static void ep93xx_tx_complete(struct net_device *dev) | |
382 | { | |
383 | struct ep93xx_priv *ep = netdev_priv(dev); | |
1d22e05d LB |
384 | int wake; |
385 | ||
1d22e05d LB |
386 | wake = 0; |
387 | ||
388 | spin_lock(&ep->tx_pending_lock); | |
389 | while (1) { | |
390 | int entry; | |
391 | struct ep93xx_tstat *tstat; | |
392 | u32 tstat0; | |
393 | ||
394 | entry = ep->tx_clean_pointer; | |
395 | tstat = ep->descs->tstat + entry; | |
1d22e05d LB |
396 | |
397 | tstat0 = tstat->tstat0; | |
2d38caba LB |
398 | if (!(tstat0 & TSTAT0_TXFP)) |
399 | break; | |
400 | ||
1d22e05d LB |
401 | tstat->tstat0 = 0; |
402 | ||
1d22e05d | 403 | if (tstat0 & TSTAT0_FA) |
df2f7ec8 | 404 | pr_crit("frame aborted %.8x\n", tstat0); |
1d22e05d | 405 | if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry) |
df2f7ec8 | 406 | pr_crit("entry mismatch %.8x\n", tstat0); |
1d22e05d LB |
407 | |
408 | if (tstat0 & TSTAT0_TXWE) { | |
409 | int length = ep->descs->tdesc[entry].tdesc1 & 0xfff; | |
410 | ||
5dbfbc40 TK |
411 | dev->stats.tx_packets++; |
412 | dev->stats.tx_bytes += length; | |
1d22e05d | 413 | } else { |
5dbfbc40 | 414 | dev->stats.tx_errors++; |
1d22e05d LB |
415 | } |
416 | ||
417 | if (tstat0 & TSTAT0_OW) | |
5dbfbc40 | 418 | dev->stats.tx_window_errors++; |
1d22e05d | 419 | if (tstat0 & TSTAT0_TXU) |
5dbfbc40 TK |
420 | dev->stats.tx_fifo_errors++; |
421 | dev->stats.collisions += (tstat0 >> 16) & 0x1f; | |
1d22e05d LB |
422 | |
423 | ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1); | |
424 | if (ep->tx_pending == TX_QUEUE_ENTRIES) | |
425 | wake = 1; | |
426 | ep->tx_pending--; | |
427 | } | |
428 | spin_unlock(&ep->tx_pending_lock); | |
429 | ||
430 | if (wake) | |
431 | netif_wake_queue(dev); | |
432 | } | |
433 | ||
7d12e780 | 434 | static irqreturn_t ep93xx_irq(int irq, void *dev_id) |
1d22e05d LB |
435 | { |
436 | struct net_device *dev = dev_id; | |
437 | struct ep93xx_priv *ep = netdev_priv(dev); | |
438 | u32 status; | |
439 | ||
440 | status = rdl(ep, REG_INTSTSC); | |
441 | if (status == 0) | |
442 | return IRQ_NONE; | |
443 | ||
444 | if (status & REG_INTSTS_RX) { | |
445 | spin_lock(&ep->rx_lock); | |
288379f0 | 446 | if (likely(napi_schedule_prep(&ep->napi))) { |
1d22e05d | 447 | wrl(ep, REG_INTEN, REG_INTEN_TX); |
288379f0 | 448 | __napi_schedule(&ep->napi); |
1d22e05d LB |
449 | } |
450 | spin_unlock(&ep->rx_lock); | |
451 | } | |
452 | ||
453 | if (status & REG_INTSTS_TX) | |
454 | ep93xx_tx_complete(dev); | |
455 | ||
456 | return IRQ_HANDLED; | |
457 | } | |
458 | ||
459 | static void ep93xx_free_buffers(struct ep93xx_priv *ep) | |
460 | { | |
461 | int i; | |
462 | ||
463 | for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) { | |
464 | dma_addr_t d; | |
465 | ||
466 | d = ep->descs->rdesc[i].buf_addr; | |
467 | if (d) | |
468 | dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE); | |
469 | ||
470 | if (ep->rx_buf[i] != NULL) | |
471 | free_page((unsigned long)ep->rx_buf[i]); | |
472 | } | |
473 | ||
474 | for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) { | |
475 | dma_addr_t d; | |
476 | ||
477 | d = ep->descs->tdesc[i].buf_addr; | |
478 | if (d) | |
479 | dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE); | |
480 | ||
481 | if (ep->tx_buf[i] != NULL) | |
482 | free_page((unsigned long)ep->tx_buf[i]); | |
483 | } | |
484 | ||
485 | dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs, | |
486 | ep->descs_dma_addr); | |
487 | } | |
488 | ||
489 | /* | |
490 | * The hardware enforces a sub-2K maximum packet size, so we put | |
491 | * two buffers on every hardware page. | |
492 | */ | |
493 | static int ep93xx_alloc_buffers(struct ep93xx_priv *ep) | |
494 | { | |
495 | int i; | |
496 | ||
497 | ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs), | |
498 | &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA); | |
499 | if (ep->descs == NULL) | |
500 | return 1; | |
501 | ||
502 | for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) { | |
503 | void *page; | |
504 | dma_addr_t d; | |
505 | ||
506 | page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
507 | if (page == NULL) | |
508 | goto err; | |
509 | ||
510 | d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE); | |
8d8bb39b | 511 | if (dma_mapping_error(NULL, d)) { |
1d22e05d LB |
512 | free_page((unsigned long)page); |
513 | goto err; | |
514 | } | |
515 | ||
516 | ep->rx_buf[i] = page; | |
517 | ep->descs->rdesc[i].buf_addr = d; | |
518 | ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE; | |
519 | ||
520 | ep->rx_buf[i + 1] = page + PKT_BUF_SIZE; | |
521 | ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE; | |
522 | ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE; | |
523 | } | |
524 | ||
525 | for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) { | |
526 | void *page; | |
527 | dma_addr_t d; | |
528 | ||
529 | page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
530 | if (page == NULL) | |
531 | goto err; | |
532 | ||
533 | d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE); | |
8d8bb39b | 534 | if (dma_mapping_error(NULL, d)) { |
1d22e05d LB |
535 | free_page((unsigned long)page); |
536 | goto err; | |
537 | } | |
538 | ||
539 | ep->tx_buf[i] = page; | |
540 | ep->descs->tdesc[i].buf_addr = d; | |
541 | ||
542 | ep->tx_buf[i + 1] = page + PKT_BUF_SIZE; | |
543 | ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE; | |
544 | } | |
545 | ||
546 | return 0; | |
547 | ||
548 | err: | |
549 | ep93xx_free_buffers(ep); | |
550 | return 1; | |
551 | } | |
552 | ||
553 | static int ep93xx_start_hw(struct net_device *dev) | |
554 | { | |
555 | struct ep93xx_priv *ep = netdev_priv(dev); | |
556 | unsigned long addr; | |
557 | int i; | |
558 | ||
559 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
560 | for (i = 0; i < 10; i++) { | |
561 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
562 | break; | |
563 | msleep(1); | |
564 | } | |
565 | ||
566 | if (i == 10) { | |
df2f7ec8 | 567 | pr_crit("hw failed to reset\n"); |
1d22e05d LB |
568 | return 1; |
569 | } | |
570 | ||
571 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9)); | |
572 | ||
573 | /* Does the PHY support preamble suppress? */ | |
574 | if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0) | |
575 | wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8)); | |
576 | ||
577 | /* Receive descriptor ring. */ | |
578 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc); | |
579 | wrl(ep, REG_RXDQBADD, addr); | |
580 | wrl(ep, REG_RXDCURADD, addr); | |
581 | wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc)); | |
582 | ||
583 | /* Receive status ring. */ | |
584 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat); | |
585 | wrl(ep, REG_RXSTSQBADD, addr); | |
586 | wrl(ep, REG_RXSTSQCURADD, addr); | |
587 | wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat)); | |
588 | ||
589 | /* Transmit descriptor ring. */ | |
590 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc); | |
591 | wrl(ep, REG_TXDQBADD, addr); | |
592 | wrl(ep, REG_TXDQCURADD, addr); | |
593 | wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc)); | |
594 | ||
595 | /* Transmit status ring. */ | |
596 | addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat); | |
597 | wrl(ep, REG_TXSTSQBADD, addr); | |
598 | wrl(ep, REG_TXSTSQCURADD, addr); | |
599 | wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat)); | |
600 | ||
601 | wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX); | |
602 | wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); | |
603 | wrl(ep, REG_GIINTMSK, 0); | |
604 | ||
605 | for (i = 0; i < 10; i++) { | |
606 | if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0) | |
607 | break; | |
608 | msleep(1); | |
609 | } | |
610 | ||
611 | if (i == 10) { | |
df2f7ec8 | 612 | pr_crit("hw failed to start\n"); |
1d22e05d LB |
613 | return 1; |
614 | } | |
615 | ||
616 | wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES); | |
617 | wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES); | |
618 | ||
619 | wrb(ep, REG_INDAD0, dev->dev_addr[0]); | |
620 | wrb(ep, REG_INDAD1, dev->dev_addr[1]); | |
621 | wrb(ep, REG_INDAD2, dev->dev_addr[2]); | |
622 | wrb(ep, REG_INDAD3, dev->dev_addr[3]); | |
623 | wrb(ep, REG_INDAD4, dev->dev_addr[4]); | |
624 | wrb(ep, REG_INDAD5, dev->dev_addr[5]); | |
625 | wrl(ep, REG_AFP, 0); | |
626 | ||
627 | wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE); | |
628 | ||
629 | wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT); | |
630 | wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE); | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static void ep93xx_stop_hw(struct net_device *dev) | |
636 | { | |
637 | struct ep93xx_priv *ep = netdev_priv(dev); | |
638 | int i; | |
639 | ||
640 | wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); | |
641 | for (i = 0; i < 10; i++) { | |
642 | if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0) | |
643 | break; | |
644 | msleep(1); | |
645 | } | |
646 | ||
647 | if (i == 10) | |
df2f7ec8 | 648 | pr_crit("hw failed to reset\n"); |
1d22e05d LB |
649 | } |
650 | ||
651 | static int ep93xx_open(struct net_device *dev) | |
652 | { | |
653 | struct ep93xx_priv *ep = netdev_priv(dev); | |
654 | int err; | |
655 | ||
656 | if (ep93xx_alloc_buffers(ep)) | |
657 | return -ENOMEM; | |
658 | ||
bea3348e SH |
659 | napi_enable(&ep->napi); |
660 | ||
1d22e05d | 661 | if (ep93xx_start_hw(dev)) { |
bea3348e | 662 | napi_disable(&ep->napi); |
1d22e05d LB |
663 | ep93xx_free_buffers(ep); |
664 | return -EIO; | |
665 | } | |
666 | ||
667 | spin_lock_init(&ep->rx_lock); | |
668 | ep->rx_pointer = 0; | |
669 | ep->tx_clean_pointer = 0; | |
670 | ep->tx_pointer = 0; | |
671 | spin_lock_init(&ep->tx_pending_lock); | |
672 | ep->tx_pending = 0; | |
673 | ||
674 | err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev); | |
675 | if (err) { | |
bea3348e | 676 | napi_disable(&ep->napi); |
1d22e05d LB |
677 | ep93xx_stop_hw(dev); |
678 | ep93xx_free_buffers(ep); | |
679 | return err; | |
680 | } | |
681 | ||
682 | wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE); | |
683 | ||
684 | netif_start_queue(dev); | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | static int ep93xx_close(struct net_device *dev) | |
690 | { | |
691 | struct ep93xx_priv *ep = netdev_priv(dev); | |
692 | ||
bea3348e | 693 | napi_disable(&ep->napi); |
1d22e05d LB |
694 | netif_stop_queue(dev); |
695 | ||
696 | wrl(ep, REG_GIINTMSK, 0); | |
697 | free_irq(ep->irq, dev); | |
698 | ep93xx_stop_hw(dev); | |
699 | ep93xx_free_buffers(ep); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
705 | { | |
706 | struct ep93xx_priv *ep = netdev_priv(dev); | |
707 | struct mii_ioctl_data *data = if_mii(ifr); | |
708 | ||
709 | return generic_mii_ioctl(&ep->mii, data, cmd, NULL); | |
710 | } | |
711 | ||
1d22e05d LB |
712 | static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
713 | { | |
714 | strcpy(info->driver, DRV_MODULE_NAME); | |
715 | strcpy(info->version, DRV_MODULE_VERSION); | |
716 | } | |
717 | ||
718 | static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
719 | { | |
720 | struct ep93xx_priv *ep = netdev_priv(dev); | |
721 | return mii_ethtool_gset(&ep->mii, cmd); | |
722 | } | |
723 | ||
724 | static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
725 | { | |
726 | struct ep93xx_priv *ep = netdev_priv(dev); | |
727 | return mii_ethtool_sset(&ep->mii, cmd); | |
728 | } | |
729 | ||
730 | static int ep93xx_nway_reset(struct net_device *dev) | |
731 | { | |
732 | struct ep93xx_priv *ep = netdev_priv(dev); | |
733 | return mii_nway_restart(&ep->mii); | |
734 | } | |
735 | ||
736 | static u32 ep93xx_get_link(struct net_device *dev) | |
737 | { | |
738 | struct ep93xx_priv *ep = netdev_priv(dev); | |
739 | return mii_link_ok(&ep->mii); | |
740 | } | |
741 | ||
0fc0b732 | 742 | static const struct ethtool_ops ep93xx_ethtool_ops = { |
1d22e05d LB |
743 | .get_drvinfo = ep93xx_get_drvinfo, |
744 | .get_settings = ep93xx_get_settings, | |
745 | .set_settings = ep93xx_set_settings, | |
746 | .nway_reset = ep93xx_nway_reset, | |
747 | .get_link = ep93xx_get_link, | |
748 | }; | |
749 | ||
9aa7b30c AB |
750 | static const struct net_device_ops ep93xx_netdev_ops = { |
751 | .ndo_open = ep93xx_open, | |
752 | .ndo_stop = ep93xx_close, | |
753 | .ndo_start_xmit = ep93xx_xmit, | |
9aa7b30c AB |
754 | .ndo_do_ioctl = ep93xx_ioctl, |
755 | .ndo_validate_addr = eth_validate_addr, | |
756 | .ndo_change_mtu = eth_change_mtu, | |
757 | .ndo_set_mac_address = eth_mac_addr, | |
758 | }; | |
759 | ||
760 | static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data) | |
1d22e05d LB |
761 | { |
762 | struct net_device *dev; | |
1d22e05d LB |
763 | |
764 | dev = alloc_etherdev(sizeof(struct ep93xx_priv)); | |
765 | if (dev == NULL) | |
766 | return NULL; | |
1d22e05d LB |
767 | |
768 | memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN); | |
769 | ||
1d22e05d | 770 | dev->ethtool_ops = &ep93xx_ethtool_ops; |
9aa7b30c | 771 | dev->netdev_ops = &ep93xx_netdev_ops; |
1d22e05d LB |
772 | |
773 | dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM; | |
1d22e05d LB |
774 | |
775 | return dev; | |
776 | } | |
777 | ||
778 | ||
779 | static int ep93xx_eth_remove(struct platform_device *pdev) | |
780 | { | |
781 | struct net_device *dev; | |
782 | struct ep93xx_priv *ep; | |
783 | ||
784 | dev = platform_get_drvdata(pdev); | |
785 | if (dev == NULL) | |
786 | return 0; | |
787 | platform_set_drvdata(pdev, NULL); | |
788 | ||
789 | ep = netdev_priv(dev); | |
790 | ||
791 | /* @@@ Force down. */ | |
792 | unregister_netdev(dev); | |
793 | ep93xx_free_buffers(ep); | |
794 | ||
795 | if (ep->base_addr != NULL) | |
796 | iounmap(ep->base_addr); | |
797 | ||
798 | if (ep->res != NULL) { | |
799 | release_resource(ep->res); | |
800 | kfree(ep->res); | |
801 | } | |
802 | ||
803 | free_netdev(dev); | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | static int ep93xx_eth_probe(struct platform_device *pdev) | |
809 | { | |
810 | struct ep93xx_eth_data *data; | |
811 | struct net_device *dev; | |
812 | struct ep93xx_priv *ep; | |
df2f7ec8 HS |
813 | struct resource *mem; |
814 | int irq; | |
1d22e05d LB |
815 | int err; |
816 | ||
1d22e05d LB |
817 | if (pdev == NULL) |
818 | return -ENODEV; | |
ebf5112c | 819 | data = pdev->dev.platform_data; |
1d22e05d | 820 | |
df2f7ec8 HS |
821 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
822 | irq = platform_get_irq(pdev, 0); | |
823 | if (!mem || irq < 0) | |
824 | return -ENXIO; | |
825 | ||
1d22e05d LB |
826 | dev = ep93xx_dev_alloc(data); |
827 | if (dev == NULL) { | |
828 | err = -ENOMEM; | |
829 | goto err_out; | |
830 | } | |
831 | ep = netdev_priv(dev); | |
bea3348e SH |
832 | ep->dev = dev; |
833 | netif_napi_add(dev, &ep->napi, ep93xx_poll, 64); | |
1d22e05d LB |
834 | |
835 | platform_set_drvdata(pdev, dev); | |
836 | ||
df2f7ec8 HS |
837 | ep->res = request_mem_region(mem->start, resource_size(mem), |
838 | dev_name(&pdev->dev)); | |
1d22e05d LB |
839 | if (ep->res == NULL) { |
840 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
841 | err = -ENOMEM; | |
842 | goto err_out; | |
843 | } | |
844 | ||
df2f7ec8 | 845 | ep->base_addr = ioremap(mem->start, resource_size(mem)); |
1d22e05d LB |
846 | if (ep->base_addr == NULL) { |
847 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
848 | err = -EIO; | |
849 | goto err_out; | |
850 | } | |
df2f7ec8 | 851 | ep->irq = irq; |
1d22e05d LB |
852 | |
853 | ep->mii.phy_id = data->phy_id; | |
854 | ep->mii.phy_id_mask = 0x1f; | |
855 | ep->mii.reg_num_mask = 0x1f; | |
856 | ep->mii.dev = dev; | |
857 | ep->mii.mdio_read = ep93xx_mdio_read; | |
858 | ep->mii.mdio_write = ep93xx_mdio_write; | |
859 | ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */ | |
860 | ||
3c91c7ae FF |
861 | if (is_zero_ether_addr(dev->dev_addr)) |
862 | random_ether_addr(dev->dev_addr); | |
863 | ||
1d22e05d LB |
864 | err = register_netdev(dev); |
865 | if (err) { | |
866 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
867 | goto err_out; | |
868 | } | |
869 | ||
df2f7ec8 HS |
870 | printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n", |
871 | dev->name, ep->irq, dev->dev_addr); | |
1d22e05d LB |
872 | |
873 | return 0; | |
874 | ||
875 | err_out: | |
876 | ep93xx_eth_remove(pdev); | |
877 | return err; | |
878 | } | |
879 | ||
880 | ||
881 | static struct platform_driver ep93xx_eth_driver = { | |
882 | .probe = ep93xx_eth_probe, | |
883 | .remove = ep93xx_eth_remove, | |
884 | .driver = { | |
885 | .name = "ep93xx-eth", | |
72abb461 | 886 | .owner = THIS_MODULE, |
1d22e05d LB |
887 | }, |
888 | }; | |
889 | ||
890 | static int __init ep93xx_eth_init_module(void) | |
891 | { | |
892 | printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n"); | |
893 | return platform_driver_register(&ep93xx_eth_driver); | |
894 | } | |
895 | ||
896 | static void __exit ep93xx_eth_cleanup_module(void) | |
897 | { | |
898 | platform_driver_unregister(&ep93xx_eth_driver); | |
899 | } | |
900 | ||
901 | module_init(ep93xx_eth_init_module); | |
902 | module_exit(ep93xx_eth_cleanup_module); | |
903 | MODULE_LICENSE("GPL"); | |
72abb461 | 904 | MODULE_ALIAS("platform:ep93xx-eth"); |