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amd8111e: fix dma_free_coherent context
[linux-2.6-block.git] / drivers / net / arm / at91_ether.c
CommitLineData
d4b7780e
AV		 1/*
2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
3 *
4 * Copyright (C) 2003 SAN People (Pty) Ltd
5 *
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
8 *
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
11 *
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/module.h>
21#include <linux/init.h>
d4b7780e
AV		 22#include <linux/mii.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/dma-mapping.h>
27#include <linux/ethtool.h>
28#include <linux/platform_device.h>
29#include <linux/clk.h>
30
31#include <asm/io.h>
32#include <asm/uaccess.h>
33#include <asm/mach-types.h>
34
a09e64fb
RK		 35#include <mach/at91rm9200_emac.h>
36#include <mach/gpio.h>
37#include <mach/board.h>
d4b7780e
AV		 38
39#include "at91_ether.h"
40
41#define DRV_NAME "at91_ether"
42#define DRV_VERSION "1.0"
43
775637df
AV		 44#define LINK_POLL_INTERVAL (HZ)
45
d4b7780e
AV		 46/* ..................................................................... */
47
48/*
49 * Read from a EMAC register.
50 */
51static inline unsigned long at91_emac_read(unsigned int reg)
52{
53 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
54
55 return __raw_readl(emac_base + reg);
56}
57
58/*
59 * Write to a EMAC register.
60 */
61static inline void at91_emac_write(unsigned int reg, unsigned long value)
62{
63 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
64
65 __raw_writel(value, emac_base + reg);
66}
67
68/* ........................... PHY INTERFACE ........................... */
69
70/*
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
74 */
75static void enable_mdi(void)
76{
77 unsigned long ctl;
78
79 ctl = at91_emac_read(AT91_EMAC_CTL);
80 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
81}
82
83/*
84 * Disable the MDIO bit in the MAC control register
85 */
86static void disable_mdi(void)
87{
88 unsigned long ctl;
89
90 ctl = at91_emac_read(AT91_EMAC_CTL);
91 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
92}
93
94/*
95 * Wait until the PHY operation is complete.
96 */
97static inline void at91_phy_wait(void) {
98 unsigned long timeout = jiffies + 2;
99
100 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
101 if (time_after(jiffies, timeout)) {
102 printk("at91_ether: MIO timeout\n");
103 break;
104 }
105 cpu_relax();
106 }
107}
108
109/*
110 * Write value to the a PHY register
111 * Note: MDI interface is assumed to already have been enabled.
112 */
113static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
114{
115 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
116 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
117
118 /* Wait until IDLE bit in Network Status register is cleared */
119 at91_phy_wait();
120}
121
122/*
123 * Read value stored in a PHY register.
124 * Note: MDI interface is assumed to already have been enabled.
125 */
126static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
127{
128 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
129 | ((phy_addr & 0x1f) << 23) | (address << 18));
130
131 /* Wait until IDLE bit in Network Status register is cleared */
132 at91_phy_wait();
133
134 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
135}
136
137/* ........................... PHY MANAGEMENT .......................... */
138
139/*
140 * Access the PHY to determine the current link speed and mode, and update the
141 * MAC accordingly.
142 * If no link or auto-negotiation is busy, then no changes are made.
143 */
775637df 144static void update_linkspeed(struct net_device *dev, int silent)
d4b7780e 145{
c57ee096 146 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 147 unsigned int bmsr, bmcr, lpa, mac_cfg;
148 unsigned int speed, duplex;
149
150 if (!mii_link_ok(&lp->mii)) { /* no link */
151 netif_carrier_off(dev);
775637df
AV		 152 if (!silent)
153 printk(KERN_INFO "%s: Link down.\n", dev->name);
d4b7780e
AV		 154 return;
155 }
156
157 /* Link up, or auto-negotiation still in progress */
158 read_phy(lp->phy_address, MII_BMSR, &bmsr);
159 read_phy(lp->phy_address, MII_BMCR, &bmcr);
160 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
161 if (!(bmsr & BMSR_ANEGCOMPLETE))
162 return; /* Do nothing - another interrupt generated when negotiation complete */
163
164 read_phy(lp->phy_address, MII_LPA, &lpa);
165 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
166 else speed = SPEED_10;
167 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
168 else duplex = DUPLEX_HALF;
169 } else {
170 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
171 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
172 }
173
174 /* Update the MAC */
175 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
176 if (speed == SPEED_100) {
177 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
178 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
179 else /* 100 Half Duplex */
180 mac_cfg |= AT91_EMAC_SPD;
181 } else {
182 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
183 mac_cfg |= AT91_EMAC_FD;
184 else {} /* 10 Half Duplex */
185 }
186 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
187
775637df
AV		 188 if (!silent)
189 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
d4b7780e
AV		 190 netif_carrier_on(dev);
191}
192
193/*
194 * Handle interrupts from the PHY
195 */
7d12e780 196static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
d4b7780e
AV		 197{
198 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 199 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 200 unsigned int phy;
201
202 /*
203 * This hander is triggered on both edges, but the PHY chips expect
204 * level-triggering. We therefore have to check if the PHY actually has
205 * an IRQ pending.
206 */
207 enable_mdi();
208 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
209 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
210 if (!(phy & (1 << 0)))
211 goto done;
212 }
213 else if (lp->phy_type == MII_LXT971A_ID) {
214 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
215 if (!(phy & (1 << 2)))
216 goto done;
217 }
218 else if (lp->phy_type == MII_BCM5221_ID) {
219 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
220 if (!(phy & (1 << 0)))
221 goto done;
222 }
223 else if (lp->phy_type == MII_KS8721_ID) {
224 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
225 if (!(phy & ((1 << 2) | 1)))
226 goto done;
227 }
6b4aea73
AV		 228 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
229 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
230 if (!(phy & ((1 << 2) | 1)))
231 goto done;
232 }
233 else if (lp->phy_type == MII_DP83848_ID) {
234 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
235 if (!(phy & (1 << 7)))
236 goto done;
237 }
d4b7780e 238
775637df 239 update_linkspeed(dev, 0);
d4b7780e
AV		 240
241done:
242 disable_mdi();
243
244 return IRQ_HANDLED;
245}
246
247/*
248 * Initialize and enable the PHY interrupt for link-state changes
249 */
250static void enable_phyirq(struct net_device *dev)
251{
c57ee096 252 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 253 unsigned int dsintr, irq_number;
254 int status;
255
775637df
AV		 256 irq_number = lp->board_data.phy_irq_pin;
257 if (!irq_number) {
258 /*
259 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
260 * or board does not have it connected.
261 */
cf42553a 262 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
d4b7780e 263 return;
775637df 264 }
d4b7780e 265
d4b7780e
AV		 266 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
267 if (status) {
268 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
269 return;
270 }
271
272 spin_lock_irq(&lp->lock);
273 enable_mdi();
274
275 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
276 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
277 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
278 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
279 }
280 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
281 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
282 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
283 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
284 }
285 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
286 dsintr = (1 << 15) | ( 1 << 14);
287 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
288 }
289 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
290 dsintr = (1 << 10) | ( 1 << 8);
291 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
292 }
6b4aea73
AV		 293 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
294 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
295 dsintr = dsintr | 0x500; /* set bits 8, 10 */
296 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
297 }
298 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
299 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
300 dsintr = dsintr | 0x3c; /* set bits 2..5 */
301 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
302 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
303 dsintr = dsintr | 0x3; /* set bits 0,1 */
304 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
305 }
d4b7780e
AV		 306
307 disable_mdi();
308 spin_unlock_irq(&lp->lock);
309}
310
311/*
312 * Disable the PHY interrupt
313 */
314static void disable_phyirq(struct net_device *dev)
315{
c57ee096 316 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 317 unsigned int dsintr;
318 unsigned int irq_number;
319
775637df
AV		 320 irq_number = lp->board_data.phy_irq_pin;
321 if (!irq_number) {
cf42553a 322 del_timer_sync(&lp->check_timer);
d4b7780e 323 return;
775637df 324 }
d4b7780e
AV		 325
326 spin_lock_irq(&lp->lock);
327 enable_mdi();
328
329 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
330 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
331 dsintr = dsintr | 0xf00; /* set bits 8..11 */
332 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
333 }
334 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
335 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
336 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
337 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
338 }
339 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
340 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
341 dsintr = ~(1 << 14);
342 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
343 }
344 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
345 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
346 dsintr = ~((1 << 10) | (1 << 8));
347 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
348 }
6b4aea73
AV		 349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
350 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
351 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
352 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
353 }
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
355 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
356 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
357 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
358 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
359 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
360 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
361 }
d4b7780e
AV		 362
363 disable_mdi();
364 spin_unlock_irq(&lp->lock);
365
d4b7780e
AV		 366 free_irq(irq_number, dev); /* Free interrupt handler */
367}
368
369/*
370 * Perform a software reset of the PHY.
371 */
372#if 0
373static void reset_phy(struct net_device *dev)
374{
c57ee096 375 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 376 unsigned int bmcr;
377
378 spin_lock_irq(&lp->lock);
379 enable_mdi();
380
381 /* Perform PHY reset */
382 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
383
384 /* Wait until PHY reset is complete */
385 do {
386 read_phy(lp->phy_address, MII_BMCR, &bmcr);
10a5a80b 387 } while (!(bmcr & BMCR_RESET));
d4b7780e
AV		 388
389 disable_mdi();
390 spin_unlock_irq(&lp->lock);
391}
392#endif
393
775637df
AV		 394static void at91ether_check_link(unsigned long dev_id)
395{
396 struct net_device *dev = (struct net_device *) dev_id;
cf42553a 397 struct at91_private *lp = netdev_priv(dev);
775637df
AV		 398
399 enable_mdi();
400 update_linkspeed(dev, 1);
401 disable_mdi();
402
cf42553a 403 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
775637df
AV		 404}
405
d4b7780e
AV		 406/* ......................... ADDRESS MANAGEMENT ........................ */
407
408/*
409 * NOTE: Your bootloader must always set the MAC address correctly before
410 * booting into Linux.
411 *
412 * - It must always set the MAC address after reset, even if it doesn't
413 * happen to access the Ethernet while it's booting. Some versions of
414 * U-Boot on the AT91RM9200-DK do not do this.
415 *
416 * - Likewise it must store the addresses in the correct byte order.
417 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
418 * continues to do so, for bug-compatibility).
419 */
420
421static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
422{
423 char addr[6];
424
425 if (machine_is_csb337()) {
426 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
427 addr[4] = (lo & 0xff00) >> 8;
428 addr[3] = (lo & 0xff0000) >> 16;
429 addr[2] = (lo & 0xff000000) >> 24;
430 addr[1] = (hi & 0xff);
431 addr[0] = (hi & 0xff00) >> 8;
432 }
433 else {
434 addr[0] = (lo & 0xff);
435 addr[1] = (lo & 0xff00) >> 8;
436 addr[2] = (lo & 0xff0000) >> 16;
437 addr[3] = (lo & 0xff000000) >> 24;
438 addr[4] = (hi & 0xff);
439 addr[5] = (hi & 0xff00) >> 8;
440 }
441
442 if (is_valid_ether_addr(addr)) {
443 memcpy(dev->dev_addr, &addr, 6);
444 return 1;
445 }
446 return 0;
447}
448
449/*
450 * Set the ethernet MAC address in dev->dev_addr
451 */
452static void __init get_mac_address(struct net_device *dev)
453{
454 /* Check Specific-Address 1 */
455 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
456 return;
457 /* Check Specific-Address 2 */
458 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
459 return;
460 /* Check Specific-Address 3 */
461 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
462 return;
463 /* Check Specific-Address 4 */
464 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
465 return;
466
467 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
468}
469
470/*
471 * Program the hardware MAC address from dev->dev_addr.
472 */
473static void update_mac_address(struct net_device *dev)
474{
475 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
476 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
477
478 at91_emac_write(AT91_EMAC_SA2L, 0);
479 at91_emac_write(AT91_EMAC_SA2H, 0);
480}
481
482/*
483 * Store the new hardware address in dev->dev_addr, and update the MAC.
484 */
485static int set_mac_address(struct net_device *dev, void* addr)
486{
487 struct sockaddr *address = addr;
0795af57 488 DECLARE_MAC_BUF(mac);
d4b7780e
AV		 489
490 if (!is_valid_ether_addr(address->sa_data))
491 return -EADDRNOTAVAIL;
492
493 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
494 update_mac_address(dev);
495
0795af57
JP		 496 printk("%s: Setting MAC address to %s\n", dev->name,
497 print_mac(mac, dev->dev_addr));
d4b7780e
AV		 498
499 return 0;
500}
501
502static int inline hash_bit_value(int bitnr, __u8 *addr)
503{
504 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
505 return 1;
506 return 0;
507}
508
509/*
510 * The hash address register is 64 bits long and takes up two locations in the memory map.
511 * The least significant bits are stored in EMAC_HSL and the most significant
512 * bits in EMAC_HSH.
513 *
514 * The unicast hash enable and the multicast hash enable bits in the network configuration
515 * register enable the reception of hash matched frames. The destination address is
516 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
517 * The hash function is an exclusive or of every sixth bit of the destination address.
518 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
519 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
520 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
521 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
522 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
523 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
524 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
525 * unicast indicator, and da[47] represents the most significant bit of the last byte
526 * received.
527 * If the hash index points to a bit that is set in the hash register then the frame will be
528 * matched according to whether the frame is multicast or unicast.
529 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
530 * the hash index points to a bit set in the hash register.
531 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
532 * hash index points to a bit set in the hash register.
533 * To receive all multicast frames, the hash register should be set with all ones and the
534 * multicast hash enable bit should be set in the network configuration register.
535 */
536
537/*
538 * Return the hash index value for the specified address.
539 */
540static int hash_get_index(__u8 *addr)
541{
542 int i, j, bitval;
543 int hash_index = 0;
544
545 for (j = 0; j < 6; j++) {
546 for (i = 0, bitval = 0; i < 8; i++)
547 bitval ^= hash_bit_value(i*6 + j, addr);
548
549 hash_index |= (bitval << j);
550 }
551
427d269f 552 return hash_index;
d4b7780e
AV		 553}
554
555/*
556 * Add multicast addresses to the internal multicast-hash table.
557 */
558static void at91ether_sethashtable(struct net_device *dev)
559{
560 struct dev_mc_list *curr;
561 unsigned long mc_filter[2];
562 unsigned int i, bitnr;
563
564 mc_filter[0] = mc_filter[1] = 0;
565
566 curr = dev->mc_list;
567 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
568 if (!curr) break; /* unexpected end of list */
569
570 bitnr = hash_get_index(curr->dmi_addr);
571 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
572 }
573
8bc35473
AV		 574 at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
575 at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
d4b7780e
AV		 576}
577
578/*
579 * Enable/Disable promiscuous and multicast modes.
580 */
581static void at91ether_set_rx_mode(struct net_device *dev)
582{
583 unsigned long cfg;
584
585 cfg = at91_emac_read(AT91_EMAC_CFG);
586
587 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
588 cfg |= AT91_EMAC_CAF;
589 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
590 cfg &= ~AT91_EMAC_CAF;
591
592 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
593 at91_emac_write(AT91_EMAC_HSH, -1);
594 at91_emac_write(AT91_EMAC_HSL, -1);
595 cfg |= AT91_EMAC_MTI;
596 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
597 at91ether_sethashtable(dev);
598 cfg |= AT91_EMAC_MTI;
599 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
600 at91_emac_write(AT91_EMAC_HSH, 0);
601 at91_emac_write(AT91_EMAC_HSL, 0);
602 cfg &= ~AT91_EMAC_MTI;
603 }
604
605 at91_emac_write(AT91_EMAC_CFG, cfg);
606}
607
d4b7780e
AV		 608/* ......................... ETHTOOL SUPPORT ........................... */
609
d4b7780e
AV		 610static int mdio_read(struct net_device *dev, int phy_id, int location)
611{
612 unsigned int value;
613
614 read_phy(phy_id, location, &value);
615 return value;
616}
617
618static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
619{
620 write_phy(phy_id, location, value);
621}
622
623static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
624{
c57ee096 625 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 626 int ret;
627
628 spin_lock_irq(&lp->lock);
629 enable_mdi();
630
631 ret = mii_ethtool_gset(&lp->mii, cmd);
632
633 disable_mdi();
634 spin_unlock_irq(&lp->lock);
635
636 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
637 cmd->supported = SUPPORTED_FIBRE;
638 cmd->port = PORT_FIBRE;
639 }
640
641 return ret;
642}
643
644static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
645{
c57ee096 646 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 647 int ret;
648
649 spin_lock_irq(&lp->lock);
650 enable_mdi();
651
652 ret = mii_ethtool_sset(&lp->mii, cmd);
653
654 disable_mdi();
655 spin_unlock_irq(&lp->lock);
656
657 return ret;
658}
659
660static int at91ether_nwayreset(struct net_device *dev)
661{
c57ee096 662 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 663 int ret;
664
665 spin_lock_irq(&lp->lock);
666 enable_mdi();
667
668 ret = mii_nway_restart(&lp->mii);
669
670 disable_mdi();
671 spin_unlock_irq(&lp->lock);
672
673 return ret;
674}
675
676static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
677{
678 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
679 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3f978704 680 strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
d4b7780e
AV		 681}
682
7282d491 683static const struct ethtool_ops at91ether_ethtool_ops = {
d4b7780e
AV		 684 .get_settings = at91ether_get_settings,
685 .set_settings = at91ether_set_settings,
686 .get_drvinfo = at91ether_get_drvinfo,
687 .nway_reset = at91ether_nwayreset,
688 .get_link = ethtool_op_get_link,
689};
690
ca5585ed
AV		 691static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
692{
c57ee096 693 struct at91_private *lp = netdev_priv(dev);
ca5585ed
AV		 694 int res;
695
696 if (!netif_running(dev))
697 return -EINVAL;
698
699 spin_lock_irq(&lp->lock);
700 enable_mdi();
701 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
702 disable_mdi();
703 spin_unlock_irq(&lp->lock);
704
705 return res;
706}
d4b7780e
AV		 707
708/* ................................ MAC ................................ */
709
710/*
711 * Initialize and start the Receiver and Transmit subsystems
712 */
713static void at91ether_start(struct net_device *dev)
714{
c57ee096 715 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 716 struct recv_desc_bufs *dlist, *dlist_phys;
717 int i;
718 unsigned long ctl;
719
720 dlist = lp->dlist;
721 dlist_phys = lp->dlist_phys;
722
723 for (i = 0; i < MAX_RX_DESCR; i++) {
724 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
725 dlist->descriptors[i].size = 0;
726 }
727
728 /* Set the Wrap bit on the last descriptor */
729 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
730
731 /* Reset buffer index */
732 lp->rxBuffIndex = 0;
733
734 /* Program address of descriptor list in Rx Buffer Queue register */
735 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
736
737 /* Enable Receive and Transmit */
738 ctl = at91_emac_read(AT91_EMAC_CTL);
739 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
740}
741
742/*
743 * Open the ethernet interface
744 */
745static int at91ether_open(struct net_device *dev)
746{
c57ee096 747 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 748 unsigned long ctl;
749
427d269f
AV		 750 if (!is_valid_ether_addr(dev->dev_addr))
751 return -EADDRNOTAVAIL;
d4b7780e 752
427d269f 753 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
d4b7780e
AV		 754
755 /* Clear internal statistics */
756 ctl = at91_emac_read(AT91_EMAC_CTL);
757 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
758
759 /* Update the MAC address (incase user has changed it) */
760 update_mac_address(dev);
761
762 /* Enable PHY interrupt */
763 enable_phyirq(dev);
764
765 /* Enable MAC interrupts */
766 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
767 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
768 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
769
770 /* Determine current link speed */
771 spin_lock_irq(&lp->lock);
772 enable_mdi();
775637df 773 update_linkspeed(dev, 0);
d4b7780e
AV		 774 disable_mdi();
775 spin_unlock_irq(&lp->lock);
776
777 at91ether_start(dev);
778 netif_start_queue(dev);
779 return 0;
780}
781
782/*
783 * Close the interface
784 */
785static int at91ether_close(struct net_device *dev)
786{
c57ee096 787 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 788 unsigned long ctl;
789
790 /* Disable Receiver and Transmitter */
791 ctl = at91_emac_read(AT91_EMAC_CTL);
792 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
793
794 /* Disable PHY interrupt */
795 disable_phyirq(dev);
796
797 /* Disable MAC interrupts */
798 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
799 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
800 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
801
802 netif_stop_queue(dev);
803
427d269f 804 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
d4b7780e
AV		 805
806 return 0;
807}
808
809/*
810 * Transmit packet.
811 */
812static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
813{
c57ee096 814 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 815
816 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
817 netif_stop_queue(dev);
818
819 /* Store packet information (to free when Tx completed) */
820 lp->skb = skb;
821 lp->skb_length = skb->len;
822 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
7a2f53ee 823 dev->stats.tx_bytes += skb->len;
d4b7780e
AV		 824
825 /* Set address of the data in the Transmit Address register */
826 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
827 /* Set length of the packet in the Transmit Control register */
828 at91_emac_write(AT91_EMAC_TCR, skb->len);
829
830 dev->trans_start = jiffies;
831 } else {
832 printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
833 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
834 on this skb, he also reports -ENETDOWN and printk's, so either
835 we free and return(0) or don't free and return 1 */
836 }
837
838 return 0;
839}
840
841/*
842 * Update the current statistics from the internal statistics registers.
843 */
844static struct net_device_stats *at91ether_stats(struct net_device *dev)
845{
d4b7780e
AV		 846 int ale, lenerr, seqe, lcol, ecol;
847
848 if (netif_running(dev)) {
7a2f53ee 849 dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
d4b7780e 850 ale = at91_emac_read(AT91_EMAC_ALE);
7a2f53ee 851 dev->stats.rx_frame_errors += ale; /* Alignment errors */
d4b7780e 852 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
7a2f53ee 853 dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
d4b7780e 854 seqe = at91_emac_read(AT91_EMAC_SEQE);
7a2f53ee
PZ		 855 dev->stats.rx_crc_errors += seqe; /* CRC error */
856 dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
857 dev->stats.rx_errors += (ale + lenerr + seqe
d4b7780e
AV		 858 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
859
7a2f53ee
PZ		 860 dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
861 dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
862 dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
863 dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
d4b7780e
AV		 864
865 lcol = at91_emac_read(AT91_EMAC_LCOL);
866 ecol = at91_emac_read(AT91_EMAC_ECOL);
7a2f53ee
PZ		 867 dev->stats.tx_window_errors += lcol; /* Late collisions */
868 dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
d4b7780e 869
7a2f53ee 870 dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
d4b7780e 871 }
7a2f53ee 872 return &dev->stats;
d4b7780e
AV		 873}
874
875/*
876 * Extract received frame from buffer descriptors and sent to upper layers.
877 * (Called from interrupt context)
878 */
879static void at91ether_rx(struct net_device *dev)
880{
c57ee096 881 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 882 struct recv_desc_bufs *dlist;
883 unsigned char *p_recv;
884 struct sk_buff *skb;
885 unsigned int pktlen;
886
887 dlist = lp->dlist;
888 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
889 p_recv = dlist->recv_buf[lp->rxBuffIndex];
890 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
a3f63e4f 891 skb = dev_alloc_skb(pktlen + 2);
d4b7780e
AV		 892 if (skb != NULL) {
893 skb_reserve(skb, 2);
894 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
895
d4b7780e 896 skb->protocol = eth_type_trans(skb, dev);
d4b7780e 897 dev->last_rx = jiffies;
7a2f53ee 898 dev->stats.rx_bytes += pktlen;
d4b7780e
AV		 899 netif_rx(skb);
900 }
901 else {
7a2f53ee 902 dev->stats.rx_dropped += 1;
d4b7780e
AV		 903 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
904 }
905
906 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
7a2f53ee 907 dev->stats.multicast++;
d4b7780e
AV		 908
909 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
910 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
911 lp->rxBuffIndex = 0;
912 else
913 lp->rxBuffIndex++;
914 }
915}
916
917/*
918 * MAC interrupt handler
919 */
7d12e780 920static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
d4b7780e
AV		 921{
922 struct net_device *dev = (struct net_device *) dev_id;
c57ee096 923 struct at91_private *lp = netdev_priv(dev);
d4b7780e
AV		 924 unsigned long intstatus, ctl;
925
926 /* MAC Interrupt Status register indicates what interrupts are pending.
927 It is automatically cleared once read. */
928 intstatus = at91_emac_read(AT91_EMAC_ISR);
929
930 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
931 at91ether_rx(dev);
932
427d269f 933 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
d4b7780e
AV		 934 /* The TCOM bit is set even if the transmission failed. */
935 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
7a2f53ee 936 dev->stats.tx_errors += 1;
d4b7780e
AV		 937
938 if (lp->skb) {
939 dev_kfree_skb_irq(lp->skb);
940 lp->skb = NULL;
941 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
942 }
943 netif_wake_queue(dev);
944 }
945
946 /* Work-around for Errata #11 */
947 if (intstatus & AT91_EMAC_RBNA) {
948 ctl = at91_emac_read(AT91_EMAC_CTL);
949 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
950 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
951 }
952
953 if (intstatus & AT91_EMAC_ROVR)
954 printk("%s: ROVR error\n", dev->name);
955
956 return IRQ_HANDLED;
957}
958
51cc2104
AV		 959#ifdef CONFIG_NET_POLL_CONTROLLER
960static void at91ether_poll_controller(struct net_device *dev)
961{
962 unsigned long flags;
963
964 local_irq_save(flags);
965 at91ether_interrupt(dev->irq, dev);
966 local_irq_restore(flags);
967}
968#endif
969
d4b7780e
AV		 970/*
971 * Initialize the ethernet interface
972 */
427d269f
AV		 973static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
974 struct platform_device *pdev, struct clk *ether_clk)
d4b7780e
AV		 975{
976 struct at91_eth_data *board_data = pdev->dev.platform_data;
977 struct net_device *dev;
978 struct at91_private *lp;
979 unsigned int val;
980 int res;
0795af57 981 DECLARE_MAC_BUF(mac);
d4b7780e 982
d4b7780e
AV		 983 dev = alloc_etherdev(sizeof(struct at91_private));
984 if (!dev)
985 return -ENOMEM;
986
987 dev->base_addr = AT91_VA_BASE_EMAC;
72729910 988 dev->irq = AT91RM9200_ID_EMAC;
d4b7780e
AV		 989
990 /* Install the interrupt handler */
991 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
992 free_netdev(dev);
993 return -EBUSY;
994 }
995
996 /* Allocate memory for DMA Receive descriptors */
c57ee096 997 lp = netdev_priv(dev);
d4b7780e
AV		 998 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
999 if (lp->dlist == NULL) {
1000 free_irq(dev->irq, dev);
1001 free_netdev(dev);
1002 return -ENOMEM;
1003 }
1004 lp->board_data = *board_data;
427d269f 1005 lp->ether_clk = ether_clk;
d4b7780e
AV		 1006 platform_set_drvdata(pdev, dev);
1007
1008 spin_lock_init(&lp->lock);
1009
1010 ether_setup(dev);
1011 dev->open = at91ether_open;
1012 dev->stop = at91ether_close;
1013 dev->hard_start_xmit = at91ether_tx;
1014 dev->get_stats = at91ether_stats;
1015 dev->set_multicast_list = at91ether_set_rx_mode;
1016 dev->set_mac_address = set_mac_address;
1017 dev->ethtool_ops = &at91ether_ethtool_ops;
ca5585ed 1018 dev->do_ioctl = at91ether_ioctl;
51cc2104
AV		 1019#ifdef CONFIG_NET_POLL_CONTROLLER
1020 dev->poll_controller = at91ether_poll_controller;
1021#endif
d4b7780e
AV		 1022
1023 SET_NETDEV_DEV(dev, &pdev->dev);
1024
1025 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
1026 update_mac_address(dev); /* Program ethernet address into MAC */
1027
1028 at91_emac_write(AT91_EMAC_CTL, 0);
1029
1030 if (lp->board_data.is_rmii)
1031 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
1032 else
1033 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
1034
1035 /* Perform PHY-specific initialization */
1036 spin_lock_irq(&lp->lock);
1037 enable_mdi();
1038 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1039 read_phy(phy_address, MII_DSCR_REG, &val);
1040 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1041 lp->phy_media = PORT_FIBRE;
1042 } else if (machine_is_csb337()) {
1043 /* mix link activity status into LED2 link state */
1044 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
2f036ac6
AV		 1045 } else if (machine_is_ecbat91())
1046 write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
1047
d4b7780e
AV		 1048 disable_mdi();
1049 spin_unlock_irq(&lp->lock);
1050
1051 lp->mii.dev = dev; /* Support for ethtool */
1052 lp->mii.mdio_read = mdio_read;
1053 lp->mii.mdio_write = mdio_write;
ca5585ed
AV		 1054 lp->mii.phy_id = phy_address;
1055 lp->mii.phy_id_mask = 0x1f;
1056 lp->mii.reg_num_mask = 0x1f;
d4b7780e
AV		 1057
1058 lp->phy_type = phy_type; /* Type of PHY connected */
1059 lp->phy_address = phy_address; /* MDI address of PHY */
1060
1061 /* Register the network interface */
1062 res = register_netdev(dev);
1063 if (res) {
1064 free_irq(dev->irq, dev);
1065 free_netdev(dev);
1066 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1067 return res;
1068 }
d4b7780e
AV		 1069
1070 /* Determine current link speed */
1071 spin_lock_irq(&lp->lock);
1072 enable_mdi();
775637df 1073 update_linkspeed(dev, 0);
d4b7780e
AV		 1074 disable_mdi();
1075 spin_unlock_irq(&lp->lock);
1076 netif_carrier_off(dev); /* will be enabled in open() */
1077
775637df
AV		 1078 /* If board has no PHY IRQ, use a timer to poll the PHY */
1079 if (!lp->board_data.phy_irq_pin) {
cf42553a
AV		 1080 init_timer(&lp->check_timer);
1081 lp->check_timer.data = (unsigned long)dev;
1082 lp->check_timer.function = at91ether_check_link;
775637df
AV		 1083 }
1084
d4b7780e 1085 /* Display ethernet banner */
0795af57
JP		 1086 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%s)\n",
1087 dev->name, (uint) dev->base_addr, dev->irq,
1088 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1089 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1090 print_mac(mac, dev->dev_addr));
d4b7780e 1091 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
427d269f 1092 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
d4b7780e
AV		 1093 else if (phy_type == MII_LXT971A_ID)
1094 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1095 else if (phy_type == MII_RTL8201_ID)
1096 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1097 else if (phy_type == MII_BCM5221_ID)
1098 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1099 else if (phy_type == MII_DP83847_ID)
1100 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
6b4aea73
AV		 1101 else if (phy_type == MII_DP83848_ID)
1102 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
d4b7780e
AV		 1103 else if (phy_type == MII_AC101L_ID)
1104 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1105 else if (phy_type == MII_KS8721_ID)
1106 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
6b4aea73
AV		 1107 else if (phy_type == MII_T78Q21x3_ID)
1108 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1109 else if (phy_type == MII_LAN83C185_ID)
1110 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
d4b7780e
AV		 1111
1112 return 0;
1113}
1114
1115/*
1116 * Detect MAC and PHY and perform initialization
1117 */
1118static int __init at91ether_probe(struct platform_device *pdev)
1119{
1120 unsigned int phyid1, phyid2;
1121 int detected = -1;
1122 unsigned long phy_id;
1123 unsigned short phy_address = 0;
427d269f 1124 struct clk *ether_clk;
d4b7780e
AV		 1125
1126 ether_clk = clk_get(&pdev->dev, "ether_clk");
427d269f 1127 if (IS_ERR(ether_clk)) {
d4b7780e
AV		 1128 printk(KERN_ERR "at91_ether: no clock defined\n");
1129 return -ENODEV;
1130 }
1131 clk_enable(ether_clk); /* Enable Peripheral clock */
1132
1133 while ((detected != 0) && (phy_address < 32)) {
1134 /* Read the PHY ID registers */
1135 enable_mdi();
1136 read_phy(phy_address, MII_PHYSID1, &phyid1);
1137 read_phy(phy_address, MII_PHYSID2, &phyid2);
1138 disable_mdi();
1139
1140 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1141 switch (phy_id) {
1142 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1143 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1144 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1145 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1146 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1147 case MII_DP83847_ID: /* National Semiconductor DP83847: */
6b4aea73 1148 case MII_DP83848_ID: /* National Semiconductor DP83848: */
d4b7780e
AV		 1149 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1150 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
6b4aea73
AV		 1151 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1152 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
427d269f 1153 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
d4b7780e
AV		 1154 break;
1155 }
1156
1157 phy_address++;
1158 }
1159
1160 clk_disable(ether_clk); /* Disable Peripheral clock */
1161
1162 return detected;
1163}
1164
1165static int __devexit at91ether_remove(struct platform_device *pdev)
1166{
c57ee096
AV		 1167 struct net_device *dev = platform_get_drvdata(pdev);
1168 struct at91_private *lp = netdev_priv(dev);
d4b7780e 1169
c57ee096
AV		 1170 unregister_netdev(dev);
1171 free_irq(dev->irq, dev);
d4b7780e 1172 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
427d269f 1173 clk_put(lp->ether_clk);
d4b7780e 1174
c57ee096
AV		 1175 platform_set_drvdata(pdev, NULL);
1176 free_netdev(dev);
d4b7780e
AV		 1177 return 0;
1178}
1179
00e5edcb
AV		 1180#ifdef CONFIG_PM
1181
1182static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1183{
00e5edcb 1184 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1185 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV		 1186 int phy_irq = lp->board_data.phy_irq_pin;
1187
1188 if (netif_running(net_dev)) {
1189 if (phy_irq)
1190 disable_irq(phy_irq);
1191
1192 netif_stop_queue(net_dev);
1193 netif_device_detach(net_dev);
1194
1195 clk_disable(lp->ether_clk);
1196 }
1197 return 0;
1198}
1199
1200static int at91ether_resume(struct platform_device *pdev)
1201{
00e5edcb 1202 struct net_device *net_dev = platform_get_drvdata(pdev);
c57ee096 1203 struct at91_private *lp = netdev_priv(net_dev);
00e5edcb
AV		 1204 int phy_irq = lp->board_data.phy_irq_pin;
1205
1206 if (netif_running(net_dev)) {
1207 clk_enable(lp->ether_clk);
1208
1209 netif_device_attach(net_dev);
1210 netif_start_queue(net_dev);
1211
1212 if (phy_irq)
1213 enable_irq(phy_irq);
1214 }
1215 return 0;
1216}
1217
1218#else
1219#define at91ether_suspend NULL
1220#define at91ether_resume NULL
1221#endif
1222
d4b7780e
AV		 1223static struct platform_driver at91ether_driver = {
1224 .probe = at91ether_probe,
1225 .remove = __devexit_p(at91ether_remove),
00e5edcb
AV		 1226 .suspend = at91ether_suspend,
1227 .resume = at91ether_resume,
d4b7780e
AV		 1228 .driver = {
1229 .name = DRV_NAME,
1230 .owner = THIS_MODULE,
1231 },
1232};
1233
1234static int __init at91ether_init(void)
1235{
1236 return platform_driver_register(&at91ether_driver);
1237}
1238
1239static void __exit at91ether_exit(void)
1240{
1241 platform_driver_unregister(&at91ether_driver);
1242}
1243
1244module_init(at91ether_init)
1245module_exit(at91ether_exit)
1246
1247MODULE_LICENSE("GPL");
1248MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1249MODULE_AUTHOR("Andrew Victor");
72abb461 1250MODULE_ALIAS("platform:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)