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d4b7780e AV |
1 | /* |
2 | * Ethernet driver for the Atmel AT91RM9200 (Thunder) | |
3 | * | |
4 | * Copyright (C) 2003 SAN People (Pty) Ltd | |
5 | * | |
6 | * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. | |
7 | * Initial version by Rick Bronson 01/11/2003 | |
8 | * | |
9 | * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker | |
10 | * (Polaroid Corporation) | |
11 | * | |
12 | * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License | |
16 | * as published by the Free Software Foundation; either version | |
17 | * 2 of the License, or (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
d4b7780e AV |
22 | #include <linux/mii.h> |
23 | #include <linux/netdevice.h> | |
24 | #include <linux/etherdevice.h> | |
25 | #include <linux/skbuff.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/clk.h> | |
30 | ||
31 | #include <asm/io.h> | |
32 | #include <asm/uaccess.h> | |
33 | #include <asm/mach-types.h> | |
34 | ||
a09e64fb RK |
35 | #include <mach/at91rm9200_emac.h> |
36 | #include <mach/gpio.h> | |
37 | #include <mach/board.h> | |
d4b7780e AV |
38 | |
39 | #include "at91_ether.h" | |
40 | ||
41 | #define DRV_NAME "at91_ether" | |
42 | #define DRV_VERSION "1.0" | |
43 | ||
775637df AV |
44 | #define LINK_POLL_INTERVAL (HZ) |
45 | ||
d4b7780e AV |
46 | /* ..................................................................... */ |
47 | ||
48 | /* | |
49 | * Read from a EMAC register. | |
50 | */ | |
51 | static inline unsigned long at91_emac_read(unsigned int reg) | |
52 | { | |
53 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; | |
54 | ||
55 | return __raw_readl(emac_base + reg); | |
56 | } | |
57 | ||
58 | /* | |
59 | * Write to a EMAC register. | |
60 | */ | |
61 | static inline void at91_emac_write(unsigned int reg, unsigned long value) | |
62 | { | |
63 | void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC; | |
64 | ||
65 | __raw_writel(value, emac_base + reg); | |
66 | } | |
67 | ||
68 | /* ........................... PHY INTERFACE ........................... */ | |
69 | ||
70 | /* | |
71 | * Enable the MDIO bit in MAC control register | |
72 | * When not called from an interrupt-handler, access to the PHY must be | |
73 | * protected by a spinlock. | |
74 | */ | |
75 | static void enable_mdi(void) | |
76 | { | |
77 | unsigned long ctl; | |
78 | ||
79 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
80 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */ | |
81 | } | |
82 | ||
83 | /* | |
84 | * Disable the MDIO bit in the MAC control register | |
85 | */ | |
86 | static void disable_mdi(void) | |
87 | { | |
88 | unsigned long ctl; | |
89 | ||
90 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
91 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */ | |
92 | } | |
93 | ||
94 | /* | |
95 | * Wait until the PHY operation is complete. | |
96 | */ | |
97 | static inline void at91_phy_wait(void) { | |
98 | unsigned long timeout = jiffies + 2; | |
99 | ||
100 | while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) { | |
101 | if (time_after(jiffies, timeout)) { | |
102 | printk("at91_ether: MIO timeout\n"); | |
103 | break; | |
104 | } | |
105 | cpu_relax(); | |
106 | } | |
107 | } | |
108 | ||
109 | /* | |
110 | * Write value to the a PHY register | |
111 | * Note: MDI interface is assumed to already have been enabled. | |
112 | */ | |
113 | static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value) | |
114 | { | |
115 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W | |
116 | | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA)); | |
117 | ||
118 | /* Wait until IDLE bit in Network Status register is cleared */ | |
119 | at91_phy_wait(); | |
120 | } | |
121 | ||
122 | /* | |
123 | * Read value stored in a PHY register. | |
124 | * Note: MDI interface is assumed to already have been enabled. | |
125 | */ | |
126 | static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value) | |
127 | { | |
128 | at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R | |
129 | | ((phy_addr & 0x1f) << 23) | (address << 18)); | |
130 | ||
131 | /* Wait until IDLE bit in Network Status register is cleared */ | |
132 | at91_phy_wait(); | |
133 | ||
134 | *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA; | |
135 | } | |
136 | ||
137 | /* ........................... PHY MANAGEMENT .......................... */ | |
138 | ||
139 | /* | |
140 | * Access the PHY to determine the current link speed and mode, and update the | |
141 | * MAC accordingly. | |
142 | * If no link or auto-negotiation is busy, then no changes are made. | |
143 | */ | |
775637df | 144 | static void update_linkspeed(struct net_device *dev, int silent) |
d4b7780e | 145 | { |
c57ee096 | 146 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
147 | unsigned int bmsr, bmcr, lpa, mac_cfg; |
148 | unsigned int speed, duplex; | |
149 | ||
150 | if (!mii_link_ok(&lp->mii)) { /* no link */ | |
151 | netif_carrier_off(dev); | |
775637df AV |
152 | if (!silent) |
153 | printk(KERN_INFO "%s: Link down.\n", dev->name); | |
d4b7780e AV |
154 | return; |
155 | } | |
156 | ||
157 | /* Link up, or auto-negotiation still in progress */ | |
158 | read_phy(lp->phy_address, MII_BMSR, &bmsr); | |
159 | read_phy(lp->phy_address, MII_BMCR, &bmcr); | |
160 | if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ | |
161 | if (!(bmsr & BMSR_ANEGCOMPLETE)) | |
162 | return; /* Do nothing - another interrupt generated when negotiation complete */ | |
163 | ||
164 | read_phy(lp->phy_address, MII_LPA, &lpa); | |
165 | if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; | |
166 | else speed = SPEED_10; | |
167 | if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; | |
168 | else duplex = DUPLEX_HALF; | |
169 | } else { | |
170 | speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; | |
171 | duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; | |
172 | } | |
173 | ||
174 | /* Update the MAC */ | |
175 | mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD); | |
176 | if (speed == SPEED_100) { | |
177 | if (duplex == DUPLEX_FULL) /* 100 Full Duplex */ | |
178 | mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD; | |
179 | else /* 100 Half Duplex */ | |
180 | mac_cfg |= AT91_EMAC_SPD; | |
181 | } else { | |
182 | if (duplex == DUPLEX_FULL) /* 10 Full Duplex */ | |
183 | mac_cfg |= AT91_EMAC_FD; | |
184 | else {} /* 10 Half Duplex */ | |
185 | } | |
186 | at91_emac_write(AT91_EMAC_CFG, mac_cfg); | |
187 | ||
775637df AV |
188 | if (!silent) |
189 | printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex"); | |
d4b7780e AV |
190 | netif_carrier_on(dev); |
191 | } | |
192 | ||
193 | /* | |
194 | * Handle interrupts from the PHY | |
195 | */ | |
7d12e780 | 196 | static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id) |
d4b7780e AV |
197 | { |
198 | struct net_device *dev = (struct net_device *) dev_id; | |
c57ee096 | 199 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
200 | unsigned int phy; |
201 | ||
202 | /* | |
203 | * This hander is triggered on both edges, but the PHY chips expect | |
204 | * level-triggering. We therefore have to check if the PHY actually has | |
205 | * an IRQ pending. | |
206 | */ | |
207 | enable_mdi(); | |
208 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { | |
209 | read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ | |
210 | if (!(phy & (1 << 0))) | |
211 | goto done; | |
212 | } | |
213 | else if (lp->phy_type == MII_LXT971A_ID) { | |
214 | read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ | |
215 | if (!(phy & (1 << 2))) | |
216 | goto done; | |
217 | } | |
218 | else if (lp->phy_type == MII_BCM5221_ID) { | |
219 | read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */ | |
220 | if (!(phy & (1 << 0))) | |
221 | goto done; | |
222 | } | |
223 | else if (lp->phy_type == MII_KS8721_ID) { | |
224 | read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */ | |
225 | if (!(phy & ((1 << 2) | 1))) | |
226 | goto done; | |
227 | } | |
6b4aea73 AV |
228 | else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */ |
229 | read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy); | |
230 | if (!(phy & ((1 << 2) | 1))) | |
231 | goto done; | |
232 | } | |
233 | else if (lp->phy_type == MII_DP83848_ID) { | |
234 | read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */ | |
235 | if (!(phy & (1 << 7))) | |
236 | goto done; | |
237 | } | |
d4b7780e | 238 | |
775637df | 239 | update_linkspeed(dev, 0); |
d4b7780e AV |
240 | |
241 | done: | |
242 | disable_mdi(); | |
243 | ||
244 | return IRQ_HANDLED; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Initialize and enable the PHY interrupt for link-state changes | |
249 | */ | |
250 | static void enable_phyirq(struct net_device *dev) | |
251 | { | |
c57ee096 | 252 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
253 | unsigned int dsintr, irq_number; |
254 | int status; | |
255 | ||
775637df AV |
256 | irq_number = lp->board_data.phy_irq_pin; |
257 | if (!irq_number) { | |
258 | /* | |
259 | * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L), | |
260 | * or board does not have it connected. | |
261 | */ | |
cf42553a | 262 | mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); |
d4b7780e | 263 | return; |
775637df | 264 | } |
d4b7780e | 265 | |
d4b7780e AV |
266 | status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev); |
267 | if (status) { | |
268 | printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status); | |
269 | return; | |
270 | } | |
271 | ||
272 | spin_lock_irq(&lp->lock); | |
273 | enable_mdi(); | |
274 | ||
275 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ | |
276 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); | |
277 | dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ | |
278 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); | |
279 | } | |
280 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ | |
281 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); | |
282 | dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ | |
283 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); | |
284 | } | |
285 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ | |
286 | dsintr = (1 << 15) | ( 1 << 14); | |
287 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); | |
288 | } | |
289 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ | |
290 | dsintr = (1 << 10) | ( 1 << 8); | |
291 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); | |
292 | } | |
6b4aea73 AV |
293 | else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ |
294 | read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); | |
295 | dsintr = dsintr | 0x500; /* set bits 8, 10 */ | |
296 | write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); | |
297 | } | |
298 | else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ | |
299 | read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); | |
300 | dsintr = dsintr | 0x3c; /* set bits 2..5 */ | |
301 | write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); | |
302 | read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); | |
303 | dsintr = dsintr | 0x3; /* set bits 0,1 */ | |
304 | write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); | |
305 | } | |
d4b7780e AV |
306 | |
307 | disable_mdi(); | |
308 | spin_unlock_irq(&lp->lock); | |
309 | } | |
310 | ||
311 | /* | |
312 | * Disable the PHY interrupt | |
313 | */ | |
314 | static void disable_phyirq(struct net_device *dev) | |
315 | { | |
c57ee096 | 316 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
317 | unsigned int dsintr; |
318 | unsigned int irq_number; | |
319 | ||
775637df AV |
320 | irq_number = lp->board_data.phy_irq_pin; |
321 | if (!irq_number) { | |
cf42553a | 322 | del_timer_sync(&lp->check_timer); |
d4b7780e | 323 | return; |
775637df | 324 | } |
d4b7780e AV |
325 | |
326 | spin_lock_irq(&lp->lock); | |
327 | enable_mdi(); | |
328 | ||
329 | if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */ | |
330 | read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr); | |
331 | dsintr = dsintr | 0xf00; /* set bits 8..11 */ | |
332 | write_phy(lp->phy_address, MII_DSINTR_REG, dsintr); | |
333 | } | |
334 | else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ | |
335 | read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr); | |
336 | dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ | |
337 | write_phy(lp->phy_address, MII_ISINTE_REG, dsintr); | |
338 | } | |
339 | else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */ | |
340 | read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr); | |
341 | dsintr = ~(1 << 14); | |
342 | write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr); | |
343 | } | |
344 | else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */ | |
345 | read_phy(lp->phy_address, MII_TPISTATUS, &dsintr); | |
346 | dsintr = ~((1 << 10) | (1 << 8)); | |
347 | write_phy(lp->phy_address, MII_TPISTATUS, dsintr); | |
348 | } | |
6b4aea73 AV |
349 | else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */ |
350 | read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr); | |
351 | dsintr = dsintr & ~0x500; /* clear bits 8, 10 */ | |
352 | write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr); | |
353 | } | |
354 | else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */ | |
355 | read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr); | |
356 | dsintr = dsintr & ~0x3; /* clear bits 0, 1 */ | |
357 | write_phy(lp->phy_address, MII_DPMICR_REG, dsintr); | |
358 | read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr); | |
359 | dsintr = dsintr & ~0x3c; /* clear bits 2..5 */ | |
360 | write_phy(lp->phy_address, MII_DPMISR_REG, dsintr); | |
361 | } | |
d4b7780e AV |
362 | |
363 | disable_mdi(); | |
364 | spin_unlock_irq(&lp->lock); | |
365 | ||
d4b7780e AV |
366 | free_irq(irq_number, dev); /* Free interrupt handler */ |
367 | } | |
368 | ||
369 | /* | |
370 | * Perform a software reset of the PHY. | |
371 | */ | |
372 | #if 0 | |
373 | static void reset_phy(struct net_device *dev) | |
374 | { | |
c57ee096 | 375 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
376 | unsigned int bmcr; |
377 | ||
378 | spin_lock_irq(&lp->lock); | |
379 | enable_mdi(); | |
380 | ||
381 | /* Perform PHY reset */ | |
382 | write_phy(lp->phy_address, MII_BMCR, BMCR_RESET); | |
383 | ||
384 | /* Wait until PHY reset is complete */ | |
385 | do { | |
386 | read_phy(lp->phy_address, MII_BMCR, &bmcr); | |
10a5a80b | 387 | } while (!(bmcr & BMCR_RESET)); |
d4b7780e AV |
388 | |
389 | disable_mdi(); | |
390 | spin_unlock_irq(&lp->lock); | |
391 | } | |
392 | #endif | |
393 | ||
775637df AV |
394 | static void at91ether_check_link(unsigned long dev_id) |
395 | { | |
396 | struct net_device *dev = (struct net_device *) dev_id; | |
cf42553a | 397 | struct at91_private *lp = netdev_priv(dev); |
775637df AV |
398 | |
399 | enable_mdi(); | |
400 | update_linkspeed(dev, 1); | |
401 | disable_mdi(); | |
402 | ||
cf42553a | 403 | mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL); |
775637df AV |
404 | } |
405 | ||
d4b7780e AV |
406 | /* ......................... ADDRESS MANAGEMENT ........................ */ |
407 | ||
408 | /* | |
409 | * NOTE: Your bootloader must always set the MAC address correctly before | |
410 | * booting into Linux. | |
411 | * | |
412 | * - It must always set the MAC address after reset, even if it doesn't | |
413 | * happen to access the Ethernet while it's booting. Some versions of | |
414 | * U-Boot on the AT91RM9200-DK do not do this. | |
415 | * | |
416 | * - Likewise it must store the addresses in the correct byte order. | |
417 | * MicroMonitor (uMon) on the CSB337 does this incorrectly (and | |
418 | * continues to do so, for bug-compatibility). | |
419 | */ | |
420 | ||
421 | static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo) | |
422 | { | |
423 | char addr[6]; | |
424 | ||
425 | if (machine_is_csb337()) { | |
426 | addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */ | |
427 | addr[4] = (lo & 0xff00) >> 8; | |
428 | addr[3] = (lo & 0xff0000) >> 16; | |
429 | addr[2] = (lo & 0xff000000) >> 24; | |
430 | addr[1] = (hi & 0xff); | |
431 | addr[0] = (hi & 0xff00) >> 8; | |
432 | } | |
433 | else { | |
434 | addr[0] = (lo & 0xff); | |
435 | addr[1] = (lo & 0xff00) >> 8; | |
436 | addr[2] = (lo & 0xff0000) >> 16; | |
437 | addr[3] = (lo & 0xff000000) >> 24; | |
438 | addr[4] = (hi & 0xff); | |
439 | addr[5] = (hi & 0xff00) >> 8; | |
440 | } | |
441 | ||
442 | if (is_valid_ether_addr(addr)) { | |
443 | memcpy(dev->dev_addr, &addr, 6); | |
444 | return 1; | |
445 | } | |
446 | return 0; | |
447 | } | |
448 | ||
449 | /* | |
450 | * Set the ethernet MAC address in dev->dev_addr | |
451 | */ | |
452 | static void __init get_mac_address(struct net_device *dev) | |
453 | { | |
454 | /* Check Specific-Address 1 */ | |
455 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L))) | |
456 | return; | |
457 | /* Check Specific-Address 2 */ | |
458 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L))) | |
459 | return; | |
460 | /* Check Specific-Address 3 */ | |
461 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L))) | |
462 | return; | |
463 | /* Check Specific-Address 4 */ | |
464 | if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L))) | |
465 | return; | |
466 | ||
467 | printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n"); | |
468 | } | |
469 | ||
470 | /* | |
471 | * Program the hardware MAC address from dev->dev_addr. | |
472 | */ | |
473 | static void update_mac_address(struct net_device *dev) | |
474 | { | |
475 | at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0])); | |
476 | at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4])); | |
477 | ||
478 | at91_emac_write(AT91_EMAC_SA2L, 0); | |
479 | at91_emac_write(AT91_EMAC_SA2H, 0); | |
480 | } | |
481 | ||
482 | /* | |
483 | * Store the new hardware address in dev->dev_addr, and update the MAC. | |
484 | */ | |
485 | static int set_mac_address(struct net_device *dev, void* addr) | |
486 | { | |
487 | struct sockaddr *address = addr; | |
488 | ||
489 | if (!is_valid_ether_addr(address->sa_data)) | |
490 | return -EADDRNOTAVAIL; | |
491 | ||
492 | memcpy(dev->dev_addr, address->sa_data, dev->addr_len); | |
493 | update_mac_address(dev); | |
494 | ||
e174961c JB |
495 | printk("%s: Setting MAC address to %pM\n", dev->name, |
496 | dev->dev_addr); | |
d4b7780e AV |
497 | |
498 | return 0; | |
499 | } | |
500 | ||
501 | static int inline hash_bit_value(int bitnr, __u8 *addr) | |
502 | { | |
503 | if (addr[bitnr / 8] & (1 << (bitnr % 8))) | |
504 | return 1; | |
505 | return 0; | |
506 | } | |
507 | ||
508 | /* | |
509 | * The hash address register is 64 bits long and takes up two locations in the memory map. | |
510 | * The least significant bits are stored in EMAC_HSL and the most significant | |
511 | * bits in EMAC_HSH. | |
512 | * | |
513 | * The unicast hash enable and the multicast hash enable bits in the network configuration | |
514 | * register enable the reception of hash matched frames. The destination address is | |
515 | * reduced to a 6 bit index into the 64 bit hash register using the following hash function. | |
516 | * The hash function is an exclusive or of every sixth bit of the destination address. | |
517 | * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] | |
518 | * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] | |
519 | * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] | |
520 | * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] | |
521 | * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] | |
522 | * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] | |
523 | * da[0] represents the least significant bit of the first byte received, that is, the multicast/ | |
524 | * unicast indicator, and da[47] represents the most significant bit of the last byte | |
525 | * received. | |
526 | * If the hash index points to a bit that is set in the hash register then the frame will be | |
527 | * matched according to whether the frame is multicast or unicast. | |
528 | * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and | |
529 | * the hash index points to a bit set in the hash register. | |
530 | * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the | |
531 | * hash index points to a bit set in the hash register. | |
532 | * To receive all multicast frames, the hash register should be set with all ones and the | |
533 | * multicast hash enable bit should be set in the network configuration register. | |
534 | */ | |
535 | ||
536 | /* | |
537 | * Return the hash index value for the specified address. | |
538 | */ | |
539 | static int hash_get_index(__u8 *addr) | |
540 | { | |
541 | int i, j, bitval; | |
542 | int hash_index = 0; | |
543 | ||
544 | for (j = 0; j < 6; j++) { | |
545 | for (i = 0, bitval = 0; i < 8; i++) | |
546 | bitval ^= hash_bit_value(i*6 + j, addr); | |
547 | ||
548 | hash_index |= (bitval << j); | |
549 | } | |
550 | ||
427d269f | 551 | return hash_index; |
d4b7780e AV |
552 | } |
553 | ||
554 | /* | |
555 | * Add multicast addresses to the internal multicast-hash table. | |
556 | */ | |
557 | static void at91ether_sethashtable(struct net_device *dev) | |
558 | { | |
22bedad3 | 559 | struct netdev_hw_addr *ha; |
d4b7780e | 560 | unsigned long mc_filter[2]; |
3b9a7728 | 561 | unsigned int bitnr; |
d4b7780e AV |
562 | |
563 | mc_filter[0] = mc_filter[1] = 0; | |
564 | ||
22bedad3 JP |
565 | netdev_for_each_mc_addr(ha, dev) { |
566 | bitnr = hash_get_index(ha->addr); | |
d4b7780e AV |
567 | mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); |
568 | } | |
569 | ||
8bc35473 AV |
570 | at91_emac_write(AT91_EMAC_HSL, mc_filter[0]); |
571 | at91_emac_write(AT91_EMAC_HSH, mc_filter[1]); | |
d4b7780e AV |
572 | } |
573 | ||
574 | /* | |
575 | * Enable/Disable promiscuous and multicast modes. | |
576 | */ | |
531c6804 | 577 | static void at91ether_set_multicast_list(struct net_device *dev) |
d4b7780e AV |
578 | { |
579 | unsigned long cfg; | |
580 | ||
581 | cfg = at91_emac_read(AT91_EMAC_CFG); | |
582 | ||
583 | if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */ | |
584 | cfg |= AT91_EMAC_CAF; | |
585 | else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */ | |
586 | cfg &= ~AT91_EMAC_CAF; | |
587 | ||
588 | if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */ | |
589 | at91_emac_write(AT91_EMAC_HSH, -1); | |
590 | at91_emac_write(AT91_EMAC_HSL, -1); | |
591 | cfg |= AT91_EMAC_MTI; | |
4cd24eaf | 592 | } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */ |
d4b7780e AV |
593 | at91ether_sethashtable(dev); |
594 | cfg |= AT91_EMAC_MTI; | |
595 | } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */ | |
596 | at91_emac_write(AT91_EMAC_HSH, 0); | |
597 | at91_emac_write(AT91_EMAC_HSL, 0); | |
598 | cfg &= ~AT91_EMAC_MTI; | |
599 | } | |
600 | ||
601 | at91_emac_write(AT91_EMAC_CFG, cfg); | |
602 | } | |
603 | ||
d4b7780e AV |
604 | /* ......................... ETHTOOL SUPPORT ........................... */ |
605 | ||
d4b7780e AV |
606 | static int mdio_read(struct net_device *dev, int phy_id, int location) |
607 | { | |
608 | unsigned int value; | |
609 | ||
610 | read_phy(phy_id, location, &value); | |
611 | return value; | |
612 | } | |
613 | ||
614 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
615 | { | |
616 | write_phy(phy_id, location, value); | |
617 | } | |
618 | ||
619 | static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
620 | { | |
c57ee096 | 621 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
622 | int ret; |
623 | ||
624 | spin_lock_irq(&lp->lock); | |
625 | enable_mdi(); | |
626 | ||
627 | ret = mii_ethtool_gset(&lp->mii, cmd); | |
628 | ||
629 | disable_mdi(); | |
630 | spin_unlock_irq(&lp->lock); | |
631 | ||
632 | if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ | |
633 | cmd->supported = SUPPORTED_FIBRE; | |
634 | cmd->port = PORT_FIBRE; | |
635 | } | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
641 | { | |
c57ee096 | 642 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
643 | int ret; |
644 | ||
645 | spin_lock_irq(&lp->lock); | |
646 | enable_mdi(); | |
647 | ||
648 | ret = mii_ethtool_sset(&lp->mii, cmd); | |
649 | ||
650 | disable_mdi(); | |
651 | spin_unlock_irq(&lp->lock); | |
652 | ||
653 | return ret; | |
654 | } | |
655 | ||
656 | static int at91ether_nwayreset(struct net_device *dev) | |
657 | { | |
c57ee096 | 658 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
659 | int ret; |
660 | ||
661 | spin_lock_irq(&lp->lock); | |
662 | enable_mdi(); | |
663 | ||
664 | ret = mii_nway_restart(&lp->mii); | |
665 | ||
666 | disable_mdi(); | |
667 | spin_unlock_irq(&lp->lock); | |
668 | ||
669 | return ret; | |
670 | } | |
671 | ||
672 | static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
673 | { | |
674 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); | |
675 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
3f978704 | 676 | strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info)); |
d4b7780e AV |
677 | } |
678 | ||
7282d491 | 679 | static const struct ethtool_ops at91ether_ethtool_ops = { |
d4b7780e AV |
680 | .get_settings = at91ether_get_settings, |
681 | .set_settings = at91ether_set_settings, | |
682 | .get_drvinfo = at91ether_get_drvinfo, | |
683 | .nway_reset = at91ether_nwayreset, | |
684 | .get_link = ethtool_op_get_link, | |
685 | }; | |
686 | ||
ca5585ed AV |
687 | static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
688 | { | |
c57ee096 | 689 | struct at91_private *lp = netdev_priv(dev); |
ca5585ed AV |
690 | int res; |
691 | ||
692 | if (!netif_running(dev)) | |
693 | return -EINVAL; | |
694 | ||
695 | spin_lock_irq(&lp->lock); | |
696 | enable_mdi(); | |
697 | res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL); | |
698 | disable_mdi(); | |
699 | spin_unlock_irq(&lp->lock); | |
700 | ||
701 | return res; | |
702 | } | |
d4b7780e AV |
703 | |
704 | /* ................................ MAC ................................ */ | |
705 | ||
706 | /* | |
707 | * Initialize and start the Receiver and Transmit subsystems | |
708 | */ | |
709 | static void at91ether_start(struct net_device *dev) | |
710 | { | |
c57ee096 | 711 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
712 | struct recv_desc_bufs *dlist, *dlist_phys; |
713 | int i; | |
714 | unsigned long ctl; | |
715 | ||
716 | dlist = lp->dlist; | |
717 | dlist_phys = lp->dlist_phys; | |
718 | ||
719 | for (i = 0; i < MAX_RX_DESCR; i++) { | |
720 | dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0]; | |
721 | dlist->descriptors[i].size = 0; | |
722 | } | |
723 | ||
724 | /* Set the Wrap bit on the last descriptor */ | |
725 | dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP; | |
726 | ||
727 | /* Reset buffer index */ | |
728 | lp->rxBuffIndex = 0; | |
729 | ||
730 | /* Program address of descriptor list in Rx Buffer Queue register */ | |
731 | at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys); | |
732 | ||
733 | /* Enable Receive and Transmit */ | |
734 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
735 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE); | |
736 | } | |
737 | ||
738 | /* | |
739 | * Open the ethernet interface | |
740 | */ | |
741 | static int at91ether_open(struct net_device *dev) | |
742 | { | |
c57ee096 | 743 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
744 | unsigned long ctl; |
745 | ||
427d269f AV |
746 | if (!is_valid_ether_addr(dev->dev_addr)) |
747 | return -EADDRNOTAVAIL; | |
d4b7780e | 748 | |
427d269f | 749 | clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */ |
d4b7780e AV |
750 | |
751 | /* Clear internal statistics */ | |
752 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
753 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); | |
754 | ||
755 | /* Update the MAC address (incase user has changed it) */ | |
756 | update_mac_address(dev); | |
757 | ||
758 | /* Enable PHY interrupt */ | |
759 | enable_phyirq(dev); | |
760 | ||
761 | /* Enable MAC interrupts */ | |
762 | at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA | |
763 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM | |
764 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); | |
765 | ||
766 | /* Determine current link speed */ | |
767 | spin_lock_irq(&lp->lock); | |
768 | enable_mdi(); | |
775637df | 769 | update_linkspeed(dev, 0); |
d4b7780e AV |
770 | disable_mdi(); |
771 | spin_unlock_irq(&lp->lock); | |
772 | ||
773 | at91ether_start(dev); | |
774 | netif_start_queue(dev); | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /* | |
779 | * Close the interface | |
780 | */ | |
781 | static int at91ether_close(struct net_device *dev) | |
782 | { | |
c57ee096 | 783 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
784 | unsigned long ctl; |
785 | ||
786 | /* Disable Receiver and Transmitter */ | |
787 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
788 | at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE)); | |
789 | ||
790 | /* Disable PHY interrupt */ | |
791 | disable_phyirq(dev); | |
792 | ||
793 | /* Disable MAC interrupts */ | |
794 | at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA | |
795 | | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM | |
796 | | AT91_EMAC_ROVR | AT91_EMAC_ABT); | |
797 | ||
798 | netif_stop_queue(dev); | |
799 | ||
427d269f | 800 | clk_disable(lp->ether_clk); /* Disable Peripheral clock */ |
d4b7780e AV |
801 | |
802 | return 0; | |
803 | } | |
804 | ||
805 | /* | |
806 | * Transmit packet. | |
807 | */ | |
531c6804 | 808 | static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev) |
d4b7780e | 809 | { |
c57ee096 | 810 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
811 | |
812 | if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) { | |
813 | netif_stop_queue(dev); | |
814 | ||
815 | /* Store packet information (to free when Tx completed) */ | |
816 | lp->skb = skb; | |
817 | lp->skb_length = skb->len; | |
818 | lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); | |
7a2f53ee | 819 | dev->stats.tx_bytes += skb->len; |
d4b7780e AV |
820 | |
821 | /* Set address of the data in the Transmit Address register */ | |
822 | at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr); | |
823 | /* Set length of the packet in the Transmit Control register */ | |
824 | at91_emac_write(AT91_EMAC_TCR, skb->len); | |
825 | ||
826 | dev->trans_start = jiffies; | |
827 | } else { | |
531c6804 | 828 | printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n"); |
5b548140 | 829 | return NETDEV_TX_BUSY; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb) |
d4b7780e AV |
830 | on this skb, he also reports -ENETDOWN and printk's, so either |
831 | we free and return(0) or don't free and return 1 */ | |
832 | } | |
833 | ||
6ed10654 | 834 | return NETDEV_TX_OK; |
d4b7780e AV |
835 | } |
836 | ||
837 | /* | |
838 | * Update the current statistics from the internal statistics registers. | |
839 | */ | |
840 | static struct net_device_stats *at91ether_stats(struct net_device *dev) | |
841 | { | |
d4b7780e AV |
842 | int ale, lenerr, seqe, lcol, ecol; |
843 | ||
844 | if (netif_running(dev)) { | |
7a2f53ee | 845 | dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */ |
d4b7780e | 846 | ale = at91_emac_read(AT91_EMAC_ALE); |
7a2f53ee | 847 | dev->stats.rx_frame_errors += ale; /* Alignment errors */ |
d4b7780e | 848 | lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF); |
7a2f53ee | 849 | dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ |
d4b7780e | 850 | seqe = at91_emac_read(AT91_EMAC_SEQE); |
7a2f53ee PZ |
851 | dev->stats.rx_crc_errors += seqe; /* CRC error */ |
852 | dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */ | |
853 | dev->stats.rx_errors += (ale + lenerr + seqe | |
d4b7780e AV |
854 | + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB)); |
855 | ||
7a2f53ee PZ |
856 | dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */ |
857 | dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */ | |
858 | dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */ | |
859 | dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */ | |
d4b7780e AV |
860 | |
861 | lcol = at91_emac_read(AT91_EMAC_LCOL); | |
862 | ecol = at91_emac_read(AT91_EMAC_ECOL); | |
7a2f53ee PZ |
863 | dev->stats.tx_window_errors += lcol; /* Late collisions */ |
864 | dev->stats.tx_aborted_errors += ecol; /* 16 collisions */ | |
d4b7780e | 865 | |
7a2f53ee | 866 | dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol); |
d4b7780e | 867 | } |
7a2f53ee | 868 | return &dev->stats; |
d4b7780e AV |
869 | } |
870 | ||
871 | /* | |
872 | * Extract received frame from buffer descriptors and sent to upper layers. | |
873 | * (Called from interrupt context) | |
874 | */ | |
875 | static void at91ether_rx(struct net_device *dev) | |
876 | { | |
c57ee096 | 877 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
878 | struct recv_desc_bufs *dlist; |
879 | unsigned char *p_recv; | |
880 | struct sk_buff *skb; | |
881 | unsigned int pktlen; | |
882 | ||
883 | dlist = lp->dlist; | |
884 | while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) { | |
885 | p_recv = dlist->recv_buf[lp->rxBuffIndex]; | |
886 | pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */ | |
a3f63e4f | 887 | skb = dev_alloc_skb(pktlen + 2); |
d4b7780e AV |
888 | if (skb != NULL) { |
889 | skb_reserve(skb, 2); | |
890 | memcpy(skb_put(skb, pktlen), p_recv, pktlen); | |
891 | ||
d4b7780e | 892 | skb->protocol = eth_type_trans(skb, dev); |
7a2f53ee | 893 | dev->stats.rx_bytes += pktlen; |
d4b7780e AV |
894 | netif_rx(skb); |
895 | } | |
896 | else { | |
7a2f53ee | 897 | dev->stats.rx_dropped += 1; |
d4b7780e AV |
898 | printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); |
899 | } | |
900 | ||
901 | if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST) | |
7a2f53ee | 902 | dev->stats.multicast++; |
d4b7780e AV |
903 | |
904 | dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ | |
905 | if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */ | |
906 | lp->rxBuffIndex = 0; | |
907 | else | |
908 | lp->rxBuffIndex++; | |
909 | } | |
910 | } | |
911 | ||
912 | /* | |
913 | * MAC interrupt handler | |
914 | */ | |
7d12e780 | 915 | static irqreturn_t at91ether_interrupt(int irq, void *dev_id) |
d4b7780e AV |
916 | { |
917 | struct net_device *dev = (struct net_device *) dev_id; | |
c57ee096 | 918 | struct at91_private *lp = netdev_priv(dev); |
d4b7780e AV |
919 | unsigned long intstatus, ctl; |
920 | ||
921 | /* MAC Interrupt Status register indicates what interrupts are pending. | |
922 | It is automatically cleared once read. */ | |
923 | intstatus = at91_emac_read(AT91_EMAC_ISR); | |
924 | ||
925 | if (intstatus & AT91_EMAC_RCOM) /* Receive complete */ | |
926 | at91ether_rx(dev); | |
927 | ||
427d269f | 928 | if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */ |
d4b7780e AV |
929 | /* The TCOM bit is set even if the transmission failed. */ |
930 | if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY)) | |
7a2f53ee | 931 | dev->stats.tx_errors += 1; |
d4b7780e AV |
932 | |
933 | if (lp->skb) { | |
934 | dev_kfree_skb_irq(lp->skb); | |
935 | lp->skb = NULL; | |
936 | dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE); | |
937 | } | |
938 | netif_wake_queue(dev); | |
939 | } | |
940 | ||
941 | /* Work-around for Errata #11 */ | |
942 | if (intstatus & AT91_EMAC_RBNA) { | |
943 | ctl = at91_emac_read(AT91_EMAC_CTL); | |
944 | at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE); | |
945 | at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE); | |
946 | } | |
947 | ||
948 | if (intstatus & AT91_EMAC_ROVR) | |
949 | printk("%s: ROVR error\n", dev->name); | |
950 | ||
951 | return IRQ_HANDLED; | |
952 | } | |
953 | ||
51cc2104 AV |
954 | #ifdef CONFIG_NET_POLL_CONTROLLER |
955 | static void at91ether_poll_controller(struct net_device *dev) | |
956 | { | |
957 | unsigned long flags; | |
958 | ||
959 | local_irq_save(flags); | |
960 | at91ether_interrupt(dev->irq, dev); | |
961 | local_irq_restore(flags); | |
962 | } | |
963 | #endif | |
964 | ||
531c6804 AB |
965 | static const struct net_device_ops at91ether_netdev_ops = { |
966 | .ndo_open = at91ether_open, | |
967 | .ndo_stop = at91ether_close, | |
968 | .ndo_start_xmit = at91ether_start_xmit, | |
969 | .ndo_get_stats = at91ether_stats, | |
970 | .ndo_set_multicast_list = at91ether_set_multicast_list, | |
971 | .ndo_set_mac_address = set_mac_address, | |
972 | .ndo_do_ioctl = at91ether_ioctl, | |
973 | .ndo_validate_addr = eth_validate_addr, | |
974 | .ndo_change_mtu = eth_change_mtu, | |
975 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
976 | .ndo_poll_controller = at91ether_poll_controller, | |
977 | #endif | |
978 | }; | |
979 | ||
d4b7780e AV |
980 | /* |
981 | * Initialize the ethernet interface | |
982 | */ | |
427d269f AV |
983 | static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, |
984 | struct platform_device *pdev, struct clk *ether_clk) | |
d4b7780e AV |
985 | { |
986 | struct at91_eth_data *board_data = pdev->dev.platform_data; | |
987 | struct net_device *dev; | |
988 | struct at91_private *lp; | |
989 | unsigned int val; | |
990 | int res; | |
991 | ||
d4b7780e AV |
992 | dev = alloc_etherdev(sizeof(struct at91_private)); |
993 | if (!dev) | |
994 | return -ENOMEM; | |
995 | ||
996 | dev->base_addr = AT91_VA_BASE_EMAC; | |
72729910 | 997 | dev->irq = AT91RM9200_ID_EMAC; |
d4b7780e AV |
998 | |
999 | /* Install the interrupt handler */ | |
1000 | if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) { | |
1001 | free_netdev(dev); | |
1002 | return -EBUSY; | |
1003 | } | |
1004 | ||
1005 | /* Allocate memory for DMA Receive descriptors */ | |
c57ee096 | 1006 | lp = netdev_priv(dev); |
d4b7780e AV |
1007 | lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL); |
1008 | if (lp->dlist == NULL) { | |
1009 | free_irq(dev->irq, dev); | |
1010 | free_netdev(dev); | |
1011 | return -ENOMEM; | |
1012 | } | |
1013 | lp->board_data = *board_data; | |
427d269f | 1014 | lp->ether_clk = ether_clk; |
d4b7780e AV |
1015 | platform_set_drvdata(pdev, dev); |
1016 | ||
1017 | spin_lock_init(&lp->lock); | |
1018 | ||
1019 | ether_setup(dev); | |
531c6804 | 1020 | dev->netdev_ops = &at91ether_netdev_ops; |
d4b7780e AV |
1021 | dev->ethtool_ops = &at91ether_ethtool_ops; |
1022 | ||
1023 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1024 | ||
1025 | get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ | |
1026 | update_mac_address(dev); /* Program ethernet address into MAC */ | |
1027 | ||
1028 | at91_emac_write(AT91_EMAC_CTL, 0); | |
1029 | ||
1030 | if (lp->board_data.is_rmii) | |
1031 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII); | |
1032 | else | |
1033 | at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG); | |
1034 | ||
1035 | /* Perform PHY-specific initialization */ | |
1036 | spin_lock_irq(&lp->lock); | |
1037 | enable_mdi(); | |
1038 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { | |
1039 | read_phy(phy_address, MII_DSCR_REG, &val); | |
1040 | if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ | |
1041 | lp->phy_media = PORT_FIBRE; | |
1042 | } else if (machine_is_csb337()) { | |
1043 | /* mix link activity status into LED2 link state */ | |
1044 | write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22); | |
2f036ac6 AV |
1045 | } else if (machine_is_ecbat91()) |
1046 | write_phy(phy_address, MII_LEDCTRL_REG, 0x156A); | |
1047 | ||
d4b7780e AV |
1048 | disable_mdi(); |
1049 | spin_unlock_irq(&lp->lock); | |
1050 | ||
1051 | lp->mii.dev = dev; /* Support for ethtool */ | |
1052 | lp->mii.mdio_read = mdio_read; | |
1053 | lp->mii.mdio_write = mdio_write; | |
ca5585ed AV |
1054 | lp->mii.phy_id = phy_address; |
1055 | lp->mii.phy_id_mask = 0x1f; | |
1056 | lp->mii.reg_num_mask = 0x1f; | |
d4b7780e AV |
1057 | |
1058 | lp->phy_type = phy_type; /* Type of PHY connected */ | |
1059 | lp->phy_address = phy_address; /* MDI address of PHY */ | |
1060 | ||
1061 | /* Register the network interface */ | |
1062 | res = register_netdev(dev); | |
1063 | if (res) { | |
1064 | free_irq(dev->irq, dev); | |
1065 | free_netdev(dev); | |
1066 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); | |
1067 | return res; | |
1068 | } | |
d4b7780e AV |
1069 | |
1070 | /* Determine current link speed */ | |
1071 | spin_lock_irq(&lp->lock); | |
1072 | enable_mdi(); | |
775637df | 1073 | update_linkspeed(dev, 0); |
d4b7780e AV |
1074 | disable_mdi(); |
1075 | spin_unlock_irq(&lp->lock); | |
1076 | netif_carrier_off(dev); /* will be enabled in open() */ | |
1077 | ||
775637df AV |
1078 | /* If board has no PHY IRQ, use a timer to poll the PHY */ |
1079 | if (!lp->board_data.phy_irq_pin) { | |
cf42553a AV |
1080 | init_timer(&lp->check_timer); |
1081 | lp->check_timer.data = (unsigned long)dev; | |
1082 | lp->check_timer.function = at91ether_check_link; | |
71527ef4 DB |
1083 | } else if (lp->board_data.phy_irq_pin >= 32) |
1084 | gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy"); | |
775637df | 1085 | |
d4b7780e | 1086 | /* Display ethernet banner */ |
e174961c | 1087 | printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n", |
0795af57 JP |
1088 | dev->name, (uint) dev->base_addr, dev->irq, |
1089 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-", | |
1090 | at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex", | |
e174961c | 1091 | dev->dev_addr); |
d4b7780e | 1092 | if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) |
427d269f | 1093 | printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); |
d4b7780e AV |
1094 | else if (phy_type == MII_LXT971A_ID) |
1095 | printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); | |
1096 | else if (phy_type == MII_RTL8201_ID) | |
1097 | printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name); | |
1098 | else if (phy_type == MII_BCM5221_ID) | |
1099 | printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); | |
1100 | else if (phy_type == MII_DP83847_ID) | |
1101 | printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); | |
6b4aea73 AV |
1102 | else if (phy_type == MII_DP83848_ID) |
1103 | printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name); | |
d4b7780e AV |
1104 | else if (phy_type == MII_AC101L_ID) |
1105 | printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); | |
1106 | else if (phy_type == MII_KS8721_ID) | |
1107 | printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); | |
6b4aea73 AV |
1108 | else if (phy_type == MII_T78Q21x3_ID) |
1109 | printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name); | |
1110 | else if (phy_type == MII_LAN83C185_ID) | |
1111 | printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name); | |
d4b7780e AV |
1112 | |
1113 | return 0; | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * Detect MAC and PHY and perform initialization | |
1118 | */ | |
1119 | static int __init at91ether_probe(struct platform_device *pdev) | |
1120 | { | |
1121 | unsigned int phyid1, phyid2; | |
1122 | int detected = -1; | |
1123 | unsigned long phy_id; | |
1124 | unsigned short phy_address = 0; | |
427d269f | 1125 | struct clk *ether_clk; |
d4b7780e AV |
1126 | |
1127 | ether_clk = clk_get(&pdev->dev, "ether_clk"); | |
427d269f | 1128 | if (IS_ERR(ether_clk)) { |
d4b7780e AV |
1129 | printk(KERN_ERR "at91_ether: no clock defined\n"); |
1130 | return -ENODEV; | |
1131 | } | |
1132 | clk_enable(ether_clk); /* Enable Peripheral clock */ | |
1133 | ||
1134 | while ((detected != 0) && (phy_address < 32)) { | |
1135 | /* Read the PHY ID registers */ | |
1136 | enable_mdi(); | |
1137 | read_phy(phy_address, MII_PHYSID1, &phyid1); | |
1138 | read_phy(phy_address, MII_PHYSID2, &phyid2); | |
1139 | disable_mdi(); | |
1140 | ||
1141 | phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); | |
1142 | switch (phy_id) { | |
1143 | case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ | |
1144 | case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ | |
1145 | case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */ | |
1146 | case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ | |
1147 | case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ | |
1148 | case MII_DP83847_ID: /* National Semiconductor DP83847: */ | |
6b4aea73 | 1149 | case MII_DP83848_ID: /* National Semiconductor DP83848: */ |
d4b7780e AV |
1150 | case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ |
1151 | case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ | |
6b4aea73 AV |
1152 | case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */ |
1153 | case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */ | |
427d269f | 1154 | detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); |
d4b7780e AV |
1155 | break; |
1156 | } | |
1157 | ||
1158 | phy_address++; | |
1159 | } | |
1160 | ||
1161 | clk_disable(ether_clk); /* Disable Peripheral clock */ | |
1162 | ||
1163 | return detected; | |
1164 | } | |
1165 | ||
1166 | static int __devexit at91ether_remove(struct platform_device *pdev) | |
1167 | { | |
c57ee096 AV |
1168 | struct net_device *dev = platform_get_drvdata(pdev); |
1169 | struct at91_private *lp = netdev_priv(dev); | |
d4b7780e | 1170 | |
71527ef4 DB |
1171 | if (lp->board_data.phy_irq_pin >= 32) |
1172 | gpio_free(lp->board_data.phy_irq_pin); | |
1173 | ||
c57ee096 AV |
1174 | unregister_netdev(dev); |
1175 | free_irq(dev->irq, dev); | |
d4b7780e | 1176 | dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys); |
427d269f | 1177 | clk_put(lp->ether_clk); |
d4b7780e | 1178 | |
c57ee096 AV |
1179 | platform_set_drvdata(pdev, NULL); |
1180 | free_netdev(dev); | |
d4b7780e AV |
1181 | return 0; |
1182 | } | |
1183 | ||
00e5edcb AV |
1184 | #ifdef CONFIG_PM |
1185 | ||
1186 | static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1187 | { | |
00e5edcb | 1188 | struct net_device *net_dev = platform_get_drvdata(pdev); |
c57ee096 | 1189 | struct at91_private *lp = netdev_priv(net_dev); |
00e5edcb AV |
1190 | int phy_irq = lp->board_data.phy_irq_pin; |
1191 | ||
1192 | if (netif_running(net_dev)) { | |
1193 | if (phy_irq) | |
1194 | disable_irq(phy_irq); | |
1195 | ||
1196 | netif_stop_queue(net_dev); | |
1197 | netif_device_detach(net_dev); | |
1198 | ||
1199 | clk_disable(lp->ether_clk); | |
1200 | } | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static int at91ether_resume(struct platform_device *pdev) | |
1205 | { | |
00e5edcb | 1206 | struct net_device *net_dev = platform_get_drvdata(pdev); |
c57ee096 | 1207 | struct at91_private *lp = netdev_priv(net_dev); |
00e5edcb AV |
1208 | int phy_irq = lp->board_data.phy_irq_pin; |
1209 | ||
1210 | if (netif_running(net_dev)) { | |
1211 | clk_enable(lp->ether_clk); | |
1212 | ||
1213 | netif_device_attach(net_dev); | |
1214 | netif_start_queue(net_dev); | |
1215 | ||
1216 | if (phy_irq) | |
1217 | enable_irq(phy_irq); | |
1218 | } | |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | #else | |
1223 | #define at91ether_suspend NULL | |
1224 | #define at91ether_resume NULL | |
1225 | #endif | |
1226 | ||
d4b7780e | 1227 | static struct platform_driver at91ether_driver = { |
d4b7780e | 1228 | .remove = __devexit_p(at91ether_remove), |
00e5edcb AV |
1229 | .suspend = at91ether_suspend, |
1230 | .resume = at91ether_resume, | |
d4b7780e AV |
1231 | .driver = { |
1232 | .name = DRV_NAME, | |
1233 | .owner = THIS_MODULE, | |
1234 | }, | |
1235 | }; | |
1236 | ||
1237 | static int __init at91ether_init(void) | |
1238 | { | |
78a9c9c9 | 1239 | return platform_driver_probe(&at91ether_driver, at91ether_probe); |
d4b7780e AV |
1240 | } |
1241 | ||
1242 | static void __exit at91ether_exit(void) | |
1243 | { | |
1244 | platform_driver_unregister(&at91ether_driver); | |
1245 | } | |
1246 | ||
1247 | module_init(at91ether_init) | |
1248 | module_exit(at91ether_exit) | |
1249 | ||
1250 | MODULE_LICENSE("GPL"); | |
1251 | MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver"); | |
1252 | MODULE_AUTHOR("Andrew Victor"); | |
72abb461 | 1253 | MODULE_ALIAS("platform:" DRV_NAME); |