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acenic: convert to net_device_ops
[linux-2.6-block.git] / drivers / net / acenic.c
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1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
69
70#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
71#include <linux/if_vlan.h>
72#endif
73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
81#include <asm/system.h>
82#include <asm/io.h>
83#include <asm/irq.h>
84#include <asm/byteorder.h>
85#include <asm/uaccess.h>
86
87
88#define DRV_NAME "acenic"
89
90#undef INDEX_DEBUG
91
92#ifdef CONFIG_ACENIC_OMIT_TIGON_I
93#define ACE_IS_TIGON_I(ap) 0
94#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
95#else
96#define ACE_IS_TIGON_I(ap) (ap->version == 1)
97#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
98#endif
99
100#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 101#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 102#endif
103#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
104#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
105#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
106#endif
107#ifndef PCI_DEVICE_ID_3COM_3C985
108#define PCI_DEVICE_ID_3COM_3C985 0x0001
109#endif
110#ifndef PCI_VENDOR_ID_NETGEAR
111#define PCI_VENDOR_ID_NETGEAR 0x1385
112#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
113#endif
114#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
115#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
116#endif
117
118
119/*
120 * Farallon used the DEC vendor ID by mistake and they seem not
121 * to care - stinky!
122 */
123#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
124#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
125#endif
126#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
127#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
128#endif
129#ifndef PCI_VENDOR_ID_SGI
130#define PCI_VENDOR_ID_SGI 0x10a9
131#endif
132#ifndef PCI_DEVICE_ID_SGI_ACENIC
133#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
134#endif
135
136static struct pci_device_id acenic_pci_tbl[] = {
137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 /*
148 * Farallon used the DEC vendor ID on their cards incorrectly,
149 * then later Alteon's ID.
150 */
151 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
153 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
157 { }
158};
159MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
160
1da177e4 161#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 162
163#ifndef offset_in_page
164#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
165#endif
166
167#define ACE_MAX_MOD_PARMS 8
168#define BOARD_IDX_STATIC 0
169#define BOARD_IDX_OVERFLOW -1
170
171#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
172 defined(NETIF_F_HW_VLAN_RX)
173#define ACENIC_DO_VLAN 1
174#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
175#else
176#define ACENIC_DO_VLAN 0
177#define ACE_RCB_VLAN_FLAG 0
178#endif
179
180#include "acenic.h"
181
182/*
183 * These must be defined before the firmware is included.
184 */
185#define MAX_TEXT_LEN 96*1024
186#define MAX_RODATA_LEN 8*1024
187#define MAX_DATA_LEN 2*1024
188
189#include "acenic_firmware.h"
190
191#ifndef tigon2FwReleaseLocal
192#define tigon2FwReleaseLocal 0
193#endif
194
195/*
196 * This driver currently supports Tigon I and Tigon II based cards
197 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
198 * GA620. The driver should also work on the SGI, DEC and Farallon
199 * versions of the card, however I have not been able to test that
200 * myself.
201 *
202 * This card is really neat, it supports receive hardware checksumming
203 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
204 * firmware. Also the programming interface is quite neat, except for
205 * the parts dealing with the i2c eeprom on the card ;-)
206 *
207 * Using jumbo frames:
208 *
209 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
210 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
211 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
212 * interface number and <MTU> being the MTU value.
213 *
214 * Module parameters:
215 *
216 * When compiled as a loadable module, the driver allows for a number
217 * of module parameters to be specified. The driver supports the
218 * following module parameters:
219 *
220 * trace=<val> - Firmware trace level. This requires special traced
221 * firmware to replace the firmware supplied with
222 * the driver - for debugging purposes only.
223 *
224 * link=<val> - Link state. Normally you want to use the default link
225 * parameters set by the driver. This can be used to
226 * override these in case your switch doesn't negotiate
227 * the link properly. Valid values are:
228 * 0x0001 - Force half duplex link.
229 * 0x0002 - Do not negotiate line speed with the other end.
230 * 0x0010 - 10Mbit/sec link.
231 * 0x0020 - 100Mbit/sec link.
232 * 0x0040 - 1000Mbit/sec link.
233 * 0x0100 - Do not negotiate flow control.
234 * 0x0200 - Enable RX flow control Y
235 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
236 * Default value is 0x0270, ie. enable link+flow
237 * control negotiation. Negotiating the highest
238 * possible link speed with RX flow control enabled.
239 *
240 * When disabling link speed negotiation, only one link
241 * speed is allowed to be specified!
242 *
243 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
244 * to wait for more packets to arive before
245 * interrupting the host, from the time the first
246 * packet arrives.
247 *
248 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
249 * to wait for more packets to arive in the transmit ring,
250 * before interrupting the host, after transmitting the
251 * first packet in the ring.
252 *
253 * max_tx_desc=<val> - maximum number of transmit descriptors
254 * (packets) transmitted before interrupting the host.
255 *
256 * max_rx_desc=<val> - maximum number of receive descriptors
257 * (packets) received before interrupting the host.
258 *
259 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
260 * increments of the NIC's on board memory to be used for
261 * transmit and receive buffers. For the 1MB NIC app. 800KB
262 * is available, on the 1/2MB NIC app. 300KB is available.
263 * 68KB will always be available as a minimum for both
264 * directions. The default value is a 50/50 split.
265 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
266 * operations, default (1) is to always disable this as
267 * that is what Alteon does on NT. I have not been able
268 * to measure any real performance differences with
269 * this on my systems. Set <val>=0 if you want to
270 * enable these operations.
271 *
272 * If you use more than one NIC, specify the parameters for the
273 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
274 * run tracing on NIC #2 but not on NIC #1 and #3.
275 *
276 * TODO:
277 *
278 * - Proper multicast support.
279 * - NIC dump support.
280 * - More tuning parameters.
281 *
282 * The mini ring is not used under Linux and I am not sure it makes sense
283 * to actually use it.
284 *
285 * New interrupt handler strategy:
286 *
287 * The old interrupt handler worked using the traditional method of
288 * replacing an skbuff with a new one when a packet arrives. However
289 * the rx rings do not need to contain a static number of buffer
290 * descriptors, thus it makes sense to move the memory allocation out
291 * of the main interrupt handler and do it in a bottom half handler
292 * and only allocate new buffers when the number of buffers in the
293 * ring is below a certain threshold. In order to avoid starving the
294 * NIC under heavy load it is however necessary to force allocation
295 * when hitting a minimum threshold. The strategy for alloction is as
296 * follows:
297 *
298 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
299 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
300 * the buffers in the interrupt handler
301 * RX_RING_THRES - maximum number of buffers in the rx ring
302 * RX_MINI_THRES - maximum number of buffers in the mini ring
303 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
304 *
305 * One advantagous side effect of this allocation approach is that the
306 * entire rx processing can be done without holding any spin lock
307 * since the rx rings and registers are totally independent of the tx
308 * ring and its registers. This of course includes the kmalloc's of
309 * new skb's. Thus start_xmit can run in parallel with rx processing
310 * and the memory allocation on SMP systems.
311 *
312 * Note that running the skb reallocation in a bottom half opens up
313 * another can of races which needs to be handled properly. In
314 * particular it can happen that the interrupt handler tries to run
315 * the reallocation while the bottom half is either running on another
316 * CPU or was interrupted on the same CPU. To get around this the
317 * driver uses bitops to prevent the reallocation routines from being
318 * reentered.
319 *
320 * TX handling can also be done without holding any spin lock, wheee
321 * this is fun! since tx_ret_csm is only written to by the interrupt
322 * handler. The case to be aware of is when shutting down the device
323 * and cleaning up where it is necessary to make sure that
324 * start_xmit() is not running while this is happening. Well DaveM
325 * informs me that this case is already protected against ... bye bye
326 * Mr. Spin Lock, it was nice to know you.
327 *
328 * TX interrupts are now partly disabled so the NIC will only generate
329 * TX interrupts for the number of coal ticks, not for the number of
330 * TX packets in the queue. This should reduce the number of TX only,
331 * ie. when no RX processing is done, interrupts seen.
332 */
333
334/*
335 * Threshold values for RX buffer allocation - the low water marks for
336 * when to start refilling the rings are set to 75% of the ring
337 * sizes. It seems to make sense to refill the rings entirely from the
338 * intrrupt handler once it gets below the panic threshold, that way
339 * we don't risk that the refilling is moved to another CPU when the
340 * one running the interrupt handler just got the slab code hot in its
341 * cache.
342 */
343#define RX_RING_SIZE 72
344#define RX_MINI_SIZE 64
345#define RX_JUMBO_SIZE 48
346
347#define RX_PANIC_STD_THRES 16
348#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
349#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
350#define RX_PANIC_MINI_THRES 12
351#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
352#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
353#define RX_PANIC_JUMBO_THRES 6
354#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
355#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
356
357
358/*
359 * Size of the mini ring entries, basically these just should be big
360 * enough to take TCP ACKs
361 */
362#define ACE_MINI_SIZE 100
363
364#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
365#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
366#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
367
368/*
369 * There seems to be a magic difference in the effect between 995 and 996
370 * but little difference between 900 and 995 ... no idea why.
371 *
372 * There is now a default set of tuning parameters which is set, depending
373 * on whether or not the user enables Jumbo frames. It's assumed that if
374 * Jumbo frames are enabled, the user wants optimal tuning for that case.
375 */
376#define DEF_TX_COAL 400 /* 996 */
377#define DEF_TX_MAX_DESC 60 /* was 40 */
378#define DEF_RX_COAL 120 /* 1000 */
379#define DEF_RX_MAX_DESC 25
380#define DEF_TX_RATIO 21 /* 24 */
381
382#define DEF_JUMBO_TX_COAL 20
383#define DEF_JUMBO_TX_MAX_DESC 60
384#define DEF_JUMBO_RX_COAL 30
385#define DEF_JUMBO_RX_MAX_DESC 6
386#define DEF_JUMBO_TX_RATIO 21
387
388#if tigon2FwReleaseLocal < 20001118
389/*
390 * Standard firmware and early modifications duplicate
391 * IRQ load without this flag (coal timer is never reset).
392 * Note that with this flag tx_coal should be less than
393 * time to xmit full tx ring.
394 * 400usec is not so bad for tx ring size of 128.
395 */
396#define TX_COAL_INTS_ONLY 1 /* worth it */
397#else
398/*
399 * With modified firmware, this is not necessary, but still useful.
400 */
401#define TX_COAL_INTS_ONLY 1
402#endif
403
404#define DEF_TRACE 0
405#define DEF_STAT (2 * TICKS_PER_SEC)
406
407
ddfce6bb 408static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 409static int trace[ACE_MAX_MOD_PARMS];
410static int tx_coal_tick[ACE_MAX_MOD_PARMS];
411static int rx_coal_tick[ACE_MAX_MOD_PARMS];
412static int max_tx_desc[ACE_MAX_MOD_PARMS];
413static int max_rx_desc[ACE_MAX_MOD_PARMS];
414static int tx_ratio[ACE_MAX_MOD_PARMS];
415static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
416
417MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
418MODULE_LICENSE("GPL");
419MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
420
ddfce6bb 421module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 422module_param_array(trace, int, NULL, 0);
423module_param_array(tx_coal_tick, int, NULL, 0);
424module_param_array(max_tx_desc, int, NULL, 0);
425module_param_array(rx_coal_tick, int, NULL, 0);
426module_param_array(max_rx_desc, int, NULL, 0);
427module_param_array(tx_ratio, int, NULL, 0);
428MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
429MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
430MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
431MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
432MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
433MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
434MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
435
436
6aa20a22 437static char version[] __devinitdata =
1da177e4
LT		 438 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
439 " http://home.cern.ch/~jes/gige/acenic.html\n";
440
441static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
442static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
443static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
444
7282d491 445static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 446 .get_settings = ace_get_settings,
447 .set_settings = ace_set_settings,
448 .get_drvinfo = ace_get_drvinfo,
449};
450
451static void ace_watchdog(struct net_device *dev);
452
d8b83c57
SH		 453static const struct net_device_ops ace_netdev_ops = {
454 .ndo_open = ace_open,
455 .ndo_stop = ace_close,
456 .ndo_tx_timeout = ace_watchdog,
457 .ndo_get_stats = ace_get_stats,
458 .ndo_set_multicast_list = ace_set_multicast_list,
459 .ndo_set_mac_address = ace_set_mac_addr,
460 .ndo_change_mtu = ace_change_mtu,
461 .ndo_vlan_rx_register = ace_vlan_rx_register,
462};
463
1da177e4
LT		 464static int __devinit acenic_probe_one(struct pci_dev *pdev,
465 const struct pci_device_id *id)
466{
467 struct net_device *dev;
468 struct ace_private *ap;
469 static int boards_found;
470
471 dev = alloc_etherdev(sizeof(struct ace_private));
472 if (dev == NULL) {
473 printk(KERN_ERR "acenic: Unable to allocate "
474 "net_device structure!\n");
475 return -ENOMEM;
476 }
477
1da177e4
LT		 478 SET_NETDEV_DEV(dev, &pdev->dev);
479
454d7c9b 480 ap = netdev_priv(dev);
1da177e4
LT		 481 ap->pdev = pdev;
482 ap->name = pci_name(pdev);
483
484 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
485#if ACENIC_DO_VLAN
486 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 487#endif
25805dcf 488
25805dcf 489 dev->watchdog_timeo = 5*HZ;
1da177e4 490
d8b83c57 491 dev->netdev_ops = &ace_netdev_ops;
1da177e4 492 dev->hard_start_xmit = &ace_start_xmit;
1da177e4 493 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 494
495 /* we only display this string ONCE */
496 if (!boards_found)
497 printk(version);
498
499 if (pci_enable_device(pdev))
500 goto fail_free_netdev;
501
502 /*
503 * Enable master mode before we start playing with the
504 * pci_command word since pci_set_master() will modify
505 * it.
506 */
507 pci_set_master(pdev);
508
509 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
510
6aa20a22 511 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 512 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
513 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
514 "access - was not enabled by BIOS/Firmware\n",
515 ap->name);
516 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
517 pci_write_config_word(ap->pdev, PCI_COMMAND,
518 ap->pci_command);
519 wmb();
520 }
521
522 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
523 if (ap->pci_latency <= 0x40) {
524 ap->pci_latency = 0x40;
525 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
526 }
527
528 /*
529 * Remap the regs into kernel space - this is abuse of
530 * dev->base_addr since it was means for I/O port
531 * addresses but who gives a damn.
532 */
533 dev->base_addr = pci_resource_start(pdev, 0);
534 ap->regs = ioremap(dev->base_addr, 0x4000);
535 if (!ap->regs) {
536 printk(KERN_ERR "%s: Unable to map I/O register, "
537 "AceNIC %i will be disabled.\n",
538 ap->name, boards_found);
539 goto fail_free_netdev;
540 }
541
542 switch(pdev->vendor) {
543 case PCI_VENDOR_ID_ALTEON:
544 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
545 printk(KERN_INFO "%s: Farallon PN9100-T ",
546 ap->name);
547 } else {
548 printk(KERN_INFO "%s: Alteon AceNIC ",
549 ap->name);
550 }
551 break;
552 case PCI_VENDOR_ID_3COM:
553 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
554 break;
555 case PCI_VENDOR_ID_NETGEAR:
556 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
557 break;
558 case PCI_VENDOR_ID_DEC:
559 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
560 printk(KERN_INFO "%s: Farallon PN9000-SX ",
561 ap->name);
562 break;
563 }
564 case PCI_VENDOR_ID_SGI:
565 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
566 break;
567 default:
568 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
569 break;
570 }
571
572 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 573 printk("irq %d\n", pdev->irq);
1da177e4
LT		 574
575#ifdef CONFIG_ACENIC_OMIT_TIGON_I
576 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
577 printk(KERN_ERR "%s: Driver compiled without Tigon I"
578 " support - NIC disabled\n", dev->name);
579 goto fail_uninit;
580 }
581#endif
582
583 if (ace_allocate_descriptors(dev))
584 goto fail_free_netdev;
585
586#ifdef MODULE
587 if (boards_found >= ACE_MAX_MOD_PARMS)
588 ap->board_idx = BOARD_IDX_OVERFLOW;
589 else
590 ap->board_idx = boards_found;
591#else
592 ap->board_idx = BOARD_IDX_STATIC;
593#endif
594
595 if (ace_init(dev))
596 goto fail_free_netdev;
597
598 if (register_netdev(dev)) {
599 printk(KERN_ERR "acenic: device registration failed\n");
600 goto fail_uninit;
601 }
602 ap->name = dev->name;
603
604 if (ap->pci_using_dac)
605 dev->features |= NETIF_F_HIGHDMA;
606
607 pci_set_drvdata(pdev, dev);
608
609 boards_found++;
610 return 0;
611
612 fail_uninit:
613 ace_init_cleanup(dev);
614 fail_free_netdev:
615 free_netdev(dev);
616 return -ENODEV;
617}
618
619static void __devexit acenic_remove_one(struct pci_dev *pdev)
620{
621 struct net_device *dev = pci_get_drvdata(pdev);
622 struct ace_private *ap = netdev_priv(dev);
623 struct ace_regs __iomem *regs = ap->regs;
624 short i;
625
626 unregister_netdev(dev);
627
628 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
629 if (ap->version >= 2)
630 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 631
1da177e4
LT		 632 /*
633 * This clears any pending interrupts
634 */
635 writel(1, &regs->Mb0Lo);
636 readl(&regs->CpuCtrl); /* flush */
637
638 /*
639 * Make sure no other CPUs are processing interrupts
640 * on the card before the buffers are being released.
641 * Otherwise one might experience some `interesting'
642 * effects.
643 *
644 * Then release the RX buffers - jumbo buffers were
645 * already released in ace_close().
646 */
647 ace_sync_irq(dev->irq);
648
649 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
650 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
651
652 if (skb) {
653 struct ring_info *ringp;
654 dma_addr_t mapping;
655
656 ringp = &ap->skb->rx_std_skbuff[i];
657 mapping = pci_unmap_addr(ringp, mapping);
658 pci_unmap_page(ap->pdev, mapping,
659 ACE_STD_BUFSIZE,
660 PCI_DMA_FROMDEVICE);
661
662 ap->rx_std_ring[i].size = 0;
663 ap->skb->rx_std_skbuff[i].skb = NULL;
664 dev_kfree_skb(skb);
665 }
666 }
667
668 if (ap->version >= 2) {
669 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
670 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
671
672 if (skb) {
673 struct ring_info *ringp;
674 dma_addr_t mapping;
675
676 ringp = &ap->skb->rx_mini_skbuff[i];
677 mapping = pci_unmap_addr(ringp,mapping);
678 pci_unmap_page(ap->pdev, mapping,
679 ACE_MINI_BUFSIZE,
680 PCI_DMA_FROMDEVICE);
681
682 ap->rx_mini_ring[i].size = 0;
683 ap->skb->rx_mini_skbuff[i].skb = NULL;
684 dev_kfree_skb(skb);
685 }
686 }
687 }
688
689 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
690 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
691 if (skb) {
692 struct ring_info *ringp;
693 dma_addr_t mapping;
694
695 ringp = &ap->skb->rx_jumbo_skbuff[i];
696 mapping = pci_unmap_addr(ringp, mapping);
697 pci_unmap_page(ap->pdev, mapping,
698 ACE_JUMBO_BUFSIZE,
699 PCI_DMA_FROMDEVICE);
700
701 ap->rx_jumbo_ring[i].size = 0;
702 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
703 dev_kfree_skb(skb);
704 }
705 }
706
707 ace_init_cleanup(dev);
708 free_netdev(dev);
709}
710
711static struct pci_driver acenic_pci_driver = {
712 .name = "acenic",
713 .id_table = acenic_pci_tbl,
714 .probe = acenic_probe_one,
715 .remove = __devexit_p(acenic_remove_one),
716};
717
718static int __init acenic_init(void)
719{
29917620 720 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 721}
722
723static void __exit acenic_exit(void)
724{
725 pci_unregister_driver(&acenic_pci_driver);
726}
727
728module_init(acenic_init);
729module_exit(acenic_exit);
730
731static void ace_free_descriptors(struct net_device *dev)
732{
733 struct ace_private *ap = netdev_priv(dev);
734 int size;
735
736 if (ap->rx_std_ring != NULL) {
737 size = (sizeof(struct rx_desc) *
738 (RX_STD_RING_ENTRIES +
739 RX_JUMBO_RING_ENTRIES +
740 RX_MINI_RING_ENTRIES +
741 RX_RETURN_RING_ENTRIES));
742 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
743 ap->rx_ring_base_dma);
744 ap->rx_std_ring = NULL;
745 ap->rx_jumbo_ring = NULL;
746 ap->rx_mini_ring = NULL;
747 ap->rx_return_ring = NULL;
748 }
749 if (ap->evt_ring != NULL) {
750 size = (sizeof(struct event) * EVT_RING_ENTRIES);
751 pci_free_consistent(ap->pdev, size, ap->evt_ring,
752 ap->evt_ring_dma);
753 ap->evt_ring = NULL;
754 }
755 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
756 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
757 pci_free_consistent(ap->pdev, size, ap->tx_ring,
758 ap->tx_ring_dma);
759 }
760 ap->tx_ring = NULL;
761
762 if (ap->evt_prd != NULL) {
763 pci_free_consistent(ap->pdev, sizeof(u32),
764 (void *)ap->evt_prd, ap->evt_prd_dma);
765 ap->evt_prd = NULL;
766 }
767 if (ap->rx_ret_prd != NULL) {
768 pci_free_consistent(ap->pdev, sizeof(u32),
769 (void *)ap->rx_ret_prd,
770 ap->rx_ret_prd_dma);
771 ap->rx_ret_prd = NULL;
772 }
773 if (ap->tx_csm != NULL) {
774 pci_free_consistent(ap->pdev, sizeof(u32),
775 (void *)ap->tx_csm, ap->tx_csm_dma);
776 ap->tx_csm = NULL;
777 }
778}
779
780
781static int ace_allocate_descriptors(struct net_device *dev)
782{
783 struct ace_private *ap = netdev_priv(dev);
784 int size;
785
786 size = (sizeof(struct rx_desc) *
787 (RX_STD_RING_ENTRIES +
788 RX_JUMBO_RING_ENTRIES +
789 RX_MINI_RING_ENTRIES +
790 RX_RETURN_RING_ENTRIES));
791
792 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
793 &ap->rx_ring_base_dma);
794 if (ap->rx_std_ring == NULL)
795 goto fail;
796
797 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
798 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
799 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
800
801 size = (sizeof(struct event) * EVT_RING_ENTRIES);
802
803 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
804
805 if (ap->evt_ring == NULL)
806 goto fail;
807
808 /*
809 * Only allocate a host TX ring for the Tigon II, the Tigon I
810 * has to use PCI registers for this ;-(
811 */
812 if (!ACE_IS_TIGON_I(ap)) {
813 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
814
815 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
816 &ap->tx_ring_dma);
817
818 if (ap->tx_ring == NULL)
819 goto fail;
820 }
821
822 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
823 &ap->evt_prd_dma);
824 if (ap->evt_prd == NULL)
825 goto fail;
826
827 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
828 &ap->rx_ret_prd_dma);
829 if (ap->rx_ret_prd == NULL)
830 goto fail;
831
832 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
833 &ap->tx_csm_dma);
834 if (ap->tx_csm == NULL)
835 goto fail;
836
837 return 0;
838
839fail:
840 /* Clean up. */
841 ace_init_cleanup(dev);
842 return 1;
843}
844
845
846/*
847 * Generic cleanup handling data allocated during init. Used when the
848 * module is unloaded or if an error occurs during initialization
849 */
850static void ace_init_cleanup(struct net_device *dev)
851{
852 struct ace_private *ap;
853
854 ap = netdev_priv(dev);
855
856 ace_free_descriptors(dev);
857
858 if (ap->info)
859 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
860 ap->info, ap->info_dma);
b4558ea9
JJ		 861 kfree(ap->skb);
862 kfree(ap->trace_buf);
1da177e4
LT		 863
864 if (dev->irq)
865 free_irq(dev->irq, dev);
866
867 iounmap(ap->regs);
868}
869
870
871/*
872 * Commands are considered to be slow.
873 */
874static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
875{
876 u32 idx;
877
878 idx = readl(&regs->CmdPrd);
879
880 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
881 idx = (idx + 1) % CMD_RING_ENTRIES;
882
883 writel(idx, &regs->CmdPrd);
884}
885
886
887static int __devinit ace_init(struct net_device *dev)
888{
889 struct ace_private *ap;
890 struct ace_regs __iomem *regs;
891 struct ace_info *info = NULL;
892 struct pci_dev *pdev;
893 unsigned long myjif;
894 u64 tmp_ptr;
895 u32 tig_ver, mac1, mac2, tmp, pci_state;
896 int board_idx, ecode = 0;
897 short i;
898 unsigned char cache_size;
899
900 ap = netdev_priv(dev);
901 regs = ap->regs;
902
903 board_idx = ap->board_idx;
904
905 /*
906 * aman@sgi.com - its useful to do a NIC reset here to
907 * address the `Firmware not running' problem subsequent
908 * to any crashes involving the NIC
909 */
910 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
911 readl(&regs->HostCtrl); /* PCI write posting */
912 udelay(5);
913
914 /*
915 * Don't access any other registers before this point!
916 */
917#ifdef __BIG_ENDIAN
918 /*
919 * This will most likely need BYTE_SWAP once we switch
920 * to using __raw_writel()
921 */
922 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
923 &regs->HostCtrl);
924#else
925 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
926 &regs->HostCtrl);
927#endif
928 readl(&regs->HostCtrl); /* PCI write posting */
929
930 /*
931 * Stop the NIC CPU and clear pending interrupts
932 */
933 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
934 readl(&regs->CpuCtrl); /* PCI write posting */
935 writel(0, &regs->Mb0Lo);
936
937 tig_ver = readl(&regs->HostCtrl) >> 28;
938
939 switch(tig_ver){
940#ifndef CONFIG_ACENIC_OMIT_TIGON_I
941 case 4:
942 case 5:
943 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
944 tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
945 tigonFwReleaseFix);
946 writel(0, &regs->LocalCtrl);
947 ap->version = 1;
948 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
949 break;
950#endif
951 case 6:
952 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
953 tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
954 tigon2FwReleaseFix);
955 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
956 readl(&regs->CpuBCtrl); /* PCI write posting */
957 /*
958 * The SRAM bank size does _not_ indicate the amount
959 * of memory on the card, it controls the _bank_ size!
960 * Ie. a 1MB AceNIC will have two banks of 512KB.
961 */
962 writel(SRAM_BANK_512K, &regs->LocalCtrl);
963 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
964 ap->version = 2;
965 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
966 break;
967 default:
968 printk(KERN_WARNING " Unsupported Tigon version detected "
969 "(%i)\n", tig_ver);
970 ecode = -ENODEV;
971 goto init_error;
972 }
973
974 /*
975 * ModeStat _must_ be set after the SRAM settings as this change
976 * seems to corrupt the ModeStat and possible other registers.
977 * The SRAM settings survive resets and setting it to the same
978 * value a second time works as well. This is what caused the
979 * `Firmware not running' problem on the Tigon II.
980 */
981#ifdef __BIG_ENDIAN
982 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
983 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
984#else
985 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
986 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
987#endif
988 readl(&regs->ModeStat); /* PCI write posting */
989
990 mac1 = 0;
991 for(i = 0; i < 4; i++) {
ddfce6bb 992 int t;
6f9d4722 993
1da177e4 994 mac1 = mac1 << 8;
ddfce6bb
SH		 995 t = read_eeprom_byte(dev, 0x8c+i);
996 if (t < 0) {
1da177e4
LT		 997 ecode = -EIO;
998 goto init_error;
999 } else
ddfce6bb 1000 mac1 |= (t & 0xff);
1da177e4
LT		 1001 }
1002 mac2 = 0;
1003 for(i = 4; i < 8; i++) {
ddfce6bb 1004 int t;
6f9d4722 1005
1da177e4 1006 mac2 = mac2 << 8;
ddfce6bb
SH		 1007 t = read_eeprom_byte(dev, 0x8c+i);
1008 if (t < 0) {
1da177e4
LT		 1009 ecode = -EIO;
1010 goto init_error;
1011 } else
ddfce6bb 1012 mac2 |= (t & 0xff);
1da177e4
LT		 1013 }
1014
1015 writel(mac1, &regs->MacAddrHi);
1016 writel(mac2, &regs->MacAddrLo);
1017
1da177e4
LT		 1018 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1019 dev->dev_addr[1] = mac1 & 0xff;
1020 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1021 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1022 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1023 dev->dev_addr[5] = mac2 & 0xff;
1024
e174961c 1025 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1026
1da177e4
LT		 1027 /*
1028 * Looks like this is necessary to deal with on all architectures,
1029 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1030 * Ie. having two NICs in the machine, one will have the cache
1031 * line set at boot time, the other will not.
1032 */
1033 pdev = ap->pdev;
1034 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1035 cache_size <<= 2;
1036 if (cache_size != SMP_CACHE_BYTES) {
1037 printk(KERN_INFO " PCI cache line size set incorrectly "
1038 "(%i bytes) by BIOS/FW, ", cache_size);
1039 if (cache_size > SMP_CACHE_BYTES)
1040 printk("expecting %i\n", SMP_CACHE_BYTES);
1041 else {
1042 printk("correcting to %i\n", SMP_CACHE_BYTES);
1043 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1044 SMP_CACHE_BYTES >> 2);
1045 }
1046 }
1047
1048 pci_state = readl(&regs->PciState);
1049 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1050 "latency: %i clks\n",
1051 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1052 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1053 ap->pci_latency);
1054
1055 /*
1056 * Set the max DMA transfer size. Seems that for most systems
1057 * the performance is better when no MAX parameter is
1058 * set. However for systems enabling PCI write and invalidate,
1059 * DMA writes must be set to the L1 cache line size to get
1060 * optimal performance.
1061 *
1062 * The default is now to turn the PCI write and invalidate off
1063 * - that is what Alteon does for NT.
1064 */
1065 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1066 if (ap->version >= 2) {
1067 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1068 /*
1069 * Tuning parameters only supported for 8 cards
1070 */
1071 if (board_idx == BOARD_IDX_OVERFLOW ||
1072 dis_pci_mem_inval[board_idx]) {
1073 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1074 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1075 pci_write_config_word(pdev, PCI_COMMAND,
1076 ap->pci_command);
1077 printk(KERN_INFO " Disabling PCI memory "
1078 "write and invalidate\n");
1079 }
1080 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1081 printk(KERN_INFO " PCI memory write & invalidate "
1082 "enabled by BIOS, enabling counter measures\n");
1083
1084 switch(SMP_CACHE_BYTES) {
1085 case 16:
1086 tmp |= DMA_WRITE_MAX_16;
1087 break;
1088 case 32:
1089 tmp |= DMA_WRITE_MAX_32;
1090 break;
1091 case 64:
1092 tmp |= DMA_WRITE_MAX_64;
1093 break;
1094 case 128:
1095 tmp |= DMA_WRITE_MAX_128;
1096 break;
1097 default:
1098 printk(KERN_INFO " Cache line size %i not "
1099 "supported, PCI write and invalidate "
1100 "disabled\n", SMP_CACHE_BYTES);
1101 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1102 pci_write_config_word(pdev, PCI_COMMAND,
1103 ap->pci_command);
1104 }
1105 }
1106 }
1107
1108#ifdef __sparc__
1109 /*
1110 * On this platform, we know what the best dma settings
1111 * are. We use 64-byte maximum bursts, because if we
1112 * burst larger than the cache line size (or even cross
1113 * a 64byte boundary in a single burst) the UltraSparc
1114 * PCI controller will disconnect at 64-byte multiples.
1115 *
1116 * Read-multiple will be properly enabled above, and when
1117 * set will give the PCI controller proper hints about
1118 * prefetching.
1119 */
1120 tmp &= ~DMA_READ_WRITE_MASK;
1121 tmp |= DMA_READ_MAX_64;
1122 tmp |= DMA_WRITE_MAX_64;
1123#endif
1124#ifdef __alpha__
1125 tmp &= ~DMA_READ_WRITE_MASK;
1126 tmp |= DMA_READ_MAX_128;
1127 /*
1128 * All the docs say MUST NOT. Well, I did.
1129 * Nothing terrible happens, if we load wrong size.
1130 * Bit w&i still works better!
1131 */
1132 tmp |= DMA_WRITE_MAX_128;
1133#endif
1134 writel(tmp, &regs->PciState);
1135
1136#if 0
1137 /*
1138 * The Host PCI bus controller driver has to set FBB.
1139 * If all devices on that PCI bus support FBB, then the controller
1140 * can enable FBB support in the Host PCI Bus controller (or on
1141 * the PCI-PCI bridge if that applies).
1142 * -ggg
1143 */
1144 /*
1145 * I have received reports from people having problems when this
1146 * bit is enabled.
1147 */
1148 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1149 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1150 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1151 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1152 }
1153#endif
6aa20a22 1154
1da177e4
LT		 1155 /*
1156 * Configure DMA attributes.
1157 */
1e7f0bd8 1158 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4 1159 ap->pci_using_dac = 1;
1e7f0bd8 1160 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 1161 ap->pci_using_dac = 0;
1162 } else {
1163 ecode = -ENODEV;
1164 goto init_error;
1165 }
1166
1167 /*
1168 * Initialize the generic info block and the command+event rings
1169 * and the control blocks for the transmit and receive rings
1170 * as they need to be setup once and for all.
1171 */
1172 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1173 &ap->info_dma))) {
1174 ecode = -EAGAIN;
1175 goto init_error;
1176 }
1177 ap->info = info;
1178
1179 /*
1180 * Get the memory for the skb rings.
1181 */
1182 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1183 ecode = -EAGAIN;
1184 goto init_error;
1185 }
1186
1fb9df5d 1187 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1188 DRV_NAME, dev);
1189 if (ecode) {
1190 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1191 DRV_NAME, pdev->irq);
1192 goto init_error;
1193 } else
1194 dev->irq = pdev->irq;
1195
1196#ifdef INDEX_DEBUG
1197 spin_lock_init(&ap->debug_lock);
1198 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1199 ap->last_std_rx = 0;
1200 ap->last_mini_rx = 0;
1201#endif
1202
1203 memset(ap->info, 0, sizeof(struct ace_info));
1204 memset(ap->skb, 0, sizeof(struct ace_skb));
1205
1206 ace_load_firmware(dev);
1207 ap->fw_running = 0;
1208
1209 tmp_ptr = ap->info_dma;
1210 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1211 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1212
1213 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1214
1215 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1216 info->evt_ctrl.flags = 0;
1217
1218 *(ap->evt_prd) = 0;
1219 wmb();
1220 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1221 writel(0, &regs->EvtCsm);
1222
1223 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1224 info->cmd_ctrl.flags = 0;
1225 info->cmd_ctrl.max_len = 0;
1226
1227 for (i = 0; i < CMD_RING_ENTRIES; i++)
1228 writel(0, &regs->CmdRng[i]);
1229
1230 writel(0, &regs->CmdPrd);
1231 writel(0, &regs->CmdCsm);
1232
1233 tmp_ptr = ap->info_dma;
1234 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1235 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1236
1237 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1238 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1239 info->rx_std_ctrl.flags =
1240 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1241
1242 memset(ap->rx_std_ring, 0,
1243 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1244
1245 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1246 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1247
1248 ap->rx_std_skbprd = 0;
1249 atomic_set(&ap->cur_rx_bufs, 0);
1250
1251 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1252 (ap->rx_ring_base_dma +
1253 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1254 info->rx_jumbo_ctrl.max_len = 0;
1255 info->rx_jumbo_ctrl.flags =
1256 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1257
1258 memset(ap->rx_jumbo_ring, 0,
1259 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1260
1261 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1262 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1263
1264 ap->rx_jumbo_skbprd = 0;
1265 atomic_set(&ap->cur_jumbo_bufs, 0);
1266
1267 memset(ap->rx_mini_ring, 0,
1268 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1269
1270 if (ap->version >= 2) {
1271 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1272 (ap->rx_ring_base_dma +
1273 (sizeof(struct rx_desc) *
1274 (RX_STD_RING_ENTRIES +
1275 RX_JUMBO_RING_ENTRIES))));
1276 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1277 info->rx_mini_ctrl.flags =
1da177e4
LT		 1278 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1279
1280 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1281 ap->rx_mini_ring[i].flags =
1282 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1283 } else {
1284 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1285 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1286 info->rx_mini_ctrl.max_len = 0;
1287 }
1288
1289 ap->rx_mini_skbprd = 0;
1290 atomic_set(&ap->cur_mini_bufs, 0);
1291
1292 set_aceaddr(&info->rx_return_ctrl.rngptr,
1293 (ap->rx_ring_base_dma +
1294 (sizeof(struct rx_desc) *
1295 (RX_STD_RING_ENTRIES +
1296 RX_JUMBO_RING_ENTRIES +
1297 RX_MINI_RING_ENTRIES))));
1298 info->rx_return_ctrl.flags = 0;
1299 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1300
1301 memset(ap->rx_return_ring, 0,
1302 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1303
1304 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1305 *(ap->rx_ret_prd) = 0;
1306
1307 writel(TX_RING_BASE, &regs->WinBase);
1308
1309 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1310 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1311 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1312 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1313 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1314
1315 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1316 } else {
1317 memset(ap->tx_ring, 0,
1318 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1319
1320 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1321 }
1322
1323 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1324 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1325
1326 /*
1327 * The Tigon I does not like having the TX ring in host memory ;-(
1328 */
1329 if (!ACE_IS_TIGON_I(ap))
1330 tmp |= RCB_FLG_TX_HOST_RING;
1331#if TX_COAL_INTS_ONLY
1332 tmp |= RCB_FLG_COAL_INT_ONLY;
1333#endif
1334 info->tx_ctrl.flags = tmp;
1335
1336 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1337
1338 /*
1339 * Potential item for tuning parameter
1340 */
1341#if 0 /* NO */
1342 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1343 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1344#else
1345 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1346 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1347#endif
1348
1349 writel(0, &regs->MaskInt);
1350 writel(1, &regs->IfIdx);
1351#if 0
1352 /*
1353 * McKinley boxes do not like us fiddling with AssistState
1354 * this early
1355 */
1356 writel(1, &regs->AssistState);
1357#endif
1358
1359 writel(DEF_STAT, &regs->TuneStatTicks);
1360 writel(DEF_TRACE, &regs->TuneTrace);
1361
1362 ace_set_rxtx_parms(dev, 0);
1363
1364 if (board_idx == BOARD_IDX_OVERFLOW) {
1365 printk(KERN_WARNING "%s: more than %i NICs detected, "
1366 "ignoring module parameters!\n",
1367 ap->name, ACE_MAX_MOD_PARMS);
1368 } else if (board_idx >= 0) {
1369 if (tx_coal_tick[board_idx])
1370 writel(tx_coal_tick[board_idx],
1371 &regs->TuneTxCoalTicks);
1372 if (max_tx_desc[board_idx])
1373 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1374
1375 if (rx_coal_tick[board_idx])
1376 writel(rx_coal_tick[board_idx],
1377 &regs->TuneRxCoalTicks);
1378 if (max_rx_desc[board_idx])
1379 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1380
1381 if (trace[board_idx])
1382 writel(trace[board_idx], &regs->TuneTrace);
1383
1384 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1385 writel(tx_ratio[board_idx], &regs->TxBufRat);
1386 }
1387
1388 /*
1389 * Default link parameters
1390 */
1391 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1392 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1393 if(ap->version >= 2)
1394 tmp |= LNK_TX_FLOW_CTL_Y;
1395
1396 /*
1397 * Override link default parameters
1398 */
ddfce6bb
SH		 1399 if ((board_idx >= 0) && link_state[board_idx]) {
1400 int option = link_state[board_idx];
1da177e4
LT		 1401
1402 tmp = LNK_ENABLE;
1403
1404 if (option & 0x01) {
1405 printk(KERN_INFO "%s: Setting half duplex link\n",
1406 ap->name);
1407 tmp &= ~LNK_FULL_DUPLEX;
1408 }
1409 if (option & 0x02)
1410 tmp &= ~LNK_NEGOTIATE;
1411 if (option & 0x10)
1412 tmp |= LNK_10MB;
1413 if (option & 0x20)
1414 tmp |= LNK_100MB;
1415 if (option & 0x40)
1416 tmp |= LNK_1000MB;
1417 if ((option & 0x70) == 0) {
1418 printk(KERN_WARNING "%s: No media speed specified, "
1419 "forcing auto negotiation\n", ap->name);
1420 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1421 LNK_100MB | LNK_10MB;
1422 }
1423 if ((option & 0x100) == 0)
1424 tmp |= LNK_NEG_FCTL;
1425 else
1426 printk(KERN_INFO "%s: Disabling flow control "
1427 "negotiation\n", ap->name);
1428 if (option & 0x200)
1429 tmp |= LNK_RX_FLOW_CTL_Y;
1430 if ((option & 0x400) && (ap->version >= 2)) {
1431 printk(KERN_INFO "%s: Enabling TX flow control\n",
1432 ap->name);
1433 tmp |= LNK_TX_FLOW_CTL_Y;
1434 }
1435 }
1436
1437 ap->link = tmp;
1438 writel(tmp, &regs->TuneLink);
1439 if (ap->version >= 2)
1440 writel(tmp, &regs->TuneFastLink);
1441
1442 if (ACE_IS_TIGON_I(ap))
1443 writel(tigonFwStartAddr, &regs->Pc);
1444 if (ap->version == 2)
1445 writel(tigon2FwStartAddr, &regs->Pc);
1446
1447 writel(0, &regs->Mb0Lo);
1448
1449 /*
1450 * Set tx_csm before we start receiving interrupts, otherwise
1451 * the interrupt handler might think it is supposed to process
1452 * tx ints before we are up and running, which may cause a null
1453 * pointer access in the int handler.
1454 */
1455 ap->cur_rx = 0;
1456 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1457
1458 wmb();
1459 ace_set_txprd(regs, ap, 0);
1460 writel(0, &regs->RxRetCsm);
1461
1da177e4
LT		 1462 /*
1463 * Enable DMA engine now.
1464 * If we do this sooner, Mckinley box pukes.
1465 * I assume it's because Tigon II DMA engine wants to check
1466 * *something* even before the CPU is started.
1467 */
1468 writel(1, &regs->AssistState); /* enable DMA */
1469
1470 /*
1471 * Start the NIC CPU
1472 */
1473 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1474 readl(&regs->CpuCtrl);
1475
1476 /*
1477 * Wait for the firmware to spin up - max 3 seconds.
1478 */
1479 myjif = jiffies + 3 * HZ;
1480 while (time_before(jiffies, myjif) && !ap->fw_running)
1481 cpu_relax();
1482
1483 if (!ap->fw_running) {
1484 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1485
1486 ace_dump_trace(ap);
1487 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1488 readl(&regs->CpuCtrl);
1489
1490 /* aman@sgi.com - account for badly behaving firmware/NIC:
1491 * - have observed that the NIC may continue to generate
1492 * interrupts for some reason; attempt to stop it - halt
1493 * second CPU for Tigon II cards, and also clear Mb0
1494 * - if we're a module, we'll fail to load if this was
1495 * the only GbE card in the system => if the kernel does
1496 * see an interrupt from the NIC, code to handle it is
1497 * gone and OOps! - so free_irq also
1498 */
1499 if (ap->version >= 2)
1500 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1501 &regs->CpuBCtrl);
1502 writel(0, &regs->Mb0Lo);
1503 readl(&regs->Mb0Lo);
1504
1505 ecode = -EBUSY;
1506 goto init_error;
1507 }
1508
1509 /*
1510 * We load the ring here as there seem to be no way to tell the
1511 * firmware to wipe the ring without re-initializing it.
1512 */
1513 if (!test_and_set_bit(0, &ap->std_refill_busy))
1514 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1515 else
1516 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1517 ap->name);
1518 if (ap->version >= 2) {
1519 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1520 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1521 else
1522 printk(KERN_ERR "%s: Someone is busy refilling "
1523 "the RX mini ring\n", ap->name);
1524 }
1525 return 0;
1526
1527 init_error:
1528 ace_init_cleanup(dev);
1529 return ecode;
1530}
1531
1532
1533static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1534{
1535 struct ace_private *ap = netdev_priv(dev);
1536 struct ace_regs __iomem *regs = ap->regs;
1537 int board_idx = ap->board_idx;
1538
1539 if (board_idx >= 0) {
1540 if (!jumbo) {
1541 if (!tx_coal_tick[board_idx])
1542 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1543 if (!max_tx_desc[board_idx])
1544 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1545 if (!rx_coal_tick[board_idx])
1546 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1547 if (!max_rx_desc[board_idx])
1548 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1549 if (!tx_ratio[board_idx])
1550 writel(DEF_TX_RATIO, &regs->TxBufRat);
1551 } else {
1552 if (!tx_coal_tick[board_idx])
1553 writel(DEF_JUMBO_TX_COAL,
1554 &regs->TuneTxCoalTicks);
1555 if (!max_tx_desc[board_idx])
1556 writel(DEF_JUMBO_TX_MAX_DESC,
1557 &regs->TuneMaxTxDesc);
1558 if (!rx_coal_tick[board_idx])
1559 writel(DEF_JUMBO_RX_COAL,
1560 &regs->TuneRxCoalTicks);
1561 if (!max_rx_desc[board_idx])
1562 writel(DEF_JUMBO_RX_MAX_DESC,
1563 &regs->TuneMaxRxDesc);
1564 if (!tx_ratio[board_idx])
1565 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1566 }
1567 }
1568}
1569
1570
1571static void ace_watchdog(struct net_device *data)
1572{
1573 struct net_device *dev = data;
1574 struct ace_private *ap = netdev_priv(dev);
1575 struct ace_regs __iomem *regs = ap->regs;
1576
1577 /*
1578 * We haven't received a stats update event for more than 2.5
1579 * seconds and there is data in the transmit queue, thus we
1580 * asume the card is stuck.
1581 */
1582 if (*ap->tx_csm != ap->tx_ret_csm) {
1583 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1584 dev->name, (unsigned int)readl(&regs->HostCtrl));
1585 /* This can happen due to ieee flow control. */
1586 } else {
1587 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1588 dev->name);
1589#if 0
1590 netif_wake_queue(dev);
1591#endif
1592 }
1593}
1594
1595
1596static void ace_tasklet(unsigned long dev)
1597{
1598 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1599 int cur_size;
1600
1601 cur_size = atomic_read(&ap->cur_rx_bufs);
1602 if ((cur_size < RX_LOW_STD_THRES) &&
1603 !test_and_set_bit(0, &ap->std_refill_busy)) {
1604#ifdef DEBUG
1605 printk("refilling buffers (current %i)\n", cur_size);
1606#endif
1607 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1608 }
1609
1610 if (ap->version >= 2) {
1611 cur_size = atomic_read(&ap->cur_mini_bufs);
1612 if ((cur_size < RX_LOW_MINI_THRES) &&
1613 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1614#ifdef DEBUG
1615 printk("refilling mini buffers (current %i)\n",
1616 cur_size);
1617#endif
1618 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1619 }
1620 }
1621
1622 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1623 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1624 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1625#ifdef DEBUG
1626 printk("refilling jumbo buffers (current %i)\n", cur_size);
1627#endif
1628 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1629 }
1630 ap->tasklet_pending = 0;
1631}
1632
1633
1634/*
1635 * Copy the contents of the NIC's trace buffer to kernel memory.
1636 */
1637static void ace_dump_trace(struct ace_private *ap)
1638{
1639#if 0
1640 if (!ap->trace_buf)
1641 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1642 return;
1643#endif
1644}
1645
1646
1647/*
1648 * Load the standard rx ring.
1649 *
1650 * Loading rings is safe without holding the spin lock since this is
1651 * done only before the device is enabled, thus no interrupts are
1652 * generated and by the interrupt handler/tasklet handler.
1653 */
1654static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1655{
1656 struct ace_regs __iomem *regs = ap->regs;
1657 short i, idx;
6aa20a22 1658
1da177e4
LT		 1659
1660 prefetchw(&ap->cur_rx_bufs);
1661
1662 idx = ap->rx_std_skbprd;
1663
1664 for (i = 0; i < nr_bufs; i++) {
1665 struct sk_buff *skb;
1666 struct rx_desc *rd;
1667 dma_addr_t mapping;
1668
1669 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1670 if (!skb)
1671 break;
1672
1673 skb_reserve(skb, NET_IP_ALIGN);
1674 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1675 offset_in_page(skb->data),
1676 ACE_STD_BUFSIZE,
1677 PCI_DMA_FROMDEVICE);
1678 ap->skb->rx_std_skbuff[idx].skb = skb;
1679 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1680 mapping, mapping);
1681
1682 rd = &ap->rx_std_ring[idx];
1683 set_aceaddr(&rd->addr, mapping);
1684 rd->size = ACE_STD_BUFSIZE;
1685 rd->idx = idx;
1686 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1687 }
1688
1689 if (!i)
1690 goto error_out;
1691
1692 atomic_add(i, &ap->cur_rx_bufs);
1693 ap->rx_std_skbprd = idx;
1694
1695 if (ACE_IS_TIGON_I(ap)) {
1696 struct cmd cmd;
1697 cmd.evt = C_SET_RX_PRD_IDX;
1698 cmd.code = 0;
1699 cmd.idx = ap->rx_std_skbprd;
1700 ace_issue_cmd(regs, &cmd);
1701 } else {
1702 writel(idx, &regs->RxStdPrd);
1703 wmb();
1704 }
1705
1706 out:
1707 clear_bit(0, &ap->std_refill_busy);
1708 return;
1709
1710 error_out:
1711 printk(KERN_INFO "Out of memory when allocating "
1712 "standard receive buffers\n");
1713 goto out;
1714}
1715
1716
1717static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1718{
1719 struct ace_regs __iomem *regs = ap->regs;
1720 short i, idx;
1721
1722 prefetchw(&ap->cur_mini_bufs);
1723
1724 idx = ap->rx_mini_skbprd;
1725 for (i = 0; i < nr_bufs; i++) {
1726 struct sk_buff *skb;
1727 struct rx_desc *rd;
1728 dma_addr_t mapping;
1729
1730 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1731 if (!skb)
1732 break;
1733
1734 skb_reserve(skb, NET_IP_ALIGN);
1735 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1736 offset_in_page(skb->data),
1737 ACE_MINI_BUFSIZE,
1738 PCI_DMA_FROMDEVICE);
1739 ap->skb->rx_mini_skbuff[idx].skb = skb;
1740 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1741 mapping, mapping);
1742
1743 rd = &ap->rx_mini_ring[idx];
1744 set_aceaddr(&rd->addr, mapping);
1745 rd->size = ACE_MINI_BUFSIZE;
1746 rd->idx = idx;
1747 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1748 }
1749
1750 if (!i)
1751 goto error_out;
1752
1753 atomic_add(i, &ap->cur_mini_bufs);
1754
1755 ap->rx_mini_skbprd = idx;
1756
1757 writel(idx, &regs->RxMiniPrd);
1758 wmb();
1759
1760 out:
1761 clear_bit(0, &ap->mini_refill_busy);
1762 return;
1763 error_out:
1764 printk(KERN_INFO "Out of memory when allocating "
1765 "mini receive buffers\n");
1766 goto out;
1767}
1768
1769
1770/*
1771 * Load the jumbo rx ring, this may happen at any time if the MTU
1772 * is changed to a value > 1500.
1773 */
1774static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1775{
1776 struct ace_regs __iomem *regs = ap->regs;
1777 short i, idx;
1778
1779 idx = ap->rx_jumbo_skbprd;
1780
1781 for (i = 0; i < nr_bufs; i++) {
1782 struct sk_buff *skb;
1783 struct rx_desc *rd;
1784 dma_addr_t mapping;
1785
1786 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1787 if (!skb)
1788 break;
1789
1790 skb_reserve(skb, NET_IP_ALIGN);
1791 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1792 offset_in_page(skb->data),
1793 ACE_JUMBO_BUFSIZE,
1794 PCI_DMA_FROMDEVICE);
1795 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1796 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1797 mapping, mapping);
1798
1799 rd = &ap->rx_jumbo_ring[idx];
1800 set_aceaddr(&rd->addr, mapping);
1801 rd->size = ACE_JUMBO_BUFSIZE;
1802 rd->idx = idx;
1803 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1804 }
1805
1806 if (!i)
1807 goto error_out;
1808
1809 atomic_add(i, &ap->cur_jumbo_bufs);
1810 ap->rx_jumbo_skbprd = idx;
1811
1812 if (ACE_IS_TIGON_I(ap)) {
1813 struct cmd cmd;
1814 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1815 cmd.code = 0;
1816 cmd.idx = ap->rx_jumbo_skbprd;
1817 ace_issue_cmd(regs, &cmd);
1818 } else {
1819 writel(idx, &regs->RxJumboPrd);
1820 wmb();
1821 }
1822
1823 out:
1824 clear_bit(0, &ap->jumbo_refill_busy);
1825 return;
1826 error_out:
1827 if (net_ratelimit())
1828 printk(KERN_INFO "Out of memory when allocating "
1829 "jumbo receive buffers\n");
1830 goto out;
1831}
1832
1833
1834/*
1835 * All events are considered to be slow (RX/TX ints do not generate
1836 * events) and are handled here, outside the main interrupt handler,
1837 * to reduce the size of the handler.
1838 */
1839static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1840{
1841 struct ace_private *ap;
1842
1843 ap = netdev_priv(dev);
1844
1845 while (evtcsm != evtprd) {
1846 switch (ap->evt_ring[evtcsm].evt) {
1847 case E_FW_RUNNING:
1848 printk(KERN_INFO "%s: Firmware up and running\n",
1849 ap->name);
1850 ap->fw_running = 1;
1851 wmb();
1852 break;
1853 case E_STATS_UPDATED:
1854 break;
1855 case E_LNK_STATE:
1856 {
1857 u16 code = ap->evt_ring[evtcsm].code;
1858 switch (code) {
1859 case E_C_LINK_UP:
1860 {
1861 u32 state = readl(&ap->regs->GigLnkState);
1862 printk(KERN_WARNING "%s: Optical link UP "
1863 "(%s Duplex, Flow Control: %s%s)\n",
1864 ap->name,
1865 state & LNK_FULL_DUPLEX ? "Full":"Half",
1866 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1867 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1868 break;
1869 }
1870 case E_C_LINK_DOWN:
1871 printk(KERN_WARNING "%s: Optical link DOWN\n",
1872 ap->name);
1873 break;
1874 case E_C_LINK_10_100:
1875 printk(KERN_WARNING "%s: 10/100BaseT link "
1876 "UP\n", ap->name);
1877 break;
1878 default:
1879 printk(KERN_ERR "%s: Unknown optical link "
1880 "state %02x\n", ap->name, code);
1881 }
1882 break;
1883 }
1884 case E_ERROR:
1885 switch(ap->evt_ring[evtcsm].code) {
1886 case E_C_ERR_INVAL_CMD:
1887 printk(KERN_ERR "%s: invalid command error\n",
1888 ap->name);
1889 break;
1890 case E_C_ERR_UNIMP_CMD:
1891 printk(KERN_ERR "%s: unimplemented command "
1892 "error\n", ap->name);
1893 break;
1894 case E_C_ERR_BAD_CFG:
1895 printk(KERN_ERR "%s: bad config error\n",
1896 ap->name);
1897 break;
1898 default:
1899 printk(KERN_ERR "%s: unknown error %02x\n",
1900 ap->name, ap->evt_ring[evtcsm].code);
1901 }
1902 break;
1903 case E_RESET_JUMBO_RNG:
1904 {
1905 int i;
1906 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1907 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1908 ap->rx_jumbo_ring[i].size = 0;
1909 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1910 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1911 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1912 }
1913 }
1914
1915 if (ACE_IS_TIGON_I(ap)) {
1916 struct cmd cmd;
1917 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1918 cmd.code = 0;
1919 cmd.idx = 0;
1920 ace_issue_cmd(ap->regs, &cmd);
1921 } else {
1922 writel(0, &((ap->regs)->RxJumboPrd));
1923 wmb();
1924 }
1925
1926 ap->jumbo = 0;
1927 ap->rx_jumbo_skbprd = 0;
1928 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1929 ap->name);
1930 clear_bit(0, &ap->jumbo_refill_busy);
1931 break;
1932 }
1933 default:
1934 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1935 ap->name, ap->evt_ring[evtcsm].evt);
1936 }
1937 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1938 }
1939
1940 return evtcsm;
1941}
1942
1943
1944static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1945{
1946 struct ace_private *ap = netdev_priv(dev);
1947 u32 idx;
1948 int mini_count = 0, std_count = 0;
1949
1950 idx = rxretcsm;
1951
1952 prefetchw(&ap->cur_rx_bufs);
1953 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1954
1da177e4
LT		 1955 while (idx != rxretprd) {
1956 struct ring_info *rip;
1957 struct sk_buff *skb;
1958 struct rx_desc *rxdesc, *retdesc;
1959 u32 skbidx;
1960 int bd_flags, desc_type, mapsize;
1961 u16 csum;
1962
1963
1964 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1965 if (idx == rxretcsm)
1da177e4
LT		 1966 rmb();
1967
1968 retdesc = &ap->rx_return_ring[idx];
1969 skbidx = retdesc->idx;
1970 bd_flags = retdesc->flags;
1971 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1972
1973 switch(desc_type) {
1974 /*
1975 * Normal frames do not have any flags set
1976 *
1977 * Mini and normal frames arrive frequently,
1978 * so use a local counter to avoid doing
1979 * atomic operations for each packet arriving.
1980 */
1981 case 0:
1982 rip = &ap->skb->rx_std_skbuff[skbidx];
1983 mapsize = ACE_STD_BUFSIZE;
1984 rxdesc = &ap->rx_std_ring[skbidx];
1985 std_count++;
1986 break;
1987 case BD_FLG_JUMBO:
1988 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1989 mapsize = ACE_JUMBO_BUFSIZE;
1990 rxdesc = &ap->rx_jumbo_ring[skbidx];
1991 atomic_dec(&ap->cur_jumbo_bufs);
1992 break;
1993 case BD_FLG_MINI:
1994 rip = &ap->skb->rx_mini_skbuff[skbidx];
1995 mapsize = ACE_MINI_BUFSIZE;
1996 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 1997 mini_count++;
1da177e4
LT		 1998 break;
1999 default:
2000 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2001 "returned by NIC\n", dev->name,
2002 retdesc->flags);
2003 goto error;
2004 }
2005
2006 skb = rip->skb;
2007 rip->skb = NULL;
2008 pci_unmap_page(ap->pdev,
2009 pci_unmap_addr(rip, mapping),
2010 mapsize,
2011 PCI_DMA_FROMDEVICE);
2012 skb_put(skb, retdesc->size);
2013
2014 /*
2015 * Fly baby, fly!
2016 */
2017 csum = retdesc->tcp_udp_csum;
2018
1da177e4
LT		 2019 skb->protocol = eth_type_trans(skb, dev);
2020
2021 /*
2022 * Instead of forcing the poor tigon mips cpu to calculate
2023 * pseudo hdr checksum, we do this ourselves.
2024 */
2025 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2026 skb->csum = htons(csum);
84fa7933 2027 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2028 } else {
2029 skb->ip_summed = CHECKSUM_NONE;
2030 }
2031
2032 /* send it up */
2033#if ACENIC_DO_VLAN
2034 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2035 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2036 } else
2037#endif
2038 netif_rx(skb);
2039
966e37bc
PZ		 2040 dev->stats.rx_packets++;
2041 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2042
2043 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2044 }
2045
2046 atomic_sub(std_count, &ap->cur_rx_bufs);
2047 if (!ACE_IS_TIGON_I(ap))
2048 atomic_sub(mini_count, &ap->cur_mini_bufs);
2049
2050 out:
2051 /*
2052 * According to the documentation RxRetCsm is obsolete with
2053 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2054 */
2055 if (ACE_IS_TIGON_I(ap)) {
2056 writel(idx, &ap->regs->RxRetCsm);
2057 }
2058 ap->cur_rx = idx;
2059
2060 return;
2061 error:
2062 idx = rxretprd;
2063 goto out;
2064}
2065
2066
2067static inline void ace_tx_int(struct net_device *dev,
2068 u32 txcsm, u32 idx)
2069{
2070 struct ace_private *ap = netdev_priv(dev);
2071
2072 do {
2073 struct sk_buff *skb;
2074 dma_addr_t mapping;
2075 struct tx_ring_info *info;
2076
2077 info = ap->skb->tx_skbuff + idx;
2078 skb = info->skb;
2079 mapping = pci_unmap_addr(info, mapping);
2080
2081 if (mapping) {
2082 pci_unmap_page(ap->pdev, mapping,
2083 pci_unmap_len(info, maplen),
2084 PCI_DMA_TODEVICE);
2085 pci_unmap_addr_set(info, mapping, 0);
2086 }
2087
2088 if (skb) {
966e37bc
PZ		 2089 dev->stats.tx_packets++;
2090 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2091 dev_kfree_skb_irq(skb);
2092 info->skb = NULL;
2093 }
2094
2095 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2096 } while (idx != txcsm);
2097
2098 if (netif_queue_stopped(dev))
2099 netif_wake_queue(dev);
2100
2101 wmb();
2102 ap->tx_ret_csm = txcsm;
2103
2104 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2105 *
2106 * We could try to make it before. In this case we would get
2107 * the following race condition: hard_start_xmit on other cpu
2108 * enters after we advanced tx_ret_csm and fills space,
2109 * which we have just freed, so that we make illegal device wakeup.
2110 * There is no good way to workaround this (at entry
2111 * to ace_start_xmit detects this condition and prevents
2112 * ring corruption, but it is not a good workaround.)
2113 *
2114 * When tx_ret_csm is advanced after, we wake up device _only_
2115 * if we really have some space in ring (though the core doing
2116 * hard_start_xmit can see full ring for some period and has to
2117 * synchronize.) Superb.
2118 * BUT! We get another subtle race condition. hard_start_xmit
2119 * may think that ring is full between wakeup and advancing
2120 * tx_ret_csm and will stop device instantly! It is not so bad.
2121 * We are guaranteed that there is something in ring, so that
2122 * the next irq will resume transmission. To speedup this we could
2123 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2124 * (see ace_start_xmit).
2125 *
2126 * Well, this dilemma exists in all lock-free devices.
2127 * We, following scheme used in drivers by Donald Becker,
2128 * select the least dangerous.
2129 * --ANK
2130 */
2131}
2132
2133
7d12e780 2134static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2135{
2136 struct net_device *dev = (struct net_device *)dev_id;
2137 struct ace_private *ap = netdev_priv(dev);
2138 struct ace_regs __iomem *regs = ap->regs;
2139 u32 idx;
2140 u32 txcsm, rxretcsm, rxretprd;
2141 u32 evtcsm, evtprd;
2142
2143 /*
2144 * In case of PCI shared interrupts or spurious interrupts,
2145 * we want to make sure it is actually our interrupt before
2146 * spending any time in here.
2147 */
2148 if (!(readl(&regs->HostCtrl) & IN_INT))
2149 return IRQ_NONE;
2150
2151 /*
2152 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2153 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2154 * writel(0, &regs->Mb0Lo).
2155 *
2156 * "IRQ avoidance" recommended in docs applies to IRQs served
2157 * threads and it is wrong even for that case.
2158 */
2159 writel(0, &regs->Mb0Lo);
2160 readl(&regs->Mb0Lo);
2161
2162 /*
2163 * There is no conflict between transmit handling in
2164 * start_xmit and receive processing, thus there is no reason
2165 * to take a spin lock for RX handling. Wait until we start
2166 * working on the other stuff - hey we don't need a spin lock
2167 * anymore.
2168 */
2169 rxretprd = *ap->rx_ret_prd;
2170 rxretcsm = ap->cur_rx;
2171
2172 if (rxretprd != rxretcsm)
2173 ace_rx_int(dev, rxretprd, rxretcsm);
2174
2175 txcsm = *ap->tx_csm;
2176 idx = ap->tx_ret_csm;
2177
2178 if (txcsm != idx) {
2179 /*
2180 * If each skb takes only one descriptor this check degenerates
2181 * to identity, because new space has just been opened.
2182 * But if skbs are fragmented we must check that this index
2183 * update releases enough of space, otherwise we just
2184 * wait for device to make more work.
2185 */
2186 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2187 ace_tx_int(dev, txcsm, idx);
2188 }
2189
2190 evtcsm = readl(&regs->EvtCsm);
2191 evtprd = *ap->evt_prd;
2192
2193 if (evtcsm != evtprd) {
2194 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2195 writel(evtcsm, &regs->EvtCsm);
2196 }
2197
2198 /*
2199 * This has to go last in the interrupt handler and run with
2200 * the spin lock released ... what lock?
2201 */
2202 if (netif_running(dev)) {
2203 int cur_size;
2204 int run_tasklet = 0;
2205
2206 cur_size = atomic_read(&ap->cur_rx_bufs);
2207 if (cur_size < RX_LOW_STD_THRES) {
2208 if ((cur_size < RX_PANIC_STD_THRES) &&
2209 !test_and_set_bit(0, &ap->std_refill_busy)) {
2210#ifdef DEBUG
2211 printk("low on std buffers %i\n", cur_size);
2212#endif
2213 ace_load_std_rx_ring(ap,
2214 RX_RING_SIZE - cur_size);
2215 } else
2216 run_tasklet = 1;
2217 }
2218
2219 if (!ACE_IS_TIGON_I(ap)) {
2220 cur_size = atomic_read(&ap->cur_mini_bufs);
2221 if (cur_size < RX_LOW_MINI_THRES) {
2222 if ((cur_size < RX_PANIC_MINI_THRES) &&
2223 !test_and_set_bit(0,
2224 &ap->mini_refill_busy)) {
2225#ifdef DEBUG
2226 printk("low on mini buffers %i\n",
2227 cur_size);
2228#endif
2229 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2230 } else
2231 run_tasklet = 1;
2232 }
2233 }
2234
2235 if (ap->jumbo) {
2236 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2237 if (cur_size < RX_LOW_JUMBO_THRES) {
2238 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2239 !test_and_set_bit(0,
2240 &ap->jumbo_refill_busy)){
2241#ifdef DEBUG
2242 printk("low on jumbo buffers %i\n",
2243 cur_size);
2244#endif
2245 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2246 } else
2247 run_tasklet = 1;
2248 }
2249 }
2250 if (run_tasklet && !ap->tasklet_pending) {
2251 ap->tasklet_pending = 1;
2252 tasklet_schedule(&ap->ace_tasklet);
2253 }
2254 }
2255
2256 return IRQ_HANDLED;
2257}
2258
2259
2260#if ACENIC_DO_VLAN
2261static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2262{
2263 struct ace_private *ap = netdev_priv(dev);
2264 unsigned long flags;
2265
2266 local_irq_save(flags);
2267 ace_mask_irq(dev);
2268
2269 ap->vlgrp = grp;
2270
2271 ace_unmask_irq(dev);
2272 local_irq_restore(flags);
2273}
1da177e4
LT		 2274#endif /* ACENIC_DO_VLAN */
2275
2276
2277static int ace_open(struct net_device *dev)
2278{
2279 struct ace_private *ap = netdev_priv(dev);
2280 struct ace_regs __iomem *regs = ap->regs;
2281 struct cmd cmd;
2282
2283 if (!(ap->fw_running)) {
2284 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2285 return -EBUSY;
2286 }
2287
2288 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2289
2290 cmd.evt = C_CLEAR_STATS;
2291 cmd.code = 0;
2292 cmd.idx = 0;
2293 ace_issue_cmd(regs, &cmd);
2294
2295 cmd.evt = C_HOST_STATE;
2296 cmd.code = C_C_STACK_UP;
2297 cmd.idx = 0;
2298 ace_issue_cmd(regs, &cmd);
2299
2300 if (ap->jumbo &&
2301 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2302 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2303
2304 if (dev->flags & IFF_PROMISC) {
2305 cmd.evt = C_SET_PROMISC_MODE;
2306 cmd.code = C_C_PROMISC_ENABLE;
2307 cmd.idx = 0;
2308 ace_issue_cmd(regs, &cmd);
2309
2310 ap->promisc = 1;
2311 }else
2312 ap->promisc = 0;
2313 ap->mcast_all = 0;
2314
2315#if 0
2316 cmd.evt = C_LNK_NEGOTIATION;
2317 cmd.code = 0;
2318 cmd.idx = 0;
2319 ace_issue_cmd(regs, &cmd);
2320#endif
2321
2322 netif_start_queue(dev);
2323
2324 /*
2325 * Setup the bottom half rx ring refill handler
2326 */
2327 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2328 return 0;
2329}
2330
2331
2332static int ace_close(struct net_device *dev)
2333{
2334 struct ace_private *ap = netdev_priv(dev);
2335 struct ace_regs __iomem *regs = ap->regs;
2336 struct cmd cmd;
2337 unsigned long flags;
2338 short i;
2339
2340 /*
2341 * Without (or before) releasing irq and stopping hardware, this
2342 * is an absolute non-sense, by the way. It will be reset instantly
2343 * by the first irq.
2344 */
2345 netif_stop_queue(dev);
2346
6aa20a22 2347
1da177e4
LT		 2348 if (ap->promisc) {
2349 cmd.evt = C_SET_PROMISC_MODE;
2350 cmd.code = C_C_PROMISC_DISABLE;
2351 cmd.idx = 0;
2352 ace_issue_cmd(regs, &cmd);
2353 ap->promisc = 0;
2354 }
2355
2356 cmd.evt = C_HOST_STATE;
2357 cmd.code = C_C_STACK_DOWN;
2358 cmd.idx = 0;
2359 ace_issue_cmd(regs, &cmd);
2360
2361 tasklet_kill(&ap->ace_tasklet);
2362
2363 /*
2364 * Make sure one CPU is not processing packets while
2365 * buffers are being released by another.
2366 */
2367
2368 local_irq_save(flags);
2369 ace_mask_irq(dev);
2370
2371 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2372 struct sk_buff *skb;
2373 dma_addr_t mapping;
2374 struct tx_ring_info *info;
2375
2376 info = ap->skb->tx_skbuff + i;
2377 skb = info->skb;
2378 mapping = pci_unmap_addr(info, mapping);
2379
2380 if (mapping) {
2381 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2382 /* NB: TIGON_1 is special, tx_ring is in io space */
2383 struct tx_desc __iomem *tx;
2384 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2385 writel(0, &tx->addr.addrhi);
2386 writel(0, &tx->addr.addrlo);
2387 writel(0, &tx->flagsize);
2388 } else
2389 memset(ap->tx_ring + i, 0,
2390 sizeof(struct tx_desc));
2391 pci_unmap_page(ap->pdev, mapping,
2392 pci_unmap_len(info, maplen),
2393 PCI_DMA_TODEVICE);
2394 pci_unmap_addr_set(info, mapping, 0);
2395 }
2396 if (skb) {
2397 dev_kfree_skb(skb);
2398 info->skb = NULL;
2399 }
2400 }
2401
2402 if (ap->jumbo) {
2403 cmd.evt = C_RESET_JUMBO_RNG;
2404 cmd.code = 0;
2405 cmd.idx = 0;
2406 ace_issue_cmd(regs, &cmd);
2407 }
2408
2409 ace_unmask_irq(dev);
2410 local_irq_restore(flags);
2411
2412 return 0;
2413}
2414
2415
2416static inline dma_addr_t
2417ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2418 struct sk_buff *tail, u32 idx)
2419{
2420 dma_addr_t mapping;
2421 struct tx_ring_info *info;
2422
2423 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2424 offset_in_page(skb->data),
2425 skb->len, PCI_DMA_TODEVICE);
2426
2427 info = ap->skb->tx_skbuff + idx;
2428 info->skb = tail;
2429 pci_unmap_addr_set(info, mapping, mapping);
2430 pci_unmap_len_set(info, maplen, skb->len);
2431 return mapping;
2432}
2433
2434
2435static inline void
2436ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2437 u32 flagsize, u32 vlan_tag)
2438{
2439#if !USE_TX_COAL_NOW
2440 flagsize &= ~BD_FLG_COAL_NOW;
2441#endif
2442
2443 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2444 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2445 writel(addr >> 32, &io->addr.addrhi);
2446 writel(addr & 0xffffffff, &io->addr.addrlo);
2447 writel(flagsize, &io->flagsize);
2448#if ACENIC_DO_VLAN
2449 writel(vlan_tag, &io->vlanres);
2450#endif
2451 } else {
2452 desc->addr.addrhi = addr >> 32;
2453 desc->addr.addrlo = addr;
2454 desc->flagsize = flagsize;
2455#if ACENIC_DO_VLAN
2456 desc->vlanres = vlan_tag;
2457#endif
2458 }
2459}
2460
2461
2462static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2463{
2464 struct ace_private *ap = netdev_priv(dev);
2465 struct ace_regs __iomem *regs = ap->regs;
2466 struct tx_desc *desc;
2467 u32 idx, flagsize;
2468 unsigned long maxjiff = jiffies + 3*HZ;
2469
2470restart:
2471 idx = ap->tx_prd;
2472
2473 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2474 goto overflow;
2475
2476 if (!skb_shinfo(skb)->nr_frags) {
2477 dma_addr_t mapping;
2478 u32 vlan_tag = 0;
2479
2480 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2481 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2482 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2483 flagsize |= BD_FLG_TCP_UDP_SUM;
2484#if ACENIC_DO_VLAN
2485 if (vlan_tx_tag_present(skb)) {
2486 flagsize |= BD_FLG_VLAN_TAG;
2487 vlan_tag = vlan_tx_tag_get(skb);
2488 }
2489#endif
2490 desc = ap->tx_ring + idx;
2491 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2492
2493 /* Look at ace_tx_int for explanations. */
2494 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2495 flagsize |= BD_FLG_COAL_NOW;
2496
2497 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2498 } else {
2499 dma_addr_t mapping;
2500 u32 vlan_tag = 0;
2501 int i, len = 0;
2502
2503 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2504 flagsize = (skb_headlen(skb) << 16);
84fa7933 2505 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2506 flagsize |= BD_FLG_TCP_UDP_SUM;
2507#if ACENIC_DO_VLAN
2508 if (vlan_tx_tag_present(skb)) {
2509 flagsize |= BD_FLG_VLAN_TAG;
2510 vlan_tag = vlan_tx_tag_get(skb);
2511 }
2512#endif
2513
2514 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2515
2516 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2517
2518 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2519 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2520 struct tx_ring_info *info;
2521
2522 len += frag->size;
2523 info = ap->skb->tx_skbuff + idx;
2524 desc = ap->tx_ring + idx;
2525
2526 mapping = pci_map_page(ap->pdev, frag->page,
2527 frag->page_offset, frag->size,
2528 PCI_DMA_TODEVICE);
2529
2530 flagsize = (frag->size << 16);
84fa7933 2531 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2532 flagsize |= BD_FLG_TCP_UDP_SUM;
2533 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2534
2535 if (i == skb_shinfo(skb)->nr_frags - 1) {
2536 flagsize |= BD_FLG_END;
2537 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2538 flagsize |= BD_FLG_COAL_NOW;
2539
2540 /*
2541 * Only the last fragment frees
2542 * the skb!
2543 */
2544 info->skb = skb;
2545 } else {
2546 info->skb = NULL;
2547 }
2548 pci_unmap_addr_set(info, mapping, mapping);
2549 pci_unmap_len_set(info, maplen, frag->size);
2550 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2551 }
2552 }
2553
2554 wmb();
2555 ap->tx_prd = idx;
2556 ace_set_txprd(regs, ap, idx);
2557
2558 if (flagsize & BD_FLG_COAL_NOW) {
2559 netif_stop_queue(dev);
2560
2561 /*
2562 * A TX-descriptor producer (an IRQ) might have gotten
2563 * inbetween, making the ring free again. Since xmit is
2564 * serialized, this is the only situation we have to
2565 * re-test.
2566 */
2567 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2568 netif_wake_queue(dev);
2569 }
2570
2571 dev->trans_start = jiffies;
2572 return NETDEV_TX_OK;
2573
2574overflow:
2575 /*
2576 * This race condition is unavoidable with lock-free drivers.
2577 * We wake up the queue _before_ tx_prd is advanced, so that we can
2578 * enter hard_start_xmit too early, while tx ring still looks closed.
2579 * This happens ~1-4 times per 100000 packets, so that we can allow
2580 * to loop syncing to other CPU. Probably, we need an additional
2581 * wmb() in ace_tx_intr as well.
2582 *
2583 * Note that this race is relieved by reserving one more entry
2584 * in tx ring than it is necessary (see original non-SG driver).
2585 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2586 * is already overkill.
2587 *
2588 * Alternative is to return with 1 not throttling queue. In this
2589 * case loop becomes longer, no more useful effects.
2590 */
2591 if (time_before(jiffies, maxjiff)) {
2592 barrier();
2593 cpu_relax();
2594 goto restart;
2595 }
6aa20a22 2596
1da177e4
LT		 2597 /* The ring is stuck full. */
2598 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2599 return NETDEV_TX_BUSY;
2600}
2601
2602
2603static int ace_change_mtu(struct net_device *dev, int new_mtu)
2604{
2605 struct ace_private *ap = netdev_priv(dev);
2606 struct ace_regs __iomem *regs = ap->regs;
2607
2608 if (new_mtu > ACE_JUMBO_MTU)
2609 return -EINVAL;
2610
2611 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2612 dev->mtu = new_mtu;
2613
2614 if (new_mtu > ACE_STD_MTU) {
2615 if (!(ap->jumbo)) {
2616 printk(KERN_INFO "%s: Enabling Jumbo frame "
2617 "support\n", dev->name);
2618 ap->jumbo = 1;
2619 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2620 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2621 ace_set_rxtx_parms(dev, 1);
2622 }
2623 } else {
2624 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2625 ace_sync_irq(dev->irq);
2626 ace_set_rxtx_parms(dev, 0);
2627 if (ap->jumbo) {
2628 struct cmd cmd;
2629
2630 cmd.evt = C_RESET_JUMBO_RNG;
2631 cmd.code = 0;
2632 cmd.idx = 0;
2633 ace_issue_cmd(regs, &cmd);
2634 }
2635 }
2636
2637 return 0;
2638}
2639
2640static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2641{
2642 struct ace_private *ap = netdev_priv(dev);
2643 struct ace_regs __iomem *regs = ap->regs;
2644 u32 link;
2645
2646 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2647 ecmd->supported =
2648 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2649 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2650 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2651 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2652
2653 ecmd->port = PORT_FIBRE;
2654 ecmd->transceiver = XCVR_INTERNAL;
2655
2656 link = readl(&regs->GigLnkState);
2657 if (link & LNK_1000MB)
2658 ecmd->speed = SPEED_1000;
2659 else {
2660 link = readl(&regs->FastLnkState);
2661 if (link & LNK_100MB)
2662 ecmd->speed = SPEED_100;
2663 else if (link & LNK_10MB)
2664 ecmd->speed = SPEED_10;
2665 else
2666 ecmd->speed = 0;
2667 }
2668 if (link & LNK_FULL_DUPLEX)
2669 ecmd->duplex = DUPLEX_FULL;
2670 else
2671 ecmd->duplex = DUPLEX_HALF;
2672
2673 if (link & LNK_NEGOTIATE)
2674 ecmd->autoneg = AUTONEG_ENABLE;
2675 else
2676 ecmd->autoneg = AUTONEG_DISABLE;
2677
2678#if 0
2679 /*
2680 * Current struct ethtool_cmd is insufficient
2681 */
2682 ecmd->trace = readl(&regs->TuneTrace);
2683
2684 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2685 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2686#endif
2687 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2688 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2689
2690 return 0;
2691}
2692
2693static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2694{
2695 struct ace_private *ap = netdev_priv(dev);
2696 struct ace_regs __iomem *regs = ap->regs;
2697 u32 link, speed;
2698
2699 link = readl(&regs->GigLnkState);
2700 if (link & LNK_1000MB)
2701 speed = SPEED_1000;
2702 else {
2703 link = readl(&regs->FastLnkState);
2704 if (link & LNK_100MB)
2705 speed = SPEED_100;
2706 else if (link & LNK_10MB)
2707 speed = SPEED_10;
2708 else
2709 speed = SPEED_100;
2710 }
2711
2712 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2713 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2714 if (!ACE_IS_TIGON_I(ap))
2715 link |= LNK_TX_FLOW_CTL_Y;
2716 if (ecmd->autoneg == AUTONEG_ENABLE)
2717 link |= LNK_NEGOTIATE;
2718 if (ecmd->speed != speed) {
2719 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2720 switch (speed) {
2721 case SPEED_1000:
2722 link |= LNK_1000MB;
2723 break;
2724 case SPEED_100:
2725 link |= LNK_100MB;
2726 break;
2727 case SPEED_10:
2728 link |= LNK_10MB;
2729 break;
2730 }
2731 }
2732
2733 if (ecmd->duplex == DUPLEX_FULL)
2734 link |= LNK_FULL_DUPLEX;
2735
2736 if (link != ap->link) {
2737 struct cmd cmd;
2738 printk(KERN_INFO "%s: Renegotiating link state\n",
2739 dev->name);
2740
2741 ap->link = link;
2742 writel(link, &regs->TuneLink);
2743 if (!ACE_IS_TIGON_I(ap))
2744 writel(link, &regs->TuneFastLink);
2745 wmb();
2746
2747 cmd.evt = C_LNK_NEGOTIATION;
2748 cmd.code = 0;
2749 cmd.idx = 0;
2750 ace_issue_cmd(regs, &cmd);
2751 }
2752 return 0;
2753}
2754
6aa20a22 2755static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2756 struct ethtool_drvinfo *info)
2757{
2758 struct ace_private *ap = netdev_priv(dev);
2759
2760 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2761 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
1da177e4
LT		 2762 tigonFwReleaseMajor, tigonFwReleaseMinor,
2763 tigonFwReleaseFix);
2764
2765 if (ap->pdev)
6aa20a22 2766 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2767 sizeof(info->bus_info));
2768
2769}
2770
2771/*
2772 * Set the hardware MAC address.
2773 */
2774static int ace_set_mac_addr(struct net_device *dev, void *p)
2775{
2776 struct ace_private *ap = netdev_priv(dev);
2777 struct ace_regs __iomem *regs = ap->regs;
2778 struct sockaddr *addr=p;
2779 u8 *da;
2780 struct cmd cmd;
2781
2782 if(netif_running(dev))
2783 return -EBUSY;
2784
2785 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2786
2787 da = (u8 *)dev->dev_addr;
2788
2789 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2790 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2791 &regs->MacAddrLo);
2792
2793 cmd.evt = C_SET_MAC_ADDR;
2794 cmd.code = 0;
2795 cmd.idx = 0;
2796 ace_issue_cmd(regs, &cmd);
2797
2798 return 0;
2799}
2800
2801
2802static void ace_set_multicast_list(struct net_device *dev)
2803{
2804 struct ace_private *ap = netdev_priv(dev);
2805 struct ace_regs __iomem *regs = ap->regs;
2806 struct cmd cmd;
2807
2808 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2809 cmd.evt = C_SET_MULTICAST_MODE;
2810 cmd.code = C_C_MCAST_ENABLE;
2811 cmd.idx = 0;
2812 ace_issue_cmd(regs, &cmd);
2813 ap->mcast_all = 1;
2814 } else if (ap->mcast_all) {
2815 cmd.evt = C_SET_MULTICAST_MODE;
2816 cmd.code = C_C_MCAST_DISABLE;
2817 cmd.idx = 0;
2818 ace_issue_cmd(regs, &cmd);
2819 ap->mcast_all = 0;
2820 }
2821
2822 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2823 cmd.evt = C_SET_PROMISC_MODE;
2824 cmd.code = C_C_PROMISC_ENABLE;
2825 cmd.idx = 0;
2826 ace_issue_cmd(regs, &cmd);
2827 ap->promisc = 1;
2828 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2829 cmd.evt = C_SET_PROMISC_MODE;
2830 cmd.code = C_C_PROMISC_DISABLE;
2831 cmd.idx = 0;
2832 ace_issue_cmd(regs, &cmd);
2833 ap->promisc = 0;
2834 }
2835
2836 /*
2837 * For the time being multicast relies on the upper layers
2838 * filtering it properly. The Firmware does not allow one to
2839 * set the entire multicast list at a time and keeping track of
2840 * it here is going to be messy.
2841 */
2842 if ((dev->mc_count) && !(ap->mcast_all)) {
2843 cmd.evt = C_SET_MULTICAST_MODE;
2844 cmd.code = C_C_MCAST_ENABLE;
2845 cmd.idx = 0;
2846 ace_issue_cmd(regs, &cmd);
2847 }else if (!ap->mcast_all) {
2848 cmd.evt = C_SET_MULTICAST_MODE;
2849 cmd.code = C_C_MCAST_DISABLE;
2850 cmd.idx = 0;
2851 ace_issue_cmd(regs, &cmd);
2852 }
2853}
2854
2855
2856static struct net_device_stats *ace_get_stats(struct net_device *dev)
2857{
2858 struct ace_private *ap = netdev_priv(dev);
2859 struct ace_mac_stats __iomem *mac_stats =
2860 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2861
966e37bc
PZ		 2862 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2863 dev->stats.multicast = readl(&mac_stats->kept_mc);
2864 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2865
966e37bc 2866 return &dev->stats;
1da177e4
LT		 2867}
2868
2869
2870static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
2871 u32 dest, int size)
2872{
2873 void __iomem *tdest;
2874 u32 *wsrc;
2875 short tsize, i;
2876
2877 if (size <= 0)
2878 return;
2879
2880 while (size > 0) {
2881 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2882 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2883 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2884 (dest & (ACE_WINDOW_SIZE - 1));
2885 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2886 /*
2887 * This requires byte swapping on big endian, however
2888 * writel does that for us
2889 */
2890 wsrc = src;
2891 for (i = 0; i < (tsize / 4); i++) {
2892 writel(wsrc[i], tdest + i*4);
2893 }
2894 dest += tsize;
2895 src += tsize;
2896 size -= tsize;
2897 }
2898
2899 return;
2900}
2901
2902
2903static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2904{
2905 void __iomem *tdest;
2906 short tsize = 0, i;
2907
2908 if (size <= 0)
2909 return;
2910
2911 while (size > 0) {
2912 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2913 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2914 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2915 (dest & (ACE_WINDOW_SIZE - 1));
2916 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2917
2918 for (i = 0; i < (tsize / 4); i++) {
2919 writel(0, tdest + i*4);
2920 }
2921
2922 dest += tsize;
2923 size -= tsize;
2924 }
2925
2926 return;
2927}
2928
2929
2930/*
2931 * Download the firmware into the SRAM on the NIC
2932 *
2933 * This operation requires the NIC to be halted and is performed with
2934 * interrupts disabled and with the spinlock hold.
2935 */
ddfce6bb 2936static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4
LT		 2937{
2938 struct ace_private *ap = netdev_priv(dev);
2939 struct ace_regs __iomem *regs = ap->regs;
2940
2941 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2942 printk(KERN_ERR "%s: trying to download firmware while the "
2943 "CPU is running!\n", ap->name);
2944 return -EFAULT;
2945 }
2946
2947 /*
2948 * Do not try to clear more than 512KB or we end up seeing
2949 * funny things on NICs with only 512KB SRAM
2950 */
2951 ace_clear(regs, 0x2000, 0x80000-0x2000);
2952 if (ACE_IS_TIGON_I(ap)) {
2953 ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
2954 ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
2955 ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
2956 tigonFwRodataLen);
2957 ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
2958 ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
2959 }else if (ap->version == 2) {
2960 ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
2961 ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
2962 ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
2963 ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
2964 tigon2FwRodataLen);
2965 ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
2966 }
2967
2968 return 0;
2969}
2970
2971
2972/*
2973 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2974 *
2975 * Accessing the EEPROM is `interesting' to say the least - don't read
2976 * this code right after dinner.
2977 *
2978 * This is all about black magic and bit-banging the device .... I
2979 * wonder in what hospital they have put the guy who designed the i2c
2980 * specs.
2981 *
2982 * Oh yes, this is only the beginning!
2983 *
2984 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2985 * code i2c readout code by beta testing all my hacks.
2986 */
2987static void __devinit eeprom_start(struct ace_regs __iomem *regs)
2988{
2989 u32 local;
2990
2991 readl(&regs->LocalCtrl);
2992 udelay(ACE_SHORT_DELAY);
2993 local = readl(&regs->LocalCtrl);
2994 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2995 writel(local, &regs->LocalCtrl);
2996 readl(&regs->LocalCtrl);
2997 mb();
2998 udelay(ACE_SHORT_DELAY);
2999 local |= EEPROM_CLK_OUT;
3000 writel(local, &regs->LocalCtrl);
3001 readl(&regs->LocalCtrl);
3002 mb();
3003 udelay(ACE_SHORT_DELAY);
3004 local &= ~EEPROM_DATA_OUT;
3005 writel(local, &regs->LocalCtrl);
3006 readl(&regs->LocalCtrl);
3007 mb();
3008 udelay(ACE_SHORT_DELAY);
3009 local &= ~EEPROM_CLK_OUT;
3010 writel(local, &regs->LocalCtrl);
3011 readl(&regs->LocalCtrl);
3012 mb();
3013}
3014
3015
3016static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3017{
3018 short i;
3019 u32 local;
3020
3021 udelay(ACE_SHORT_DELAY);
3022 local = readl(&regs->LocalCtrl);
3023 local &= ~EEPROM_DATA_OUT;
3024 local |= EEPROM_WRITE_ENABLE;
3025 writel(local, &regs->LocalCtrl);
3026 readl(&regs->LocalCtrl);
3027 mb();
3028
3029 for (i = 0; i < 8; i++, magic <<= 1) {
3030 udelay(ACE_SHORT_DELAY);
6aa20a22 3031 if (magic & 0x80)
1da177e4
LT		 3032 local |= EEPROM_DATA_OUT;
3033 else
3034 local &= ~EEPROM_DATA_OUT;
3035 writel(local, &regs->LocalCtrl);
3036 readl(&regs->LocalCtrl);
3037 mb();
3038
3039 udelay(ACE_SHORT_DELAY);
3040 local |= EEPROM_CLK_OUT;
3041 writel(local, &regs->LocalCtrl);
3042 readl(&regs->LocalCtrl);
3043 mb();
3044 udelay(ACE_SHORT_DELAY);
3045 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3046 writel(local, &regs->LocalCtrl);
3047 readl(&regs->LocalCtrl);
3048 mb();
3049 }
3050}
3051
3052
3053static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3054{
3055 int state;
3056 u32 local;
3057
3058 local = readl(&regs->LocalCtrl);
3059 local &= ~EEPROM_WRITE_ENABLE;
3060 writel(local, &regs->LocalCtrl);
3061 readl(&regs->LocalCtrl);
3062 mb();
3063 udelay(ACE_LONG_DELAY);
3064 local |= EEPROM_CLK_OUT;
3065 writel(local, &regs->LocalCtrl);
3066 readl(&regs->LocalCtrl);
3067 mb();
3068 udelay(ACE_SHORT_DELAY);
3069 /* sample data in middle of high clk */
3070 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3071 udelay(ACE_SHORT_DELAY);
3072 mb();
3073 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3074 readl(&regs->LocalCtrl);
3075 mb();
3076
3077 return state;
3078}
3079
3080
3081static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3082{
3083 u32 local;
3084
3085 udelay(ACE_SHORT_DELAY);
3086 local = readl(&regs->LocalCtrl);
3087 local |= EEPROM_WRITE_ENABLE;
3088 writel(local, &regs->LocalCtrl);
3089 readl(&regs->LocalCtrl);
3090 mb();
3091 udelay(ACE_SHORT_DELAY);
3092 local &= ~EEPROM_DATA_OUT;
3093 writel(local, &regs->LocalCtrl);
3094 readl(&regs->LocalCtrl);
3095 mb();
3096 udelay(ACE_SHORT_DELAY);
3097 local |= EEPROM_CLK_OUT;
3098 writel(local, &regs->LocalCtrl);
3099 readl(&regs->LocalCtrl);
3100 mb();
3101 udelay(ACE_SHORT_DELAY);
3102 local |= EEPROM_DATA_OUT;
3103 writel(local, &regs->LocalCtrl);
3104 readl(&regs->LocalCtrl);
3105 mb();
3106 udelay(ACE_LONG_DELAY);
3107 local &= ~EEPROM_CLK_OUT;
3108 writel(local, &regs->LocalCtrl);
3109 mb();
3110}
3111
3112
3113/*
3114 * Read a whole byte from the EEPROM.
3115 */
3116static int __devinit read_eeprom_byte(struct net_device *dev,
3117 unsigned long offset)
3118{
3119 struct ace_private *ap = netdev_priv(dev);
3120 struct ace_regs __iomem *regs = ap->regs;
3121 unsigned long flags;
3122 u32 local;
3123 int result = 0;
3124 short i;
3125
1da177e4
LT		 3126 /*
3127 * Don't take interrupts on this CPU will bit banging
3128 * the %#%#@$ I2C device
3129 */
3130 local_irq_save(flags);
3131
3132 eeprom_start(regs);
3133
3134 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3135 if (eeprom_check_ack(regs)) {
3136 local_irq_restore(flags);
3137 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3138 result = -EIO;
3139 goto eeprom_read_error;
3140 }
3141
3142 eeprom_prep(regs, (offset >> 8) & 0xff);
3143 if (eeprom_check_ack(regs)) {
3144 local_irq_restore(flags);
3145 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3146 ap->name);
3147 result = -EIO;
3148 goto eeprom_read_error;
3149 }
3150
3151 eeprom_prep(regs, offset & 0xff);
3152 if (eeprom_check_ack(regs)) {
3153 local_irq_restore(flags);
3154 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3155 ap->name);
3156 result = -EIO;
3157 goto eeprom_read_error;
3158 }
3159
3160 eeprom_start(regs);
3161 eeprom_prep(regs, EEPROM_READ_SELECT);
3162 if (eeprom_check_ack(regs)) {
3163 local_irq_restore(flags);
3164 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3165 ap->name);
3166 result = -EIO;
3167 goto eeprom_read_error;
3168 }
3169
3170 for (i = 0; i < 8; i++) {
3171 local = readl(&regs->LocalCtrl);
3172 local &= ~EEPROM_WRITE_ENABLE;
3173 writel(local, &regs->LocalCtrl);
3174 readl(&regs->LocalCtrl);
3175 udelay(ACE_LONG_DELAY);
3176 mb();
3177 local |= EEPROM_CLK_OUT;
3178 writel(local, &regs->LocalCtrl);
3179 readl(&regs->LocalCtrl);
3180 mb();
3181 udelay(ACE_SHORT_DELAY);
3182 /* sample data mid high clk */
3183 result = (result << 1) |
3184 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3185 udelay(ACE_SHORT_DELAY);
3186 mb();
3187 local = readl(&regs->LocalCtrl);
3188 local &= ~EEPROM_CLK_OUT;
3189 writel(local, &regs->LocalCtrl);
3190 readl(&regs->LocalCtrl);
3191 udelay(ACE_SHORT_DELAY);
3192 mb();
3193 if (i == 7) {
3194 local |= EEPROM_WRITE_ENABLE;
3195 writel(local, &regs->LocalCtrl);
3196 readl(&regs->LocalCtrl);
3197 mb();
3198 udelay(ACE_SHORT_DELAY);
3199 }
3200 }
3201
3202 local |= EEPROM_DATA_OUT;
3203 writel(local, &regs->LocalCtrl);
3204 readl(&regs->LocalCtrl);
3205 mb();
3206 udelay(ACE_SHORT_DELAY);
3207 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3208 readl(&regs->LocalCtrl);
3209 udelay(ACE_LONG_DELAY);
3210 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3211 readl(&regs->LocalCtrl);
3212 mb();
3213 udelay(ACE_SHORT_DELAY);
3214 eeprom_stop(regs);
3215
3216 local_irq_restore(flags);
3217 out:
3218 return result;
3219
3220 eeprom_read_error:
3221 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3222 ap->name, offset);
3223 goto out;
3224}
3225
3226
3227/*
3228 * Local variables:
3229 * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
3230 * End:
3231 */
Linux 6.x block layer and io_uring tree(s)