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net: remove interrupt.h inclusion from netdevice.h
[linux-2.6-block.git] / drivers / net / 8139cp.c
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1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
b4f18b3f
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
1da177e4 51#define DRV_NAME "8139cp"
d5b20697 52#define DRV_VERSION "1.3"
1da177e4
LT		 53#define DRV_RELDATE "Mar 22, 2004"
54
55
1da177e4 56#include <linux/module.h>
e21ba282 57#include <linux/moduleparam.h>
1da177e4
LT		 58#include <linux/kernel.h>
59#include <linux/compiler.h>
60#include <linux/netdevice.h>
61#include <linux/etherdevice.h>
62#include <linux/init.h>
a6b7a407 63#include <linux/interrupt.h>
1da177e4 64#include <linux/pci.h>
8662d061 65#include <linux/dma-mapping.h>
1da177e4
LT		 66#include <linux/delay.h>
67#include <linux/ethtool.h>
5a0e3ad6 68#include <linux/gfp.h>
1da177e4
LT		 69#include <linux/mii.h>
70#include <linux/if_vlan.h>
71#include <linux/crc32.h>
72#include <linux/in.h>
73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <linux/udp.h>
76#include <linux/cache.h>
77#include <asm/io.h>
78#include <asm/irq.h>
79#include <asm/uaccess.h>
80
81/* VLAN tagging feature enable/disable */
82#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
83#define CP_VLAN_TAG_USED 1
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 85 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 86#else
87#define CP_VLAN_TAG_USED 0
88#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
89 do { (tx_desc)->opts2 = 0; } while (0)
90#endif
91
92/* These identify the driver base version and may not be removed. */
93static char version[] =
9cc40855 94DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
1da177e4
LT		 95
96MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
97MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 98MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 99MODULE_LICENSE("GPL");
100
101static int debug = -1;
e21ba282 102module_param(debug, int, 0);
1da177e4
LT		 103MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
104
105/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
106 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
107static int multicast_filter_limit = 32;
e21ba282 108module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 109MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
110
1da177e4
LT		 111#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
112 NETIF_MSG_PROBE | \
113 NETIF_MSG_LINK)
114#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
115#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
116#define CP_REGS_SIZE (0xff + 1)
117#define CP_REGS_VER 1 /* version 1 */
118#define CP_RX_RING_SIZE 64
119#define CP_TX_RING_SIZE 64
120#define CP_RING_BYTES \
121 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
122 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
123 CP_STATS_SIZE)
124#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
125#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
126#define TX_BUFFS_AVAIL(CP) \
127 (((CP)->tx_tail <= (CP)->tx_head) ? \
128 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
129 (CP)->tx_tail - (CP)->tx_head - 1)
130
131#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 132#define CP_INTERNAL_PHY 32
133
134/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
135#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
136#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
137#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
138#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
139
140/* Time in jiffies before concluding the transmitter is hung. */
141#define TX_TIMEOUT (6*HZ)
142
143/* hardware minimum and maximum for a single frame's data payload */
144#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
145#define CP_MAX_MTU 4096
146
147enum {
148 /* NIC register offsets */
149 MAC0 = 0x00, /* Ethernet hardware address. */
150 MAR0 = 0x08, /* Multicast filter. */
151 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
152 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
153 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
154 Cmd = 0x37, /* Command register */
155 IntrMask = 0x3C, /* Interrupt mask */
156 IntrStatus = 0x3E, /* Interrupt status */
157 TxConfig = 0x40, /* Tx configuration */
158 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
159 RxConfig = 0x44, /* Rx configuration */
160 RxMissed = 0x4C, /* 24 bits valid, write clears */
161 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
162 Config1 = 0x52, /* Config1 */
163 Config3 = 0x59, /* Config3 */
164 Config4 = 0x5A, /* Config4 */
165 MultiIntr = 0x5C, /* Multiple interrupt select */
166 BasicModeCtrl = 0x62, /* MII BMCR */
167 BasicModeStatus = 0x64, /* MII BMSR */
168 NWayAdvert = 0x66, /* MII ADVERTISE */
169 NWayLPAR = 0x68, /* MII LPA */
170 NWayExpansion = 0x6A, /* MII Expansion */
171 Config5 = 0xD8, /* Config5 */
172 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
173 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
174 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
175 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
176 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
177 TxThresh = 0xEC, /* Early Tx threshold */
178 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
179 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
180
181 /* Tx and Rx status descriptors */
182 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
183 RingEnd = (1 << 30), /* End of descriptor ring */
184 FirstFrag = (1 << 29), /* First segment of a packet */
185 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 186 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
187 MSSShift = 16, /* MSS value position */
188 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 189 TxError = (1 << 23), /* Tx error summary */
190 RxError = (1 << 20), /* Rx error summary */
191 IPCS = (1 << 18), /* Calculate IP checksum */
192 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
193 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
194 TxVlanTag = (1 << 17), /* Add VLAN tag */
195 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
196 IPFail = (1 << 15), /* IP checksum failed */
197 UDPFail = (1 << 14), /* UDP/IP checksum failed */
198 TCPFail = (1 << 13), /* TCP/IP checksum failed */
199 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
200 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
201 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
202 RxProtoTCP = 1,
203 RxProtoUDP = 2,
204 RxProtoIP = 3,
205 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
206 TxOWC = (1 << 22), /* Tx Out-of-window collision */
207 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
208 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
209 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
210 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
211 RxErrFrame = (1 << 27), /* Rx frame alignment error */
212 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
213 RxErrCRC = (1 << 18), /* Rx CRC error */
214 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
215 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
216 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
217
218 /* StatsAddr register */
219 DumpStats = (1 << 3), /* Begin stats dump */
220
221 /* RxConfig register */
222 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
223 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
224 AcceptErr = 0x20, /* Accept packets with CRC errors */
225 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
226 AcceptBroadcast = 0x08, /* Accept broadcast packets */
227 AcceptMulticast = 0x04, /* Accept multicast packets */
228 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
229 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
230
231 /* IntrMask / IntrStatus registers */
232 PciErr = (1 << 15), /* System error on the PCI bus */
233 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
234 LenChg = (1 << 13), /* Cable length change */
235 SWInt = (1 << 8), /* Software-requested interrupt */
236 TxEmpty = (1 << 7), /* No Tx descriptors available */
237 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
238 LinkChg = (1 << 5), /* Packet underrun, or link change */
239 RxEmpty = (1 << 4), /* No Rx descriptors available */
240 TxErr = (1 << 3), /* Tx error */
241 TxOK = (1 << 2), /* Tx packet sent */
242 RxErr = (1 << 1), /* Rx error */
243 RxOK = (1 << 0), /* Rx packet received */
244 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
245 but hardware likes to raise it */
246
247 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
248 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
249 RxErr | RxOK | IntrResvd,
250
251 /* C mode command register */
252 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
253 RxOn = (1 << 3), /* Rx mode enable */
254 TxOn = (1 << 2), /* Tx mode enable */
255
256 /* C+ mode command register */
257 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
258 RxChkSum = (1 << 5), /* Rx checksum offload enable */
259 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
260 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
261 CpRxOn = (1 << 1), /* Rx mode enable */
262 CpTxOn = (1 << 0), /* Tx mode enable */
263
264 /* Cfg9436 EEPROM control register */
265 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
266 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
267
268 /* TxConfig register */
269 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
270 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
271
272 /* Early Tx Threshold register */
273 TxThreshMask = 0x3f, /* Mask bits 5-0 */
274 TxThreshMax = 2048, /* Max early Tx threshold */
275
276 /* Config1 register */
277 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
278 LWACT = (1 << 4), /* LWAKE active mode */
279 PMEnable = (1 << 0), /* Enable various PM features of chip */
280
281 /* Config3 register */
282 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
283 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
284 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
285
286 /* Config4 register */
287 LWPTN = (1 << 1), /* LWAKE Pattern */
288 LWPME = (1 << 4), /* LANWAKE vs PMEB */
289
290 /* Config5 register */
291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LANWake = (1 << 1), /* Enable LANWake signal */
295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296
297 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
298 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
299 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
300};
301
302static const unsigned int cp_rx_config =
303 (RX_FIFO_THRESH << RxCfgFIFOShift) |
304 (RX_DMA_BURST << RxCfgDMAShift);
305
306struct cp_desc {
03233b90 307 __le32 opts1;
cf983019 308 __le32 opts2;
03233b90 309 __le64 addr;
1da177e4
LT		 310};
311
1da177e4 312struct cp_dma_stats {
03233b90
AV		 313 __le64 tx_ok;
314 __le64 rx_ok;
315 __le64 tx_err;
316 __le32 rx_err;
317 __le16 rx_fifo;
318 __le16 frame_align;
319 __le32 tx_ok_1col;
320 __le32 tx_ok_mcol;
321 __le64 rx_ok_phys;
322 __le64 rx_ok_bcast;
323 __le32 rx_ok_mcast;
324 __le16 tx_abort;
325 __le16 tx_underrun;
ba2d3587 326} __packed;
1da177e4
LT		 327
328struct cp_extra_stats {
329 unsigned long rx_frags;
330};
331
332struct cp_private {
333 void __iomem *regs;
334 struct net_device *dev;
335 spinlock_t lock;
336 u32 msg_enable;
337
bea3348e
SH		 338 struct napi_struct napi;
339
1da177e4
LT		 340 struct pci_dev *pdev;
341 u32 rx_config;
342 u16 cpcmd;
343
1da177e4 344 struct cp_extra_stats cp_stats;
1da177e4 345
d03d376d
FR		 346 unsigned rx_head ____cacheline_aligned;
347 unsigned rx_tail;
1da177e4 348 struct cp_desc *rx_ring;
0ba894d4 349 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 350
351 unsigned tx_head ____cacheline_aligned;
352 unsigned tx_tail;
1da177e4 353 struct cp_desc *tx_ring;
48907e39 354 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 355
356 unsigned rx_buf_sz;
357 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 358
359#if CP_VLAN_TAG_USED
360 struct vlan_group *vlgrp;
361#endif
d03d376d 362 dma_addr_t ring_dma;
1da177e4
LT		 363
364 struct mii_if_info mii_if;
365};
366
367#define cpr8(reg) readb(cp->regs + (reg))
368#define cpr16(reg) readw(cp->regs + (reg))
369#define cpr32(reg) readl(cp->regs + (reg))
370#define cpw8(reg,val) writeb((val), cp->regs + (reg))
371#define cpw16(reg,val) writew((val), cp->regs + (reg))
372#define cpw32(reg,val) writel((val), cp->regs + (reg))
373#define cpw8_f(reg,val) do { \
374 writeb((val), cp->regs + (reg)); \
375 readb(cp->regs + (reg)); \
376 } while (0)
377#define cpw16_f(reg,val) do { \
378 writew((val), cp->regs + (reg)); \
379 readw(cp->regs + (reg)); \
380 } while (0)
381#define cpw32_f(reg,val) do { \
382 writel((val), cp->regs + (reg)); \
383 readl(cp->regs + (reg)); \
384 } while (0)
385
386
387static void __cp_set_rx_mode (struct net_device *dev);
388static void cp_tx (struct cp_private *cp);
389static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 390#ifdef CONFIG_NET_POLL_CONTROLLER
391static void cp_poll_controller(struct net_device *dev);
392#endif
722fdb33
PC		 393static int cp_get_eeprom_len(struct net_device *dev);
394static int cp_get_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396static int cp_set_eeprom(struct net_device *dev,
397 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4 398
a3aa1884 399static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
cccb20d3
FR		 400 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
401 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 402 { },
403};
404MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
405
406static struct {
407 const char str[ETH_GSTRING_LEN];
408} ethtool_stats_keys[] = {
409 { "tx_ok" },
410 { "rx_ok" },
411 { "tx_err" },
412 { "rx_err" },
413 { "rx_fifo" },
414 { "frame_align" },
415 { "tx_ok_1col" },
416 { "tx_ok_mcol" },
417 { "rx_ok_phys" },
418 { "rx_ok_bcast" },
419 { "rx_ok_mcast" },
420 { "tx_abort" },
421 { "tx_underrun" },
422 { "rx_frags" },
423};
424
425
426#if CP_VLAN_TAG_USED
427static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
428{
429 struct cp_private *cp = netdev_priv(dev);
430 unsigned long flags;
431
432 spin_lock_irqsave(&cp->lock, flags);
433 cp->vlgrp = grp;
7b332244
SH		 434 if (grp)
435 cp->cpcmd |= RxVlanOn;
436 else
437 cp->cpcmd &= ~RxVlanOn;
1da177e4 438
1da177e4 439 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 440 spin_unlock_irqrestore(&cp->lock, flags);
441}
442#endif /* CP_VLAN_TAG_USED */
443
444static inline void cp_set_rxbufsize (struct cp_private *cp)
445{
446 unsigned int mtu = cp->dev->mtu;
f3b197ac 447
1da177e4
LT		 448 if (mtu > ETH_DATA_LEN)
449 /* MTU + ethernet header + FCS + optional VLAN tag */
450 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
451 else
452 cp->rx_buf_sz = PKT_BUF_SZ;
453}
454
455static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
456 struct cp_desc *desc)
457{
458 skb->protocol = eth_type_trans (skb, cp->dev);
459
237225f7
PZ		 460 cp->dev->stats.rx_packets++;
461 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 462
463#if CP_VLAN_TAG_USED
cf983019 464 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 465 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 466 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 467 } else
468#endif
469 netif_receive_skb(skb);
470}
471
472static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
473 u32 status, u32 len)
474{
b4f18b3f
JP		 475 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
476 rx_tail, status, len);
237225f7 477 cp->dev->stats.rx_errors++;
1da177e4 478 if (status & RxErrFrame)
237225f7 479 cp->dev->stats.rx_frame_errors++;
1da177e4 480 if (status & RxErrCRC)
237225f7 481 cp->dev->stats.rx_crc_errors++;
1da177e4 482 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 483 cp->dev->stats.rx_length_errors++;
1da177e4 484 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 485 cp->dev->stats.rx_length_errors++;
1da177e4 486 if (status & RxErrFIFO)
237225f7 487 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 488}
489
490static inline unsigned int cp_rx_csum_ok (u32 status)
491{
492 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 493
24b7ea9f
SW		 494 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
495 ((protocol == RxProtoUDP) && !(status & UDPFail)))
1da177e4 496 return 1;
24b7ea9f
SW		 497 else
498 return 0;
1da177e4
LT		 499}
500
bea3348e 501static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 502{
bea3348e
SH		 503 struct cp_private *cp = container_of(napi, struct cp_private, napi);
504 struct net_device *dev = cp->dev;
505 unsigned int rx_tail = cp->rx_tail;
506 int rx;
1da177e4
LT		 507
508rx_status_loop:
509 rx = 0;
510 cpw16(IntrStatus, cp_rx_intr_mask);
511
512 while (1) {
513 u32 status, len;
514 dma_addr_t mapping;
515 struct sk_buff *skb, *new_skb;
516 struct cp_desc *desc;
839d1624 517 const unsigned buflen = cp->rx_buf_sz;
1da177e4 518
0ba894d4 519 skb = cp->rx_skb[rx_tail];
5d9428de 520 BUG_ON(!skb);
1da177e4
LT		 521
522 desc = &cp->rx_ring[rx_tail];
523 status = le32_to_cpu(desc->opts1);
524 if (status & DescOwn)
525 break;
526
527 len = (status & 0x1fff) - 4;
3598b57b 528 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 529
530 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
531 /* we don't support incoming fragmented frames.
532 * instead, we attempt to ensure that the
533 * pre-allocated RX skbs are properly sized such
534 * that RX fragments are never encountered
535 */
536 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 537 dev->stats.rx_dropped++;
1da177e4
LT		 538 cp->cp_stats.rx_frags++;
539 goto rx_next;
540 }
541
542 if (status & (RxError | RxErrFIFO)) {
543 cp_rx_err_acct(cp, rx_tail, status, len);
544 goto rx_next;
545 }
546
b4f18b3f
JP		 547 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
548 rx_tail, status, len);
1da177e4 549
89d71a66 550 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
1da177e4 551 if (!new_skb) {
237225f7 552 dev->stats.rx_dropped++;
1da177e4
LT		 553 goto rx_next;
554 }
555
6cc92cdd 556 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 557 buflen, PCI_DMA_FROMDEVICE);
558
559 /* Handle checksum offloading for incoming packets. */
560 if (cp_rx_csum_ok(status))
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 else
bc8acf2c 563 skb_checksum_none_assert(skb);
1da177e4
LT		 564
565 skb_put(skb, len);
566
6cc92cdd 567 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 568 PCI_DMA_FROMDEVICE);
0ba894d4 569 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 570
571 cp_rx_skb(cp, skb, desc);
572 rx++;
573
574rx_next:
575 cp->rx_ring[rx_tail].opts2 = 0;
576 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
577 if (rx_tail == (CP_RX_RING_SIZE - 1))
578 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
579 cp->rx_buf_sz);
580 else
581 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
582 rx_tail = NEXT_RX(rx_tail);
583
bea3348e 584 if (rx >= budget)
1da177e4
LT		 585 break;
586 }
587
588 cp->rx_tail = rx_tail;
589
1da177e4
LT		 590 /* if we did not reach work limit, then we're done with
591 * this round of polling
592 */
bea3348e 593 if (rx < budget) {
d15e9c4d
FR		 594 unsigned long flags;
595
1da177e4
LT		 596 if (cpr16(IntrStatus) & cp_rx_intr_mask)
597 goto rx_status_loop;
598
bea3348e 599 spin_lock_irqsave(&cp->lock, flags);
288379f0 600 __napi_complete(napi);
349124a0 601 cpw16_f(IntrMask, cp_intr_mask);
bea3348e 602 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 603 }
604
bea3348e 605 return rx;
1da177e4
LT		 606}
607
7d12e780 608static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 609{
610 struct net_device *dev = dev_instance;
611 struct cp_private *cp;
612 u16 status;
613
614 if (unlikely(dev == NULL))
615 return IRQ_NONE;
616 cp = netdev_priv(dev);
617
618 status = cpr16(IntrStatus);
619 if (!status || (status == 0xFFFF))
620 return IRQ_NONE;
621
b4f18b3f
JP		 622 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
623 status, cpr8(Cmd), cpr16(CpCmd));
1da177e4
LT		 624
625 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
626
627 spin_lock(&cp->lock);
628
629 /* close possible race's with dev_close */
630 if (unlikely(!netif_running(dev))) {
631 cpw16(IntrMask, 0);
632 spin_unlock(&cp->lock);
633 return IRQ_HANDLED;
634 }
635
636 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
288379f0 637 if (napi_schedule_prep(&cp->napi)) {
1da177e4 638 cpw16_f(IntrMask, cp_norx_intr_mask);
288379f0 639 __napi_schedule(&cp->napi);
1da177e4
LT		 640 }
641
642 if (status & (TxOK | TxErr | TxEmpty | SWInt))
643 cp_tx(cp);
644 if (status & LinkChg)
2501f843 645 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 646
647 spin_unlock(&cp->lock);
648
649 if (status & PciErr) {
650 u16 pci_status;
651
652 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
653 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
b4f18b3f
JP		 654 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
655 status, pci_status);
1da177e4
LT		 656
657 /* TODO: reset hardware */
658 }
659
660 return IRQ_HANDLED;
661}
662
7502cd10
SK		 663#ifdef CONFIG_NET_POLL_CONTROLLER
664/*
665 * Polling receive - used by netconsole and other diagnostic tools
666 * to allow network i/o with interrupts disabled.
667 */
668static void cp_poll_controller(struct net_device *dev)
669{
670 disable_irq(dev->irq);
7d12e780 671 cp_interrupt(dev->irq, dev);
7502cd10
SK		 672 enable_irq(dev->irq);
673}
674#endif
675
1da177e4
LT		 676static void cp_tx (struct cp_private *cp)
677{
678 unsigned tx_head = cp->tx_head;
679 unsigned tx_tail = cp->tx_tail;
680
681 while (tx_tail != tx_head) {
3598b57b 682 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 683 struct sk_buff *skb;
684 u32 status;
685
686 rmb();
3598b57b 687 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 688 if (status & DescOwn)
689 break;
690
48907e39 691 skb = cp->tx_skb[tx_tail];
5d9428de 692 BUG_ON(!skb);
1da177e4 693
6cc92cdd 694 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 695 le32_to_cpu(txd->opts1) & 0xffff,
696 PCI_DMA_TODEVICE);
1da177e4
LT		 697
698 if (status & LastFrag) {
699 if (status & (TxError | TxFIFOUnder)) {
b4f18b3f
JP		 700 netif_dbg(cp, tx_err, cp->dev,
701 "tx err, status 0x%x\n", status);
237225f7 702 cp->dev->stats.tx_errors++;
1da177e4 703 if (status & TxOWC)
237225f7 704 cp->dev->stats.tx_window_errors++;
1da177e4 705 if (status & TxMaxCol)
237225f7 706 cp->dev->stats.tx_aborted_errors++;
1da177e4 707 if (status & TxLinkFail)
237225f7 708 cp->dev->stats.tx_carrier_errors++;
1da177e4 709 if (status & TxFIFOUnder)
237225f7 710 cp->dev->stats.tx_fifo_errors++;
1da177e4 711 } else {
237225f7 712 cp->dev->stats.collisions +=
1da177e4 713 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 714 cp->dev->stats.tx_packets++;
715 cp->dev->stats.tx_bytes += skb->len;
b4f18b3f
JP		 716 netif_dbg(cp, tx_done, cp->dev,
717 "tx done, slot %d\n", tx_tail);
1da177e4
LT		 718 }
719 dev_kfree_skb_irq(skb);
720 }
721
48907e39 722 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 723
724 tx_tail = NEXT_TX(tx_tail);
725 }
726
727 cp->tx_tail = tx_tail;
728
729 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
730 netif_wake_queue(cp->dev);
731}
732
61357325
SH		 733static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
734 struct net_device *dev)
1da177e4
LT		 735{
736 struct cp_private *cp = netdev_priv(dev);
737 unsigned entry;
fcec3456 738 u32 eor, flags;
553af567 739 unsigned long intr_flags;
1da177e4
LT		 740#if CP_VLAN_TAG_USED
741 u32 vlan_tag = 0;
742#endif
fcec3456 743 int mss = 0;
1da177e4 744
553af567 745 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 746
747 /* This is a hard error, log it. */
748 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
749 netif_stop_queue(dev);
553af567 750 spin_unlock_irqrestore(&cp->lock, intr_flags);
b4f18b3f 751 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5b548140 752 return NETDEV_TX_BUSY;
1da177e4
LT		 753 }
754
755#if CP_VLAN_TAG_USED
eab6d18d 756 if (vlan_tx_tag_present(skb))
cf983019 757 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 758#endif
759
760 entry = cp->tx_head;
761 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
044a890c 762 mss = skb_shinfo(skb)->gso_size;
fcec3456 763
1da177e4
LT		 764 if (skb_shinfo(skb)->nr_frags == 0) {
765 struct cp_desc *txd = &cp->tx_ring[entry];
766 u32 len;
767 dma_addr_t mapping;
768
769 len = skb->len;
6cc92cdd 770 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 771 CP_VLAN_TX_TAG(txd, vlan_tag);
772 txd->addr = cpu_to_le64(mapping);
773 wmb();
774
fcec3456
JG		 775 flags = eor | len | DescOwn | FirstFrag | LastFrag;
776
777 if (mss)
778 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 779 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 780 const struct iphdr *ip = ip_hdr(skb);
1da177e4 781 if (ip->protocol == IPPROTO_TCP)
fcec3456 782 flags |= IPCS | TCPCS;
1da177e4 783 else if (ip->protocol == IPPROTO_UDP)
fcec3456 784 flags |= IPCS | UDPCS;
1da177e4 785 else
5734418d 786 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 787 }
788
789 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 790 wmb();
791
48907e39 792 cp->tx_skb[entry] = skb;
1da177e4
LT		 793 entry = NEXT_TX(entry);
794 } else {
795 struct cp_desc *txd;
796 u32 first_len, first_eor;
797 dma_addr_t first_mapping;
798 int frag, first_entry = entry;
eddc9ec5 799 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 800
801 /* We must give this initial chunk to the device last.
802 * Otherwise we could race with the device.
803 */
804 first_eor = eor;
805 first_len = skb_headlen(skb);
6cc92cdd 806 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 807 first_len, PCI_DMA_TODEVICE);
48907e39 808 cp->tx_skb[entry] = skb;
1da177e4
LT		 809 entry = NEXT_TX(entry);
810
811 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
812 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
813 u32 len;
814 u32 ctrl;
815 dma_addr_t mapping;
816
817 len = this_frag->size;
6cc92cdd 818 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 819 ((void *) page_address(this_frag->page) +
820 this_frag->page_offset),
821 len, PCI_DMA_TODEVICE);
822 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
823
fcec3456
JG		 824 ctrl = eor | len | DescOwn;
825
826 if (mss)
827 ctrl |= LargeSend |
828 ((mss & MSSMask) << MSSShift);
84fa7933 829 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 830 if (ip->protocol == IPPROTO_TCP)
fcec3456 831 ctrl |= IPCS | TCPCS;
1da177e4 832 else if (ip->protocol == IPPROTO_UDP)
fcec3456 833 ctrl |= IPCS | UDPCS;
1da177e4
LT		 834 else
835 BUG();
fcec3456 836 }
1da177e4
LT		 837
838 if (frag == skb_shinfo(skb)->nr_frags - 1)
839 ctrl |= LastFrag;
840
841 txd = &cp->tx_ring[entry];
842 CP_VLAN_TX_TAG(txd, vlan_tag);
843 txd->addr = cpu_to_le64(mapping);
844 wmb();
845
846 txd->opts1 = cpu_to_le32(ctrl);
847 wmb();
848
48907e39 849 cp->tx_skb[entry] = skb;
1da177e4
LT		 850 entry = NEXT_TX(entry);
851 }
852
853 txd = &cp->tx_ring[first_entry];
854 CP_VLAN_TX_TAG(txd, vlan_tag);
855 txd->addr = cpu_to_le64(first_mapping);
856 wmb();
857
84fa7933 858 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 859 if (ip->protocol == IPPROTO_TCP)
860 txd->opts1 = cpu_to_le32(first_eor | first_len |
861 FirstFrag | DescOwn |
862 IPCS | TCPCS);
863 else if (ip->protocol == IPPROTO_UDP)
864 txd->opts1 = cpu_to_le32(first_eor | first_len |
865 FirstFrag | DescOwn |
866 IPCS | UDPCS);
867 else
868 BUG();
869 } else
870 txd->opts1 = cpu_to_le32(first_eor | first_len |
871 FirstFrag | DescOwn);
872 wmb();
873 }
874 cp->tx_head = entry;
b4f18b3f
JP		 875 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
876 entry, skb->len);
1da177e4
LT		 877 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
878 netif_stop_queue(dev);
879
553af567 880 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 881
882 cpw8(TxPoll, NormalTxPoll);
1da177e4 883
6ed10654 884 return NETDEV_TX_OK;
1da177e4
LT		 885}
886
887/* Set or clear the multicast filter for this adaptor.
888 This routine is not state sensitive and need not be SMP locked. */
889
890static void __cp_set_rx_mode (struct net_device *dev)
891{
892 struct cp_private *cp = netdev_priv(dev);
893 u32 mc_filter[2]; /* Multicast hash filter */
a56ed41d 894 int rx_mode;
1da177e4
LT		 895 u32 tmp;
896
897 /* Note: do not reorder, GCC is clever about common statements. */
898 if (dev->flags & IFF_PROMISC) {
899 /* Unconditionally log net taps. */
1da177e4
LT		 900 rx_mode =
901 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
902 AcceptAllPhys;
903 mc_filter[1] = mc_filter[0] = 0xffffffff;
a56ed41d 904 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 905 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 906 /* Too many to filter perfectly -- accept all multicasts. */
907 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
908 mc_filter[1] = mc_filter[0] = 0xffffffff;
909 } else {
22bedad3 910 struct netdev_hw_addr *ha;
1da177e4
LT		 911 rx_mode = AcceptBroadcast | AcceptMyPhys;
912 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 913 netdev_for_each_mc_addr(ha, dev) {
914 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 915
916 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
917 rx_mode |= AcceptMulticast;
918 }
919 }
920
921 /* We can safely update without stopping the chip. */
922 tmp = cp_rx_config | rx_mode;
923 if (cp->rx_config != tmp) {
924 cpw32_f (RxConfig, tmp);
925 cp->rx_config = tmp;
926 }
927 cpw32_f (MAR0 + 0, mc_filter[0]);
928 cpw32_f (MAR0 + 4, mc_filter[1]);
929}
930
931static void cp_set_rx_mode (struct net_device *dev)
932{
933 unsigned long flags;
934 struct cp_private *cp = netdev_priv(dev);
935
936 spin_lock_irqsave (&cp->lock, flags);
937 __cp_set_rx_mode(dev);
938 spin_unlock_irqrestore (&cp->lock, flags);
939}
940
941static void __cp_get_stats(struct cp_private *cp)
942{
943 /* only lower 24 bits valid; write any value to clear */
237225f7 944 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 945 cpw32 (RxMissed, 0);
946}
947
948static struct net_device_stats *cp_get_stats(struct net_device *dev)
949{
950 struct cp_private *cp = netdev_priv(dev);
951 unsigned long flags;
952
953 /* The chip only need report frame silently dropped. */
954 spin_lock_irqsave(&cp->lock, flags);
955 if (netif_running(dev) && netif_device_present(dev))
956 __cp_get_stats(cp);
957 spin_unlock_irqrestore(&cp->lock, flags);
958
237225f7 959 return &dev->stats;
1da177e4
LT		 960}
961
962static void cp_stop_hw (struct cp_private *cp)
963{
964 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
965 cpw16_f(IntrMask, 0);
966 cpw8(Cmd, 0);
967 cpw16_f(CpCmd, 0);
968 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
969
970 cp->rx_tail = 0;
971 cp->tx_head = cp->tx_tail = 0;
972}
973
974static void cp_reset_hw (struct cp_private *cp)
975{
976 unsigned work = 1000;
977
978 cpw8(Cmd, CmdReset);
979
980 while (work--) {
981 if (!(cpr8(Cmd) & CmdReset))
982 return;
983
3173c890 984 schedule_timeout_uninterruptible(10);
1da177e4
LT		 985 }
986
b4f18b3f 987 netdev_err(cp->dev, "hardware reset timeout\n");
1da177e4
LT		 988}
989
990static inline void cp_start_hw (struct cp_private *cp)
991{
992 cpw16(CpCmd, cp->cpcmd);
993 cpw8(Cmd, RxOn | TxOn);
994}
995
996static void cp_init_hw (struct cp_private *cp)
997{
998 struct net_device *dev = cp->dev;
999 dma_addr_t ring_dma;
1000
1001 cp_reset_hw(cp);
1002
1003 cpw8_f (Cfg9346, Cfg9346_Unlock);
1004
1005 /* Restore our idea of the MAC address. */
03233b90
AV		 1006 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1007 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1008
1009 cp_start_hw(cp);
1010 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1011
1012 __cp_set_rx_mode(dev);
1013 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1014
1015 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1016 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1017 cpw8(Config3, PARMEnable);
1018 cp->wol_enabled = 0;
1019
f3b197ac 1020 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1021
1022 cpw32_f(HiTxRingAddr, 0);
1023 cpw32_f(HiTxRingAddr + 4, 0);
1024
1025 ring_dma = cp->ring_dma;
1026 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1027 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1028
1029 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1030 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1031 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1032
1033 cpw16(MultiIntr, 0);
1034
1035 cpw16_f(IntrMask, cp_intr_mask);
1036
1037 cpw8_f(Cfg9346, Cfg9346_Lock);
1038}
1039
a52be1cb 1040static int cp_refill_rx(struct cp_private *cp)
1da177e4 1041{
a52be1cb 1042 struct net_device *dev = cp->dev;
1da177e4
LT		 1043 unsigned i;
1044
1045 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1046 struct sk_buff *skb;
3598b57b 1047 dma_addr_t mapping;
1da177e4 1048
89d71a66 1049 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1da177e4
LT		 1050 if (!skb)
1051 goto err_out;
1052
6cc92cdd
JG		 1053 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1054 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1055 cp->rx_skb[i] = skb;
1da177e4
LT		 1056
1057 cp->rx_ring[i].opts2 = 0;
3598b57b 1058 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1059 if (i == (CP_RX_RING_SIZE - 1))
1060 cp->rx_ring[i].opts1 =
1061 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1062 else
1063 cp->rx_ring[i].opts1 =
1064 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1065 }
1066
1067 return 0;
1068
1069err_out:
1070 cp_clean_rings(cp);
1071 return -ENOMEM;
1072}
1073
576cfa93
FR		 1074static void cp_init_rings_index (struct cp_private *cp)
1075{
1076 cp->rx_tail = 0;
1077 cp->tx_head = cp->tx_tail = 0;
1078}
1079
1da177e4
LT		 1080static int cp_init_rings (struct cp_private *cp)
1081{
1082 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1083 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1084
576cfa93 1085 cp_init_rings_index(cp);
1da177e4
LT		 1086
1087 return cp_refill_rx (cp);
1088}
1089
1090static int cp_alloc_rings (struct cp_private *cp)
1091{
1092 void *mem;
1093
6cc92cdd
JG		 1094 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1095 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1096 if (!mem)
1097 return -ENOMEM;
1098
1099 cp->rx_ring = mem;
1100 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1101
1da177e4
LT		 1102 return cp_init_rings(cp);
1103}
1104
1105static void cp_clean_rings (struct cp_private *cp)
1106{
3598b57b 1107 struct cp_desc *desc;
1da177e4
LT		 1108 unsigned i;
1109
1da177e4 1110 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1111 if (cp->rx_skb[i]) {
3598b57b 1112 desc = cp->rx_ring + i;
6cc92cdd 1113 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1114 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1115 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1116 }
1117 }
1118
1119 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1120 if (cp->tx_skb[i]) {
1121 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1122
3598b57b 1123 desc = cp->tx_ring + i;
6cc92cdd 1124 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1125 le32_to_cpu(desc->opts1) & 0xffff,
1126 PCI_DMA_TODEVICE);
3598b57b 1127 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1128 dev_kfree_skb(skb);
237225f7 1129 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1130 }
1131 }
1132
5734418d
FR		 1133 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1134 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1135
0ba894d4 1136 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1137 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1138}
1139
1140static void cp_free_rings (struct cp_private *cp)
1141{
1142 cp_clean_rings(cp);
6cc92cdd
JG		 1143 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1144 cp->ring_dma);
1da177e4
LT		 1145 cp->rx_ring = NULL;
1146 cp->tx_ring = NULL;
1da177e4
LT		 1147}
1148
1149static int cp_open (struct net_device *dev)
1150{
1151 struct cp_private *cp = netdev_priv(dev);
1152 int rc;
1153
b4f18b3f 1154 netif_dbg(cp, ifup, dev, "enabling interface\n");
1da177e4
LT		 1155
1156 rc = cp_alloc_rings(cp);
1157 if (rc)
1158 return rc;
1159
bea3348e
SH		 1160 napi_enable(&cp->napi);
1161
1da177e4
LT		 1162 cp_init_hw(cp);
1163
1fb9df5d 1164 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1165 if (rc)
1166 goto err_out_hw;
1167
1168 netif_carrier_off(dev);
2501f843 1169 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1170 netif_start_queue(dev);
1171
1172 return 0;
1173
1174err_out_hw:
bea3348e 1175 napi_disable(&cp->napi);
1da177e4
LT		 1176 cp_stop_hw(cp);
1177 cp_free_rings(cp);
1178 return rc;
1179}
1180
1181static int cp_close (struct net_device *dev)
1182{
1183 struct cp_private *cp = netdev_priv(dev);
1184 unsigned long flags;
1185
bea3348e
SH		 1186 napi_disable(&cp->napi);
1187
b4f18b3f 1188 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1da177e4
LT		 1189
1190 spin_lock_irqsave(&cp->lock, flags);
1191
1192 netif_stop_queue(dev);
1193 netif_carrier_off(dev);
1194
1195 cp_stop_hw(cp);
1196
1197 spin_unlock_irqrestore(&cp->lock, flags);
1198
1da177e4
LT		 1199 free_irq(dev->irq, dev);
1200
1201 cp_free_rings(cp);
1202 return 0;
1203}
1204
9030c0d2
FR		 1205static void cp_tx_timeout(struct net_device *dev)
1206{
1207 struct cp_private *cp = netdev_priv(dev);
1208 unsigned long flags;
1209 int rc;
1210
b4f18b3f
JP		 1211 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1212 cpr8(Cmd), cpr16(CpCmd),
1213 cpr16(IntrStatus), cpr16(IntrMask));
9030c0d2
FR		 1214
1215 spin_lock_irqsave(&cp->lock, flags);
1216
1217 cp_stop_hw(cp);
1218 cp_clean_rings(cp);
1219 rc = cp_init_rings(cp);
1220 cp_start_hw(cp);
1221
1222 netif_wake_queue(dev);
1223
1224 spin_unlock_irqrestore(&cp->lock, flags);
9030c0d2
FR		 1225}
1226
1da177e4
LT		 1227#ifdef BROKEN
1228static int cp_change_mtu(struct net_device *dev, int new_mtu)
1229{
1230 struct cp_private *cp = netdev_priv(dev);
1231 int rc;
1232 unsigned long flags;
1233
1234 /* check for invalid MTU, according to hardware limits */
1235 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1236 return -EINVAL;
1237
1238 /* if network interface not up, no need for complexity */
1239 if (!netif_running(dev)) {
1240 dev->mtu = new_mtu;
1241 cp_set_rxbufsize(cp); /* set new rx buf size */
1242 return 0;
1243 }
1244
1245 spin_lock_irqsave(&cp->lock, flags);
1246
1247 cp_stop_hw(cp); /* stop h/w and free rings */
1248 cp_clean_rings(cp);
1249
1250 dev->mtu = new_mtu;
1251 cp_set_rxbufsize(cp); /* set new rx buf size */
1252
1253 rc = cp_init_rings(cp); /* realloc and restart h/w */
1254 cp_start_hw(cp);
1255
1256 spin_unlock_irqrestore(&cp->lock, flags);
1257
1258 return rc;
1259}
1260#endif /* BROKEN */
1261
f71e1309 1262static const char mii_2_8139_map[8] = {
1da177e4
LT		 1263 BasicModeCtrl,
1264 BasicModeStatus,
1265 0,
1266 0,
1267 NWayAdvert,
1268 NWayLPAR,
1269 NWayExpansion,
1270 0
1271};
1272
1273static int mdio_read(struct net_device *dev, int phy_id, int location)
1274{
1275 struct cp_private *cp = netdev_priv(dev);
1276
1277 return location < 8 && mii_2_8139_map[location] ?
1278 readw(cp->regs + mii_2_8139_map[location]) : 0;
1279}
1280
1281
1282static void mdio_write(struct net_device *dev, int phy_id, int location,
1283 int value)
1284{
1285 struct cp_private *cp = netdev_priv(dev);
1286
1287 if (location == 0) {
1288 cpw8(Cfg9346, Cfg9346_Unlock);
1289 cpw16(BasicModeCtrl, value);
1290 cpw8(Cfg9346, Cfg9346_Lock);
1291 } else if (location < 8 && mii_2_8139_map[location])
1292 cpw16(mii_2_8139_map[location], value);
1293}
1294
1295/* Set the ethtool Wake-on-LAN settings */
1296static int netdev_set_wol (struct cp_private *cp,
1297 const struct ethtool_wolinfo *wol)
1298{
1299 u8 options;
1300
1301 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1302 /* If WOL is being disabled, no need for complexity */
1303 if (wol->wolopts) {
1304 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1305 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1306 }
1307
1308 cpw8 (Cfg9346, Cfg9346_Unlock);
1309 cpw8 (Config3, options);
1310 cpw8 (Cfg9346, Cfg9346_Lock);
1311
1312 options = 0; /* Paranoia setting */
1313 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1314 /* If WOL is being disabled, no need for complexity */
1315 if (wol->wolopts) {
1316 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1317 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1318 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1319 }
1320
1321 cpw8 (Config5, options);
1322
1323 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1324
1325 return 0;
1326}
1327
1328/* Get the ethtool Wake-on-LAN settings */
1329static void netdev_get_wol (struct cp_private *cp,
1330 struct ethtool_wolinfo *wol)
1331{
1332 u8 options;
1333
1334 wol->wolopts = 0; /* Start from scratch */
1335 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1336 WAKE_MCAST | WAKE_UCAST;
1337 /* We don't need to go on if WOL is disabled */
1338 if (!cp->wol_enabled) return;
f3b197ac 1339
1da177e4
LT		 1340 options = cpr8 (Config3);
1341 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1342 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1343
1344 options = 0; /* Paranoia setting */
1345 options = cpr8 (Config5);
1346 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1347 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1348 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1349}
1350
1351static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1352{
1353 struct cp_private *cp = netdev_priv(dev);
1354
1355 strcpy (info->driver, DRV_NAME);
1356 strcpy (info->version, DRV_VERSION);
1357 strcpy (info->bus_info, pci_name(cp->pdev));
1358}
1359
1360static int cp_get_regs_len(struct net_device *dev)
1361{
1362 return CP_REGS_SIZE;
1363}
1364
b9f2c044 1365static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1366{
b9f2c044
JG		 1367 switch (sset) {
1368 case ETH_SS_STATS:
1369 return CP_NUM_STATS;
1370 default:
1371 return -EOPNOTSUPP;
1372 }
1da177e4
LT		 1373}
1374
1375static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1376{
1377 struct cp_private *cp = netdev_priv(dev);
1378 int rc;
1379 unsigned long flags;
1380
1381 spin_lock_irqsave(&cp->lock, flags);
1382 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1383 spin_unlock_irqrestore(&cp->lock, flags);
1384
1385 return rc;
1386}
1387
1388static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1389{
1390 struct cp_private *cp = netdev_priv(dev);
1391 int rc;
1392 unsigned long flags;
1393
1394 spin_lock_irqsave(&cp->lock, flags);
1395 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1396 spin_unlock_irqrestore(&cp->lock, flags);
1397
1398 return rc;
1399}
1400
1401static int cp_nway_reset(struct net_device *dev)
1402{
1403 struct cp_private *cp = netdev_priv(dev);
1404 return mii_nway_restart(&cp->mii_if);
1405}
1406
1407static u32 cp_get_msglevel(struct net_device *dev)
1408{
1409 struct cp_private *cp = netdev_priv(dev);
1410 return cp->msg_enable;
1411}
1412
1413static void cp_set_msglevel(struct net_device *dev, u32 value)
1414{
1415 struct cp_private *cp = netdev_priv(dev);
1416 cp->msg_enable = value;
1417}
1418
044a890c 1419static int cp_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1420{
1421 struct cp_private *cp = netdev_priv(dev);
044a890c 1422 unsigned long flags;
1da177e4 1423
044a890c
MM		 1424 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1425 return 0;
1da177e4 1426
044a890c 1427 spin_lock_irqsave(&cp->lock, flags);
1da177e4 1428
044a890c
MM		 1429 if (features & NETIF_F_RXCSUM)
1430 cp->cpcmd |= RxChkSum;
1da177e4 1431 else
044a890c 1432 cp->cpcmd &= ~RxChkSum;
1da177e4 1433
044a890c
MM		 1434 cpw16_f(CpCmd, cp->cpcmd);
1435 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 1436
1437 return 0;
1438}
1439
1440static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1441 void *p)
1442{
1443 struct cp_private *cp = netdev_priv(dev);
1444 unsigned long flags;
1445
1446 if (regs->len < CP_REGS_SIZE)
1447 return /* -EINVAL */;
1448
1449 regs->version = CP_REGS_VER;
1450
1451 spin_lock_irqsave(&cp->lock, flags);
1452 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1453 spin_unlock_irqrestore(&cp->lock, flags);
1454}
1455
1456static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1457{
1458 struct cp_private *cp = netdev_priv(dev);
1459 unsigned long flags;
1460
1461 spin_lock_irqsave (&cp->lock, flags);
1462 netdev_get_wol (cp, wol);
1463 spin_unlock_irqrestore (&cp->lock, flags);
1464}
1465
1466static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1467{
1468 struct cp_private *cp = netdev_priv(dev);
1469 unsigned long flags;
1470 int rc;
1471
1472 spin_lock_irqsave (&cp->lock, flags);
1473 rc = netdev_set_wol (cp, wol);
1474 spin_unlock_irqrestore (&cp->lock, flags);
1475
1476 return rc;
1477}
1478
1479static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1480{
1481 switch (stringset) {
1482 case ETH_SS_STATS:
1483 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1484 break;
1485 default:
1486 BUG();
1487 break;
1488 }
1489}
1490
1491static void cp_get_ethtool_stats (struct net_device *dev,
1492 struct ethtool_stats *estats, u64 *tmp_stats)
1493{
1494 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1495 struct cp_dma_stats *nic_stats;
1496 dma_addr_t dma;
1da177e4
LT		 1497 int i;
1498
6cc92cdd
JG		 1499 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1500 &dma, GFP_KERNEL);
8b512927
SH		 1501 if (!nic_stats)
1502 return;
97f568d8 1503
1da177e4 1504 /* begin NIC statistics dump */
8b512927 1505 cpw32(StatsAddr + 4, (u64)dma >> 32);
284901a9 1506 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1da177e4
LT		 1507 cpr32(StatsAddr);
1508
97f568d8 1509 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1510 if ((cpr32(StatsAddr) & DumpStats) == 0)
1511 break;
97f568d8 1512 udelay(10);
1da177e4 1513 }
97f568d8
SH		 1514 cpw32(StatsAddr, 0);
1515 cpw32(StatsAddr + 4, 0);
8b512927 1516 cpr32(StatsAddr);
1da177e4
LT		 1517
1518 i = 0;
8b512927
SH		 1519 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1520 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1521 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1522 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1523 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1524 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1525 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1526 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1527 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1528 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1529 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1530 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1531 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1532 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1533 BUG_ON(i != CP_NUM_STATS);
8b512927 1534
6cc92cdd 1535 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1536}
1537
7282d491 1538static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1539 .get_drvinfo = cp_get_drvinfo,
1540 .get_regs_len = cp_get_regs_len,
b9f2c044 1541 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1542 .get_settings = cp_get_settings,
1543 .set_settings = cp_set_settings,
1544 .nway_reset = cp_nway_reset,
1545 .get_link = ethtool_op_get_link,
1546 .get_msglevel = cp_get_msglevel,
1547 .set_msglevel = cp_set_msglevel,
1da177e4
LT		 1548 .get_regs = cp_get_regs,
1549 .get_wol = cp_get_wol,
1550 .set_wol = cp_set_wol,
1551 .get_strings = cp_get_strings,
1552 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1553 .get_eeprom_len = cp_get_eeprom_len,
1554 .get_eeprom = cp_get_eeprom,
1555 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1556};
1557
1558static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1559{
1560 struct cp_private *cp = netdev_priv(dev);
1561 int rc;
1562 unsigned long flags;
1563
1564 if (!netif_running(dev))
1565 return -EINVAL;
1566
1567 spin_lock_irqsave(&cp->lock, flags);
1568 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1569 spin_unlock_irqrestore(&cp->lock, flags);
1570 return rc;
1571}
1572
c048aaf4
JP		 1573static int cp_set_mac_address(struct net_device *dev, void *p)
1574{
1575 struct cp_private *cp = netdev_priv(dev);
1576 struct sockaddr *addr = p;
1577
1578 if (!is_valid_ether_addr(addr->sa_data))
1579 return -EADDRNOTAVAIL;
1580
1581 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1582
1583 spin_lock_irq(&cp->lock);
1584
1585 cpw8_f(Cfg9346, Cfg9346_Unlock);
1586 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1587 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1588 cpw8_f(Cfg9346, Cfg9346_Lock);
1589
1590 spin_unlock_irq(&cp->lock);
1591
1592 return 0;
1593}
1594
1da177e4
LT		 1595/* Serial EEPROM section. */
1596
1597/* EEPROM_Ctrl bits. */
1598#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1599#define EE_CS 0x08 /* EEPROM chip select. */
1600#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1601#define EE_WRITE_0 0x00
1602#define EE_WRITE_1 0x02
1603#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1604#define EE_ENB (0x80 | EE_CS)
1605
1606/* Delay between EEPROM clock transitions.
1607 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1608 */
1609
1610#define eeprom_delay() readl(ee_addr)
1611
1612/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1613#define EE_EXTEND_CMD (4)
1da177e4
LT		 1614#define EE_WRITE_CMD (5)
1615#define EE_READ_CMD (6)
1616#define EE_ERASE_CMD (7)
1617
722fdb33
PC		 1618#define EE_EWDS_ADDR (0)
1619#define EE_WRAL_ADDR (1)
1620#define EE_ERAL_ADDR (2)
1621#define EE_EWEN_ADDR (3)
1622
1623#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1624
722fdb33
PC		 1625static void eeprom_cmd_start(void __iomem *ee_addr)
1626{
1da177e4
LT		 1627 writeb (EE_ENB & ~EE_CS, ee_addr);
1628 writeb (EE_ENB, ee_addr);
1629 eeprom_delay ();
722fdb33 1630}
1da177e4 1631
722fdb33
PC		 1632static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1633{
1634 int i;
1635
1636 /* Shift the command bits out. */
1637 for (i = cmd_len - 1; i >= 0; i--) {
1638 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1639 writeb (EE_ENB | dataval, ee_addr);
1640 eeprom_delay ();
1641 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1642 eeprom_delay ();
1643 }
1644 writeb (EE_ENB, ee_addr);
1645 eeprom_delay ();
722fdb33
PC		 1646}
1647
1648static void eeprom_cmd_end(void __iomem *ee_addr)
1649{
1650 writeb (~EE_CS, ee_addr);
1651 eeprom_delay ();
1652}
1653
1654static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1655 int addr_len)
1656{
1657 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1658
1659 eeprom_cmd_start(ee_addr);
1660 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1661 eeprom_cmd_end(ee_addr);
1662}
1663
1664static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1665{
1666 int i;
1667 u16 retval = 0;
1668 void __iomem *ee_addr = ioaddr + Cfg9346;
1669 int read_cmd = location | (EE_READ_CMD << addr_len);
1670
1671 eeprom_cmd_start(ee_addr);
1672 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1673
1674 for (i = 16; i > 0; i--) {
1675 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1676 eeprom_delay ();
1677 retval =
1678 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1679 0);
1680 writeb (EE_ENB, ee_addr);
1681 eeprom_delay ();
1682 }
1683
722fdb33 1684 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1685
1686 return retval;
1687}
1688
722fdb33
PC		 1689static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1690 int addr_len)
1691{
1692 int i;
1693 void __iomem *ee_addr = ioaddr + Cfg9346;
1694 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1695
1696 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1697
1698 eeprom_cmd_start(ee_addr);
1699 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1700 eeprom_cmd(ee_addr, val, 16);
1701 eeprom_cmd_end(ee_addr);
1702
1703 eeprom_cmd_start(ee_addr);
1704 for (i = 0; i < 20000; i++)
1705 if (readb(ee_addr) & EE_DATA_READ)
1706 break;
1707 eeprom_cmd_end(ee_addr);
1708
1709 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1710}
1711
1712static int cp_get_eeprom_len(struct net_device *dev)
1713{
1714 struct cp_private *cp = netdev_priv(dev);
1715 int size;
1716
1717 spin_lock_irq(&cp->lock);
1718 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1719 spin_unlock_irq(&cp->lock);
1720
1721 return size;
1722}
1723
1724static int cp_get_eeprom(struct net_device *dev,
1725 struct ethtool_eeprom *eeprom, u8 *data)
1726{
1727 struct cp_private *cp = netdev_priv(dev);
1728 unsigned int addr_len;
1729 u16 val;
1730 u32 offset = eeprom->offset >> 1;
1731 u32 len = eeprom->len;
1732 u32 i = 0;
1733
1734 eeprom->magic = CP_EEPROM_MAGIC;
1735
1736 spin_lock_irq(&cp->lock);
1737
1738 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1739
1740 if (eeprom->offset & 1) {
1741 val = read_eeprom(cp->regs, offset, addr_len);
1742 data[i++] = (u8)(val >> 8);
1743 offset++;
1744 }
1745
1746 while (i < len - 1) {
1747 val = read_eeprom(cp->regs, offset, addr_len);
1748 data[i++] = (u8)val;
1749 data[i++] = (u8)(val >> 8);
1750 offset++;
1751 }
1752
1753 if (i < len) {
1754 val = read_eeprom(cp->regs, offset, addr_len);
1755 data[i] = (u8)val;
1756 }
1757
1758 spin_unlock_irq(&cp->lock);
1759 return 0;
1760}
1761
1762static int cp_set_eeprom(struct net_device *dev,
1763 struct ethtool_eeprom *eeprom, u8 *data)
1764{
1765 struct cp_private *cp = netdev_priv(dev);
1766 unsigned int addr_len;
1767 u16 val;
1768 u32 offset = eeprom->offset >> 1;
1769 u32 len = eeprom->len;
1770 u32 i = 0;
1771
1772 if (eeprom->magic != CP_EEPROM_MAGIC)
1773 return -EINVAL;
1774
1775 spin_lock_irq(&cp->lock);
1776
1777 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1778
1779 if (eeprom->offset & 1) {
1780 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1781 val |= (u16)data[i++] << 8;
1782 write_eeprom(cp->regs, offset, val, addr_len);
1783 offset++;
1784 }
1785
1786 while (i < len - 1) {
1787 val = (u16)data[i++];
1788 val |= (u16)data[i++] << 8;
1789 write_eeprom(cp->regs, offset, val, addr_len);
1790 offset++;
1791 }
1792
1793 if (i < len) {
1794 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1795 val |= (u16)data[i];
1796 write_eeprom(cp->regs, offset, val, addr_len);
1797 }
1798
1799 spin_unlock_irq(&cp->lock);
1800 return 0;
1801}
1802
1da177e4
LT		 1803/* Put the board into D3cold state and wait for WakeUp signal */
1804static void cp_set_d3_state (struct cp_private *cp)
1805{
1806 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1807 pci_set_power_state (cp->pdev, PCI_D3hot);
1808}
1809
48dfcde4
SH		 1810static const struct net_device_ops cp_netdev_ops = {
1811 .ndo_open = cp_open,
1812 .ndo_stop = cp_close,
1813 .ndo_validate_addr = eth_validate_addr,
c048aaf4 1814 .ndo_set_mac_address = cp_set_mac_address,
48dfcde4
SH		 1815 .ndo_set_multicast_list = cp_set_rx_mode,
1816 .ndo_get_stats = cp_get_stats,
1817 .ndo_do_ioctl = cp_ioctl,
00829823 1818 .ndo_start_xmit = cp_start_xmit,
48dfcde4 1819 .ndo_tx_timeout = cp_tx_timeout,
044a890c 1820 .ndo_set_features = cp_set_features,
48dfcde4
SH		 1821#if CP_VLAN_TAG_USED
1822 .ndo_vlan_rx_register = cp_vlan_rx_register,
1823#endif
1824#ifdef BROKEN
1825 .ndo_change_mtu = cp_change_mtu,
1826#endif
fe96aaa1 1827
48dfcde4
SH		 1828#ifdef CONFIG_NET_POLL_CONTROLLER
1829 .ndo_poll_controller = cp_poll_controller,
1830#endif
1831};
1832
1da177e4
LT		 1833static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1834{
1835 struct net_device *dev;
1836 struct cp_private *cp;
1837 int rc;
1838 void __iomem *regs;
2427ddd8 1839 resource_size_t pciaddr;
1da177e4 1840 unsigned int addr_len, i, pci_using_dac;
1da177e4
LT		 1841
1842#ifndef MODULE
1843 static int version_printed;
1844 if (version_printed++ == 0)
b93d5847 1845 pr_info("%s", version);
1da177e4
LT		 1846#endif
1847
1da177e4 1848 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1849 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
de4549ca 1850 dev_info(&pdev->dev,
b4f18b3f
JP		 1851 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1852 pdev->vendor, pdev->device, pdev->revision);
1da177e4
LT		 1853 return -ENODEV;
1854 }
1855
1856 dev = alloc_etherdev(sizeof(struct cp_private));
1857 if (!dev)
1858 return -ENOMEM;
1da177e4
LT		 1859 SET_NETDEV_DEV(dev, &pdev->dev);
1860
1861 cp = netdev_priv(dev);
1862 cp->pdev = pdev;
1863 cp->dev = dev;
1864 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1865 spin_lock_init (&cp->lock);
1866 cp->mii_if.dev = dev;
1867 cp->mii_if.mdio_read = mdio_read;
1868 cp->mii_if.mdio_write = mdio_write;
1869 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1870 cp->mii_if.phy_id_mask = 0x1f;
1871 cp->mii_if.reg_num_mask = 0x1f;
1872 cp_set_rxbufsize(cp);
1873
1874 rc = pci_enable_device(pdev);
1875 if (rc)
1876 goto err_out_free;
1877
1878 rc = pci_set_mwi(pdev);
1879 if (rc)
1880 goto err_out_disable;
1881
1882 rc = pci_request_regions(pdev, DRV_NAME);
1883 if (rc)
1884 goto err_out_mwi;
1885
1886 pciaddr = pci_resource_start(pdev, 1);
1887 if (!pciaddr) {
1888 rc = -EIO;
9b91cf9d 1889 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1890 goto err_out_res;
1891 }
1892 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1893 rc = -EIO;
9b91cf9d 1894 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1895 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1896 goto err_out_res;
1897 }
1898
1899 /* Configure DMA attributes. */
1900 if ((sizeof(dma_addr_t) > 4) &&
6a35528a
YH		 1901 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1902 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 1903 pci_using_dac = 1;
1904 } else {
1905 pci_using_dac = 0;
1906
284901a9 1907 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1908 if (rc) {
9b91cf9d 1909 dev_err(&pdev->dev,
b4f18b3f 1910 "No usable DMA configuration, aborting\n");
1da177e4
LT		 1911 goto err_out_res;
1912 }
284901a9 1913 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1914 if (rc) {
9b91cf9d 1915 dev_err(&pdev->dev,
b4f18b3f 1916 "No usable consistent DMA configuration, aborting\n");
1da177e4
LT		 1917 goto err_out_res;
1918 }
1919 }
1920
1921 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1922 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1923
044a890c
MM		 1924 dev->features |= NETIF_F_RXCSUM;
1925 dev->hw_features |= NETIF_F_RXCSUM;
1926
1da177e4
LT		 1927 regs = ioremap(pciaddr, CP_REGS_SIZE);
1928 if (!regs) {
1929 rc = -EIO;
4626dd46 1930 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
b4f18b3f 1931 (unsigned long long)pci_resource_len(pdev, 1),
2e8a538d 1932 (unsigned long long)pciaddr);
1da177e4
LT		 1933 goto err_out_res;
1934 }
1935 dev->base_addr = (unsigned long) regs;
1936 cp->regs = regs;
1937
1938 cp_stop_hw(cp);
1939
1940 /* read MAC address from EEPROM */
1941 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1942 for (i = 0; i < 3; i++)
03233b90
AV		 1943 ((__le16 *) (dev->dev_addr))[i] =
1944 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1945 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 1946
48dfcde4 1947 dev->netdev_ops = &cp_netdev_ops;
bea3348e 1948 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4 1949 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4 1950 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1951
1952#if CP_VLAN_TAG_USED
1953 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 1954#endif
1955
1956 if (pci_using_dac)
1957 dev->features |= NETIF_F_HIGHDMA;
1958
044a890c
MM		 1959 /* disabled by default until verified */
1960 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
fcec3456 1961
1da177e4
LT		 1962 dev->irq = pdev->irq;
1963
1964 rc = register_netdev(dev);
1965 if (rc)
1966 goto err_out_iomap;
1967
b4f18b3f
JP		 1968 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1969 dev->base_addr, dev->dev_addr, dev->irq);
1da177e4
LT		 1970
1971 pci_set_drvdata(pdev, dev);
1972
1973 /* enable busmastering and memory-write-invalidate */
1974 pci_set_master(pdev);
1975
2e8a538d
JG		 1976 if (cp->wol_enabled)
1977 cp_set_d3_state (cp);
1da177e4
LT		 1978
1979 return 0;
1980
1981err_out_iomap:
1982 iounmap(regs);
1983err_out_res:
1984 pci_release_regions(pdev);
1985err_out_mwi:
1986 pci_clear_mwi(pdev);
1987err_out_disable:
1988 pci_disable_device(pdev);
1989err_out_free:
1990 free_netdev(dev);
1991 return rc;
1992}
1993
1994static void cp_remove_one (struct pci_dev *pdev)
1995{
1996 struct net_device *dev = pci_get_drvdata(pdev);
1997 struct cp_private *cp = netdev_priv(dev);
1998
1da177e4
LT		 1999 unregister_netdev(dev);
2000 iounmap(cp->regs);
2e8a538d
JG		 2001 if (cp->wol_enabled)
2002 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2003 pci_release_regions(pdev);
2004 pci_clear_mwi(pdev);
2005 pci_disable_device(pdev);
2006 pci_set_drvdata(pdev, NULL);
2007 free_netdev(dev);
2008}
2009
2010#ifdef CONFIG_PM
05adc3b7 2011static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2012{
7668a494
FR		 2013 struct net_device *dev = pci_get_drvdata(pdev);
2014 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2015 unsigned long flags;
2016
7668a494
FR		 2017 if (!netif_running(dev))
2018 return 0;
1da177e4
LT		 2019
2020 netif_device_detach (dev);
2021 netif_stop_queue (dev);
2022
2023 spin_lock_irqsave (&cp->lock, flags);
2024
2025 /* Disable Rx and Tx */
2026 cpw16 (IntrMask, 0);
2027 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2028
2029 spin_unlock_irqrestore (&cp->lock, flags);
2030
576cfa93
FR		 2031 pci_save_state(pdev);
2032 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2033 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2034
2035 return 0;
2036}
2037
2038static int cp_resume (struct pci_dev *pdev)
2039{
576cfa93
FR		 2040 struct net_device *dev = pci_get_drvdata (pdev);
2041 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2042 unsigned long flags;
1da177e4 2043
576cfa93
FR		 2044 if (!netif_running(dev))
2045 return 0;
1da177e4
LT		 2046
2047 netif_device_attach (dev);
576cfa93
FR		 2048
2049 pci_set_power_state(pdev, PCI_D0);
2050 pci_restore_state(pdev);
2051 pci_enable_wake(pdev, PCI_D0, 0);
2052
2053 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2054 cp_init_rings_index (cp);
1da177e4
LT		 2055 cp_init_hw (cp);
2056 netif_start_queue (dev);
a4cf0761
PO		 2057
2058 spin_lock_irqsave (&cp->lock, flags);
2059
2501f843 2060 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2061
2062 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2063
1da177e4
LT		 2064 return 0;
2065}
2066#endif /* CONFIG_PM */
2067
2068static struct pci_driver cp_driver = {
2069 .name = DRV_NAME,
2070 .id_table = cp_pci_tbl,
2071 .probe = cp_init_one,
2072 .remove = cp_remove_one,
2073#ifdef CONFIG_PM
2074 .resume = cp_resume,
2075 .suspend = cp_suspend,
2076#endif
2077};
2078
2079static int __init cp_init (void)
2080{
2081#ifdef MODULE
b93d5847 2082 pr_info("%s", version);
1da177e4 2083#endif
29917620 2084 return pci_register_driver(&cp_driver);
1da177e4
LT		 2085}
2086
2087static void __exit cp_exit (void)
2088{
2089 pci_unregister_driver (&cp_driver);
2090}
2091
2092module_init(cp_init);
2093module_exit(cp_exit);
Linux 6.x block layer and io_uring tree(s)