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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / drivers / net / 7990.c
CommitLineData
6aa20a22
JG		 1/*
2 * 7990.c -- LANCE ethernet IC generic routines.
1da177e4 3 * This is an attempt to separate out the bits of various ethernet
6aa20a22 4 * drivers that are common because they all use the AMD 7990 LANCE
1da177e4
LT		 5 * (Local Area Network Controller for Ethernet) chip.
6 *
7 * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
8 *
9 * Most of this stuff was obtained by looking at other LANCE drivers,
10 * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
11 * NB: this was made easy by the fact that Jes Sorensen had cleaned up
6aa20a22 12 * most of a2025 and sunlance with the aim of merging them, so the
1da177e4
LT		 13 * common code was pretty obvious.
14 */
15#include <linux/crc32.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/fcntl.h>
25#include <linux/interrupt.h>
26#include <linux/ioport.h>
27#include <linux/in.h>
28#include <linux/route.h>
1da177e4
LT		 29#include <linux/string.h>
30#include <linux/skbuff.h>
3c139586 31#include <asm/irq.h>
1da177e4
LT		 32/* Used for the temporal inet entries and routing */
33#include <linux/socket.h>
34#include <linux/bitops.h>
35
36#include <asm/system.h>
37#include <asm/io.h>
38#include <asm/dma.h>
39#include <asm/pgtable.h>
40#ifdef CONFIG_HP300
41#include <asm/blinken.h>
42#endif
43
44#include "7990.h"
45
46#define WRITERAP(lp,x) out_be16(lp->base + LANCE_RAP, (x))
47#define WRITERDP(lp,x) out_be16(lp->base + LANCE_RDP, (x))
48#define READRDP(lp) in_be16(lp->base + LANCE_RDP)
49
50#if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
51#include "hplance.h"
52
53#undef WRITERAP
54#undef WRITERDP
55#undef READRDP
56
57#if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
58
59/* Lossage Factor Nine, Mr Sulu. */
60#define WRITERAP(lp,x) (lp->writerap(lp,x))
61#define WRITERDP(lp,x) (lp->writerdp(lp,x))
62#define READRDP(lp) (lp->readrdp(lp))
63
64#else
65
66/* These inlines can be used if only CONFIG_HPLANCE is defined */
67static inline void WRITERAP(struct lance_private *lp, __u16 value)
68{
69 do {
70 out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
71 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
72}
73
74static inline void WRITERDP(struct lance_private *lp, __u16 value)
75{
76 do {
77 out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
78 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
79}
80
81static inline __u16 READRDP(struct lance_private *lp)
82{
83 __u16 value;
84 do {
85 value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
86 } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
87 return value;
88}
89
90#endif
91#endif /* CONFIG_HPLANCE || CONFIG_HPLANCE_MODULE */
92
93/* debugging output macros, various flavours */
94/* #define TEST_HITS */
95#ifdef UNDEF
96#define PRINT_RINGS() \
97do { \
98 int t; \
99 for (t=0; t < RX_RING_SIZE; t++) { \
100 printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n",\
101 t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0,\
102 ib->brx_ring[t].length,\
103 ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits);\
104 }\
105 for (t=0; t < TX_RING_SIZE; t++) { \
106 printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n",\
107 t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0,\
108 ib->btx_ring[t].length,\
109 ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits);\
110 }\
6aa20a22 111} while (0)
1da177e4
LT		 112#else
113#define PRINT_RINGS()
6aa20a22 114#endif
1da177e4
LT		 115
116/* Load the CSR registers. The LANCE has to be STOPped when we do this! */
117static void load_csrs (struct lance_private *lp)
118{
119 volatile struct lance_init_block *aib = lp->lance_init_block;
120 int leptr;
121
122 leptr = LANCE_ADDR (aib);
123
124 WRITERAP(lp, LE_CSR1); /* load address of init block */
125 WRITERDP(lp, leptr & 0xFFFF);
126 WRITERAP(lp, LE_CSR2);
127 WRITERDP(lp, leptr >> 16);
128 WRITERAP(lp, LE_CSR3);
129 WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
130
131 /* Point back to csr0 */
132 WRITERAP(lp, LE_CSR0);
133}
134
135/* #define to 0 or 1 appropriately */
136#define DEBUG_IRING 0
137/* Set up the Lance Rx and Tx rings and the init block */
138static void lance_init_ring (struct net_device *dev)
139{
140 struct lance_private *lp = netdev_priv(dev);
141 volatile struct lance_init_block *ib = lp->init_block;
142 volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
143 int leptr;
144 int i;
145
146 aib = lp->lance_init_block;
147
148 lp->rx_new = lp->tx_new = 0;
149 lp->rx_old = lp->tx_old = 0;
150
151 ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
152
153 /* Copy the ethernet address to the lance init block
154 * Notice that we do a byteswap if we're big endian.
155 * [I think this is the right criterion; at least, sunlance,
156 * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
157 * However, the datasheet says that the BSWAP bit doesn't affect
158 * the init block, so surely it should be low byte first for
6aa20a22 159 * everybody? Um.]
1da177e4
LT		 160 * We could define the ib->physaddr as three 16bit values and
161 * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
162 */
163#ifdef __BIG_ENDIAN
164 ib->phys_addr [0] = dev->dev_addr [1];
165 ib->phys_addr [1] = dev->dev_addr [0];
166 ib->phys_addr [2] = dev->dev_addr [3];
167 ib->phys_addr [3] = dev->dev_addr [2];
168 ib->phys_addr [4] = dev->dev_addr [5];
169 ib->phys_addr [5] = dev->dev_addr [4];
170#else
171 for (i=0; i<6; i++)
172 ib->phys_addr[i] = dev->dev_addr[i];
6aa20a22 173#endif
1da177e4
LT		 174
175 if (DEBUG_IRING)
176 printk ("TX rings:\n");
6aa20a22 177
1da177e4
LT		 178 lp->tx_full = 0;
179 /* Setup the Tx ring entries */
180 for (i = 0; i < (1<<lp->lance_log_tx_bufs); i++) {
181 leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
182 ib->btx_ring [i].tmd0 = leptr;
183 ib->btx_ring [i].tmd1_hadr = leptr >> 16;
184 ib->btx_ring [i].tmd1_bits = 0;
185 ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */
186 ib->btx_ring [i].misc = 0;
6aa20a22 187 if (DEBUG_IRING)
1da177e4
LT		 188 printk ("%d: 0x%8.8x\n", i, leptr);
189 }
190
191 /* Setup the Rx ring entries */
192 if (DEBUG_IRING)
193 printk ("RX rings:\n");
194 for (i = 0; i < (1<<lp->lance_log_rx_bufs); i++) {
195 leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
196
197 ib->brx_ring [i].rmd0 = leptr;
198 ib->brx_ring [i].rmd1_hadr = leptr >> 16;
199 ib->brx_ring [i].rmd1_bits = LE_R1_OWN;
200 /* 0xf000 == bits that must be one (reserved, presumably) */
201 ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000;
202 ib->brx_ring [i].mblength = 0;
203 if (DEBUG_IRING)
204 printk ("%d: 0x%8.8x\n", i, leptr);
205 }
206
207 /* Setup the initialization block */
6aa20a22 208
1da177e4
LT		 209 /* Setup rx descriptor pointer */
210 leptr = LANCE_ADDR(&aib->brx_ring);
211 ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
212 ib->rx_ptr = leptr;
213 if (DEBUG_IRING)
214 printk ("RX ptr: %8.8x\n", leptr);
6aa20a22 215
1da177e4
LT		 216 /* Setup tx descriptor pointer */
217 leptr = LANCE_ADDR(&aib->btx_ring);
218 ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
219 ib->tx_ptr = leptr;
220 if (DEBUG_IRING)
221 printk ("TX ptr: %8.8x\n", leptr);
222
223 /* Clear the multicast filter */
224 ib->filter [0] = 0;
225 ib->filter [1] = 0;
226 PRINT_RINGS();
227}
228
229/* LANCE must be STOPped before we do this, too... */
230static int init_restart_lance (struct lance_private *lp)
231{
232 int i;
233
234 WRITERAP(lp, LE_CSR0);
235 WRITERDP(lp, LE_C0_INIT);
236
237 /* Need a hook here for sunlance ledma stuff */
238
239 /* Wait for the lance to complete initialization */
240 for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
241 barrier();
242 if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
243 printk ("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
244 return -1;
245 }
246
247 /* Clear IDON by writing a "1", enable interrupts and start lance */
248 WRITERDP(lp, LE_C0_IDON);
249 WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
250
251 return 0;
252}
253
254static int lance_reset (struct net_device *dev)
255{
256 struct lance_private *lp = netdev_priv(dev);
257 int status;
6aa20a22 258
1da177e4
LT		 259 /* Stop the lance */
260 WRITERAP(lp, LE_CSR0);
261 WRITERDP(lp, LE_C0_STOP);
262
263 load_csrs (lp);
264 lance_init_ring (dev);
265 dev->trans_start = jiffies;
266 status = init_restart_lance (lp);
267#ifdef DEBUG_DRIVER
268 printk ("Lance restart=%d\n", status);
269#endif
270 return status;
271}
272
273static int lance_rx (struct net_device *dev)
274{
275 struct lance_private *lp = netdev_priv(dev);
276 volatile struct lance_init_block *ib = lp->init_block;
277 volatile struct lance_rx_desc *rd;
278 unsigned char bits;
1da177e4
LT		 279#ifdef TEST_HITS
280 int i;
281#endif
282
283#ifdef TEST_HITS
284 printk ("[");
285 for (i = 0; i < RX_RING_SIZE; i++) {
286 if (i == lp->rx_new)
287 printk ("%s",
288 ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "_" : "X");
289 else
290 printk ("%s",
291 ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "." : "1");
292 }
293 printk ("]");
294#endif
295#ifdef CONFIG_HP300
296 blinken_leds(0x40, 0);
6aa20a22 297#endif
1da177e4
LT		 298 WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
299 for (rd = &ib->brx_ring [lp->rx_new]; /* For each Rx ring we own... */
300 !((bits = rd->rmd1_bits) & LE_R1_OWN);
301 rd = &ib->brx_ring [lp->rx_new]) {
302
303 /* We got an incomplete frame? */
304 if ((bits & LE_R1_POK) != LE_R1_POK) {
09f75cd7
JG		 305 dev->stats.rx_over_errors++;
306 dev->stats.rx_errors++;
1da177e4
LT		 307 continue;
308 } else if (bits & LE_R1_ERR) {
309 /* Count only the end frame as a rx error,
310 * not the beginning
311 */
09f75cd7
JG		 312 if (bits & LE_R1_BUF) dev->stats.rx_fifo_errors++;
313 if (bits & LE_R1_CRC) dev->stats.rx_crc_errors++;
314 if (bits & LE_R1_OFL) dev->stats.rx_over_errors++;
315 if (bits & LE_R1_FRA) dev->stats.rx_frame_errors++;
316 if (bits & LE_R1_EOP) dev->stats.rx_errors++;
1da177e4 317 } else {
79ea13ce
AV		 318 int len = (rd->mblength & 0xfff) - 4;
319 struct sk_buff *skb = dev_alloc_skb (len+2);
1da177e4 320
79ea13ce 321 if (!skb) {
1da177e4
LT		 322 printk ("%s: Memory squeeze, deferring packet.\n",
323 dev->name);
09f75cd7 324 dev->stats.rx_dropped++;
1da177e4
LT		 325 rd->mblength = 0;
326 rd->rmd1_bits = LE_R1_OWN;
327 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
328 return 0;
329 }
6aa20a22 330
1da177e4
LT		 331 skb_reserve (skb, 2); /* 16 byte align */
332 skb_put (skb, len); /* make room */
8c7b7faa 333 skb_copy_to_linear_data(skb,
1da177e4 334 (unsigned char *)&(ib->rx_buf [lp->rx_new][0]),
8c7b7faa 335 len);
1da177e4
LT		 336 skb->protocol = eth_type_trans (skb, dev);
337 netif_rx (skb);
09f75cd7
JG		 338 dev->stats.rx_packets++;
339 dev->stats.rx_bytes += len;
1da177e4
LT		 340 }
341
342 /* Return the packet to the pool */
343 rd->mblength = 0;
344 rd->rmd1_bits = LE_R1_OWN;
345 lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
346 }
347 return 0;
348}
349
350static int lance_tx (struct net_device *dev)
351{
352 struct lance_private *lp = netdev_priv(dev);
353 volatile struct lance_init_block *ib = lp->init_block;
354 volatile struct lance_tx_desc *td;
355 int i, j;
356 int status;
357
358#ifdef CONFIG_HP300
359 blinken_leds(0x80, 0);
360#endif
361 /* csr0 is 2f3 */
362 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
363 /* csr0 is 73 */
364
365 j = lp->tx_old;
366 for (i = j; i != lp->tx_new; i = j) {
367 td = &ib->btx_ring [i];
368
369 /* If we hit a packet not owned by us, stop */
370 if (td->tmd1_bits & LE_T1_OWN)
371 break;
6aa20a22 372
1da177e4
LT		 373 if (td->tmd1_bits & LE_T1_ERR) {
374 status = td->misc;
6aa20a22 375
09f75cd7
JG		 376 dev->stats.tx_errors++;
377 if (status & LE_T3_RTY) dev->stats.tx_aborted_errors++;
378 if (status & LE_T3_LCOL) dev->stats.tx_window_errors++;
1da177e4
LT		 379
380 if (status & LE_T3_CLOS) {
09f75cd7 381 dev->stats.tx_carrier_errors++;
1da177e4
LT		 382 if (lp->auto_select) {
383 lp->tpe = 1 - lp->tpe;
384 printk("%s: Carrier Lost, trying %s\n",
385 dev->name, lp->tpe?"TPE":"AUI");
386 /* Stop the lance */
387 WRITERAP(lp, LE_CSR0);
388 WRITERDP(lp, LE_C0_STOP);
389 lance_init_ring (dev);
390 load_csrs (lp);
391 init_restart_lance (lp);
392 return 0;
393 }
394 }
395
396 /* buffer errors and underflows turn off the transmitter */
397 /* Restart the adapter */
398 if (status & (LE_T3_BUF|LE_T3_UFL)) {
09f75cd7 399 dev->stats.tx_fifo_errors++;
1da177e4
LT		 400
401 printk ("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
402 dev->name);
403 /* Stop the lance */
404 WRITERAP(lp, LE_CSR0);
405 WRITERDP(lp, LE_C0_STOP);
406 lance_init_ring (dev);
407 load_csrs (lp);
408 init_restart_lance (lp);
409 return 0;
410 }
411 } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
412 /*
413 * So we don't count the packet more than once.
414 */
415 td->tmd1_bits &= ~(LE_T1_POK);
416
417 /* One collision before packet was sent. */
418 if (td->tmd1_bits & LE_T1_EONE)
09f75cd7 419 dev->stats.collisions++;
1da177e4
LT		 420
421 /* More than one collision, be optimistic. */
422 if (td->tmd1_bits & LE_T1_EMORE)
09f75cd7 423 dev->stats.collisions += 2;
1da177e4 424
09f75cd7 425 dev->stats.tx_packets++;
1da177e4 426 }
6aa20a22 427
1da177e4
LT		 428 j = (j + 1) & lp->tx_ring_mod_mask;
429 }
430 lp->tx_old = j;
431 WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
432 return 0;
433}
434
435static irqreturn_t
7d12e780 436lance_interrupt (int irq, void *dev_id)
1da177e4
LT		 437{
438 struct net_device *dev = (struct net_device *)dev_id;
439 struct lance_private *lp = netdev_priv(dev);
440 int csr0;
441
442 spin_lock (&lp->devlock);
443
444 WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
445 csr0 = READRDP(lp);
446
447 PRINT_RINGS();
6aa20a22 448
1da177e4
LT		 449 if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
450 spin_unlock (&lp->devlock);
451 return IRQ_NONE; /* been generated by the Lance. */
452 }
453
454 /* Acknowledge all the interrupt sources ASAP */
455 WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
456
457 if ((csr0 & LE_C0_ERR)) {
458 /* Clear the error condition */
459 WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
460 }
461
462 if (csr0 & LE_C0_RINT)
463 lance_rx (dev);
464
465 if (csr0 & LE_C0_TINT)
466 lance_tx (dev);
467
468 /* Log misc errors. */
469 if (csr0 & LE_C0_BABL)
09f75cd7 470 dev->stats.tx_errors++; /* Tx babble. */
1da177e4 471 if (csr0 & LE_C0_MISS)
09f75cd7 472 dev->stats.rx_errors++; /* Missed a Rx frame. */
1da177e4 473 if (csr0 & LE_C0_MERR) {
6aa20a22 474 printk("%s: Bus master arbitration failure, status %4.4x.\n",
1da177e4
LT		 475 dev->name, csr0);
476 /* Restart the chip. */
477 WRITERDP(lp, LE_C0_STRT);
478 }
479
480 if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
481 lp->tx_full = 0;
482 netif_wake_queue (dev);
483 }
6aa20a22 484
1da177e4
LT		 485 WRITERAP(lp, LE_CSR0);
486 WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
487
488 spin_unlock (&lp->devlock);
489 return IRQ_HANDLED;
490}
491
492int lance_open (struct net_device *dev)
493{
494 struct lance_private *lp = netdev_priv(dev);
495 int res;
6aa20a22 496
1da177e4 497 /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
38515e90 498 if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
1da177e4
LT		 499 return -EAGAIN;
500
501 res = lance_reset(dev);
502 spin_lock_init(&lp->devlock);
503 netif_start_queue (dev);
504
505 return res;
506}
bf4d5934 507EXPORT_SYMBOL_GPL(lance_open);
1da177e4
LT		 508
509int lance_close (struct net_device *dev)
510{
511 struct lance_private *lp = netdev_priv(dev);
6aa20a22 512
1da177e4
LT		 513 netif_stop_queue (dev);
514
515 /* Stop the LANCE */
516 WRITERAP(lp, LE_CSR0);
517 WRITERDP(lp, LE_C0_STOP);
518
519 free_irq(lp->irq, dev);
520
521 return 0;
522}
bf4d5934 523EXPORT_SYMBOL_GPL(lance_close);
1da177e4
LT		 524
525void lance_tx_timeout(struct net_device *dev)
526{
527 printk("lance_tx_timeout\n");
528 lance_reset(dev);
529 dev->trans_start = jiffies;
530 netif_wake_queue (dev);
531}
bf4d5934 532EXPORT_SYMBOL_GPL(lance_tx_timeout);
1da177e4
LT		 533
534int lance_start_xmit (struct sk_buff *skb, struct net_device *dev)
535{
536 struct lance_private *lp = netdev_priv(dev);
537 volatile struct lance_init_block *ib = lp->init_block;
538 int entry, skblen, len;
539 static int outs;
540 unsigned long flags;
541
542 if (!TX_BUFFS_AVAIL)
5b548140 543 return NETDEV_TX_LOCKED;
1da177e4
LT		 544
545 netif_stop_queue (dev);
546
547 skblen = skb->len;
548
549#ifdef DEBUG_DRIVER
550 /* dump the packet */
551 {
552 int i;
6aa20a22 553
1da177e4
LT		 554 for (i = 0; i < 64; i++) {
555 if ((i % 16) == 0)
556 printk ("\n");
557 printk ("%2.2x ", skb->data [i]);
558 }
559 }
560#endif
561 len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
562 entry = lp->tx_new & lp->tx_ring_mod_mask;
563 ib->btx_ring [entry].length = (-len) | 0xf000;
564 ib->btx_ring [entry].misc = 0;
6aa20a22 565
cfa08bb5
GU		 566 if (skb->len < ETH_ZLEN)
567 memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
568 skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
6aa20a22 569
1da177e4
LT		 570 /* Now, give the packet to the lance */
571 ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
572 lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask;
573
574 outs++;
575 /* Kick the lance: transmit now */
576 WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
577 dev->trans_start = jiffies;
578 dev_kfree_skb (skb);
6aa20a22 579
1da177e4
LT		 580 spin_lock_irqsave (&lp->devlock, flags);
581 if (TX_BUFFS_AVAIL)
582 netif_start_queue (dev);
583 else
584 lp->tx_full = 1;
585 spin_unlock_irqrestore (&lp->devlock, flags);
586
ec634fe3 587 return NETDEV_TX_OK;
1da177e4 588}
bf4d5934 589EXPORT_SYMBOL_GPL(lance_start_xmit);
1da177e4 590
1da177e4
LT		 591/* taken from the depca driver via a2065.c */
592static void lance_load_multicast (struct net_device *dev)
593{
594 struct lance_private *lp = netdev_priv(dev);
595 volatile struct lance_init_block *ib = lp->init_block;
596 volatile u16 *mcast_table = (u16 *)&ib->filter;
0ddf477b 597 struct dev_mc_list *dmi;
1da177e4 598 char *addrs;
1da177e4 599 u32 crc;
6aa20a22 600
1da177e4 601 /* set all multicast bits */
6aa20a22 602 if (dev->flags & IFF_ALLMULTI){
1da177e4
LT		 603 ib->filter [0] = 0xffffffff;
604 ib->filter [1] = 0xffffffff;
605 return;
606 }
607 /* clear the multicast filter */
608 ib->filter [0] = 0;
609 ib->filter [1] = 0;
610
611 /* Add addresses */
0ddf477b 612 netdev_for_each_mc_addr(dmi, dev) {
1da177e4 613 addrs = dmi->dmi_addr;
1da177e4
LT		 614
615 /* multicast address? */
616 if (!(*addrs & 1))
617 continue;
6aa20a22 618
1da177e4
LT		 619 crc = ether_crc_le(6, addrs);
620 crc = crc >> 26;
621 mcast_table [crc >> 4] |= 1 << (crc & 0xf);
622 }
623 return;
624}
625
626
627void lance_set_multicast (struct net_device *dev)
628{
629 struct lance_private *lp = netdev_priv(dev);
630 volatile struct lance_init_block *ib = lp->init_block;
631 int stopped;
632
633 stopped = netif_queue_stopped(dev);
634 if (!stopped)
635 netif_stop_queue (dev);
636
637 while (lp->tx_old != lp->tx_new)
638 schedule();
639
640 WRITERAP(lp, LE_CSR0);
641 WRITERDP(lp, LE_C0_STOP);
642 lance_init_ring (dev);
643
644 if (dev->flags & IFF_PROMISC) {
645 ib->mode |= LE_MO_PROM;
646 } else {
647 ib->mode &= ~LE_MO_PROM;
648 lance_load_multicast (dev);
649 }
650 load_csrs (lp);
651 init_restart_lance (lp);
652
653 if (!stopped)
654 netif_start_queue (dev);
655}
bf4d5934 656EXPORT_SYMBOL_GPL(lance_set_multicast);
1da177e4
LT		 657
658#ifdef CONFIG_NET_POLL_CONTROLLER
659void lance_poll(struct net_device *dev)
660{
661 struct lance_private *lp = netdev_priv(dev);
662
663 spin_lock (&lp->devlock);
664 WRITERAP(lp, LE_CSR0);
665 WRITERDP(lp, LE_C0_STRT);
666 spin_unlock (&lp->devlock);
2850bc27 667 lance_interrupt(dev->irq, dev);
1da177e4
LT		 668}
669#endif
670
671MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)