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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[linux-2.6-block.git] / drivers / net / 3c59x.c
CommitLineData
1da177e4
LT		 1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
1da177e4
LT		 20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
1da177e4
LT		 33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
1da177e4
LT		 73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/slab.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/mii.h>
84#include <linux/init.h>
85#include <linux/netdevice.h>
86#include <linux/etherdevice.h>
87#include <linux/skbuff.h>
88#include <linux/ethtool.h>
89#include <linux/highmem.h>
90#include <linux/eisa.h>
91#include <linux/bitops.h>
ff5688ae 92#include <linux/jiffies.h>
60e4ad7a 93#include <asm/irq.h> /* For nr_irqs only. */
1da177e4
LT		 94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
86de79b6
SH		 105static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
1da177e4
LT		 107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
61238602 109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
1da177e4 110MODULE_LICENSE("GPL");
1da177e4
LT		 111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
1f1bd5fc 211 PCI_USES_MASTER=4,
1da177e4
LT		 212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
b4adbb4d 238 CH_3C905B_TX,
1da177e4
LT		 239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
1f1bd5fc 282 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 284 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
1f1bd5fc 286 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 287 {"3c595 Vortex 100baseTx",
1f1bd5fc 288 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 289 {"3c595 Vortex 100baseT4",
1f1bd5fc 290 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4
LT		 291
292 {"3c595 Vortex 100base-MII",
1f1bd5fc 293 PCI_USES_MASTER, IS_VORTEX, 32, },
1da177e4 294 {"3c900 Boomerang 10baseT",
1f1bd5fc 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 296 {"3c900 Boomerang 10Mbps Combo",
1f1bd5fc 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
1da177e4 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
1f1bd5fc 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 300 {"3c900 Cyclone 10Mbps Combo",
1f1bd5fc 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4
LT		 302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
1f1bd5fc 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 305 {"3c900B-FL Cyclone 10base-FL",
1f1bd5fc 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 307 {"3c905 Boomerang 100baseTx",
1f1bd5fc 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
1da177e4 309 {"3c905 Boomerang 100baseT4",
1f1bd5fc 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
b4adbb4d
PT		 311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 313 {"3c905B Cyclone 100baseTx",
1f1bd5fc 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 315
316 {"3c905B Cyclone 10/100/BNC",
1f1bd5fc 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 318 {"3c905B-FX Cyclone 100baseFx",
1f1bd5fc 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
1da177e4 320 {"3c905C Tornado",
1f1bd5fc 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
1f1bd5fc 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
1da177e4 324 {"3c980 Cyclone",
aa807f79 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4
LT		 326
327 {"3c980C Python-T",
1f1bd5fc 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 329 {"3cSOHO100-TX Hurricane",
b8a1fcee 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 331 {"3c555 Laptop Hurricane",
1f1bd5fc 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
1da177e4 333 {"3c556 Laptop Tornado",
1f1bd5fc 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
1f1bd5fc 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
1da177e4
LT		 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
1f1bd5fc 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 342 {"3c575 Boomerang CardBus",
1f1bd5fc 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
1da177e4 344 {"3CCFE575BT Cyclone CardBus",
1f1bd5fc 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
1da177e4
LT		 346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
1f1bd5fc 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
1f1bd5fc 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
1f1bd5fc 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
1f1bd5fc 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
1da177e4
LT		 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
1f1bd5fc 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 362 {"3c920 Tornado",
1f1bd5fc 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4 364 {"3c982 Hydra Dual Port A",
1f1bd5fc 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4
LT		 366
367 {"3c982 Hydra Dual Port B",
1f1bd5fc 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
1da177e4 369 {"3c905B-T4",
1f1bd5fc 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
1da177e4 371 {"3c920B-EMB-WNM Tornado",
1f1bd5fc 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
1da177e4
LT		 373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
378static struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
b4adbb4d 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
1da177e4
LT		 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
62afe595 438#define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
1da177e4
LT		 439#define EL3_CMD 0x0e
440#define EL3_STATUS 0x0e
441
442/* The top five bits written to EL3_CMD are a command, the lower
443 11 bits are the parameter, if applicable.
444 Note that 11 parameters bits was fine for ethernet, but the new chip
445 can handle FDDI length frames (~4500 octets) and now parameters count
446 32-bit 'Dwords' rather than octets. */
447
448enum vortex_cmd {
449 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
450 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
451 UpStall = 6<<11, UpUnstall = (6<<11)+1,
452 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
453 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
454 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
455 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
456 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
457 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
458 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459
460/* The SetRxFilter command accepts the following classes: */
461enum RxFilter {
462 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463
464/* Bits in the general status register. */
465enum vortex_status {
466 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
467 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
468 IntReq = 0x0040, StatsFull = 0x0080,
469 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
470 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
471 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
472};
473
474/* Register window 1 offsets, the window used in normal operation.
475 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476enum Window1 {
477 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
478 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
479 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
480};
481enum Window0 {
482 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
483 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
484 IntrStatus=0x0E, /* Valid in all windows. */
485};
486enum Win0_EEPROM_bits {
487 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
488 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
489 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490};
491/* EEPROM locations. */
492enum eeprom_offset {
493 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
494 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
495 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
496 DriverTune=13, Checksum=15};
497
498enum Window2 { /* Window 2. */
499 Wn2_ResetOptions=12,
500};
501enum Window3 { /* Window 3: MAC/config bits. */
502 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
503};
504
505#define BFEXT(value, offset, bitcount) \
506 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507
508#define BFINS(lhs, rhs, offset, bitcount) \
509 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
510 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511
512#define RAM_SIZE(v) BFEXT(v, 0, 3)
513#define RAM_WIDTH(v) BFEXT(v, 3, 1)
514#define RAM_SPEED(v) BFEXT(v, 4, 2)
515#define ROM_SIZE(v) BFEXT(v, 6, 2)
516#define RAM_SPLIT(v) BFEXT(v, 16, 2)
517#define XCVR(v) BFEXT(v, 20, 4)
518#define AUTOSELECT(v) BFEXT(v, 24, 1)
519
520enum Window4 { /* Window 4: Xcvr/media bits. */
521 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522};
523enum Win4_Media_bits {
524 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
525 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
526 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
527 Media_LnkBeat = 0x0800,
528};
529enum Window7 { /* Window 7: Bus Master control. */
530 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
531 Wn7_MasterStatus = 12,
532};
533/* Boomerang bus master control registers. */
534enum MasterCtrl {
535 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
536 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
537};
538
539/* The Rx and Tx descriptor lists.
540 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
541 alignment contraint on tx_ring[] and rx_ring[]. */
542#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
543#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
544struct boom_rx_desc {
cc2d6596
AV		 545 __le32 next; /* Last entry points to 0. */
546 __le32 status;
547 __le32 addr; /* Up to 63 addr/len pairs possible. */
548 __le32 length; /* Set LAST_FRAG to indicate last pair. */
1da177e4
LT		 549};
550/* Values for the Rx status entry. */
551enum rx_desc_status {
552 RxDComplete=0x00008000, RxDError=0x4000,
553 /* See boomerang_rx() for actual error bits */
554 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
555 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
556};
557
558#ifdef MAX_SKB_FRAGS
559#define DO_ZEROCOPY 1
560#else
561#define DO_ZEROCOPY 0
562#endif
563
564struct boom_tx_desc {
cc2d6596
AV		 565 __le32 next; /* Last entry points to 0. */
566 __le32 status; /* bits 0:12 length, others see below. */
1da177e4
LT		 567#if DO_ZEROCOPY
568 struct {
cc2d6596
AV		 569 __le32 addr;
570 __le32 length;
1da177e4
LT		 571 } frag[1+MAX_SKB_FRAGS];
572#else
cc2d6596
AV		 573 __le32 addr;
574 __le32 length;
1da177e4
LT		 575#endif
576};
577
578/* Values for the Tx status entry. */
579enum tx_desc_status {
580 CRCDisable=0x2000, TxDComplete=0x8000,
581 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
582 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
583};
584
585/* Chip features we care about in vp->capabilities, read from the EEPROM. */
586enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587
588struct vortex_extra_stats {
8d1d0340
SK		 589 unsigned long tx_deferred;
590 unsigned long tx_max_collisions;
591 unsigned long tx_multiple_collisions;
592 unsigned long tx_single_collisions;
593 unsigned long rx_bad_ssd;
1da177e4
LT		 594};
595
596struct vortex_private {
597 /* The Rx and Tx rings should be quad-word-aligned. */
598 struct boom_rx_desc* rx_ring;
599 struct boom_tx_desc* tx_ring;
600 dma_addr_t rx_ring_dma;
601 dma_addr_t tx_ring_dma;
602 /* The addresses of transmit- and receive-in-place skbuffs. */
603 struct sk_buff* rx_skbuff[RX_RING_SIZE];
604 struct sk_buff* tx_skbuff[TX_RING_SIZE];
605 unsigned int cur_rx, cur_tx; /* The next free ring entry */
606 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
1da177e4
LT		 607 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
608 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
609 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610
611 /* PCI configuration space information. */
612 struct device *gendev;
62afe595
JL		 613 void __iomem *ioaddr; /* IO address space */
614 void __iomem *cb_fn_base; /* CardBus function status addr space. */
1da177e4
LT		 615
616 /* Some values here only for performance evaluation and path-coverage */
617 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
618 int card_idx;
619
620 /* The remainder are related to chip state, mostly media selection. */
621 struct timer_list timer; /* Media selection timer. */
622 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
623 int options; /* User-settable misc. driver options. */
624 unsigned int media_override:4, /* Passed-in media type. */
625 default_media:4, /* Read from the EEPROM/Wn3_Config. */
09ce3512 626 full_duplex:1, autoselect:1,
1da177e4
LT		 627 bus_master:1, /* Vortex can only do a fragment bus-m. */
628 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
629 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
630 partner_flow_ctrl:1, /* Partner supports flow control */
631 has_nway:1,
632 enable_wol:1, /* Wake-on-LAN is enabled */
633 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
634 open:1,
635 medialock:1,
636 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
637 large_frames:1; /* accept large frames */
638 int drv_flags;
639 u16 status_enable;
640 u16 intr_enable;
641 u16 available_media; /* From Wn3_Options. */
642 u16 capabilities, info1, info2; /* Various, from EEPROM. */
643 u16 advertising; /* NWay media advertisement */
644 unsigned char phys[2]; /* MII device addresses. */
645 u16 deferred; /* Resend these interrupts when we
646 * bale from the ISR */
647 u16 io_size; /* Size of PCI region (for release_region) */
648 spinlock_t lock; /* Serialise access to device & its vortex_private */
649 struct mii_if_info mii; /* MII lib hooks/info */
650};
651
652#ifdef CONFIG_PCI
653#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
654#else
655#define DEVICE_PCI(dev) NULL
656#endif
657
658#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
659
660#ifdef CONFIG_EISA
661#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
662#else
663#define DEVICE_EISA(dev) NULL
664#endif
665
666#define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
667
668/* The action to take with a media selection timer tick.
669 Note that we deviate from the 3Com order by checking 10base2 before AUI.
670 */
671enum xcvr_types {
672 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
673 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
674};
675
f71e1309 676static const struct media_table {
1da177e4
LT		 677 char *name;
678 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
679 mask:8, /* The transceiver-present bit in Wn3_Config.*/
680 next:8; /* The media type to try next. */
681 int wait; /* Time before we check media status. */
682} media_tbl[] = {
683 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
684 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
685 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
686 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
687 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
688 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
689 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
690 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
691 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
692 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
693 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
694};
695
696static struct {
697 const char str[ETH_GSTRING_LEN];
698} ethtool_stats_keys[] = {
699 { "tx_deferred" },
8d1d0340 700 { "tx_max_collisions" },
1da177e4 701 { "tx_multiple_collisions" },
8d1d0340 702 { "tx_single_collisions" },
1da177e4
LT		 703 { "rx_bad_ssd" },
704};
705
706/* number of ETHTOOL_GSTATS u64's */
8d1d0340 707#define VORTEX_NUM_STATS 5
1da177e4 708
62afe595 709static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1da177e4 710 int chip_idx, int card_idx);
c8303d10 711static int vortex_up(struct net_device *dev);
1da177e4
LT		 712static void vortex_down(struct net_device *dev, int final);
713static int vortex_open(struct net_device *dev);
62afe595 714static void mdio_sync(void __iomem *ioaddr, int bits);
1da177e4
LT		 715static int mdio_read(struct net_device *dev, int phy_id, int location);
716static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
717static void vortex_timer(unsigned long arg);
718static void rx_oom_timer(unsigned long arg);
719static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
720static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
721static int vortex_rx(struct net_device *dev);
722static int boomerang_rx(struct net_device *dev);
7d12e780
DH		 723static irqreturn_t vortex_interrupt(int irq, void *dev_id);
724static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
1da177e4
LT		 725static int vortex_close(struct net_device *dev);
726static void dump_tx_ring(struct net_device *dev);
62afe595 727static void update_stats(void __iomem *ioaddr, struct net_device *dev);
1da177e4
LT		 728static struct net_device_stats *vortex_get_stats(struct net_device *dev);
729static void set_rx_mode(struct net_device *dev);
730#ifdef CONFIG_PCI
731static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
732#endif
733static void vortex_tx_timeout(struct net_device *dev);
734static void acpi_set_WOL(struct net_device *dev);
7282d491 735static const struct ethtool_ops vortex_ethtool_ops;
1da177e4
LT		 736static void set_8021q_mode(struct net_device *dev, int enable);
737
1da177e4
LT		 738/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
739/* Option count limit only -- unlimited interfaces are supported. */
740#define MAX_UNITS 8
9954ab7f
JL		 741static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
742static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
743static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
744static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
745static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
900fd17d 746static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
1da177e4
LT		 747static int global_options = -1;
748static int global_full_duplex = -1;
749static int global_enable_wol = -1;
900fd17d 750static int global_use_mmio = -1;
1da177e4 751
1da177e4
LT		 752/* Variables to work-around the Compaq PCI BIOS32 problem. */
753static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
754static struct net_device *compaq_net_device;
755
756static int vortex_cards_found;
757
758module_param(debug, int, 0);
759module_param(global_options, int, 0);
760module_param_array(options, int, NULL, 0);
761module_param(global_full_duplex, int, 0);
762module_param_array(full_duplex, int, NULL, 0);
763module_param_array(hw_checksums, int, NULL, 0);
764module_param_array(flow_ctrl, int, NULL, 0);
765module_param(global_enable_wol, int, 0);
766module_param_array(enable_wol, int, NULL, 0);
767module_param(rx_copybreak, int, 0);
768module_param(max_interrupt_work, int, 0);
769module_param(compaq_ioaddr, int, 0);
770module_param(compaq_irq, int, 0);
771module_param(compaq_device_id, int, 0);
772module_param(watchdog, int, 0);
900fd17d
JL		 773module_param(global_use_mmio, int, 0);
774module_param_array(use_mmio, int, NULL, 0);
1da177e4
LT		 775MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
776MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
777MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
778MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
46e5e4a8 779MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
1da177e4
LT		 780MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
781MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
782MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
46e5e4a8 783MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
1da177e4
LT		 784MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
785MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
786MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
787MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
788MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
789MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
900fd17d
JL		 790MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
791MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
1da177e4
LT		 792
793#ifdef CONFIG_NET_POLL_CONTROLLER
794static void poll_vortex(struct net_device *dev)
795{
796 struct vortex_private *vp = netdev_priv(dev);
797 unsigned long flags;
0d38ff1d 798 local_irq_save(flags);
7d12e780 799 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
1da177e4 800 local_irq_restore(flags);
6aa20a22 801}
1da177e4
LT		 802#endif
803
804#ifdef CONFIG_PM
805
a880c4cd 806static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 807{
808 struct net_device *dev = pci_get_drvdata(pdev);
809
454d7c9b 810 if (dev && netdev_priv(dev)) {
1da177e4
LT		 811 if (netif_running(dev)) {
812 netif_device_detach(dev);
813 vortex_down(dev, 1);
814 }
5b039e68
RW		 815 pci_save_state(pdev);
816 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
817 free_irq(dev->irq, dev);
818 pci_disable_device(pdev);
819 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 820 }
821 return 0;
822}
823
a880c4cd 824static int vortex_resume(struct pci_dev *pdev)
1da177e4
LT		 825{
826 struct net_device *dev = pci_get_drvdata(pdev);
5b039e68 827 struct vortex_private *vp = netdev_priv(dev);
e1265153 828 int err;
1da177e4 829
5b039e68
RW		 830 if (dev && vp) {
831 pci_set_power_state(pdev, PCI_D0);
832 pci_restore_state(pdev);
e1265153
DM		 833 err = pci_enable_device(pdev);
834 if (err) {
39738e16 835 pr_warning("%s: Could not enable device\n",
e1265153
DM		 836 dev->name);
837 return err;
838 }
5b039e68
RW		 839 pci_set_master(pdev);
840 if (request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 841 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
39738e16 842 pr_warning("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
5b039e68
RW		 843 pci_disable_device(pdev);
844 return -EBUSY;
845 }
1da177e4 846 if (netif_running(dev)) {
c8303d10
MH		 847 err = vortex_up(dev);
848 if (err)
849 return err;
850 else
851 netif_device_attach(dev);
1da177e4
LT		 852 }
853 }
854 return 0;
855}
856
857#endif /* CONFIG_PM */
858
859#ifdef CONFIG_EISA
860static struct eisa_device_id vortex_eisa_ids[] = {
861 { "TCM5920", CH_3C592 },
862 { "TCM5970", CH_3C597 },
863 { "" }
864};
07563c71 865MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
1da177e4 866
95c408a9 867static int __init vortex_eisa_probe(struct device *device)
1da177e4 868{
62afe595 869 void __iomem *ioaddr;
1da177e4
LT		 870 struct eisa_device *edev;
871
a880c4cd 872 edev = to_eisa_device(device);
1da177e4 873
62afe595 874 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
1da177e4
LT		 875 return -EBUSY;
876
62afe595
JL		 877 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
878
879 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
1da177e4 880 edev->id.driver_data, vortex_cards_found)) {
a880c4cd 881 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4
LT		 882 return -ENODEV;
883 }
884
885 vortex_cards_found++;
886
887 return 0;
888}
889
95c408a9 890static int __devexit vortex_eisa_remove(struct device *device)
1da177e4
LT		 891{
892 struct eisa_device *edev;
893 struct net_device *dev;
894 struct vortex_private *vp;
62afe595 895 void __iomem *ioaddr;
1da177e4 896
a880c4cd
SK		 897 edev = to_eisa_device(device);
898 dev = eisa_get_drvdata(edev);
1da177e4
LT		 899
900 if (!dev) {
39738e16 901 pr_err("vortex_eisa_remove called for Compaq device!\n");
1da177e4
LT		 902 BUG();
903 }
904
905 vp = netdev_priv(dev);
62afe595 906 ioaddr = vp->ioaddr;
6aa20a22 907
a880c4cd
SK		 908 unregister_netdev(dev);
909 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
910 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
1da177e4 911
a880c4cd 912 free_netdev(dev);
1da177e4
LT		 913 return 0;
914}
95c408a9
RB		 915
916static struct eisa_driver vortex_eisa_driver = {
917 .id_table = vortex_eisa_ids,
918 .driver = {
919 .name = "3c59x",
920 .probe = vortex_eisa_probe,
921 .remove = __devexit_p(vortex_eisa_remove)
922 }
923};
924
925#endif /* CONFIG_EISA */
1da177e4
LT		 926
927/* returns count found (>= 0), or negative on error */
a880c4cd 928static int __init vortex_eisa_init(void)
1da177e4
LT		 929{
930 int eisa_found = 0;
931 int orig_cards_found = vortex_cards_found;
932
933#ifdef CONFIG_EISA
c2f6fabb
BH		 934 int err;
935
936 err = eisa_driver_register (&vortex_eisa_driver);
937 if (!err) {
938 /*
939 * Because of the way EISA bus is probed, we cannot assume
940 * any device have been found when we exit from
941 * eisa_driver_register (the bus root driver may not be
942 * initialized yet). So we blindly assume something was
943 * found, and let the sysfs magic happend...
944 */
945 eisa_found = 1;
1da177e4
LT		 946 }
947#endif
6aa20a22 948
1da177e4
LT		 949 /* Special code to work-around the Compaq PCI BIOS32 problem. */
950 if (compaq_ioaddr) {
62afe595
JL		 951 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
952 compaq_irq, compaq_device_id, vortex_cards_found++);
1da177e4
LT		 953 }
954
955 return vortex_cards_found - orig_cards_found + eisa_found;
956}
957
958/* returns count (>= 0), or negative on error */
a880c4cd 959static int __devinit vortex_init_one(struct pci_dev *pdev,
1da177e4
LT		 960 const struct pci_device_id *ent)
961{
900fd17d
JL		 962 int rc, unit, pci_bar;
963 struct vortex_chip_info *vci;
964 void __iomem *ioaddr;
1da177e4 965
6aa20a22 966 /* wake up and enable device */
a880c4cd 967 rc = pci_enable_device(pdev);
1da177e4
LT		 968 if (rc < 0)
969 goto out;
970
900fd17d
JL		 971 unit = vortex_cards_found;
972
973 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
974 /* Determine the default if the user didn't override us */
975 vci = &vortex_info_tbl[ent->driver_data];
976 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
977 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
978 pci_bar = use_mmio[unit] ? 1 : 0;
979 else
980 pci_bar = global_use_mmio ? 1 : 0;
981
982 ioaddr = pci_iomap(pdev, pci_bar, 0);
983 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
984 ioaddr = pci_iomap(pdev, 0, 0);
985
986 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
987 ent->driver_data, unit);
1da177e4 988 if (rc < 0) {
a880c4cd 989 pci_disable_device(pdev);
1da177e4
LT		 990 goto out;
991 }
992
993 vortex_cards_found++;
994
995out:
996 return rc;
997}
998
48b47a5e
SH		 999static const struct net_device_ops boomrang_netdev_ops = {
1000 .ndo_open = vortex_open,
1001 .ndo_stop = vortex_close,
1002 .ndo_start_xmit = boomerang_start_xmit,
1003 .ndo_tx_timeout = vortex_tx_timeout,
1004 .ndo_get_stats = vortex_get_stats,
1005#ifdef CONFIG_PCI
1006 .ndo_do_ioctl = vortex_ioctl,
1007#endif
1008 .ndo_set_multicast_list = set_rx_mode,
1009 .ndo_change_mtu = eth_change_mtu,
1010 .ndo_set_mac_address = eth_mac_addr,
1011 .ndo_validate_addr = eth_validate_addr,
1012#ifdef CONFIG_NET_POLL_CONTROLLER
1013 .ndo_poll_controller = poll_vortex,
1014#endif
1015};
1016
1017static const struct net_device_ops vortex_netdev_ops = {
1018 .ndo_open = vortex_open,
1019 .ndo_stop = vortex_close,
1020 .ndo_start_xmit = vortex_start_xmit,
1021 .ndo_tx_timeout = vortex_tx_timeout,
1022 .ndo_get_stats = vortex_get_stats,
1023#ifdef CONFIG_PCI
1024 .ndo_do_ioctl = vortex_ioctl,
1025#endif
1026 .ndo_set_multicast_list = set_rx_mode,
1027 .ndo_change_mtu = eth_change_mtu,
1028 .ndo_set_mac_address = eth_mac_addr,
1029 .ndo_validate_addr = eth_validate_addr,
1030#ifdef CONFIG_NET_POLL_CONTROLLER
1031 .ndo_poll_controller = poll_vortex,
1032#endif
1033};
1034
1da177e4
LT		 1035/*
1036 * Start up the PCI/EISA device which is described by *gendev.
1037 * Return 0 on success.
1038 *
1039 * NOTE: pdev can be NULL, for the case of a Compaq device
1040 */
1041static int __devinit vortex_probe1(struct device *gendev,
62afe595 1042 void __iomem *ioaddr, int irq,
1da177e4
LT		 1043 int chip_idx, int card_idx)
1044{
1045 struct vortex_private *vp;
1046 int option;
1047 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1048 int i, step;
1049 struct net_device *dev;
1050 static int printed_version;
1051 int retval, print_info;
1052 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
361d5ee3 1053 const char *print_name = "3c59x";
1da177e4
LT		 1054 struct pci_dev *pdev = NULL;
1055 struct eisa_device *edev = NULL;
1056
1057 if (!printed_version) {
39738e16 1058 pr_info("%s", version);
1da177e4
LT		 1059 printed_version = 1;
1060 }
1061
1062 if (gendev) {
1063 if ((pdev = DEVICE_PCI(gendev))) {
1064 print_name = pci_name(pdev);
1065 }
1066
1067 if ((edev = DEVICE_EISA(gendev))) {
fb28ad35 1068 print_name = dev_name(&edev->dev);
1da177e4
LT		 1069 }
1070 }
1071
1072 dev = alloc_etherdev(sizeof(*vp));
1073 retval = -ENOMEM;
1074 if (!dev) {
39738e16 1075 pr_err(PFX "unable to allocate etherdev, aborting\n");
1da177e4
LT		 1076 goto out;
1077 }
1da177e4
LT		 1078 SET_NETDEV_DEV(dev, gendev);
1079 vp = netdev_priv(dev);
1080
1081 option = global_options;
1082
1083 /* The lower four bits are the media type. */
1084 if (dev->mem_start) {
1085 /*
1086 * The 'options' param is passed in as the third arg to the
1087 * LILO 'ether=' argument for non-modular use
1088 */
1089 option = dev->mem_start;
1090 }
1091 else if (card_idx < MAX_UNITS) {
1092 if (options[card_idx] >= 0)
1093 option = options[card_idx];
1094 }
1095
1096 if (option > 0) {
1097 if (option & 0x8000)
1098 vortex_debug = 7;
1099 if (option & 0x4000)
1100 vortex_debug = 2;
1101 if (option & 0x0400)
1102 vp->enable_wol = 1;
1103 }
1104
1105 print_info = (vortex_debug > 1);
1106 if (print_info)
39738e16 1107 pr_info("See Documentation/networking/vortex.txt\n");
1da177e4 1108
39738e16 1109 pr_info("%s: 3Com %s %s at %p.\n",
1da177e4
LT		 1110 print_name,
1111 pdev ? "PCI" : "EISA",
1112 vci->name,
1113 ioaddr);
1114
62afe595 1115 dev->base_addr = (unsigned long)ioaddr;
1da177e4
LT		 1116 dev->irq = irq;
1117 dev->mtu = mtu;
62afe595 1118 vp->ioaddr = ioaddr;
1da177e4
LT		 1119 vp->large_frames = mtu > 1500;
1120 vp->drv_flags = vci->drv_flags;
1121 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1122 vp->io_size = vci->io_size;
1123 vp->card_idx = card_idx;
1124
1125 /* module list only for Compaq device */
1126 if (gendev == NULL) {
1127 compaq_net_device = dev;
1128 }
1129
1130 /* PCI-only startup logic */
1131 if (pdev) {
1132 /* EISA resources already marked, so only PCI needs to do this here */
1133 /* Ignore return value, because Cardbus drivers already allocate for us */
62afe595 1134 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1da177e4
LT		 1135 vp->must_free_region = 1;
1136
6aa20a22 1137 /* enable bus-mastering if necessary */
1da177e4 1138 if (vci->flags & PCI_USES_MASTER)
a880c4cd 1139 pci_set_master(pdev);
1da177e4
LT		 1140
1141 if (vci->drv_flags & IS_VORTEX) {
1142 u8 pci_latency;
1143 u8 new_latency = 248;
1144
1145 /* Check the PCI latency value. On the 3c590 series the latency timer
1146 must be set to the maximum value to avoid data corruption that occurs
1147 when the timer expires during a transfer. This bug exists the Vortex
1148 chip only. */
1149 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1150 if (pci_latency < new_latency) {
39738e16 1151 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1da177e4 1152 print_name, pci_latency, new_latency);
39738e16 1153 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1da177e4
LT		 1154 }
1155 }
1156 }
1157
1158 spin_lock_init(&vp->lock);
1159 vp->gendev = gendev;
1160 vp->mii.dev = dev;
1161 vp->mii.mdio_read = mdio_read;
1162 vp->mii.mdio_write = mdio_write;
1163 vp->mii.phy_id_mask = 0x1f;
1164 vp->mii.reg_num_mask = 0x1f;
1165
1166 /* Makes sure rings are at least 16 byte aligned. */
1167 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1168 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1169 &vp->rx_ring_dma);
1170 retval = -ENOMEM;
cc2d6596 1171 if (!vp->rx_ring)
1da177e4
LT		 1172 goto free_region;
1173
1174 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1175 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1176
1177 /* if we are a PCI driver, we store info in pdev->driver_data
6aa20a22 1178 * instead of a module list */
1da177e4
LT		 1179 if (pdev)
1180 pci_set_drvdata(pdev, dev);
1181 if (edev)
a880c4cd 1182 eisa_set_drvdata(edev, dev);
1da177e4
LT		 1183
1184 vp->media_override = 7;
1185 if (option >= 0) {
1186 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1187 if (vp->media_override != 7)
1188 vp->medialock = 1;
1189 vp->full_duplex = (option & 0x200) ? 1 : 0;
1190 vp->bus_master = (option & 16) ? 1 : 0;
1191 }
1192
1193 if (global_full_duplex > 0)
1194 vp->full_duplex = 1;
1195 if (global_enable_wol > 0)
1196 vp->enable_wol = 1;
1197
1198 if (card_idx < MAX_UNITS) {
1199 if (full_duplex[card_idx] > 0)
1200 vp->full_duplex = 1;
1201 if (flow_ctrl[card_idx] > 0)
1202 vp->flow_ctrl = 1;
1203 if (enable_wol[card_idx] > 0)
1204 vp->enable_wol = 1;
1205 }
1206
125d5ce8 1207 vp->mii.force_media = vp->full_duplex;
1da177e4
LT		 1208 vp->options = option;
1209 /* Read the station address from the EEPROM. */
1210 EL3WINDOW(0);
1211 {
1212 int base;
1213
1214 if (vci->drv_flags & EEPROM_8BIT)
1215 base = 0x230;
1216 else if (vci->drv_flags & EEPROM_OFFSET)
1217 base = EEPROM_Read + 0x30;
1218 else
1219 base = EEPROM_Read;
1220
1221 for (i = 0; i < 0x40; i++) {
1222 int timer;
62afe595 1223 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1da177e4
LT		 1224 /* Pause for at least 162 us. for the read to take place. */
1225 for (timer = 10; timer >= 0; timer--) {
1226 udelay(162);
62afe595 1227 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1da177e4
LT		 1228 break;
1229 }
62afe595 1230 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1da177e4
LT		 1231 }
1232 }
1233 for (i = 0; i < 0x18; i++)
1234 checksum ^= eeprom[i];
1235 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1236 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1237 while (i < 0x21)
1238 checksum ^= eeprom[i++];
1239 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1240 }
1241 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
39738e16 1242 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1da177e4 1243 for (i = 0; i < 3; i++)
cc2d6596 1244 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
bb531fc0 1245 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
0795af57 1246 if (print_info)
39738e16 1247 pr_cont(" %pM", dev->dev_addr);
1da177e4
LT		 1248 /* Unfortunately an all zero eeprom passes the checksum and this
1249 gets found in the wild in failure cases. Crypto is hard 8) */
1250 if (!is_valid_ether_addr(dev->dev_addr)) {
1251 retval = -EINVAL;
39738e16 1252 pr_err("*** EEPROM MAC address is invalid.\n");
1da177e4
LT		 1253 goto free_ring; /* With every pack */
1254 }
1255 EL3WINDOW(2);
1256 for (i = 0; i < 6; i++)
62afe595 1257 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1258
1da177e4 1259 if (print_info)
39738e16 1260 pr_cont(", IRQ %d\n", dev->irq);
1da177e4 1261 /* Tell them about an invalid IRQ. */
60e4ad7a 1262 if (dev->irq <= 0 || dev->irq >= nr_irqs)
39738e16 1263 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1da177e4 1264 dev->irq);
1da177e4
LT		 1265
1266 EL3WINDOW(4);
62afe595 1267 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1da177e4 1268 if (print_info) {
39738e16
AB		 1269 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1270 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1da177e4
LT		 1271 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1272 }
1273
1274
1275 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1da177e4
LT		 1276 unsigned short n;
1277
62afe595
JL		 1278 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1279 if (!vp->cb_fn_base) {
1da177e4 1280 retval = -ENOMEM;
62afe595 1281 goto free_ring;
1da177e4 1282 }
62afe595 1283
1da177e4 1284 if (print_info) {
39738e16 1285 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
7c7459d1
GKH		 1286 print_name,
1287 (unsigned long long)pci_resource_start(pdev, 2),
62afe595 1288 vp->cb_fn_base);
1da177e4
LT		 1289 }
1290 EL3WINDOW(2);
1291
62afe595 1292 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1293 if (vp->drv_flags & INVERT_LED_PWR)
1294 n |= 0x10;
1295 if (vp->drv_flags & INVERT_MII_PWR)
1296 n |= 0x4000;
62afe595 1297 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1298 if (vp->drv_flags & WNO_XCVR_PWR) {
1299 EL3WINDOW(0);
62afe595 1300 iowrite16(0x0800, ioaddr);
1da177e4
LT		 1301 }
1302 }
1303
1304 /* Extract our information from the EEPROM data. */
1305 vp->info1 = eeprom[13];
1306 vp->info2 = eeprom[15];
1307 vp->capabilities = eeprom[16];
1308
1309 if (vp->info1 & 0x8000) {
1310 vp->full_duplex = 1;
1311 if (print_info)
39738e16 1312 pr_info("Full duplex capable\n");
1da177e4
LT		 1313 }
1314
1315 {
f71e1309 1316 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1da177e4
LT		 1317 unsigned int config;
1318 EL3WINDOW(3);
62afe595 1319 vp->available_media = ioread16(ioaddr + Wn3_Options);
1da177e4
LT		 1320 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1321 vp->available_media = 0x40;
62afe595 1322 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1323 if (print_info) {
39738e16
AB		 1324 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1325 config, ioread16(ioaddr + Wn3_Options));
1326 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1da177e4
LT		 1327 8 << RAM_SIZE(config),
1328 RAM_WIDTH(config) ? "word" : "byte",
1329 ram_split[RAM_SPLIT(config)],
1330 AUTOSELECT(config) ? "autoselect/" : "",
1331 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1332 media_tbl[XCVR(config)].name);
1333 }
1334 vp->default_media = XCVR(config);
1335 if (vp->default_media == XCVR_NWAY)
1336 vp->has_nway = 1;
1337 vp->autoselect = AUTOSELECT(config);
1338 }
1339
1340 if (vp->media_override != 7) {
39738e16 1341 pr_info("%s: Media override to transceiver type %d (%s).\n",
1da177e4
LT		 1342 print_name, vp->media_override,
1343 media_tbl[vp->media_override].name);
1344 dev->if_port = vp->media_override;
1345 } else
1346 dev->if_port = vp->default_media;
1347
1348 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1349 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1350 int phy, phy_idx = 0;
1351 EL3WINDOW(4);
1352 mii_preamble_required++;
1353 if (vp->drv_flags & EXTRA_PREAMBLE)
1354 mii_preamble_required++;
1355 mdio_sync(ioaddr, 32);
106427e6 1356 mdio_read(dev, 24, MII_BMSR);
1da177e4
LT		 1357 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1358 int mii_status, phyx;
1359
1360 /*
1361 * For the 3c905CX we look at index 24 first, because it bogusly
1362 * reports an external PHY at all indices
1363 */
1364 if (phy == 0)
1365 phyx = 24;
1366 else if (phy <= 24)
1367 phyx = phy - 1;
1368 else
1369 phyx = phy;
106427e6 1370 mii_status = mdio_read(dev, phyx, MII_BMSR);
1da177e4
LT		 1371 if (mii_status && mii_status != 0xffff) {
1372 vp->phys[phy_idx++] = phyx;
1373 if (print_info) {
39738e16
AB		 1374 pr_info(" MII transceiver found at address %d, status %4x.\n",
1375 phyx, mii_status);
1da177e4
LT		 1376 }
1377 if ((mii_status & 0x0040) == 0)
1378 mii_preamble_required++;
1379 }
1380 }
1381 mii_preamble_required--;
1382 if (phy_idx == 0) {
39738e16 1383 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1da177e4
LT		 1384 vp->phys[0] = 24;
1385 } else {
106427e6 1386 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1da177e4
LT		 1387 if (vp->full_duplex) {
1388 /* Only advertise the FD media types. */
1389 vp->advertising &= ~0x02A0;
1390 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1391 }
1392 }
1393 vp->mii.phy_id = vp->phys[0];
1394 }
1395
1396 if (vp->capabilities & CapBusMaster) {
1397 vp->full_bus_master_tx = 1;
1398 if (print_info) {
39738e16 1399 pr_info(" Enabling bus-master transmits and %s receives.\n",
1da177e4
LT		 1400 (vp->info2 & 1) ? "early" : "whole-frame" );
1401 }
1402 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1403 vp->bus_master = 0; /* AKPM: vortex only */
1404 }
1405
1406 /* The 3c59x-specific entries in the device structure. */
1da177e4 1407 if (vp->full_bus_master_tx) {
48b47a5e 1408 dev->netdev_ops = &boomrang_netdev_ops;
1da177e4 1409 /* Actually, it still should work with iommu. */
32fb5f06
JL		 1410 if (card_idx < MAX_UNITS &&
1411 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1412 hw_checksums[card_idx] == 1)) {
d311b0d3 1413 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1da177e4 1414 }
48b47a5e
SH		 1415 } else
1416 dev->netdev_ops = &vortex_netdev_ops;
1da177e4
LT		 1417
1418 if (print_info) {
39738e16 1419 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1da177e4
LT		 1420 print_name,
1421 (dev->features & NETIF_F_SG) ? "en":"dis",
1422 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1423 }
1424
1da177e4 1425 dev->ethtool_ops = &vortex_ethtool_ops;
1da177e4 1426 dev->watchdog_timeo = (watchdog * HZ) / 1000;
48b47a5e 1427
1da177e4
LT		 1428 if (pdev) {
1429 vp->pm_state_valid = 1;
1430 pci_save_state(VORTEX_PCI(vp));
1431 acpi_set_WOL(dev);
1432 }
1433 retval = register_netdev(dev);
1434 if (retval == 0)
1435 return 0;
1436
1437free_ring:
1438 pci_free_consistent(pdev,
1439 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1440 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1441 vp->rx_ring,
1442 vp->rx_ring_dma);
1443free_region:
1444 if (vp->must_free_region)
62afe595 1445 release_region(dev->base_addr, vci->io_size);
1da177e4 1446 free_netdev(dev);
39738e16 1447 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1da177e4
LT		 1448out:
1449 return retval;
1450}
1451
1452static void
1453issue_and_wait(struct net_device *dev, int cmd)
1454{
62afe595
JL		 1455 struct vortex_private *vp = netdev_priv(dev);
1456 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1457 int i;
1458
62afe595 1459 iowrite16(cmd, ioaddr + EL3_CMD);
1da177e4 1460 for (i = 0; i < 2000; i++) {
62afe595 1461 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 1462 return;
1463 }
1464
1465 /* OK, that didn't work. Do it the slow way. One second */
1466 for (i = 0; i < 100000; i++) {
62afe595 1467 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1da177e4 1468 if (vortex_debug > 1)
39738e16 1469 pr_info("%s: command 0x%04x took %d usecs\n",
1da177e4
LT		 1470 dev->name, cmd, i * 10);
1471 return;
1472 }
1473 udelay(10);
1474 }
39738e16 1475 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
62afe595 1476 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1da177e4
LT		 1477}
1478
125d5ce8
SK		 1479static void
1480vortex_set_duplex(struct net_device *dev)
1481{
1482 struct vortex_private *vp = netdev_priv(dev);
1483 void __iomem *ioaddr = vp->ioaddr;
1484
39738e16 1485 pr_info("%s: setting %s-duplex.\n",
125d5ce8
SK		 1486 dev->name, (vp->full_duplex) ? "full" : "half");
1487
1488 EL3WINDOW(3);
1489 /* Set the full-duplex bit. */
1490 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1491 (vp->large_frames ? 0x40 : 0) |
1492 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1493 0x100 : 0),
1494 ioaddr + Wn3_MAC_Ctrl);
125d5ce8
SK		 1495}
1496
1497static void vortex_check_media(struct net_device *dev, unsigned int init)
1498{
1499 struct vortex_private *vp = netdev_priv(dev);
1500 unsigned int ok_to_print = 0;
1501
1502 if (vortex_debug > 3)
1503 ok_to_print = 1;
1504
1505 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1506 vp->full_duplex = vp->mii.full_duplex;
1507 vortex_set_duplex(dev);
1508 } else if (init) {
1509 vortex_set_duplex(dev);
1510 }
1511}
1512
c8303d10 1513static int
1da177e4
LT		 1514vortex_up(struct net_device *dev)
1515{
1da177e4 1516 struct vortex_private *vp = netdev_priv(dev);
62afe595 1517 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1518 unsigned int config;
0280f9f9 1519 int i, mii_reg1, mii_reg5, err = 0;
1da177e4
LT		 1520
1521 if (VORTEX_PCI(vp)) {
1522 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3c8fad18
DR		 1523 if (vp->pm_state_valid)
1524 pci_restore_state(VORTEX_PCI(vp));
c8303d10
MH		 1525 err = pci_enable_device(VORTEX_PCI(vp));
1526 if (err) {
39738e16 1527 pr_warning("%s: Could not enable device\n",
c8303d10
MH		 1528 dev->name);
1529 goto err_out;
1530 }
1da177e4
LT		 1531 }
1532
1533 /* Before initializing select the active media port. */
1534 EL3WINDOW(3);
62afe595 1535 config = ioread32(ioaddr + Wn3_Config);
1da177e4
LT		 1536
1537 if (vp->media_override != 7) {
39738e16 1538 pr_info("%s: Media override to transceiver %d (%s).\n",
1da177e4
LT		 1539 dev->name, vp->media_override,
1540 media_tbl[vp->media_override].name);
1541 dev->if_port = vp->media_override;
1542 } else if (vp->autoselect) {
1543 if (vp->has_nway) {
1544 if (vortex_debug > 1)
39738e16 1545 pr_info("%s: using NWAY device table, not %d\n",
1da177e4
LT		 1546 dev->name, dev->if_port);
1547 dev->if_port = XCVR_NWAY;
1548 } else {
1549 /* Find first available media type, starting with 100baseTx. */
1550 dev->if_port = XCVR_100baseTx;
1551 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1552 dev->if_port = media_tbl[dev->if_port].next;
1553 if (vortex_debug > 1)
39738e16 1554 pr_info("%s: first available media type: %s\n",
1da177e4
LT		 1555 dev->name, media_tbl[dev->if_port].name);
1556 }
1557 } else {
1558 dev->if_port = vp->default_media;
1559 if (vortex_debug > 1)
39738e16 1560 pr_info("%s: using default media %s\n",
1da177e4
LT		 1561 dev->name, media_tbl[dev->if_port].name);
1562 }
1563
1564 init_timer(&vp->timer);
1565 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1566 vp->timer.data = (unsigned long)dev;
1567 vp->timer.function = vortex_timer; /* timer handler */
1568 add_timer(&vp->timer);
1569
1570 init_timer(&vp->rx_oom_timer);
1571 vp->rx_oom_timer.data = (unsigned long)dev;
1572 vp->rx_oom_timer.function = rx_oom_timer;
1573
1574 if (vortex_debug > 1)
39738e16 1575 pr_debug("%s: Initial media type %s.\n",
1da177e4
LT		 1576 dev->name, media_tbl[dev->if_port].name);
1577
125d5ce8 1578 vp->full_duplex = vp->mii.force_media;
1da177e4
LT		 1579 config = BFINS(config, dev->if_port, 20, 4);
1580 if (vortex_debug > 6)
39738e16 1581 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
62afe595 1582 iowrite32(config, ioaddr + Wn3_Config);
1da177e4
LT		 1583
1584 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1da177e4 1585 EL3WINDOW(4);
09ce3512
SK		 1586 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1587 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1588 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
373492d0 1589 vp->mii.full_duplex = vp->full_duplex;
09ce3512 1590
125d5ce8 1591 vortex_check_media(dev, 1);
1da177e4 1592 }
125d5ce8
SK		 1593 else
1594 vortex_set_duplex(dev);
1da177e4 1595
09ce3512
SK		 1596 issue_and_wait(dev, TxReset);
1597 /*
1598 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1599 */
1600 issue_and_wait(dev, RxReset|0x04);
1601
1da177e4 1602
62afe595 1603 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1da177e4
LT		 1604
1605 if (vortex_debug > 1) {
1606 EL3WINDOW(4);
39738e16 1607 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
62afe595 1608 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1da177e4
LT		 1609 }
1610
1611 /* Set the station address and mask in window 2 each time opened. */
1612 EL3WINDOW(2);
1613 for (i = 0; i < 6; i++)
62afe595 1614 iowrite8(dev->dev_addr[i], ioaddr + i);
1da177e4 1615 for (; i < 12; i+=2)
62afe595 1616 iowrite16(0, ioaddr + i);
1da177e4
LT		 1617
1618 if (vp->cb_fn_base) {
62afe595 1619 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1da177e4
LT		 1620 if (vp->drv_flags & INVERT_LED_PWR)
1621 n |= 0x10;
1622 if (vp->drv_flags & INVERT_MII_PWR)
1623 n |= 0x4000;
62afe595 1624 iowrite16(n, ioaddr + Wn2_ResetOptions);
1da177e4
LT		 1625 }
1626
1627 if (dev->if_port == XCVR_10base2)
1628 /* Start the thinnet transceiver. We should really wait 50ms...*/
62afe595 1629 iowrite16(StartCoax, ioaddr + EL3_CMD);
1da177e4
LT		 1630 if (dev->if_port != XCVR_NWAY) {
1631 EL3WINDOW(4);
62afe595 1632 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1633 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1634 }
1635
1636 /* Switch to the stats window, and clear all stats by reading. */
62afe595 1637 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 1638 EL3WINDOW(6);
1639 for (i = 0; i < 10; i++)
62afe595
JL		 1640 ioread8(ioaddr + i);
1641 ioread16(ioaddr + 10);
1642 ioread16(ioaddr + 12);
1da177e4
LT		 1643 /* New: On the Vortex we must also clear the BadSSD counter. */
1644 EL3WINDOW(4);
62afe595 1645 ioread8(ioaddr + 12);
1da177e4 1646 /* ..and on the Boomerang we enable the extra statistics bits. */
62afe595 1647 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1da177e4
LT		 1648
1649 /* Switch to register set 7 for normal use. */
1650 EL3WINDOW(7);
1651
1652 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1653 vp->cur_rx = vp->dirty_rx = 0;
1654 /* Initialize the RxEarly register as recommended. */
62afe595
JL		 1655 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1656 iowrite32(0x0020, ioaddr + PktStatus);
1657 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1da177e4
LT		 1658 }
1659 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1660 vp->cur_tx = vp->dirty_tx = 0;
1661 if (vp->drv_flags & IS_BOOMERANG)
62afe595 1662 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1da177e4
LT		 1663 /* Clear the Rx, Tx rings. */
1664 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1665 vp->rx_ring[i].status = 0;
1666 for (i = 0; i < TX_RING_SIZE; i++)
1667 vp->tx_skbuff[i] = NULL;
62afe595 1668 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 1669 }
1670 /* Set receiver mode: presumably accept b-case and phys addr only. */
1671 set_rx_mode(dev);
1672 /* enable 802.1q tagged frames */
1673 set_8021q_mode(dev, 1);
62afe595 1674 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1da177e4 1675
62afe595
JL		 1676 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1677 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1da177e4
LT		 1678 /* Allow status bits to be seen. */
1679 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1680 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1681 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1682 (vp->bus_master ? DMADone : 0);
1683 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1684 (vp->full_bus_master_rx ? 0 : RxComplete) |
1685 StatsFull | HostError | TxComplete | IntReq
1686 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
62afe595 1687 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1da177e4 1688 /* Ack all pending events, and set active indicator mask. */
62afe595 1689 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1da177e4 1690 ioaddr + EL3_CMD);
62afe595 1691 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4 1692 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 1693 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 1694 netif_start_queue (dev);
c8303d10
MH		 1695err_out:
1696 return err;
1da177e4
LT		 1697}
1698
1699static int
1700vortex_open(struct net_device *dev)
1701{
1702 struct vortex_private *vp = netdev_priv(dev);
1703 int i;
1704 int retval;
1705
1706 /* Use the now-standard shared IRQ implementation. */
1707 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1fb9df5d 1708 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
39738e16 1709 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
c8303d10 1710 goto err;
1da177e4
LT		 1711 }
1712
1713 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1714 if (vortex_debug > 2)
39738e16 1715 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1da177e4
LT		 1716 for (i = 0; i < RX_RING_SIZE; i++) {
1717 struct sk_buff *skb;
1718 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1719 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1720 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
9a5d3414
SH		 1721
1722 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1723 GFP_KERNEL);
1da177e4
LT		 1724 vp->rx_skbuff[i] = skb;
1725 if (skb == NULL)
1726 break; /* Bad news! */
9a5d3414
SH		 1727
1728 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
689be439 1729 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1730 }
1731 if (i != RX_RING_SIZE) {
1732 int j;
39738e16 1733 pr_emerg("%s: no memory for rx ring\n", dev->name);
1da177e4
LT		 1734 for (j = 0; j < i; j++) {
1735 if (vp->rx_skbuff[j]) {
1736 dev_kfree_skb(vp->rx_skbuff[j]);
1737 vp->rx_skbuff[j] = NULL;
1738 }
1739 }
1740 retval = -ENOMEM;
c8303d10 1741 goto err_free_irq;
1da177e4
LT		 1742 }
1743 /* Wrap the ring. */
1744 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1745 }
1746
c8303d10
MH		 1747 retval = vortex_up(dev);
1748 if (!retval)
1749 goto out;
1da177e4 1750
c8303d10 1751err_free_irq:
1da177e4 1752 free_irq(dev->irq, dev);
c8303d10 1753err:
1da177e4 1754 if (vortex_debug > 1)
39738e16 1755 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
c8303d10 1756out:
1da177e4
LT		 1757 return retval;
1758}
1759
1760static void
1761vortex_timer(unsigned long data)
1762{
1763 struct net_device *dev = (struct net_device *)data;
1764 struct vortex_private *vp = netdev_priv(dev);
62afe595 1765 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1766 int next_tick = 60*HZ;
1767 int ok = 0;
125d5ce8 1768 int media_status, old_window;
1da177e4
LT		 1769
1770 if (vortex_debug > 2) {
39738e16 1771 pr_debug("%s: Media selection timer tick happened, %s.\n",
1da177e4 1772 dev->name, media_tbl[dev->if_port].name);
39738e16 1773 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1da177e4
LT		 1774 }
1775
0a9da4bd 1776 disable_irq_lockdep(dev->irq);
62afe595 1777 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1da177e4 1778 EL3WINDOW(4);
62afe595 1779 media_status = ioread16(ioaddr + Wn4_Media);
1da177e4
LT		 1780 switch (dev->if_port) {
1781 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1782 if (media_status & Media_LnkBeat) {
1783 netif_carrier_on(dev);
1784 ok = 1;
1785 if (vortex_debug > 1)
39738e16 1786 pr_debug("%s: Media %s has link beat, %x.\n",
1da177e4
LT		 1787 dev->name, media_tbl[dev->if_port].name, media_status);
1788 } else {
1789 netif_carrier_off(dev);
1790 if (vortex_debug > 1) {
39738e16 1791 pr_debug("%s: Media %s has no link beat, %x.\n",
1da177e4
LT		 1792 dev->name, media_tbl[dev->if_port].name, media_status);
1793 }
1794 }
1795 break;
1796 case XCVR_MII: case XCVR_NWAY:
1797 {
1da177e4 1798 ok = 1;
c5643cab
IM		 1799 /* Interrupts are already disabled */
1800 spin_lock(&vp->lock);
125d5ce8 1801 vortex_check_media(dev, 0);
c5643cab 1802 spin_unlock(&vp->lock);
1da177e4
LT		 1803 }
1804 break;
1805 default: /* Other media types handled by Tx timeouts. */
1806 if (vortex_debug > 1)
39738e16 1807 pr_debug("%s: Media %s has no indication, %x.\n",
1da177e4
LT		 1808 dev->name, media_tbl[dev->if_port].name, media_status);
1809 ok = 1;
1810 }
b4ff6450
SK		 1811
1812 if (!netif_carrier_ok(dev))
1813 next_tick = 5*HZ;
1814
e94d10eb
SK		 1815 if (vp->medialock)
1816 goto leave_media_alone;
1817
a880c4cd 1818 if (!ok) {
1da177e4
LT		 1819 unsigned int config;
1820
1821 do {
1822 dev->if_port = media_tbl[dev->if_port].next;
1823 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1824 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1825 dev->if_port = vp->default_media;
1826 if (vortex_debug > 1)
39738e16 1827 pr_debug("%s: Media selection failing, using default %s port.\n",
1da177e4
LT		 1828 dev->name, media_tbl[dev->if_port].name);
1829 } else {
1830 if (vortex_debug > 1)
39738e16 1831 pr_debug("%s: Media selection failed, now trying %s port.\n",
1da177e4
LT		 1832 dev->name, media_tbl[dev->if_port].name);
1833 next_tick = media_tbl[dev->if_port].wait;
1834 }
62afe595 1835 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1da177e4
LT		 1836 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1837
1838 EL3WINDOW(3);
62afe595 1839 config = ioread32(ioaddr + Wn3_Config);
1da177e4 1840 config = BFINS(config, dev->if_port, 20, 4);
62afe595 1841 iowrite32(config, ioaddr + Wn3_Config);
1da177e4 1842
62afe595 1843 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1da177e4
LT		 1844 ioaddr + EL3_CMD);
1845 if (vortex_debug > 1)
39738e16 1846 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1da177e4
LT		 1847 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1848 }
1da177e4
LT		 1849
1850leave_media_alone:
1851 if (vortex_debug > 2)
39738e16 1852 pr_debug("%s: Media selection timer finished, %s.\n",
1da177e4
LT		 1853 dev->name, media_tbl[dev->if_port].name);
1854
e94d10eb 1855 EL3WINDOW(old_window);
0a9da4bd 1856 enable_irq_lockdep(dev->irq);
1da177e4
LT		 1857 mod_timer(&vp->timer, RUN_AT(next_tick));
1858 if (vp->deferred)
62afe595 1859 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1da177e4
LT		 1860 return;
1861}
1862
1863static void vortex_tx_timeout(struct net_device *dev)
1864{
1865 struct vortex_private *vp = netdev_priv(dev);
62afe595 1866 void __iomem *ioaddr = vp->ioaddr;
1da177e4 1867
39738e16 1868 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
62afe595
JL		 1869 dev->name, ioread8(ioaddr + TxStatus),
1870 ioread16(ioaddr + EL3_STATUS));
1da177e4 1871 EL3WINDOW(4);
39738e16 1872 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
62afe595
JL		 1873 ioread16(ioaddr + Wn4_NetDiag),
1874 ioread16(ioaddr + Wn4_Media),
1875 ioread32(ioaddr + PktStatus),
1876 ioread16(ioaddr + Wn4_FIFODiag));
1da177e4 1877 /* Slight code bloat to be user friendly. */
62afe595 1878 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
39738e16 1879 pr_err("%s: Transmitter encountered 16 collisions --"
1da177e4 1880 " network cable problem?\n", dev->name);
62afe595 1881 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
39738e16 1882 pr_err("%s: Interrupt posted but not delivered --"
1da177e4
LT		 1883 " IRQ blocked by another device?\n", dev->name);
1884 /* Bad idea here.. but we might as well handle a few events. */
1885 {
1886 /*
1887 * Block interrupts because vortex_interrupt does a bare spin_lock()
1888 */
1889 unsigned long flags;
1890 local_irq_save(flags);
1891 if (vp->full_bus_master_tx)
7d12e780 1892 boomerang_interrupt(dev->irq, dev);
1da177e4 1893 else
7d12e780 1894 vortex_interrupt(dev->irq, dev);
1da177e4
LT		 1895 local_irq_restore(flags);
1896 }
1897 }
1898
1899 if (vortex_debug > 0)
1900 dump_tx_ring(dev);
1901
1902 issue_and_wait(dev, TxReset);
1903
1daad055 1904 dev->stats.tx_errors++;
1da177e4 1905 if (vp->full_bus_master_tx) {
39738e16 1906 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
62afe595
JL		 1907 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1908 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1da177e4
LT		 1909 ioaddr + DownListPtr);
1910 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1911 netif_wake_queue (dev);
1912 if (vp->drv_flags & IS_BOOMERANG)
62afe595
JL		 1913 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1914 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4 1915 } else {
1daad055 1916 dev->stats.tx_dropped++;
1da177e4
LT		 1917 netif_wake_queue(dev);
1918 }
6aa20a22 1919
1da177e4 1920 /* Issue Tx Enable */
62afe595 1921 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 1922 dev->trans_start = jiffies;
6aa20a22 1923
1da177e4
LT		 1924 /* Switch to register set 7 for normal use. */
1925 EL3WINDOW(7);
1926}
1927
1928/*
1929 * Handle uncommon interrupt sources. This is a separate routine to minimize
1930 * the cache impact.
1931 */
1932static void
1933vortex_error(struct net_device *dev, int status)
1934{
1935 struct vortex_private *vp = netdev_priv(dev);
62afe595 1936 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 1937 int do_tx_reset = 0, reset_mask = 0;
1938 unsigned char tx_status = 0;
1939
1940 if (vortex_debug > 2) {
39738e16 1941 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1da177e4
LT		 1942 }
1943
1944 if (status & TxComplete) { /* Really "TxError" for us. */
62afe595 1945 tx_status = ioread8(ioaddr + TxStatus);
1da177e4
LT		 1946 /* Presumably a tx-timeout. We must merely re-enable. */
1947 if (vortex_debug > 2
1948 || (tx_status != 0x88 && vortex_debug > 0)) {
39738e16 1949 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1da177e4
LT		 1950 dev->name, tx_status);
1951 if (tx_status == 0x82) {
39738e16 1952 pr_err("Probably a duplex mismatch. See "
1da177e4
LT		 1953 "Documentation/networking/vortex.txt\n");
1954 }
1955 dump_tx_ring(dev);
1956 }
1daad055
PZ		 1957 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1958 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
0000754c 1959 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
62afe595 1960 iowrite8(0, ioaddr + TxStatus);
1da177e4
LT		 1961 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1962 do_tx_reset = 1;
0000754c
AM		 1963 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1964 do_tx_reset = 1;
1965 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1966 } else { /* Merely re-enable the transmitter. */
62afe595 1967 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 1968 }
1969 }
1970
1971 if (status & RxEarly) { /* Rx early is unused. */
1972 vortex_rx(dev);
62afe595 1973 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1da177e4
LT		 1974 }
1975 if (status & StatsFull) { /* Empty statistics. */
1976 static int DoneDidThat;
1977 if (vortex_debug > 4)
39738e16 1978 pr_debug("%s: Updating stats.\n", dev->name);
1da177e4
LT		 1979 update_stats(ioaddr, dev);
1980 /* HACK: Disable statistics as an interrupt source. */
1981 /* This occurs when we have the wrong media type! */
1982 if (DoneDidThat == 0 &&
62afe595 1983 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
39738e16 1984 pr_warning("%s: Updating statistics failed, disabling "
1da177e4
LT		 1985 "stats as an interrupt source.\n", dev->name);
1986 EL3WINDOW(5);
62afe595 1987 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1da177e4
LT		 1988 vp->intr_enable &= ~StatsFull;
1989 EL3WINDOW(7);
1990 DoneDidThat++;
1991 }
1992 }
1993 if (status & IntReq) { /* Restore all interrupt sources. */
62afe595
JL		 1994 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1995 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1da177e4
LT		 1996 }
1997 if (status & HostError) {
1998 u16 fifo_diag;
1999 EL3WINDOW(4);
62afe595 2000 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
39738e16 2001 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
1da177e4
LT		 2002 dev->name, fifo_diag);
2003 /* Adapter failure requires Tx/Rx reset and reinit. */
2004 if (vp->full_bus_master_tx) {
62afe595 2005 int bus_status = ioread32(ioaddr + PktStatus);
1da177e4
LT		 2006 /* 0x80000000 PCI master abort. */
2007 /* 0x40000000 PCI target abort. */
2008 if (vortex_debug)
39738e16 2009 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1da177e4
LT		 2010
2011 /* In this case, blow the card away */
2012 /* Must not enter D3 or we can't legally issue the reset! */
2013 vortex_down(dev, 0);
2014 issue_and_wait(dev, TotalReset | 0xff);
2015 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2016 } else if (fifo_diag & 0x0400)
2017 do_tx_reset = 1;
2018 if (fifo_diag & 0x3000) {
2019 /* Reset Rx fifo and upload logic */
2020 issue_and_wait(dev, RxReset|0x07);
2021 /* Set the Rx filter to the current state. */
2022 set_rx_mode(dev);
2023 /* enable 802.1q VLAN tagged frames */
2024 set_8021q_mode(dev, 1);
62afe595
JL		 2025 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2026 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
1da177e4
LT		 2027 }
2028 }
2029
2030 if (do_tx_reset) {
2031 issue_and_wait(dev, TxReset|reset_mask);
62afe595 2032 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4
LT		 2033 if (!vp->full_bus_master_tx)
2034 netif_wake_queue(dev);
2035 }
2036}
2037
2038static int
2039vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2040{
2041 struct vortex_private *vp = netdev_priv(dev);
62afe595 2042 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2043
2044 /* Put out the doubleword header... */
62afe595 2045 iowrite32(skb->len, ioaddr + TX_FIFO);
1da177e4
LT		 2046 if (vp->bus_master) {
2047 /* Set the bus-master controller to transfer the packet. */
2048 int len = (skb->len + 3) & ~3;
a880c4cd 2049 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
1da177e4 2050 ioaddr + Wn7_MasterAddr);
62afe595 2051 iowrite16(len, ioaddr + Wn7_MasterLen);
1da177e4 2052 vp->tx_skb = skb;
62afe595 2053 iowrite16(StartDMADown, ioaddr + EL3_CMD);
1da177e4
LT		 2054 /* netif_wake_queue() will be called at the DMADone interrupt. */
2055 } else {
2056 /* ... and the packet rounded to a doubleword. */
62afe595 2057 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1da177e4 2058 dev_kfree_skb (skb);
62afe595 2059 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2060 netif_start_queue (dev); /* AKPM: redundant? */
2061 } else {
2062 /* Interrupt us when the FIFO has room for max-sized packet. */
2063 netif_stop_queue(dev);
62afe595 2064 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2065 }
2066 }
2067
2068 dev->trans_start = jiffies;
2069
2070 /* Clear the Tx status stack. */
2071 {
2072 int tx_status;
2073 int i = 32;
2074
62afe595 2075 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
1da177e4
LT		 2076 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2077 if (vortex_debug > 2)
39738e16 2078 pr_debug("%s: Tx error, status %2.2x.\n",
1da177e4 2079 dev->name, tx_status);
1daad055
PZ		 2080 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2081 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1da177e4
LT		 2082 if (tx_status & 0x30) {
2083 issue_and_wait(dev, TxReset);
2084 }
62afe595 2085 iowrite16(TxEnable, ioaddr + EL3_CMD);
1da177e4 2086 }
62afe595 2087 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1da177e4
LT		 2088 }
2089 }
2090 return 0;
2091}
2092
2093static int
2094boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2095{
2096 struct vortex_private *vp = netdev_priv(dev);
62afe595 2097 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2098 /* Calculate the next Tx descriptor entry. */
2099 int entry = vp->cur_tx % TX_RING_SIZE;
2100 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2101 unsigned long flags;
2102
2103 if (vortex_debug > 6) {
39738e16
AB		 2104 pr_debug("boomerang_start_xmit()\n");
2105 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
0f667ff5 2106 dev->name, vp->cur_tx);
1da177e4
LT		 2107 }
2108
2109 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2110 if (vortex_debug > 0)
39738e16 2111 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
1da177e4
LT		 2112 dev->name);
2113 netif_stop_queue(dev);
5b548140 2114 return NETDEV_TX_BUSY;
1da177e4
LT		 2115 }
2116
2117 vp->tx_skbuff[entry] = skb;
2118
2119 vp->tx_ring[entry].next = 0;
2120#if DO_ZEROCOPY
84fa7933 2121 if (skb->ip_summed != CHECKSUM_PARTIAL)
1da177e4
LT		 2122 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2123 else
2124 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2125
2126 if (!skb_shinfo(skb)->nr_frags) {
2127 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2128 skb->len, PCI_DMA_TODEVICE));
2129 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2130 } else {
2131 int i;
2132
2133 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2134 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2135 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2136
2137 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2138 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2139
2140 vp->tx_ring[entry].frag[i+1].addr =
2141 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2142 (void*)page_address(frag->page) + frag->page_offset,
2143 frag->size, PCI_DMA_TODEVICE));
2144
2145 if (i == skb_shinfo(skb)->nr_frags-1)
2146 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2147 else
2148 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2149 }
2150 }
2151#else
2152 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2153 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2154 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2155#endif
2156
2157 spin_lock_irqsave(&vp->lock, flags);
2158 /* Wait for the stall to complete. */
2159 issue_and_wait(dev, DownStall);
2160 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
62afe595
JL		 2161 if (ioread32(ioaddr + DownListPtr) == 0) {
2162 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1da177e4
LT		 2163 vp->queued_packet++;
2164 }
2165
2166 vp->cur_tx++;
2167 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2168 netif_stop_queue (dev);
2169 } else { /* Clear previous interrupt enable. */
2170#if defined(tx_interrupt_mitigation)
2171 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2172 * were selected, this would corrupt DN_COMPLETE. No?
2173 */
2174 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2175#endif
2176 }
62afe595 2177 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2178 spin_unlock_irqrestore(&vp->lock, flags);
2179 dev->trans_start = jiffies;
2180 return 0;
2181}
2182
2183/* The interrupt handler does all of the Rx thread work and cleans up
2184 after the Tx thread. */
2185
2186/*
2187 * This is the ISR for the vortex series chips.
2188 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2189 */
2190
2191static irqreturn_t
7d12e780 2192vortex_interrupt(int irq, void *dev_id)
1da177e4
LT		 2193{
2194 struct net_device *dev = dev_id;
2195 struct vortex_private *vp = netdev_priv(dev);
62afe595 2196 void __iomem *ioaddr;
1da177e4
LT		 2197 int status;
2198 int work_done = max_interrupt_work;
2199 int handled = 0;
2200
62afe595 2201 ioaddr = vp->ioaddr;
1da177e4
LT		 2202 spin_lock(&vp->lock);
2203
62afe595 2204 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2205
2206 if (vortex_debug > 6)
39738e16 2207 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
1da177e4
LT		 2208
2209 if ((status & IntLatch) == 0)
2210 goto handler_exit; /* No interrupt: shared IRQs cause this */
2211 handled = 1;
2212
2213 if (status & IntReq) {
2214 status |= vp->deferred;
2215 vp->deferred = 0;
2216 }
2217
2218 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2219 goto handler_exit;
2220
2221 if (vortex_debug > 4)
39738e16 2222 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2223 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2224
2225 do {
2226 if (vortex_debug > 5)
39738e16 2227 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2228 dev->name, status);
2229 if (status & RxComplete)
2230 vortex_rx(dev);
2231
2232 if (status & TxAvailable) {
2233 if (vortex_debug > 5)
39738e16 2234 pr_debug(" TX room bit was handled.\n");
1da177e4 2235 /* There's room in the FIFO for a full-sized packet. */
62afe595 2236 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1da177e4
LT		 2237 netif_wake_queue (dev);
2238 }
2239
2240 if (status & DMADone) {
62afe595
JL		 2241 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2242 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1da177e4
LT		 2243 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2244 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
62afe595 2245 if (ioread16(ioaddr + TxFree) > 1536) {
1da177e4
LT		 2246 /*
2247 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2248 * insufficient FIFO room, the TxAvailable test will succeed and call
2249 * netif_wake_queue()
2250 */
2251 netif_wake_queue(dev);
2252 } else { /* Interrupt when FIFO has room for max-sized packet. */
62afe595 2253 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1da177e4
LT		 2254 netif_stop_queue(dev);
2255 }
2256 }
2257 }
2258 /* Check for all uncommon interrupts at once. */
2259 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2260 if (status == 0xffff)
2261 break;
2262 vortex_error(dev, status);
2263 }
2264
2265 if (--work_done < 0) {
39738e16
AB		 2266 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2267 dev->name, status);
1da177e4
LT		 2268 /* Disable all pending interrupts. */
2269 do {
2270 vp->deferred |= status;
62afe595 2271 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2272 ioaddr + EL3_CMD);
62afe595
JL		 2273 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2274 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2275 /* The timer will reenable interrupts. */
2276 mod_timer(&vp->timer, jiffies + 1*HZ);
2277 break;
2278 }
2279 /* Acknowledge the IRQ. */
62afe595
JL		 2280 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2281 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1da177e4
LT		 2282
2283 if (vortex_debug > 4)
39738e16 2284 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2285 dev->name, status);
2286handler_exit:
2287 spin_unlock(&vp->lock);
2288 return IRQ_RETVAL(handled);
2289}
2290
2291/*
2292 * This is the ISR for the boomerang series chips.
2293 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2294 */
2295
2296static irqreturn_t
7d12e780 2297boomerang_interrupt(int irq, void *dev_id)
1da177e4
LT		 2298{
2299 struct net_device *dev = dev_id;
2300 struct vortex_private *vp = netdev_priv(dev);
62afe595 2301 void __iomem *ioaddr;
1da177e4
LT		 2302 int status;
2303 int work_done = max_interrupt_work;
2304
62afe595 2305 ioaddr = vp->ioaddr;
1da177e4
LT		 2306
2307 /*
2308 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2309 * and boomerang_start_xmit
2310 */
2311 spin_lock(&vp->lock);
2312
62afe595 2313 status = ioread16(ioaddr + EL3_STATUS);
1da177e4
LT		 2314
2315 if (vortex_debug > 6)
39738e16 2316 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
1da177e4
LT		 2317
2318 if ((status & IntLatch) == 0)
2319 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2320
2321 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2322 if (vortex_debug > 1)
39738e16 2323 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
1da177e4
LT		 2324 goto handler_exit;
2325 }
2326
2327 if (status & IntReq) {
2328 status |= vp->deferred;
2329 vp->deferred = 0;
2330 }
2331
2332 if (vortex_debug > 4)
39738e16 2333 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
62afe595 2334 dev->name, status, ioread8(ioaddr + Timer));
1da177e4
LT		 2335 do {
2336 if (vortex_debug > 5)
39738e16 2337 pr_debug("%s: In interrupt loop, status %4.4x.\n",
1da177e4
LT		 2338 dev->name, status);
2339 if (status & UpComplete) {
62afe595 2340 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
1da177e4 2341 if (vortex_debug > 5)
39738e16 2342 pr_debug("boomerang_interrupt->boomerang_rx\n");
1da177e4
LT		 2343 boomerang_rx(dev);
2344 }
2345
2346 if (status & DownComplete) {
2347 unsigned int dirty_tx = vp->dirty_tx;
2348
62afe595 2349 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
1da177e4
LT		 2350 while (vp->cur_tx - dirty_tx > 0) {
2351 int entry = dirty_tx % TX_RING_SIZE;
2352#if 1 /* AKPM: the latter is faster, but cyclone-only */
62afe595 2353 if (ioread32(ioaddr + DownListPtr) ==
1da177e4
LT		 2354 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2355 break; /* It still hasn't been processed. */
2356#else
2357 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2358 break; /* It still hasn't been processed. */
2359#endif
6aa20a22 2360
1da177e4
LT		 2361 if (vp->tx_skbuff[entry]) {
2362 struct sk_buff *skb = vp->tx_skbuff[entry];
6aa20a22 2363#if DO_ZEROCOPY
1da177e4
LT		 2364 int i;
2365 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2366 pci_unmap_single(VORTEX_PCI(vp),
2367 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2368 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2369 PCI_DMA_TODEVICE);
2370#else
2371 pci_unmap_single(VORTEX_PCI(vp),
2372 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2373#endif
2374 dev_kfree_skb_irq(skb);
2375 vp->tx_skbuff[entry] = NULL;
2376 } else {
39738e16 2377 pr_debug("boomerang_interrupt: no skb!\n");
1da177e4 2378 }
1daad055 2379 /* dev->stats.tx_packets++; Counted below. */
1da177e4
LT		 2380 dirty_tx++;
2381 }
2382 vp->dirty_tx = dirty_tx;
2383 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2384 if (vortex_debug > 6)
39738e16 2385 pr_debug("boomerang_interrupt: wake queue\n");
1da177e4
LT		 2386 netif_wake_queue (dev);
2387 }
2388 }
2389
2390 /* Check for all uncommon interrupts at once. */
2391 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2392 vortex_error(dev, status);
2393
2394 if (--work_done < 0) {
39738e16
AB		 2395 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2396 dev->name, status);
1da177e4
LT		 2397 /* Disable all pending interrupts. */
2398 do {
2399 vp->deferred |= status;
62afe595 2400 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
1da177e4 2401 ioaddr + EL3_CMD);
62afe595
JL		 2402 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2403 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
1da177e4
LT		 2404 /* The timer will reenable interrupts. */
2405 mod_timer(&vp->timer, jiffies + 1*HZ);
2406 break;
2407 }
2408 /* Acknowledge the IRQ. */
62afe595 2409 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1da177e4 2410 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
62afe595 2411 iowrite32(0x8000, vp->cb_fn_base + 4);
1da177e4 2412
62afe595 2413 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
1da177e4
LT		 2414
2415 if (vortex_debug > 4)
39738e16 2416 pr_debug("%s: exiting interrupt, status %4.4x.\n",
1da177e4
LT		 2417 dev->name, status);
2418handler_exit:
2419 spin_unlock(&vp->lock);
2420 return IRQ_HANDLED;
2421}
2422
2423static int vortex_rx(struct net_device *dev)
2424{
2425 struct vortex_private *vp = netdev_priv(dev);
62afe595 2426 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2427 int i;
2428 short rx_status;
2429
2430 if (vortex_debug > 5)
39738e16 2431 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
62afe595
JL		 2432 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2433 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
1da177e4 2434 if (rx_status & 0x4000) { /* Error, update stats. */
62afe595 2435 unsigned char rx_error = ioread8(ioaddr + RxErrors);
1da177e4 2436 if (vortex_debug > 2)
39738e16 2437 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2438 dev->stats.rx_errors++;
2439 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2440 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2441 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2442 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2443 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2444 } else {
2445 /* The packet length: up to 4.5K!. */
2446 int pkt_len = rx_status & 0x1fff;
2447 struct sk_buff *skb;
2448
2449 skb = dev_alloc_skb(pkt_len + 5);
2450 if (vortex_debug > 4)
39738e16 2451 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2452 pkt_len, rx_status);
2453 if (skb != NULL) {
1da177e4
LT		 2454 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2455 /* 'skb_put()' points to the start of sk_buff data area. */
2456 if (vp->bus_master &&
62afe595 2457 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
1da177e4
LT		 2458 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2459 pkt_len, PCI_DMA_FROMDEVICE);
62afe595
JL		 2460 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2461 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2462 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2463 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
1da177e4
LT		 2464 ;
2465 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2466 } else {
62afe595
JL		 2467 ioread32_rep(ioaddr + RX_FIFO,
2468 skb_put(skb, pkt_len),
2469 (pkt_len + 3) >> 2);
1da177e4 2470 }
62afe595 2471 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
1da177e4
LT		 2472 skb->protocol = eth_type_trans(skb, dev);
2473 netif_rx(skb);
1daad055 2474 dev->stats.rx_packets++;
1da177e4
LT		 2475 /* Wait a limited time to go to next packet. */
2476 for (i = 200; i >= 0; i--)
62afe595 2477 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1da177e4
LT		 2478 break;
2479 continue;
2480 } else if (vortex_debug > 0)
39738e16
AB		 2481 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2482 dev->name, pkt_len);
1daad055 2483 dev->stats.rx_dropped++;
1da177e4 2484 }
1da177e4
LT		 2485 issue_and_wait(dev, RxDiscard);
2486 }
2487
2488 return 0;
2489}
2490
2491static int
2492boomerang_rx(struct net_device *dev)
2493{
2494 struct vortex_private *vp = netdev_priv(dev);
2495 int entry = vp->cur_rx % RX_RING_SIZE;
62afe595 2496 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2497 int rx_status;
2498 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2499
2500 if (vortex_debug > 5)
39738e16 2501 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
1da177e4
LT		 2502
2503 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2504 if (--rx_work_limit < 0)
2505 break;
2506 if (rx_status & RxDError) { /* Error, update stats. */
2507 unsigned char rx_error = rx_status >> 16;
2508 if (vortex_debug > 2)
39738e16 2509 pr_debug(" Rx error: status %2.2x.\n", rx_error);
1daad055
PZ		 2510 dev->stats.rx_errors++;
2511 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2512 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2513 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2514 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2515 if (rx_error & 0x10) dev->stats.rx_length_errors++;
1da177e4
LT		 2516 } else {
2517 /* The packet length: up to 4.5K!. */
2518 int pkt_len = rx_status & 0x1fff;
2519 struct sk_buff *skb;
2520 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2521
2522 if (vortex_debug > 4)
39738e16 2523 pr_debug("Receiving packet size %d status %4.4x.\n",
1da177e4
LT		 2524 pkt_len, rx_status);
2525
2526 /* Check if the packet is long enough to just accept without
2527 copying to a properly sized skbuff. */
cc2d6596 2528 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 2529 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2530 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2531 /* 'skb_put()' points to the start of sk_buff data area. */
2532 memcpy(skb_put(skb, pkt_len),
689be439 2533 vp->rx_skbuff[entry]->data,
1da177e4
LT		 2534 pkt_len);
2535 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2536 vp->rx_copy++;
2537 } else {
2538 /* Pass up the skbuff already on the Rx ring. */
2539 skb = vp->rx_skbuff[entry];
2540 vp->rx_skbuff[entry] = NULL;
2541 skb_put(skb, pkt_len);
2542 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2543 vp->rx_nocopy++;
2544 }
2545 skb->protocol = eth_type_trans(skb, dev);
2546 { /* Use hardware checksum info. */
2547 int csum_bits = rx_status & 0xee000000;
2548 if (csum_bits &&
2549 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2550 csum_bits == (IPChksumValid | UDPChksumValid))) {
2551 skb->ip_summed = CHECKSUM_UNNECESSARY;
2552 vp->rx_csumhits++;
2553 }
2554 }
2555 netif_rx(skb);
1daad055 2556 dev->stats.rx_packets++;
1da177e4
LT		 2557 }
2558 entry = (++vp->cur_rx) % RX_RING_SIZE;
2559 }
2560 /* Refill the Rx ring buffers. */
2561 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2562 struct sk_buff *skb;
2563 entry = vp->dirty_rx % RX_RING_SIZE;
2564 if (vp->rx_skbuff[entry] == NULL) {
9a5d3414 2565 skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
1da177e4
LT		 2566 if (skb == NULL) {
2567 static unsigned long last_jif;
ff5688ae 2568 if (time_after(jiffies, last_jif + 10 * HZ)) {
39738e16 2569 pr_warning("%s: memory shortage\n", dev->name);
1da177e4
LT		 2570 last_jif = jiffies;
2571 }
2572 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2573 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2574 break; /* Bad news! */
2575 }
9a5d3414
SH		 2576
2577 skb_reserve(skb, NET_IP_ALIGN);
689be439 2578 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1da177e4
LT		 2579 vp->rx_skbuff[entry] = skb;
2580 }
2581 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
62afe595 2582 iowrite16(UpUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2583 }
2584 return 0;
2585}
2586
2587/*
2588 * If we've hit a total OOM refilling the Rx ring we poll once a second
2589 * for some memory. Otherwise there is no way to restart the rx process.
2590 */
2591static void
2592rx_oom_timer(unsigned long arg)
2593{
2594 struct net_device *dev = (struct net_device *)arg;
2595 struct vortex_private *vp = netdev_priv(dev);
2596
2597 spin_lock_irq(&vp->lock);
2598 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2599 boomerang_rx(dev);
2600 if (vortex_debug > 1) {
39738e16 2601 pr_debug("%s: rx_oom_timer %s\n", dev->name,
1da177e4
LT		 2602 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2603 }
2604 spin_unlock_irq(&vp->lock);
2605}
2606
2607static void
2608vortex_down(struct net_device *dev, int final_down)
2609{
2610 struct vortex_private *vp = netdev_priv(dev);
62afe595 2611 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2612
2613 netif_stop_queue (dev);
2614
2615 del_timer_sync(&vp->rx_oom_timer);
2616 del_timer_sync(&vp->timer);
2617
1daad055 2618 /* Turn off statistics ASAP. We update dev->stats below. */
62afe595 2619 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2620
2621 /* Disable the receiver and transmitter. */
62afe595
JL		 2622 iowrite16(RxDisable, ioaddr + EL3_CMD);
2623 iowrite16(TxDisable, ioaddr + EL3_CMD);
1da177e4
LT		 2624
2625 /* Disable receiving 802.1q tagged frames */
2626 set_8021q_mode(dev, 0);
2627
2628 if (dev->if_port == XCVR_10base2)
2629 /* Turn off thinnet power. Green! */
62afe595 2630 iowrite16(StopCoax, ioaddr + EL3_CMD);
1da177e4 2631
62afe595 2632 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1da177e4
LT		 2633
2634 update_stats(ioaddr, dev);
2635 if (vp->full_bus_master_rx)
62afe595 2636 iowrite32(0, ioaddr + UpListPtr);
1da177e4 2637 if (vp->full_bus_master_tx)
62afe595 2638 iowrite32(0, ioaddr + DownListPtr);
1da177e4
LT		 2639
2640 if (final_down && VORTEX_PCI(vp)) {
3c8fad18 2641 vp->pm_state_valid = 1;
1da177e4
LT		 2642 pci_save_state(VORTEX_PCI(vp));
2643 acpi_set_WOL(dev);
2644 }
2645}
2646
2647static int
2648vortex_close(struct net_device *dev)
2649{
2650 struct vortex_private *vp = netdev_priv(dev);
62afe595 2651 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2652 int i;
2653
2654 if (netif_device_present(dev))
2655 vortex_down(dev, 1);
2656
2657 if (vortex_debug > 1) {
39738e16 2658 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
62afe595 2659 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
39738e16 2660 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
1da177e4
LT		 2661 " tx_queued %d Rx pre-checksummed %d.\n",
2662 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2663 }
2664
2665#if DO_ZEROCOPY
32fb5f06
JL		 2666 if (vp->rx_csumhits &&
2667 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2668 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
39738e16 2669 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
1da177e4
LT		 2670 }
2671#endif
6aa20a22 2672
1da177e4
LT		 2673 free_irq(dev->irq, dev);
2674
2675 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2676 for (i = 0; i < RX_RING_SIZE; i++)
2677 if (vp->rx_skbuff[i]) {
2678 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2679 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2680 dev_kfree_skb(vp->rx_skbuff[i]);
2681 vp->rx_skbuff[i] = NULL;
2682 }
2683 }
2684 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2685 for (i = 0; i < TX_RING_SIZE; i++) {
2686 if (vp->tx_skbuff[i]) {
2687 struct sk_buff *skb = vp->tx_skbuff[i];
2688#if DO_ZEROCOPY
2689 int k;
2690
2691 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2692 pci_unmap_single(VORTEX_PCI(vp),
2693 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2694 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2695 PCI_DMA_TODEVICE);
2696#else
2697 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2698#endif
2699 dev_kfree_skb(skb);
2700 vp->tx_skbuff[i] = NULL;
2701 }
2702 }
2703 }
2704
2705 return 0;
2706}
2707
2708static void
2709dump_tx_ring(struct net_device *dev)
2710{
2711 if (vortex_debug > 0) {
2712 struct vortex_private *vp = netdev_priv(dev);
62afe595 2713 void __iomem *ioaddr = vp->ioaddr;
6aa20a22 2714
1da177e4
LT		 2715 if (vp->full_bus_master_tx) {
2716 int i;
62afe595 2717 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
1da177e4 2718
39738e16 2719 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
1da177e4
LT		 2720 vp->full_bus_master_tx,
2721 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2722 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
39738e16 2723 pr_err(" Transmit list %8.8x vs. %p.\n",
62afe595 2724 ioread32(ioaddr + DownListPtr),
1da177e4
LT		 2725 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2726 issue_and_wait(dev, DownStall);
2727 for (i = 0; i < TX_RING_SIZE; i++) {
0cb13536
JD		 2728 unsigned int length;
2729
1da177e4 2730#if DO_ZEROCOPY
0cb13536 2731 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
1da177e4 2732#else
0cb13536 2733 length = le32_to_cpu(vp->tx_ring[i].length);
1da177e4 2734#endif
0cb13536
JD		 2735 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2736 i, &vp->tx_ring[i], length,
1da177e4
LT		 2737 le32_to_cpu(vp->tx_ring[i].status));
2738 }
2739 if (!stalled)
62afe595 2740 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1da177e4
LT		 2741 }
2742 }
2743}
2744
2745static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2746{
2747 struct vortex_private *vp = netdev_priv(dev);
62afe595 2748 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2749 unsigned long flags;
2750
2751 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2752 spin_lock_irqsave (&vp->lock, flags);
62afe595 2753 update_stats(ioaddr, dev);
1da177e4
LT		 2754 spin_unlock_irqrestore (&vp->lock, flags);
2755 }
1daad055 2756 return &dev->stats;
1da177e4
LT		 2757}
2758
2759/* Update statistics.
2760 Unlike with the EL3 we need not worry about interrupts changing
2761 the window setting from underneath us, but we must still guard
2762 against a race condition with a StatsUpdate interrupt updating the
2763 table. This is done by checking that the ASM (!) code generated uses
2764 atomic updates with '+='.
2765 */
62afe595 2766static void update_stats(void __iomem *ioaddr, struct net_device *dev)
1da177e4
LT		 2767{
2768 struct vortex_private *vp = netdev_priv(dev);
62afe595 2769 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2770
2771 if (old_window == 0xffff) /* Chip suspended or ejected. */
2772 return;
2773 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2774 /* Switch to the stats window, and read everything. */
2775 EL3WINDOW(6);
1daad055
PZ		 2776 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2777 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2778 dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2779 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2780 dev->stats.tx_packets += ioread8(ioaddr + 6);
2781 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
62afe595 2782 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
1da177e4
LT		 2783 /* Don't bother with register 9, an extension of registers 6&7.
2784 If we do use the 6&7 values the atomic update assumption above
2785 is invalid. */
1daad055
PZ		 2786 dev->stats.rx_bytes += ioread16(ioaddr + 10);
2787 dev->stats.tx_bytes += ioread16(ioaddr + 12);
1da177e4 2788 /* Extra stats for get_ethtool_stats() */
62afe595 2789 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
8d1d0340 2790 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
62afe595 2791 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
1da177e4 2792 EL3WINDOW(4);
62afe595 2793 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
1da177e4 2794
1daad055 2795 dev->stats.collisions = vp->xstats.tx_multiple_collisions
8d1d0340
SK		 2796 + vp->xstats.tx_single_collisions
2797 + vp->xstats.tx_max_collisions;
2798
1da177e4 2799 {
62afe595 2800 u8 up = ioread8(ioaddr + 13);
1daad055
PZ		 2801 dev->stats.rx_bytes += (up & 0x0f) << 16;
2802 dev->stats.tx_bytes += (up & 0xf0) << 12;
1da177e4
LT		 2803 }
2804
2805 EL3WINDOW(old_window >> 13);
2806 return;
2807}
2808
2809static int vortex_nway_reset(struct net_device *dev)
2810{
2811 struct vortex_private *vp = netdev_priv(dev);
62afe595 2812 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2813 unsigned long flags;
2814 int rc;
2815
2816 spin_lock_irqsave(&vp->lock, flags);
2817 EL3WINDOW(4);
2818 rc = mii_nway_restart(&vp->mii);
2819 spin_unlock_irqrestore(&vp->lock, flags);
2820 return rc;
2821}
2822
1da177e4
LT		 2823static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2824{
2825 struct vortex_private *vp = netdev_priv(dev);
62afe595 2826 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2827 unsigned long flags;
2828 int rc;
2829
2830 spin_lock_irqsave(&vp->lock, flags);
2831 EL3WINDOW(4);
2832 rc = mii_ethtool_gset(&vp->mii, cmd);
2833 spin_unlock_irqrestore(&vp->lock, flags);
2834 return rc;
2835}
2836
2837static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2838{
2839 struct vortex_private *vp = netdev_priv(dev);
62afe595 2840 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2841 unsigned long flags;
2842 int rc;
2843
2844 spin_lock_irqsave(&vp->lock, flags);
2845 EL3WINDOW(4);
2846 rc = mii_ethtool_sset(&vp->mii, cmd);
2847 spin_unlock_irqrestore(&vp->lock, flags);
2848 return rc;
2849}
2850
2851static u32 vortex_get_msglevel(struct net_device *dev)
2852{
2853 return vortex_debug;
2854}
2855
2856static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2857{
2858 vortex_debug = dbg;
2859}
2860
b9f2c044 2861static int vortex_get_sset_count(struct net_device *dev, int sset)
1da177e4 2862{
b9f2c044
JG		 2863 switch (sset) {
2864 case ETH_SS_STATS:
2865 return VORTEX_NUM_STATS;
2866 default:
2867 return -EOPNOTSUPP;
2868 }
1da177e4
LT		 2869}
2870
2871static void vortex_get_ethtool_stats(struct net_device *dev,
2872 struct ethtool_stats *stats, u64 *data)
2873{
2874 struct vortex_private *vp = netdev_priv(dev);
62afe595 2875 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2876 unsigned long flags;
2877
2878 spin_lock_irqsave(&vp->lock, flags);
62afe595 2879 update_stats(ioaddr, dev);
1da177e4
LT		 2880 spin_unlock_irqrestore(&vp->lock, flags);
2881
2882 data[0] = vp->xstats.tx_deferred;
8d1d0340
SK		 2883 data[1] = vp->xstats.tx_max_collisions;
2884 data[2] = vp->xstats.tx_multiple_collisions;
2885 data[3] = vp->xstats.tx_single_collisions;
2886 data[4] = vp->xstats.rx_bad_ssd;
1da177e4
LT		 2887}
2888
2889
2890static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2891{
2892 switch (stringset) {
2893 case ETH_SS_STATS:
2894 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2895 break;
2896 default:
2897 WARN_ON(1);
2898 break;
2899 }
2900}
2901
2902static void vortex_get_drvinfo(struct net_device *dev,
2903 struct ethtool_drvinfo *info)
2904{
2905 struct vortex_private *vp = netdev_priv(dev);
2906
2907 strcpy(info->driver, DRV_NAME);
1da177e4
LT		 2908 if (VORTEX_PCI(vp)) {
2909 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2910 } else {
2911 if (VORTEX_EISA(vp))
86de79b6 2912 strcpy(info->bus_info, dev_name(vp->gendev));
1da177e4
LT		 2913 else
2914 sprintf(info->bus_info, "EISA 0x%lx %d",
2915 dev->base_addr, dev->irq);
2916 }
2917}
2918
7282d491 2919static const struct ethtool_ops vortex_ethtool_ops = {
1da177e4
LT		 2920 .get_drvinfo = vortex_get_drvinfo,
2921 .get_strings = vortex_get_strings,
2922 .get_msglevel = vortex_get_msglevel,
2923 .set_msglevel = vortex_set_msglevel,
2924 .get_ethtool_stats = vortex_get_ethtool_stats,
b9f2c044 2925 .get_sset_count = vortex_get_sset_count,
1da177e4
LT		 2926 .get_settings = vortex_get_settings,
2927 .set_settings = vortex_set_settings,
373a6887 2928 .get_link = ethtool_op_get_link,
1da177e4
LT		 2929 .nway_reset = vortex_nway_reset,
2930};
2931
2932#ifdef CONFIG_PCI
2933/*
2934 * Must power the device up to do MDIO operations
2935 */
2936static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2937{
2938 int err;
2939 struct vortex_private *vp = netdev_priv(dev);
62afe595 2940 void __iomem *ioaddr = vp->ioaddr;
1da177e4 2941 unsigned long flags;
cc2d6596 2942 pci_power_t state = 0;
1da177e4
LT		 2943
2944 if(VORTEX_PCI(vp))
2945 state = VORTEX_PCI(vp)->current_state;
2946
2947 /* The kernel core really should have pci_get_power_state() */
2948
2949 if(state != 0)
2950 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2951 spin_lock_irqsave(&vp->lock, flags);
2952 EL3WINDOW(4);
2953 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2954 spin_unlock_irqrestore(&vp->lock, flags);
2955 if(state != 0)
2956 pci_set_power_state(VORTEX_PCI(vp), state);
2957
2958 return err;
2959}
2960#endif
2961
2962
2963/* Pre-Cyclone chips have no documented multicast filter, so the only
2964 multicast setting is to receive all multicast frames. At least
2965 the chip has a very clean way to set the mode, unlike many others. */
2966static void set_rx_mode(struct net_device *dev)
2967{
62afe595
JL		 2968 struct vortex_private *vp = netdev_priv(dev);
2969 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 2970 int new_mode;
2971
2972 if (dev->flags & IFF_PROMISC) {
d5b20697 2973 if (vortex_debug > 3)
39738e16 2974 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
1da177e4
LT		 2975 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2976 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2977 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2978 } else
2979 new_mode = SetRxFilter | RxStation | RxBroadcast;
2980
62afe595 2981 iowrite16(new_mode, ioaddr + EL3_CMD);
1da177e4
LT		 2982}
2983
2984#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2985/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2986 Note that this must be done after each RxReset due to some backwards
2987 compatibility logic in the Cyclone and Tornado ASICs */
2988
2989/* The Ethernet Type used for 802.1q tagged frames */
2990#define VLAN_ETHER_TYPE 0x8100
2991
2992static void set_8021q_mode(struct net_device *dev, int enable)
2993{
2994 struct vortex_private *vp = netdev_priv(dev);
62afe595
JL		 2995 void __iomem *ioaddr = vp->ioaddr;
2996 int old_window = ioread16(ioaddr + EL3_CMD);
1da177e4
LT		 2997 int mac_ctrl;
2998
2999 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3000 /* cyclone and tornado chipsets can recognize 802.1q
3001 * tagged frames and treat them correctly */
3002
3003 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3004 if (enable)
3005 max_pkt_size += 4; /* 802.1Q VLAN tag */
3006
3007 EL3WINDOW(3);
62afe595 3008 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
1da177e4
LT		 3009
3010 /* set VlanEtherType to let the hardware checksumming
3011 treat tagged frames correctly */
3012 EL3WINDOW(7);
62afe595 3013 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
1da177e4
LT		 3014 } else {
3015 /* on older cards we have to enable large frames */
3016
3017 vp->large_frames = dev->mtu > 1500 || enable;
3018
3019 EL3WINDOW(3);
62afe595 3020 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3021 if (vp->large_frames)
3022 mac_ctrl |= 0x40;
3023 else
3024 mac_ctrl &= ~0x40;
62afe595 3025 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
1da177e4
LT		 3026 }
3027
3028 EL3WINDOW(old_window);
3029}
3030#else
3031
3032static void set_8021q_mode(struct net_device *dev, int enable)
3033{
3034}
3035
3036
3037#endif
3038
3039/* MII transceiver control section.
3040 Read and write the MII registers using software-generated serial
3041 MDIO protocol. See the MII specifications or DP83840A data sheet
3042 for details. */
3043
3044/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3045 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3046 "overclocking" issues. */
62afe595 3047#define mdio_delay() ioread32(mdio_addr)
1da177e4
LT		 3048
3049#define MDIO_SHIFT_CLK 0x01
3050#define MDIO_DIR_WRITE 0x04
3051#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3052#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3053#define MDIO_DATA_READ 0x02
3054#define MDIO_ENB_IN 0x00
3055
3056/* Generate the preamble required for initial synchronization and
3057 a few older transceivers. */
62afe595 3058static void mdio_sync(void __iomem *ioaddr, int bits)
1da177e4 3059{
62afe595 3060 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3061
3062 /* Establish sync by sending at least 32 logic ones. */
3063 while (-- bits >= 0) {
62afe595 3064 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
1da177e4 3065 mdio_delay();
62afe595 3066 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3067 mdio_delay();
3068 }
3069}
3070
3071static int mdio_read(struct net_device *dev, int phy_id, int location)
3072{
3073 int i;
62afe595
JL		 3074 struct vortex_private *vp = netdev_priv(dev);
3075 void __iomem *ioaddr = vp->ioaddr;
1da177e4
LT		 3076 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3077 unsigned int retval = 0;
62afe595 3078 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3079
3080 if (mii_preamble_required)
3081 mdio_sync(ioaddr, 32);
3082
3083 /* Shift the read command bits out. */
3084 for (i = 14; i >= 0; i--) {
3085 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3086 iowrite16(dataval, mdio_addr);
1da177e4 3087 mdio_delay();
62afe595 3088 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3089 mdio_delay();
3090 }
3091 /* Read the two transition, 16 data, and wire-idle bits. */
3092 for (i = 19; i > 0; i--) {
62afe595 3093 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3094 mdio_delay();
62afe595
JL		 3095 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3096 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3097 mdio_delay();
3098 }
3099 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3100}
3101
3102static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3103{
62afe595
JL		 3104 struct vortex_private *vp = netdev_priv(dev);
3105 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3106 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
62afe595 3107 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
1da177e4
LT		 3108 int i;
3109
3110 if (mii_preamble_required)
3111 mdio_sync(ioaddr, 32);
3112
3113 /* Shift the command bits out. */
3114 for (i = 31; i >= 0; i--) {
3115 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
62afe595 3116 iowrite16(dataval, mdio_addr);
1da177e4 3117 mdio_delay();
62afe595 3118 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3119 mdio_delay();
3120 }
3121 /* Leave the interface idle. */
3122 for (i = 1; i >= 0; i--) {
62afe595 3123 iowrite16(MDIO_ENB_IN, mdio_addr);
1da177e4 3124 mdio_delay();
62afe595 3125 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
1da177e4
LT		 3126 mdio_delay();
3127 }
3128 return;
3129}
a880c4cd 3130
1da177e4
LT		 3131/* ACPI: Advanced Configuration and Power Interface. */
3132/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3133static void acpi_set_WOL(struct net_device *dev)
3134{
3135 struct vortex_private *vp = netdev_priv(dev);
62afe595 3136 void __iomem *ioaddr = vp->ioaddr;
1da177e4 3137
c17931c5
SK		 3138 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3139
1da177e4
LT		 3140 if (vp->enable_wol) {
3141 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3142 EL3WINDOW(7);
62afe595 3143 iowrite16(2, ioaddr + 0x0c);
1da177e4 3144 /* The RxFilter must accept the WOL frames. */
62afe595
JL		 3145 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3146 iowrite16(RxEnable, ioaddr + EL3_CMD);
1da177e4 3147
1a1769f3 3148 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
39738e16 3149 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
1a1769f3
SK		 3150
3151 vp->enable_wol = 0;
3152 return;
3153 }
3c8fad18
DR		 3154
3155 /* Change the power state to D3; RxEnable doesn't take effect. */
3156 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
1da177e4 3157 }
1da177e4
LT		 3158}
3159
3160
a880c4cd 3161static void __devexit vortex_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3162{
3163 struct net_device *dev = pci_get_drvdata(pdev);
3164 struct vortex_private *vp;
3165
3166 if (!dev) {
39738e16 3167 pr_err("vortex_remove_one called for Compaq device!\n");
1da177e4
LT		 3168 BUG();
3169 }
3170
3171 vp = netdev_priv(dev);
3172
62afe595
JL		 3173 if (vp->cb_fn_base)
3174 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3175
1da177e4
LT		 3176 unregister_netdev(dev);
3177
3178 if (VORTEX_PCI(vp)) {
3179 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3180 if (vp->pm_state_valid)
3181 pci_restore_state(VORTEX_PCI(vp));
3182 pci_disable_device(VORTEX_PCI(vp));
3183 }
3184 /* Should really use issue_and_wait() here */
62afe595
JL		 3185 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3186 vp->ioaddr + EL3_CMD);
3187
3188 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
1da177e4
LT		 3189
3190 pci_free_consistent(pdev,
3191 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3192 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3193 vp->rx_ring,
3194 vp->rx_ring_dma);
3195 if (vp->must_free_region)
3196 release_region(dev->base_addr, vp->io_size);
3197 free_netdev(dev);
3198}
3199
3200
3201static struct pci_driver vortex_driver = {
3202 .name = "3c59x",
3203 .probe = vortex_init_one,
3204 .remove = __devexit_p(vortex_remove_one),
3205 .id_table = vortex_pci_tbl,
3206#ifdef CONFIG_PM
3207 .suspend = vortex_suspend,
3208 .resume = vortex_resume,
3209#endif
3210};
3211
3212
3213static int vortex_have_pci;
3214static int vortex_have_eisa;
3215
3216
a880c4cd 3217static int __init vortex_init(void)
1da177e4
LT		 3218{
3219 int pci_rc, eisa_rc;
3220
29917620 3221 pci_rc = pci_register_driver(&vortex_driver);
1da177e4
LT		 3222 eisa_rc = vortex_eisa_init();
3223
3224 if (pci_rc == 0)
3225 vortex_have_pci = 1;
3226 if (eisa_rc > 0)
3227 vortex_have_eisa = 1;
3228
3229 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3230}
3231
3232
a880c4cd 3233static void __exit vortex_eisa_cleanup(void)
1da177e4
LT		 3234{
3235 struct vortex_private *vp;
62afe595 3236 void __iomem *ioaddr;
1da177e4
LT		 3237
3238#ifdef CONFIG_EISA
3239 /* Take care of the EISA devices */
a880c4cd 3240 eisa_driver_unregister(&vortex_eisa_driver);
1da177e4 3241#endif
6aa20a22 3242
1da177e4 3243 if (compaq_net_device) {
454d7c9b 3244 vp = netdev_priv(compaq_net_device);
62afe595
JL		 3245 ioaddr = ioport_map(compaq_net_device->base_addr,
3246 VORTEX_TOTAL_SIZE);
1da177e4 3247
a880c4cd
SK		 3248 unregister_netdev(compaq_net_device);
3249 iowrite16(TotalReset, ioaddr + EL3_CMD);
62afe595
JL		 3250 release_region(compaq_net_device->base_addr,
3251 VORTEX_TOTAL_SIZE);
1da177e4 3252
a880c4cd 3253 free_netdev(compaq_net_device);
1da177e4
LT		 3254 }
3255}
3256
3257
a880c4cd 3258static void __exit vortex_cleanup(void)
1da177e4
LT		 3259{
3260 if (vortex_have_pci)
a880c4cd 3261 pci_unregister_driver(&vortex_driver);
1da177e4 3262 if (vortex_have_eisa)
a880c4cd 3263 vortex_eisa_cleanup();
1da177e4
LT		 3264}
3265
3266
3267module_init(vortex_init);
3268module_exit(vortex_cleanup);
Linux 6.x block layer and io_uring tree(s)