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Merge tag 'mtd/for-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
[linux-2.6-block.git] / drivers / mtd / spi-nor / core.c
CommitLineData
e9f3a2bc 1// SPDX-License-Identifier: GPL-2.0
b199489d 2/*
8eabdd1e
HS		 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
5 *
6 * Copyright (C) 2005, Intec Automation Inc.
7 * Copyright (C) 2014, Freescale Semiconductor, Inc.
b199489d
HS		 8 */
9
10#include <linux/err.h>
11#include <linux/errno.h>
893fd950 12#include <linux/delay.h>
b199489d 13#include <linux/device.h>
b199489d 14#include <linux/math64.h>
893fd950 15#include <linux/module.h>
b199489d 16#include <linux/mtd/mtd.h>
893fd950
TA		 17#include <linux/mtd/spi-nor.h>
18#include <linux/mutex.h>
b199489d 19#include <linux/of_platform.h>
b35b9a10 20#include <linux/sched/task_stack.h>
893fd950
TA		 21#include <linux/sizes.h>
22#include <linux/slab.h>
b199489d 23#include <linux/spi/flash.h>
b199489d 24
cb481b92
TA		 25#include "core.h"
26
b199489d 27/* Define max times to check status register before we give up. */
09b6a377
FS		 28
29/*
30 * For everything but full-chip erase; probably could be much smaller, but kept
31 * around for safety for now
32 */
33#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34
35/*
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
37 * for larger flash
38 */
39#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
b199489d 40
c452d498 41#define SPI_NOR_MAX_ADDR_NBYTES 4
d928a259 42
d73ee753
PY		 43#define SPI_NOR_SRST_SLEEP_MIN 200
44#define SPI_NOR_SRST_SLEEP_MAX 400
45
0e30f472
PY		 46/**
47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
48 * extension type.
49 * @nor: pointer to a 'struct spi_nor'
50 * @op: pointer to the 'struct spi_mem_op' whose properties
51 * need to be initialized.
52 *
53 * Right now, only "repeat" and "invert" are supported.
54 *
55 * Return: The opcode extension.
56 */
57static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
58 const struct spi_mem_op *op)
59{
60 switch (nor->cmd_ext_type) {
61 case SPI_NOR_EXT_INVERT:
62 return ~op->cmd.opcode;
63
64 case SPI_NOR_EXT_REPEAT:
65 return op->cmd.opcode;
66
67 default:
68 dev_err(nor->dev, "Unknown command extension type\n");
69 return 0;
70 }
71}
72
73/**
74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
75 * @nor: pointer to a 'struct spi_nor'
76 * @op: pointer to the 'struct spi_mem_op' whose properties
77 * need to be initialized.
78 * @proto: the protocol from which the properties need to be set.
79 */
80void spi_nor_spimem_setup_op(const struct spi_nor *nor,
81 struct spi_mem_op *op,
82 const enum spi_nor_protocol proto)
83{
84 u8 ext;
85
86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
87
88 if (op->addr.nbytes)
89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
90
91 if (op->dummy.nbytes)
92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
93
94 if (op->data.nbytes)
95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
96
97 if (spi_nor_protocol_is_dtr(proto)) {
98 /*
99 * SPIMEM supports mixed DTR modes, but right now we can only
100 * have all phases either DTR or STR. IOW, SPIMEM can have
101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4
102 * phases to either DTR or STR.
103 */
104 op->cmd.dtr = true;
105 op->addr.dtr = true;
106 op->dummy.dtr = true;
107 op->data.dtr = true;
108
109 /* 2 bytes per clock cycle in DTR mode. */
110 op->dummy.nbytes *= 2;
111
112 ext = spi_nor_get_cmd_ext(nor, op);
113 op->cmd.opcode = (op->cmd.opcode << 8) | ext;
114 op->cmd.nbytes = 2;
115 }
116}
117
b35b9a10 118/**
b7ad6be2
SS		 119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data
120 * transfer
b35b9a10
BB		 121 * @nor: pointer to 'struct spi_nor'
122 * @op: pointer to 'struct spi_mem_op' template for transfer
123 *
b7ad6be2
SS		 124 * If we have to use the bounce buffer, the data field in @op will be updated.
125 *
126 * Return: true if the bounce buffer is needed, false if not
b35b9a10 127 */
b7ad6be2 128static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)
b35b9a10 129{
b7ad6be2
SS		 130 /* op->data.buf.in occupies the same memory as op->data.buf.out */
131 if (object_is_on_stack(op->data.buf.in) ||
132 !virt_addr_valid(op->data.buf.in)) {
b35b9a10
BB		 133 if (op->data.nbytes > nor->bouncebuf_size)
134 op->data.nbytes = nor->bouncebuf_size;
b7ad6be2
SS		 135 op->data.buf.in = nor->bouncebuf;
136 return true;
b35b9a10
BB		 137 }
138
b7ad6be2
SS		 139 return false;
140}
b35b9a10 141
b7ad6be2
SS		 142/**
143 * spi_nor_spimem_exec_op() - execute a memory operation
144 * @nor: pointer to 'struct spi_nor'
145 * @op: pointer to 'struct spi_mem_op' template for transfer
146 *
147 * Return: 0 on success, -error otherwise.
148 */
149static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)
150{
151 int error;
b35b9a10 152
b7ad6be2
SS		 153 error = spi_mem_adjust_op_size(nor->spimem, op);
154 if (error)
155 return error;
b35b9a10 156
b7ad6be2 157 return spi_mem_exec_op(nor->spimem, op);
b35b9a10
BB		 158}
159
66cf87c6
MW		 160int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,
161 u8 *buf, size_t len)
6e1bf55d 162{
0e30f472
PY		 163 if (spi_nor_protocol_is_dtr(nor->reg_proto))
164 return -EOPNOTSUPP;
165
6e1bf55d
PY		 166 return nor->controller_ops->read_reg(nor, opcode, buf, len);
167}
168
66cf87c6
MW		 169int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
170 const u8 *buf, size_t len)
6e1bf55d 171{
0e30f472
PY		 172 if (spi_nor_protocol_is_dtr(nor->reg_proto))
173 return -EOPNOTSUPP;
174
6e1bf55d
PY		 175 return nor->controller_ops->write_reg(nor, opcode, buf, len);
176}
177
178static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)
179{
f8cd9f63 180 if (spi_nor_protocol_is_dtr(nor->reg_proto))
0e30f472
PY		 181 return -EOPNOTSUPP;
182
6e1bf55d
PY		 183 return nor->controller_ops->erase(nor, offs);
184}
185
b35b9a10
BB		 186/**
187 * spi_nor_spimem_read_data() - read data from flash's memory region via
188 * spi-mem
189 * @nor: pointer to 'struct spi_nor'
190 * @from: offset to read from
191 * @len: number of bytes to read
192 * @buf: pointer to dst buffer
193 *
194 * Return: number of bytes read successfully, -errno otherwise
195 */
196static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
197 size_t len, u8 *buf)
198{
199 struct spi_mem_op op =
0e30f472 200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
c452d498 201 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0),
0e30f472
PY		 202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
203 SPI_MEM_OP_DATA_IN(len, buf, 0));
b7ad6be2 204 bool usebouncebuf;
df5c2100 205 ssize_t nbytes;
b7ad6be2 206 int error;
b35b9a10 207
0e30f472 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto);
b35b9a10
BB		 209
210 /* convert the dummy cycles to the number of bytes */
211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
0e30f472
PY		 212 if (spi_nor_protocol_is_dtr(nor->read_proto))
213 op.dummy.nbytes *= 2;
b35b9a10 214
b7ad6be2
SS		 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op);
216
df5c2100
SS		 217 if (nor->dirmap.rdesc) {
218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,
219 op.data.nbytes, op.data.buf.in);
220 } else {
221 error = spi_nor_spimem_exec_op(nor, &op);
222 if (error)
223 return error;
224 nbytes = op.data.nbytes;
225 }
b7ad6be2 226
df5c2100
SS		 227 if (usebouncebuf && nbytes > 0)
228 memcpy(buf, op.data.buf.in, nbytes);
b7ad6be2 229
df5c2100 230 return nbytes;
b35b9a10
BB		 231}
232
233/**
234 * spi_nor_read_data() - read data from flash memory
235 * @nor: pointer to 'struct spi_nor'
236 * @from: offset to read from
237 * @len: number of bytes to read
238 * @buf: pointer to dst buffer
239 *
240 * Return: number of bytes read successfully, -errno otherwise
241 */
cb481b92 242ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)
b35b9a10
BB		 243{
244 if (nor->spimem)
245 return spi_nor_spimem_read_data(nor, from, len, buf);
246
45397787 247 return nor->controller_ops->read(nor, from, len, buf);
b35b9a10
BB		 248}
249
250/**
251 * spi_nor_spimem_write_data() - write data to flash memory via
252 * spi-mem
253 * @nor: pointer to 'struct spi_nor'
254 * @to: offset to write to
255 * @len: number of bytes to write
256 * @buf: pointer to src buffer
257 *
258 * Return: number of bytes written successfully, -errno otherwise
259 */
260static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
261 size_t len, const u8 *buf)
262{
263 struct spi_mem_op op =
0e30f472 264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
c452d498 265 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0),
b35b9a10 266 SPI_MEM_OP_NO_DUMMY,
0e30f472 267 SPI_MEM_OP_DATA_OUT(len, buf, 0));
df5c2100 268 ssize_t nbytes;
b7ad6be2 269 int error;
b35b9a10 270
b35b9a10
BB		 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
272 op.addr.nbytes = 0;
273
0e30f472
PY		 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
275
b7ad6be2
SS		 276 if (spi_nor_spimem_bounce(nor, &op))
277 memcpy(nor->bouncebuf, buf, op.data.nbytes);
278
df5c2100
SS		 279 if (nor->dirmap.wdesc) {
280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,
281 op.data.nbytes, op.data.buf.out);
282 } else {
283 error = spi_nor_spimem_exec_op(nor, &op);
284 if (error)
285 return error;
286 nbytes = op.data.nbytes;
287 }
b7ad6be2 288
df5c2100 289 return nbytes;
b35b9a10
BB		 290}
291
292/**
293 * spi_nor_write_data() - write data to flash memory
294 * @nor: pointer to 'struct spi_nor'
295 * @to: offset to write to
296 * @len: number of bytes to write
297 * @buf: pointer to src buffer
298 *
299 * Return: number of bytes written successfully, -errno otherwise
300 */
4f50e102
BB		 301ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
302 const u8 *buf)
b35b9a10
BB		 303{
304 if (nor->spimem)
305 return spi_nor_spimem_write_data(nor, to, len, buf);
306
45397787 307 return nor->controller_ops->write(nor, to, len, buf);
b35b9a10
BB		 308}
309
a604ab33
TA		 310/**
311 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or
312 * volatile.
313 * @nor: pointer to 'struct spi_nor'.
314 * @op: SPI memory operation. op->data.buf must be DMA-able.
315 * @proto: SPI protocol to use for the register operation.
316 *
317 * Return: zero on success, -errno otherwise
318 */
319int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,
320 enum spi_nor_protocol proto)
321{
322 if (!nor->spimem)
323 return -EOPNOTSUPP;
324
325 spi_nor_spimem_setup_op(nor, op, proto);
326 return spi_nor_spimem_exec_op(nor, op);
327}
328
329/**
330 * spi_nor_write_any_volatile_reg() - write any volatile register to flash
331 * memory.
332 * @nor: pointer to 'struct spi_nor'
333 * @op: SPI memory operation. op->data.buf must be DMA-able.
334 * @proto: SPI protocol to use for the register operation.
335 *
336 * Writing volatile registers are instant according to some manufacturers
337 * (Cypress, Micron) and do not need any status polling.
338 *
339 * Return: zero on success, -errno otherwise
340 */
341int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,
342 enum spi_nor_protocol proto)
343{
344 int ret;
345
346 if (!nor->spimem)
347 return -EOPNOTSUPP;
348
349 ret = spi_nor_write_enable(nor);
350 if (ret)
351 return ret;
352 spi_nor_spimem_setup_op(nor, op, proto);
353 return spi_nor_spimem_exec_op(nor, op);
354}
355
78f1ddf7
TA		 356/**
357 * spi_nor_write_enable() - Set write enable latch with Write Enable command.
358 * @nor: pointer to 'struct spi_nor'.
359 *
360 * Return: 0 on success, -errno otherwise.
502c4b0a 361 */
4f50e102 362int spi_nor_write_enable(struct spi_nor *nor)
502c4b0a 363{
d1ed88ea
TA		 364 int ret;
365
502c4b0a 366 if (nor->spimem) {
c0abb861 367 struct spi_mem_op op = SPI_NOR_WREN_OP;
502c4b0a 368
0e30f472
PY		 369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
370
d1ed88ea
TA		 371 ret = spi_mem_exec_op(nor->spimem, &op);
372 } else {
6e1bf55d
PY		 373 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,
374 NULL, 0);
502c4b0a
TA		 375 }
376
d1ed88ea
TA		 377 if (ret)
378 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);
379
380 return ret;
502c4b0a
TA		 381}
382
78f1ddf7
TA		 383/**
384 * spi_nor_write_disable() - Send Write Disable instruction to the chip.
385 * @nor: pointer to 'struct spi_nor'.
386 *
387 * Return: 0 on success, -errno otherwise.
502c4b0a 388 */
4f50e102 389int spi_nor_write_disable(struct spi_nor *nor)
502c4b0a 390{
d1ed88ea
TA		 391 int ret;
392
502c4b0a 393 if (nor->spimem) {
c0abb861 394 struct spi_mem_op op = SPI_NOR_WRDI_OP;
502c4b0a 395
0e30f472
PY		 396 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
397
d1ed88ea
TA		 398 ret = spi_mem_exec_op(nor->spimem, &op);
399 } else {
6e1bf55d
PY		 400 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,
401 NULL, 0);
502c4b0a
TA		 402 }
403
d1ed88ea
TA		 404 if (ret)
405 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);
406
407 return ret;
502c4b0a
TA		 408}
409
86b6b55f
TA		 410/**
411 * spi_nor_read_id() - Read the JEDEC ID.
412 * @nor: pointer to 'struct spi_nor'.
413 * @naddr: number of address bytes to send. Can be zero if the operation
414 * does not need to send an address.
415 * @ndummy: number of dummy bytes to send after an opcode or address. Can
416 * be zero if the operation does not require dummy bytes.
417 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID
418 * will be written.
419 * @proto: the SPI protocol for register operation.
420 *
421 * Return: 0 on success, -errno otherwise.
422 */
423int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,
424 enum spi_nor_protocol proto)
425{
426 int ret;
427
428 if (nor->spimem) {
429 struct spi_mem_op op =
430 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);
431
432 spi_nor_spimem_setup_op(nor, &op, proto);
433 ret = spi_mem_exec_op(nor->spimem, &op);
434 } else {
435 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
436 SPI_NOR_MAX_ID_LEN);
437 }
438 return ret;
439}
440
cd1718f5
TA		 441/**
442 * spi_nor_read_sr() - Read the Status Register.
443 * @nor: pointer to 'struct spi_nor'.
444 * @sr: pointer to a DMA-able buffer where the value of the
354b4129 445 * Status Register will be written. Should be at least 2 bytes.
cd1718f5
TA		 446 *
447 * Return: 0 on success, -errno otherwise.
b199489d 448 */
31ad3eff 449int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
b199489d
HS		 450{
451 int ret;
b199489d 452
b35b9a10 453 if (nor->spimem) {
c0abb861 454 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);
0e30f472 455
6c6a2b2b
PY		 456 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
457 op.addr.nbytes = nor->params->rdsr_addr_nbytes;
458 op.dummy.nbytes = nor->params->rdsr_dummy;
354b4129
PY		 459 /*
460 * We don't want to read only one byte in DTR mode. So,
461 * read 2 and then discard the second byte.
462 */
463 op.data.nbytes = 2;
6c6a2b2b
PY		 464 }
465
0e30f472 466 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
b35b9a10
BB		 467
468 ret = spi_mem_exec_op(nor->spimem, &op);
469 } else {
6e1bf55d
PY		 470 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
471 1);
b35b9a10
BB		 472 }
473
cd1718f5 474 if (ret)
f633ebe4 475 dev_dbg(nor->dev, "error %d reading SR\n", ret);
b199489d 476
cd1718f5 477 return ret;
b199489d
HS		 478}
479
b662d398
TA		 480/**
481 * spi_nor_read_cr() - Read the Configuration Register using the
482 * SPINOR_OP_RDCR (35h) command.
483 * @nor: pointer to 'struct spi_nor'
484 * @cr: pointer to a DMA-able buffer where the value of the
485 * Configuration Register will be written.
486 *
487 * Return: 0 on success, -errno otherwise.
b199489d 488 */
75386810 489int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
b199489d
HS		 490{
491 int ret;
b199489d 492
b35b9a10 493 if (nor->spimem) {
c0abb861 494 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);
0e30f472
PY		 495
496 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
b35b9a10
BB		 497
498 ret = spi_mem_exec_op(nor->spimem, &op);
499 } else {
6e1bf55d
PY		 500 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,
501 1);
b35b9a10
BB		 502 }
503
b662d398 504 if (ret)
f633ebe4 505 dev_dbg(nor->dev, "error %d reading CR\n", ret);
b199489d 506
b662d398 507 return ret;
b199489d
HS		 508}
509
78f1ddf7 510/**
d75c22f3
TA		 511 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode
512 * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by
513 * Winbond and Macronix.
78f1ddf7
TA		 514 * @nor: pointer to 'struct spi_nor'.
515 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
516 * address mode.
517 *
518 * Return: 0 on success, -errno otherwise.
519 */
d75c22f3 520int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable)
b35b9a10 521{
d1ed88ea
TA		 522 int ret;
523
b35b9a10 524 if (nor->spimem) {
c0abb861 525 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);
b35b9a10 526
0e30f472
PY		 527 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
528
d1ed88ea
TA		 529 ret = spi_mem_exec_op(nor->spimem, &op);
530 } else {
6e1bf55d
PY		 531 ret = spi_nor_controller_ops_write_reg(nor,
532 enable ? SPINOR_OP_EN4B :
533 SPINOR_OP_EX4B,
534 NULL, 0);
b35b9a10
BB		 535 }
536
d1ed88ea
TA		 537 if (ret)
538 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
539
540 return ret;
b35b9a10
BB		 541}
542
78f1ddf7 543/**
288df437
TA		 544 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using
545 * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used
546 * by ST and Micron flashes.
076aa4ea
TA		 547 * @nor: pointer to 'struct spi_nor'.
548 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
549 * address mode.
550 *
551 * Return: 0 on success, -errno otherwise.
552 */
288df437 553int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable)
076aa4ea
TA		 554{
555 int ret;
556
557 ret = spi_nor_write_enable(nor);
558 if (ret)
559 return ret;
560
d75c22f3 561 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);
076aa4ea
TA		 562 if (ret)
563 return ret;
564
565 return spi_nor_write_disable(nor);
566}
567
78f1ddf7 568/**
f1f19762
TA		 569 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using
570 * SPINOR_OP_BRWR. Typically used by Spansion flashes.
78f1ddf7
TA		 571 * @nor: pointer to 'struct spi_nor'.
572 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte
573 * address mode.
574 *
f1f19762
TA		 575 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is
576 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte
577 * address mode is active and A[30:24] bits are don’t care. Write instruction is
578 * SPINOR_OP_BRWR(17h) with 1 byte of data.
579 *
78f1ddf7
TA		 580 * Return: 0 on success, -errno otherwise.
581 */
3a4d5f4a 582int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)
b35b9a10 583{
d1ed88ea
TA		 584 int ret;
585
b35b9a10
BB		 586 nor->bouncebuf[0] = enable << 7;
587
588 if (nor->spimem) {
c0abb861 589 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);
0e30f472
PY		 590
591 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
b35b9a10 592
d1ed88ea
TA		 593 ret = spi_mem_exec_op(nor->spimem, &op);
594 } else {
6e1bf55d
PY		 595 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,
596 nor->bouncebuf, 1);
b35b9a10
BB		 597 }
598
d1ed88ea
TA		 599 if (ret)
600 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);
601
602 return ret;
b35b9a10
BB		 603}
604
78f1ddf7
TA		 605/**
606 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
607 * for new commands.
608 * @nor: pointer to 'struct spi_nor'.
609 *
b8469159 610 * Return: 1 if ready, 0 if not ready, -errno on errors.
78f1ddf7 611 */
66cf87c6 612int spi_nor_sr_ready(struct spi_nor *nor)
b199489d 613{
e9d663a2 614 int ret;
c4b3eacc 615
e9d663a2 616 ret = spi_nor_read_sr(nor, nor->bouncebuf);
cd1718f5
TA		 617 if (ret)
618 return ret;
619
cd1718f5 620 return !(nor->bouncebuf[0] & SR_WIP);
51983b7d 621}
b199489d 622
74df43b3
MR		 623/**
624 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used
625 * @nor: pointer to 'struct spi_nor'.
626 *
627 * Return: true if parallel locking is enabled, false otherwise.
628 */
629static bool spi_nor_use_parallel_locking(struct spi_nor *nor)
630{
631 return nor->flags & SNOR_F_RWW;
632}
633
634/* Locking helpers for status read operations */
635static int spi_nor_rww_start_rdst(struct spi_nor *nor)
636{
637 struct spi_nor_rww *rww = &nor->rww;
638 int ret = -EAGAIN;
639
640 mutex_lock(&nor->lock);
641
642 if (rww->ongoing_io || rww->ongoing_rd)
643 goto busy;
644
645 rww->ongoing_io = true;
646 rww->ongoing_rd = true;
647 ret = 0;
648
649busy:
650 mutex_unlock(&nor->lock);
651 return ret;
652}
653
654static void spi_nor_rww_end_rdst(struct spi_nor *nor)
655{
656 struct spi_nor_rww *rww = &nor->rww;
657
658 mutex_lock(&nor->lock);
659
660 rww->ongoing_io = false;
661 rww->ongoing_rd = false;
662
663 mutex_unlock(&nor->lock);
664}
665
666static int spi_nor_lock_rdst(struct spi_nor *nor)
667{
668 if (spi_nor_use_parallel_locking(nor))
669 return spi_nor_rww_start_rdst(nor);
670
671 return 0;
672}
673
674static void spi_nor_unlock_rdst(struct spi_nor *nor)
675{
676 if (spi_nor_use_parallel_locking(nor)) {
677 spi_nor_rww_end_rdst(nor);
678 wake_up(&nor->rww.wait);
679 }
680}
681
78f1ddf7
TA		 682/**
683 * spi_nor_ready() - Query the flash to see if it is ready for new commands.
684 * @nor: pointer to 'struct spi_nor'.
685 *
b8469159 686 * Return: 1 if ready, 0 if not ready, -errno on errors.
78f1ddf7 687 */
51983b7d
BN		 688static int spi_nor_ready(struct spi_nor *nor)
689{
74df43b3
MR		 690 int ret;
691
692 ret = spi_nor_lock_rdst(nor);
693 if (ret)
694 return 0;
695
4cf1c7bd
MW		 696 /* Flashes might override the standard routine. */
697 if (nor->params->ready)
74df43b3
MR		 698 ret = nor->params->ready(nor);
699 else
700 ret = spi_nor_sr_ready(nor);
4cf1c7bd 701
74df43b3 702 spi_nor_unlock_rdst(nor);
4cf1c7bd 703
74df43b3 704 return ret;
b199489d
HS		 705}
706
78f1ddf7
TA		 707/**
708 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the
709 * Status Register until ready, or timeout occurs.
710 * @nor: pointer to "struct spi_nor".
711 * @timeout_jiffies: jiffies to wait until timeout.
712 *
713 * Return: 0 on success, -errno otherwise.
b94ed087 714 */
09b6a377
FS		 715static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
716 unsigned long timeout_jiffies)
c14dedde 717{
718 unsigned long deadline;
a95ce92e 719 int timeout = 0, ret;
c14dedde 720
09b6a377 721 deadline = jiffies + timeout_jiffies;
c14dedde 722
a95ce92e
BN		 723 while (!timeout) {
724 if (time_after_eq(jiffies, deadline))
725 timeout = 1;
c14dedde 726
51983b7d
BN		 727 ret = spi_nor_ready(nor);
728 if (ret < 0)
729 return ret;
730 if (ret)
731 return 0;
a95ce92e
BN		 732
733 cond_resched();
734 }
735
f633ebe4 736 dev_dbg(nor->dev, "flash operation timed out\n");
c14dedde 737
738 return -ETIMEDOUT;
739}
740
78f1ddf7
TA		 741/**
742 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the
743 * flash to be ready, or timeout occurs.
744 * @nor: pointer to "struct spi_nor".
745 *
746 * Return: 0 on success, -errno otherwise.
747 */
4f50e102 748int spi_nor_wait_till_ready(struct spi_nor *nor)
09b6a377
FS		 749{
750 return spi_nor_wait_till_ready_with_timeout(nor,
751 DEFAULT_READY_WAIT_JIFFIES);
752}
753
a7a5acba
TA		 754/**
755 * spi_nor_global_block_unlock() - Unlock Global Block Protection.
756 * @nor: pointer to 'struct spi_nor'.
757 *
758 * Return: 0 on success, -errno otherwise.
759 */
760int spi_nor_global_block_unlock(struct spi_nor *nor)
761{
762 int ret;
763
764 ret = spi_nor_write_enable(nor);
765 if (ret)
766 return ret;
767
768 if (nor->spimem) {
c0abb861 769 struct spi_mem_op op = SPI_NOR_GBULK_OP;
a7a5acba
TA		 770
771 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
772
773 ret = spi_mem_exec_op(nor->spimem, &op);
774 } else {
775 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,
776 NULL, 0);
777 }
778
779 if (ret) {
780 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);
781 return ret;
782 }
783
784 return spi_nor_wait_till_ready(nor);
785}
786
6e3087a8
TA		 787/**
788 * spi_nor_write_sr() - Write the Status Register.
789 * @nor: pointer to 'struct spi_nor'.
790 * @sr: pointer to DMA-able buffer to write to the Status Register.
791 * @len: number of bytes to write to the Status Register.
792 *
793 * Return: 0 on success, -errno otherwise.
718dd9e6 794 */
31ad3eff 795int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)
718dd9e6
TA		 796{
797 int ret;
798
718dd9e6
TA		 799 ret = spi_nor_write_enable(nor);
800 if (ret)
801 return ret;
802
803 if (nor->spimem) {
c0abb861 804 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);
0e30f472
PY		 805
806 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
718dd9e6
TA		 807
808 ret = spi_mem_exec_op(nor->spimem, &op);
809 } else {
6e1bf55d
PY		 810 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,
811 len);
718dd9e6
TA		 812 }
813
814 if (ret) {
815 dev_dbg(nor->dev, "error %d writing SR\n", ret);
816 return ret;
817 }
818
819 return spi_nor_wait_till_ready(nor);
820}
821
39d1e334
TA		 822/**
823 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and
824 * ensure that the byte written match the received value.
825 * @nor: pointer to a 'struct spi_nor'.
826 * @sr1: byte value to be written to the Status Register.
827 *
828 * Return: 0 on success, -errno otherwise.
829 */
830static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)
502c4b0a
TA		 831{
832 int ret;
833
39d1e334 834 nor->bouncebuf[0] = sr1;
6e3087a8
TA		 835
836 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);
502c4b0a
TA		 837 if (ret)
838 return ret;
839
cd1718f5
TA		 840 ret = spi_nor_read_sr(nor, nor->bouncebuf);
841 if (ret)
502c4b0a
TA		 842 return ret;
843
39d1e334
TA		 844 if (nor->bouncebuf[0] != sr1) {
845 dev_dbg(nor->dev, "SR1: read back test failed\n");
846 return -EIO;
847 }
848
849 return 0;
850}
851
852/**
853 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the
854 * Status Register 2 in one shot. Ensure that the byte written in the Status
855 * Register 1 match the received value, and that the 16-bit Write did not
856 * affect what was already in the Status Register 2.
857 * @nor: pointer to a 'struct spi_nor'.
858 * @sr1: byte value to be written to the Status Register 1.
859 *
860 * Return: 0 on success, -errno otherwise.
861 */
862static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
863{
864 int ret;
865 u8 *sr_cr = nor->bouncebuf;
866 u8 cr_written;
867
868 /* Make sure we don't overwrite the contents of Status Register 2. */
869 if (!(nor->flags & SNOR_F_NO_READ_CR)) {
870 ret = spi_nor_read_cr(nor, &sr_cr[1]);
871 if (ret)
872 return ret;
f01d8155
HYW		 873 } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
874 spi_nor_get_protocol_width(nor->write_proto) == 4 &&
875 nor->params->quad_enable) {
39d1e334
TA		 876 /*
877 * If the Status Register 2 Read command (35h) is not
878 * supported, we should at least be sure we don't
879 * change the value of the SR2 Quad Enable bit.
880 *
f01d8155
HYW		 881 * When the Quad Enable method is set and the buswidth is 4, we
882 * can safely assume that the value of the QE bit is one, as a
883 * consequence of the nor->params->quad_enable() call.
39d1e334 884 *
f01d8155
HYW		 885 * According to the JESD216 revB standard, BFPT DWORDS[15],
886 * bits 22:20, the 16-bit Write Status (01h) command is
887 * available just for the cases in which the QE bit is
888 * described in SR2 at BIT(1).
39d1e334 889 */
bb2dc7f4 890 sr_cr[1] = SR2_QUAD_EN_BIT1;
39d1e334
TA		 891 } else {
892 sr_cr[1] = 0;
893 }
894
895 sr_cr[0] = sr1;
896
897 ret = spi_nor_write_sr(nor, sr_cr, 2);
898 if (ret)
899 return ret;
900
70dd83d7
CTH		 901 ret = spi_nor_read_sr(nor, sr_cr);
902 if (ret)
903 return ret;
904
905 if (sr1 != sr_cr[0]) {
906 dev_dbg(nor->dev, "SR: Read back test failed\n");
907 return -EIO;
908 }
909
39d1e334
TA		 910 if (nor->flags & SNOR_F_NO_READ_CR)
911 return 0;
912
913 cr_written = sr_cr[1];
914
915 ret = spi_nor_read_cr(nor, &sr_cr[1]);
916 if (ret)
917 return ret;
918
919 if (cr_written != sr_cr[1]) {
920 dev_dbg(nor->dev, "CR: read back test failed\n");
b24eaf5f
TA		 921 return -EIO;
922 }
923
924 return 0;
502c4b0a
TA		 925}
926
7b678c69
TA		 927/**
928 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the
929 * Configuration Register in one shot. Ensure that the byte written in the
930 * Configuration Register match the received value, and that the 16-bit Write
931 * did not affect what was already in the Status Register 1.
932 * @nor: pointer to a 'struct spi_nor'.
933 * @cr: byte value to be written to the Configuration Register.
934 *
935 * Return: 0 on success, -errno otherwise.
936 */
cad3193f 937int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)
7b678c69
TA		 938{
939 int ret;
940 u8 *sr_cr = nor->bouncebuf;
941 u8 sr_written;
942
943 /* Keep the current value of the Status Register 1. */
944 ret = spi_nor_read_sr(nor, sr_cr);
945 if (ret)
946 return ret;
947
948 sr_cr[1] = cr;
949
950 ret = spi_nor_write_sr(nor, sr_cr, 2);
951 if (ret)
952 return ret;
953
954 sr_written = sr_cr[0];
955
956 ret = spi_nor_read_sr(nor, sr_cr);
957 if (ret)
958 return ret;
959
960 if (sr_written != sr_cr[0]) {
961 dev_dbg(nor->dev, "SR: Read back test failed\n");
962 return -EIO;
963 }
964
965 if (nor->flags & SNOR_F_NO_READ_CR)
966 return 0;
967
968 ret = spi_nor_read_cr(nor, &sr_cr[1]);
969 if (ret)
970 return ret;
971
972 if (cr != sr_cr[1]) {
973 dev_dbg(nor->dev, "CR: read back test failed\n");
974 return -EIO;
975 }
976
977 return 0;
978}
979
39d1e334
TA		 980/**
981 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that
982 * the byte written match the received value without affecting other bits in the
983 * Status Register 1 and 2.
984 * @nor: pointer to a 'struct spi_nor'.
985 * @sr1: byte value to be written to the Status Register.
986 *
987 * Return: 0 on success, -errno otherwise.
988 */
8c174d15 989int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)
39d1e334
TA		 990{
991 if (nor->flags & SNOR_F_HAS_16BIT_SR)
992 return spi_nor_write_16bit_sr_and_check(nor, sr1);
993
994 return spi_nor_write_sr1_and_check(nor, sr1);
995}
996
78f1ddf7
TA		 997/**
998 * spi_nor_write_sr2() - Write the Status Register 2 using the
999 * SPINOR_OP_WRSR2 (3eh) command.
1000 * @nor: pointer to 'struct spi_nor'.
1001 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.
1002 *
1003 * Return: 0 on success, -errno otherwise.
1004 */
cc86f3e7 1005static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)
502c4b0a 1006{
d1ed88ea
TA		 1007 int ret;
1008
718dd9e6
TA		 1009 ret = spi_nor_write_enable(nor);
1010 if (ret)
1011 return ret;
1012
502c4b0a 1013 if (nor->spimem) {
c0abb861 1014 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);
0e30f472
PY		 1015
1016 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
502c4b0a 1017
d1ed88ea
TA		 1018 ret = spi_mem_exec_op(nor->spimem, &op);
1019 } else {
6e1bf55d
PY		 1020 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,
1021 sr2, 1);
502c4b0a
TA		 1022 }
1023
718dd9e6 1024 if (ret) {
d1ed88ea 1025 dev_dbg(nor->dev, "error %d writing SR2\n", ret);
718dd9e6
TA		 1026 return ret;
1027 }
d1ed88ea 1028
718dd9e6 1029 return spi_nor_wait_till_ready(nor);
502c4b0a
TA		 1030}
1031
78f1ddf7
TA		 1032/**
1033 * spi_nor_read_sr2() - Read the Status Register 2 using the
1034 * SPINOR_OP_RDSR2 (3fh) command.
1035 * @nor: pointer to 'struct spi_nor'.
1036 * @sr2: pointer to DMA-able buffer where the value of the
1037 * Status Register 2 will be written.
1038 *
1039 * Return: 0 on success, -errno otherwise.
1040 */
502c4b0a
TA		 1041static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)
1042{
d1ed88ea
TA		 1043 int ret;
1044
502c4b0a 1045 if (nor->spimem) {
c0abb861 1046 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);
0e30f472
PY		 1047
1048 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
502c4b0a 1049
d1ed88ea
TA		 1050 ret = spi_mem_exec_op(nor->spimem, &op);
1051 } else {
6e1bf55d
PY		 1052 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,
1053 1);
502c4b0a
TA		 1054 }
1055
d1ed88ea
TA		 1056 if (ret)
1057 dev_dbg(nor->dev, "error %d reading SR2\n", ret);
1058
1059 return ret;
502c4b0a
TA		 1060}
1061
78f1ddf7 1062/**
96414231 1063 * spi_nor_erase_die() - Erase the entire die.
78f1ddf7 1064 * @nor: pointer to 'struct spi_nor'.
96414231
TA		 1065 * @addr: address of the die.
1066 * @die_size: size of the die.
b199489d 1067 *
78f1ddf7 1068 * Return: 0 on success, -errno otherwise.
b199489d 1069 */
96414231 1070static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)
b199489d 1071{
96414231 1072 bool multi_die = nor->mtd.size != die_size;
d1ed88ea
TA		 1073 int ret;
1074
96414231 1075 dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10));
b199489d 1076
b35b9a10 1077 if (nor->spimem) {
96414231
TA		 1078 struct spi_mem_op op =
1079 SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,
1080 nor->addr_nbytes, addr, multi_die);
b35b9a10 1081
f8cd9f63 1082 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
0e30f472 1083
d1ed88ea
TA		 1084 ret = spi_mem_exec_op(nor->spimem, &op);
1085 } else {
96414231
TA		 1086 if (multi_die)
1087 return -EOPNOTSUPP;
1088
6e1bf55d
PY		 1089 ret = spi_nor_controller_ops_write_reg(nor,
1090 SPINOR_OP_CHIP_ERASE,
1091 NULL, 0);
b35b9a10
BB		 1092 }
1093
d1ed88ea
TA		 1094 if (ret)
1095 dev_dbg(nor->dev, "error %d erasing chip\n", ret);
1096
1097 return ret;
b199489d
HS		 1098}
1099
502c4b0a
TA		 1100static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
1101{
1102 size_t i;
1103
1104 for (i = 0; i < size; i++)
1105 if (table[i][0] == opcode)
1106 return table[i][1];
1107
1108 /* No conversion found, keep input op code. */
1109 return opcode;
1110}
1111
cb481b92 1112u8 spi_nor_convert_3to4_read(u8 opcode)
502c4b0a
TA		 1113{
1114 static const u8 spi_nor_3to4_read[][2] = {
1115 { SPINOR_OP_READ, SPINOR_OP_READ_4B },
1116 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
1117 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
1118 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
1119 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
1120 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
1121 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
1122 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
1123
1124 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
1125 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
1126 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
1127 };
1128
1129 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
1130 ARRAY_SIZE(spi_nor_3to4_read));
1131}
1132
1133static u8 spi_nor_convert_3to4_program(u8 opcode)
1134{
1135 static const u8 spi_nor_3to4_program[][2] = {
1136 { SPINOR_OP_PP, SPINOR_OP_PP_4B },
1137 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
1138 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
1139 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
1140 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
1141 };
1142
1143 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
1144 ARRAY_SIZE(spi_nor_3to4_program));
1145}
1146
1147static u8 spi_nor_convert_3to4_erase(u8 opcode)
1148{
1149 static const u8 spi_nor_3to4_erase[][2] = {
1150 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
1151 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
1152 { SPINOR_OP_SE, SPINOR_OP_SE_4B },
1153 };
1154
1155 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
1156 ARRAY_SIZE(spi_nor_3to4_erase));
1157}
1158
829ec640
TA		 1159static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)
1160{
0e164238 1161 return !!nor->params->erase_map.uniform_region.erase_mask;
829ec640
TA		 1162}
1163
502c4b0a
TA		 1164static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)
1165{
1166 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
1167 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
1168 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
1169
1170 if (!spi_nor_has_uniform_erase(nor)) {
829ec640 1171 struct spi_nor_erase_map *map = &nor->params->erase_map;
502c4b0a
TA		 1172 struct spi_nor_erase_type *erase;
1173 int i;
1174
1175 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
1176 erase = &map->erase_type[i];
1177 erase->opcode =
1178 spi_nor_convert_3to4_erase(erase->opcode);
1179 }
1180 }
1181}
1182
c154dbd2 1183static int spi_nor_prep(struct spi_nor *nor)
b199489d
HS		 1184{
1185 int ret = 0;
1186
32046347
MR		 1187 if (nor->controller_ops && nor->controller_ops->prepare)
1188 ret = nor->controller_ops->prepare(nor);
1189
c154dbd2
MR		 1190 return ret;
1191}
1192
1193static void spi_nor_unprep(struct spi_nor *nor)
1194{
1195 if (nor->controller_ops && nor->controller_ops->unprepare)
1196 nor->controller_ops->unprepare(nor);
1197}
1198
74df43b3
MR		 1199static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len,
1200 u8 *first, u8 *last)
1201{
1202 /* This is currently safe, the number of banks being very small */
1203 *first = DIV_ROUND_DOWN_ULL(start, bank_size);
1204 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size);
1205}
1206
e96d4605 1207/* Generic helpers for internal locking and serialization */
74df43b3
MR		 1208static bool spi_nor_rww_start_io(struct spi_nor *nor)
1209{
1210 struct spi_nor_rww *rww = &nor->rww;
1211 bool start = false;
1212
b199489d
HS		 1213 mutex_lock(&nor->lock);
1214
74df43b3
MR		 1215 if (rww->ongoing_io)
1216 goto busy;
1217
1218 rww->ongoing_io = true;
1219 start = true;
1220
1221busy:
1222 mutex_unlock(&nor->lock);
1223 return start;
1224}
1225
1226static void spi_nor_rww_end_io(struct spi_nor *nor)
1227{
1228 mutex_lock(&nor->lock);
1229 nor->rww.ongoing_io = false;
1230 mutex_unlock(&nor->lock);
1231}
1232
1233static int spi_nor_lock_device(struct spi_nor *nor)
1234{
1235 if (!spi_nor_use_parallel_locking(nor))
1236 return 0;
1237
1238 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor));
1239}
1240
1241static void spi_nor_unlock_device(struct spi_nor *nor)
1242{
1243 if (spi_nor_use_parallel_locking(nor)) {
1244 spi_nor_rww_end_io(nor);
1245 wake_up(&nor->rww.wait);
b199489d 1246 }
74df43b3
MR		 1247}
1248
1249/* Generic helpers for internal locking and serialization */
1250static bool spi_nor_rww_start_exclusive(struct spi_nor *nor)
1251{
1252 struct spi_nor_rww *rww = &nor->rww;
1253 bool start = false;
1254
1255 mutex_lock(&nor->lock);
1256
1257 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1258 goto busy;
1259
1260 rww->ongoing_io = true;
1261 rww->ongoing_rd = true;
1262 rww->ongoing_pe = true;
1263 start = true;
1264
1265busy:
1266 mutex_unlock(&nor->lock);
1267 return start;
1268}
1269
1270static void spi_nor_rww_end_exclusive(struct spi_nor *nor)
1271{
1272 struct spi_nor_rww *rww = &nor->rww;
1273
1274 mutex_lock(&nor->lock);
1275 rww->ongoing_io = false;
1276 rww->ongoing_rd = false;
1277 rww->ongoing_pe = false;
1278 mutex_unlock(&nor->lock);
1279}
1280
c154dbd2
MR		 1281int spi_nor_prep_and_lock(struct spi_nor *nor)
1282{
1283 int ret;
1284
1285 ret = spi_nor_prep(nor);
1286 if (ret)
1287 return ret;
1288
74df43b3
MR		 1289 if (!spi_nor_use_parallel_locking(nor))
1290 mutex_lock(&nor->lock);
1291 else
1292 ret = wait_event_killable(nor->rww.wait,
1293 spi_nor_rww_start_exclusive(nor));
b199489d 1294
b199489d
HS		 1295 return ret;
1296}
1297
4f50e102 1298void spi_nor_unlock_and_unprep(struct spi_nor *nor)
b199489d 1299{
74df43b3
MR		 1300 if (!spi_nor_use_parallel_locking(nor)) {
1301 mutex_unlock(&nor->lock);
1302 } else {
1303 spi_nor_rww_end_exclusive(nor);
1304 wake_up(&nor->rww.wait);
1305 }
32046347 1306
c154dbd2 1307 spi_nor_unprep(nor);
b199489d
HS		 1308}
1309
e96d4605 1310/* Internal locking helpers for program and erase operations */
74df43b3
MR		 1311static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)
1312{
1313 struct spi_nor_rww *rww = &nor->rww;
1314 unsigned int used_banks = 0;
1315 bool started = false;
1316 u8 first, last;
1317 int bank;
1318
1319 mutex_lock(&nor->lock);
1320
1321 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)
1322 goto busy;
1323
1324 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1325 for (bank = first; bank <= last; bank++) {
1326 if (rww->used_banks & BIT(bank))
1327 goto busy;
1328
1329 used_banks |= BIT(bank);
1330 }
1331
1332 rww->used_banks |= used_banks;
1333 rww->ongoing_pe = true;
1334 started = true;
1335
1336busy:
1337 mutex_unlock(&nor->lock);
1338 return started;
1339}
1340
1341static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len)
1342{
1343 struct spi_nor_rww *rww = &nor->rww;
1344 u8 first, last;
1345 int bank;
1346
1347 mutex_lock(&nor->lock);
1348
1349 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1350 for (bank = first; bank <= last; bank++)
1351 rww->used_banks &= ~BIT(bank);
1352
1353 rww->ongoing_pe = false;
1354
b199489d
HS		 1355 mutex_unlock(&nor->lock);
1356}
1357
e96d4605
MR		 1358static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len)
1359{
1360 int ret;
1361
1362 ret = spi_nor_prep(nor);
1363 if (ret)
1364 return ret;
1365
74df43b3
MR		 1366 if (!spi_nor_use_parallel_locking(nor))
1367 mutex_lock(&nor->lock);
1368 else
1369 ret = wait_event_killable(nor->rww.wait,
1370 spi_nor_rww_start_pe(nor, start, len));
e96d4605 1371
74df43b3 1372 return ret;
e96d4605
MR		 1373}
1374
1375static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len)
1376{
74df43b3
MR		 1377 if (!spi_nor_use_parallel_locking(nor)) {
1378 mutex_unlock(&nor->lock);
1379 } else {
1380 spi_nor_rww_end_pe(nor, start, len);
1381 wake_up(&nor->rww.wait);
1382 }
e96d4605
MR		 1383
1384 spi_nor_unprep(nor);
1385}
1386
1387/* Internal locking helpers for read operations */
74df43b3
MR		 1388static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)
1389{
1390 struct spi_nor_rww *rww = &nor->rww;
1391 unsigned int used_banks = 0;
1392 bool started = false;
1393 u8 first, last;
1394 int bank;
1395
1396 mutex_lock(&nor->lock);
1397
1398 if (rww->ongoing_io || rww->ongoing_rd)
1399 goto busy;
1400
1401 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1402 for (bank = first; bank <= last; bank++) {
1403 if (rww->used_banks & BIT(bank))
1404 goto busy;
1405
1406 used_banks |= BIT(bank);
1407 }
1408
1409 rww->used_banks |= used_banks;
1410 rww->ongoing_io = true;
1411 rww->ongoing_rd = true;
1412 started = true;
1413
1414busy:
1415 mutex_unlock(&nor->lock);
1416 return started;
1417}
1418
1419static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len)
1420{
1421 struct spi_nor_rww *rww = &nor->rww;
1422 u8 first, last;
1423 int bank;
1424
1425 mutex_lock(&nor->lock);
1426
1427 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);
1428 for (bank = first; bank <= last; bank++)
1429 nor->rww.used_banks &= ~BIT(bank);
1430
1431 rww->ongoing_io = false;
1432 rww->ongoing_rd = false;
1433
1434 mutex_unlock(&nor->lock);
1435}
1436
e96d4605
MR		 1437static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len)
1438{
1439 int ret;
1440
1441 ret = spi_nor_prep(nor);
1442 if (ret)
1443 return ret;
1444
74df43b3
MR		 1445 if (!spi_nor_use_parallel_locking(nor))
1446 mutex_lock(&nor->lock);
1447 else
1448 ret = wait_event_killable(nor->rww.wait,
1449 spi_nor_rww_start_rd(nor, start, len));
e96d4605 1450
74df43b3 1451 return ret;
e96d4605
MR		 1452}
1453
1454static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len)
1455{
74df43b3
MR		 1456 if (!spi_nor_use_parallel_locking(nor)) {
1457 mutex_unlock(&nor->lock);
1458 } else {
1459 spi_nor_rww_end_rd(nor, start, len);
1460 wake_up(&nor->rww.wait);
1461 }
e96d4605
MR		 1462
1463 spi_nor_unprep(nor);
1464}
1465
36499596
BB		 1466static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
1467{
829ec640 1468 if (!nor->params->convert_addr)
36499596
BB		 1469 return addr;
1470
829ec640 1471 return nor->params->convert_addr(nor, addr);
36499596
BB		 1472}
1473
c67cbb83
BN		 1474/*
1475 * Initiate the erasure of a single sector
1476 */
c6ec3e1e 1477int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
c67cbb83 1478{
c67cbb83
BN		 1479 int i;
1480
36499596 1481 addr = spi_nor_convert_addr(nor, addr);
e99ca98f 1482
b35b9a10
BB		 1483 if (nor->spimem) {
1484 struct spi_mem_op op =
c0abb861 1485 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
c452d498 1486 nor->addr_nbytes, addr);
b35b9a10 1487
f8cd9f63 1488 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
0e30f472 1489
b35b9a10 1490 return spi_mem_exec_op(nor->spimem, &op);
9326b4e0 1491 } else if (nor->controller_ops->erase) {
6e1bf55d 1492 return spi_nor_controller_ops_erase(nor, addr);
b35b9a10
BB		 1493 }
1494
c67cbb83
BN		 1495 /*
1496 * Default implementation, if driver doesn't have a specialized HW
1497 * control
1498 */
c452d498 1499 for (i = nor->addr_nbytes - 1; i >= 0; i--) {
f173f26a 1500 nor->bouncebuf[i] = addr & 0xff;
c67cbb83
BN		 1501 addr >>= 8;
1502 }
1503
6e1bf55d 1504 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
c452d498 1505 nor->bouncebuf, nor->addr_nbytes);
c67cbb83
BN		 1506}
1507
5390a8df
TA		 1508/**
1509 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend
1510 * @erase: pointer to a structure that describes a SPI NOR erase type
1511 * @dividend: dividend value
1512 * @remainder: pointer to u32 remainder (will be updated)
1513 *
1514 * Return: the result of the division
1515 */
1516static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,
1517 u64 dividend, u32 *remainder)
1518{
1519 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
1520 *remainder = (u32)dividend & erase->size_mask;
1521 return dividend >> erase->size_shift;
1522}
1523
1524/**
1525 * spi_nor_find_best_erase_type() - find the best erase type for the given
1526 * offset in the serial flash memory and the
1527 * number of bytes to erase. The region in
1528 * which the address fits is expected to be
1529 * provided.
1530 * @map: the erase map of the SPI NOR
1531 * @region: pointer to a structure that describes a SPI NOR erase region
1532 * @addr: offset in the serial flash memory
1533 * @len: number of bytes to erase
1534 *
1535 * Return: a pointer to the best fitted erase type, NULL otherwise.
1536 */
1537static const struct spi_nor_erase_type *
1538spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,
1539 const struct spi_nor_erase_region *region,
1540 u64 addr, u32 len)
1541{
1542 const struct spi_nor_erase_type *erase;
1543 u32 rem;
1544 int i;
5390a8df
TA		 1545
1546 /*
70670734 1547 * Erase types are ordered by size, with the smallest erase type at
5390a8df
TA		 1548 * index 0.
1549 */
1550 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
1551 /* Does the erase region support the tested erase type? */
0e164238 1552 if (!(region->erase_mask & BIT(i)))
5390a8df
TA		 1553 continue;
1554
1555 erase = &map->erase_type[i];
2ebc336b
AS		 1556 if (!erase->size)
1557 continue;
5390a8df 1558
969b2767 1559 /* Alignment is not mandatory for overlaid regions */
2865ed0e 1560 if (region->overlaid && region->size <= len)
969b2767
TK		 1561 return erase;
1562
5390a8df
TA		 1563 /* Don't erase more than what the user has asked for. */
1564 if (erase->size > len)
1565 continue;
1566
5390a8df 1567 spi_nor_div_by_erase_size(erase, addr, &rem);
c17e5c85 1568 if (!rem)
5390a8df
TA		 1569 return erase;
1570 }
1571
1572 return NULL;
1573}
1574
5390a8df
TA		 1575/**
1576 * spi_nor_init_erase_cmd() - initialize an erase command
1577 * @region: pointer to a structure that describes a SPI NOR erase region
1578 * @erase: pointer to a structure that describes a SPI NOR erase type
1579 *
1580 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)
1581 * otherwise.
1582 */
1583static struct spi_nor_erase_command *
1584spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,
1585 const struct spi_nor_erase_type *erase)
1586{
1587 struct spi_nor_erase_command *cmd;
1588
1589 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
1590 if (!cmd)
1591 return ERR_PTR(-ENOMEM);
1592
1593 INIT_LIST_HEAD(&cmd->list);
1594 cmd->opcode = erase->opcode;
1595 cmd->count = 1;
1596
2865ed0e 1597 if (region->overlaid)
5390a8df
TA		 1598 cmd->size = region->size;
1599 else
1600 cmd->size = erase->size;
1601
1602 return cmd;
1603}
1604
1605/**
1606 * spi_nor_destroy_erase_cmd_list() - destroy erase command list
1607 * @erase_list: list of erase commands
1608 */
1609static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)
1610{
1611 struct spi_nor_erase_command *cmd, *next;
1612
1613 list_for_each_entry_safe(cmd, next, erase_list, list) {
1614 list_del(&cmd->list);
1615 kfree(cmd);
1616 }
1617}
1618
1619/**
1620 * spi_nor_init_erase_cmd_list() - initialize erase command list
1621 * @nor: pointer to a 'struct spi_nor'
1622 * @erase_list: list of erase commands to be executed once we validate that the
1623 * erase can be performed
1624 * @addr: offset in the serial flash memory
1625 * @len: number of bytes to erase
1626 *
1627 * Builds the list of best fitted erase commands and verifies if the erase can
1628 * be performed.
1629 *
1630 * Return: 0 on success, -errno otherwise.
1631 */
1632static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,
1633 struct list_head *erase_list,
1634 u64 addr, u32 len)
1635{
829ec640 1636 const struct spi_nor_erase_map *map = &nor->params->erase_map;
5390a8df
TA		 1637 const struct spi_nor_erase_type *erase, *prev_erase = NULL;
1638 struct spi_nor_erase_region *region;
1639 struct spi_nor_erase_command *cmd = NULL;
1640 u64 region_end;
df6e36ed 1641 unsigned int i;
5390a8df
TA		 1642 int ret = -EINVAL;
1643
df6e36ed
TK		 1644 for (i = 0; i < map->n_regions && len; i++) {
1645 region = &map->regions[i];
1646 region_end = region->offset + region->size;
5390a8df 1647
df6e36ed
TK		 1648 while (len && addr >= region->offset && addr < region_end) {
1649 erase = spi_nor_find_best_erase_type(map, region, addr,
1650 len);
1651 if (!erase)
5390a8df 1652 goto destroy_erase_cmd_list;
5390a8df 1653
df6e36ed 1654 if (prev_erase != erase || erase->size != cmd->size ||
2865ed0e 1655 region->overlaid) {
df6e36ed
TK		 1656 cmd = spi_nor_init_erase_cmd(region, erase);
1657 if (IS_ERR(cmd)) {
1658 ret = PTR_ERR(cmd);
1659 goto destroy_erase_cmd_list;
1660 }
1661
1662 list_add_tail(&cmd->list, erase_list);
1663 } else {
1664 cmd->count++;
1665 }
5390a8df 1666
df6e36ed
TK		 1667 len -= cmd->size;
1668 addr += cmd->size;
1669 prev_erase = erase;
5390a8df 1670 }
5390a8df
TA		 1671 }
1672
1673 return 0;
1674
1675destroy_erase_cmd_list:
1676 spi_nor_destroy_erase_cmd_list(erase_list);
1677 return ret;
1678}
1679
1680/**
1681 * spi_nor_erase_multi_sectors() - perform a non-uniform erase
1682 * @nor: pointer to a 'struct spi_nor'
1683 * @addr: offset in the serial flash memory
1684 * @len: number of bytes to erase
1685 *
1686 * Build a list of best fitted erase commands and execute it once we validate
1687 * that the erase can be performed.
1688 *
1689 * Return: 0 on success, -errno otherwise.
1690 */
1691static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
1692{
1693 LIST_HEAD(erase_list);
1694 struct spi_nor_erase_command *cmd, *next;
1695 int ret;
1696
1697 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);
1698 if (ret)
1699 return ret;
1700
1701 list_for_each_entry_safe(cmd, next, &erase_list, list) {
1702 nor->erase_opcode = cmd->opcode;
1703 while (cmd->count) {
8758888c
TA		 1704 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",
1705 cmd->size, cmd->opcode, cmd->count);
1706
74df43b3 1707 ret = spi_nor_lock_device(nor);
bce679e5
TA		 1708 if (ret)
1709 goto destroy_erase_cmd_list;
5390a8df 1710
74df43b3
MR		 1711 ret = spi_nor_write_enable(nor);
1712 if (ret) {
1713 spi_nor_unlock_device(nor);
1714 goto destroy_erase_cmd_list;
1715 }
1716
5390a8df 1717 ret = spi_nor_erase_sector(nor, addr);
74df43b3 1718 spi_nor_unlock_device(nor);
5390a8df
TA		 1719 if (ret)
1720 goto destroy_erase_cmd_list;
1721
5390a8df
TA		 1722 ret = spi_nor_wait_till_ready(nor);
1723 if (ret)
1724 goto destroy_erase_cmd_list;
786a0a75
TA		 1725
1726 addr += cmd->size;
1727 cmd->count--;
5390a8df
TA		 1728 }
1729 list_del(&cmd->list);
1730 kfree(cmd);
1731 }
1732
1733 return 0;
1734
1735destroy_erase_cmd_list:
1736 spi_nor_destroy_erase_cmd_list(&erase_list);
1737 return ret;
1738}
1739
96414231
TA		 1740static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr,
1741 size_t len, size_t die_size)
1742{
1743 unsigned long timeout;
1744 int ret;
1745
1746 /*
1747 * Scale the timeout linearly with the size of the flash, with
1748 * a minimum calibrated to an old 2MB flash. We could try to
1749 * pull these from CFI/SFDP, but these values should be good
1750 * enough for now.
1751 */
1752 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
1753 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
1754 (unsigned long)(nor->mtd.size / SZ_2M));
1755
1756 do {
1757 ret = spi_nor_lock_device(nor);
1758 if (ret)
1759 return ret;
1760
1761 ret = spi_nor_write_enable(nor);
1762 if (ret) {
1763 spi_nor_unlock_device(nor);
1764 return ret;
1765 }
1766
1767 ret = spi_nor_erase_die(nor, addr, die_size);
1768
1769 spi_nor_unlock_device(nor);
1770 if (ret)
1771 return ret;
1772
1773 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
1774 if (ret)
1775 return ret;
1776
1777 addr += die_size;
1778 len -= die_size;
1779
1780 } while (len);
1781
1782 return 0;
1783}
1784
b199489d
HS		 1785/*
1786 * Erase an address range on the nor chip. The address range may extend
c69942bd 1787 * one or more erase sectors. Return an error if there is a problem erasing.
b199489d
HS		 1788 */
1789static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1790{
1791 struct spi_nor *nor = mtd_to_spi_nor(mtd);
96414231
TA		 1792 u8 n_dice = nor->params->n_dice;
1793 bool multi_die_erase = false;
075ede8d 1794 u32 addr, len, rem;
96414231 1795 size_t die_size;
b199489d
HS		 1796 int ret;
1797
1798 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1799 (long long)instr->len);
1800
5390a8df
TA		 1801 if (spi_nor_has_uniform_erase(nor)) {
1802 div_u64_rem(instr->len, mtd->erasesize, &rem);
1803 if (rem)
1804 return -EINVAL;
1805 }
b199489d
HS		 1806
1807 addr = instr->addr;
1808 len = instr->len;
1809
96414231
TA		 1810 if (n_dice) {
1811 die_size = div_u64(mtd->size, n_dice);
1812 if (!(len & (die_size - 1)) && !(addr & (die_size - 1)))
1813 multi_die_erase = true;
1814 } else {
1815 die_size = mtd->size;
1816 }
1817
e96d4605 1818 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len);
b199489d
HS		 1819 if (ret)
1820 return ret;
1821
96414231
TA		 1822 /* chip (die) erase? */
1823 if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) ||
1824 multi_die_erase) {
1825 ret = spi_nor_erase_dice(nor, addr, len, die_size);
dfa9c0cb
BN		 1826 if (ret)
1827 goto erase_err;
1828
b199489d 1829 /* REVISIT in some cases we could speed up erasing large regions
b02e7f3e 1830 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
b199489d
HS		 1831 * to use "small sector erase", but that's not always optimal.
1832 */
1833
1834 /* "sector"-at-a-time erase */
5390a8df 1835 } else if (spi_nor_has_uniform_erase(nor)) {
b199489d 1836 while (len) {
74df43b3 1837 ret = spi_nor_lock_device(nor);
bce679e5
TA		 1838 if (ret)
1839 goto erase_err;
05241aea 1840
74df43b3
MR		 1841 ret = spi_nor_write_enable(nor);
1842 if (ret) {
1843 spi_nor_unlock_device(nor);
1844 goto erase_err;
1845 }
1846
c67cbb83 1847 ret = spi_nor_erase_sector(nor, addr);
74df43b3 1848 spi_nor_unlock_device(nor);
c67cbb83 1849 if (ret)
b199489d 1850 goto erase_err;
b199489d 1851
dfa9c0cb
BN		 1852 ret = spi_nor_wait_till_ready(nor);
1853 if (ret)
1854 goto erase_err;
786a0a75
TA		 1855
1856 addr += mtd->erasesize;
1857 len -= mtd->erasesize;
b199489d 1858 }
5390a8df
TA		 1859
1860 /* erase multiple sectors */
1861 } else {
1862 ret = spi_nor_erase_multi_sectors(nor, addr, len);
1863 if (ret)
1864 goto erase_err;
b199489d
HS		 1865 }
1866
bce679e5 1867 ret = spi_nor_write_disable(nor);
05241aea 1868
d6af2694 1869erase_err:
e96d4605 1870 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len);
b199489d 1871
b199489d 1872 return ret;
b199489d
HS		 1873}
1874
f10aa369 1875/**
1afc0c89
YY		 1876 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status
1877 * Register 1.
f10aa369
BB		 1878 * @nor: pointer to a 'struct spi_nor'
1879 *
658488ed 1880 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.
f10aa369
BB		 1881 *
1882 * Return: 0 on success, -errno otherwise.
1883 */
1afc0c89 1884int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)
f10aa369 1885{
cd1718f5
TA		 1886 int ret;
1887
1888 ret = spi_nor_read_sr(nor, nor->bouncebuf);
1889 if (ret)
1890 return ret;
f10aa369 1891
1afc0c89 1892 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)
f10aa369
BB		 1893 return 0;
1894
1afc0c89 1895 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;
6e3087a8 1896
4da11da1 1897 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);
f10aa369
BB		 1898}
1899
f10aa369 1900/**
1afc0c89
YY		 1901 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status
1902 * Register 2.
7b678c69 1903 * @nor: pointer to a 'struct spi_nor'.
f10aa369 1904 *
7b678c69 1905 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.
f10aa369
BB		 1906 *
1907 * Return: 0 on success, -errno otherwise.
1908 */
1afc0c89 1909int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)
f10aa369 1910{
f10aa369 1911 int ret;
4da11da1 1912
7b678c69 1913 if (nor->flags & SNOR_F_NO_READ_CR)
1afc0c89 1914 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);
f10aa369 1915
7b678c69 1916 ret = spi_nor_read_cr(nor, nor->bouncebuf);
70d2c6dc 1917 if (ret)
7380f79c 1918 return ret;
f10aa369 1919
1afc0c89 1920 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)
f10aa369
BB		 1921 return 0;
1922
1afc0c89 1923 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;
da2ef812 1924
7b678c69 1925 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);
f10aa369
BB		 1926}
1927
1928/**
1afc0c89 1929 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.
f10aa369
BB		 1930 * @nor: pointer to a 'struct spi_nor'
1931 *
1932 * Set the Quad Enable (QE) bit in the Status Register 2.
1933 *
1934 * This is one of the procedures to set the QE bit described in the SFDP
1935 * (JESD216 rev B) specification but no manufacturer using this procedure has
1936 * been identified yet, hence the name of the function.
1937 *
1938 * Return: 0 on success, -errno otherwise.
1939 */
1afc0c89 1940int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
f10aa369 1941{
f173f26a 1942 u8 *sr2 = nor->bouncebuf;
f10aa369 1943 int ret;
4da11da1 1944 u8 sr2_written;
f10aa369
BB		 1945
1946 /* Check current Quad Enable bit value. */
b35b9a10 1947 ret = spi_nor_read_sr2(nor, sr2);
f10aa369
BB		 1948 if (ret)
1949 return ret;
1afc0c89 1950 if (*sr2 & SR2_QUAD_EN_BIT7)
f10aa369
BB		 1951 return 0;
1952
1953 /* Update the Quad Enable bit. */
1afc0c89 1954 *sr2 |= SR2_QUAD_EN_BIT7;
f10aa369 1955
b35b9a10 1956 ret = spi_nor_write_sr2(nor, sr2);
d1ed88ea 1957 if (ret)
7380f79c 1958 return ret;
f10aa369 1959
4da11da1
TA		 1960 sr2_written = *sr2;
1961
f10aa369 1962 /* Read back and check it. */
b35b9a10 1963 ret = spi_nor_read_sr2(nor, sr2);
ebe04bfe
TA		 1964 if (ret)
1965 return ret;
1966
4da11da1
TA		 1967 if (*sr2 != sr2_written) {
1968 dev_dbg(nor->dev, "SR2: Read back test failed\n");
b0db77f5 1969 return -EIO;
f10aa369
BB		 1970 }
1971
1972 return 0;
1973}
65153846 1974
f7242bfc
BB		 1975static const struct spi_nor_manufacturer *manufacturers[] = {
1976 &spi_nor_atmel,
d22a3be6 1977 &spi_nor_eon,
74c7e0e3 1978 &spi_nor_esmt,
7bdbd1ce 1979 &spi_nor_everspin,
acb96ecd 1980 &spi_nor_gigadevice,
aa635187 1981 &spi_nor_intel,
0a371981 1982 &spi_nor_issi,
10526d85 1983 &spi_nor_macronix,
15f5c7e5
BB		 1984 &spi_nor_micron,
1985 &spi_nor_st,
0173c32a 1986 &spi_nor_spansion,
c53b3f92 1987 &spi_nor_sst,
7b8b2201 1988 &spi_nor_winbond,
2d47cac1 1989 &spi_nor_xilinx,
a674d5a6 1990 &spi_nor_xmc,
f7242bfc 1991};
9ec4bbcb 1992
773bbe10
MW		 1993static const struct flash_info spi_nor_generic_flash = {
1994 .name = "spi-nor-generic",
773bbe10
MW		 1995};
1996
d0ddd884
TA		 1997static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
1998 const u8 *id)
9ec4bbcb 1999{
d0ddd884
TA		 2000 const struct flash_info *part;
2001 unsigned int i, j;
9ec4bbcb 2002
d0ddd884
TA		 2003 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
2004 for (j = 0; j < manufacturers[i]->nparts; j++) {
2005 part = &manufacturers[i]->parts[j];
2d7f3a08
MW		 2006 if (part->id &&
2007 !memcmp(part->id->bytes, id, part->id->len)) {
d0ddd884
TA		 2008 nor->manufacturer = manufacturers[i];
2009 return part;
2010 }
2011 }
9ec4bbcb
BB		 2012 }
2013
2014 return NULL;
2015}
2016
86b6b55f 2017static const struct flash_info *spi_nor_detect(struct spi_nor *nor)
b199489d 2018{
9ec4bbcb 2019 const struct flash_info *info;
2dcbfe36 2020 u8 *id = nor->bouncebuf;
2dcbfe36 2021 int ret;
b199489d 2022
86b6b55f 2023 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);
2dcbfe36
JN		 2024 if (ret) {
2025 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);
2026 return ERR_PTR(ret);
b199489d 2027 }
b199489d 2028
28ef7670
MW		 2029 /* Cache the complete flash ID. */
2030 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL);
2031 if (!nor->id)
2032 return ERR_PTR(-ENOMEM);
2033
d0ddd884 2034 info = spi_nor_match_id(nor, id);
773bbe10
MW		 2035
2036 /* Fallback to a generic flash described only by its SFDP data. */
2037 if (!info) {
2038 ret = spi_nor_check_sfdp_signature(nor);
2039 if (!ret)
2040 info = &spi_nor_generic_flash;
2041 }
2042
d0ddd884
TA		 2043 if (!info) {
2044 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
2045 SPI_NOR_MAX_ID_LEN, id);
2046 return ERR_PTR(-ENODEV);
b199489d 2047 }
d0ddd884 2048 return info;
b199489d
HS		 2049}
2050
b199489d
HS		 2051static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
2052 size_t *retlen, u_char *buf)
2053{
2054 struct spi_nor *nor = mtd_to_spi_nor(mtd);
e96d4605
MR		 2055 loff_t from_lock = from;
2056 size_t len_lock = len;
a719a75a 2057 ssize_t ret;
b199489d
HS		 2058
2059 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
2060
e96d4605 2061 ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock);
b199489d
HS		 2062 if (ret)
2063 return ret;
2064
26f9bcad 2065 while (len) {
e99ca98f
RR		 2066 loff_t addr = from;
2067
36499596 2068 addr = spi_nor_convert_addr(nor, addr);
e99ca98f 2069
b35b9a10 2070 ret = spi_nor_read_data(nor, addr, len, buf);
26f9bcad
MS		 2071 if (ret == 0) {
2072 /* We shouldn't see 0-length reads */
2073 ret = -EIO;
2074 goto read_err;
2075 }
2076 if (ret < 0)
2077 goto read_err;
b199489d 2078
26f9bcad
MS		 2079 WARN_ON(ret > len);
2080 *retlen += ret;
2081 buf += ret;
2082 from += ret;
2083 len -= ret;
2084 }
2085 ret = 0;
59451e12 2086
26f9bcad 2087read_err:
e96d4605
MR		 2088 spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);
2089
26f9bcad 2090 return ret;
b199489d
HS		 2091}
2092
b199489d
HS		 2093/*
2094 * Write an address range to the nor chip. Data must be written in
2095 * FLASH_PAGESIZE chunks. The address range may be any size provided
2096 * it is within the physical boundaries.
2097 */
2098static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
2099 size_t *retlen, const u_char *buf)
2100{
2101 struct spi_nor *nor = mtd_to_spi_nor(mtd);
e5d05cbd
MS		 2102 size_t page_offset, page_remain, i;
2103 ssize_t ret;
5854d4a6 2104 u32 page_size = nor->params->page_size;
b199489d
HS		 2105
2106 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
2107
e96d4605 2108 ret = spi_nor_prep_and_lock_pe(nor, to, len);
b199489d
HS		 2109 if (ret)
2110 return ret;
2111
e5d05cbd
MS		 2112 for (i = 0; i < len; ) {
2113 ssize_t written;
e99ca98f 2114 loff_t addr = to + i;
b199489d 2115
e99ca98f
RR		 2116 /*
2117 * If page_size is a power of two, the offset can be quickly
2118 * calculated with an AND operation. On the other cases we
2119 * need to do a modulus operation (more expensive).
e99ca98f 2120 */
5854d4a6
TA		 2121 if (is_power_of_2(page_size)) {
2122 page_offset = addr & (page_size - 1);
e99ca98f 2123 } else {
075ede8d 2124 u64 aux = addr;
b199489d 2125
5854d4a6 2126 page_offset = do_div(aux, page_size);
e99ca98f 2127 }
b199489d 2128 /* the size of data remaining on the first page */
5854d4a6 2129 page_remain = min_t(size_t, page_size - page_offset, len - i);
e5d05cbd 2130
36499596 2131 addr = spi_nor_convert_addr(nor, addr);
e99ca98f 2132
74df43b3 2133 ret = spi_nor_lock_device(nor);
bce679e5
TA		 2134 if (ret)
2135 goto write_err;
2136
74df43b3
MR		 2137 ret = spi_nor_write_enable(nor);
2138 if (ret) {
2139 spi_nor_unlock_device(nor);
2140 goto write_err;
2141 }
2142
b35b9a10 2143 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
74df43b3 2144 spi_nor_unlock_device(nor);
0bad7b93
MS		 2145 if (ret < 0)
2146 goto write_err;
e5d05cbd 2147 written = ret;
1d61dcb3 2148
e5d05cbd
MS		 2149 ret = spi_nor_wait_till_ready(nor);
2150 if (ret)
2151 goto write_err;
2152 *retlen += written;
2153 i += written;
b199489d
HS		 2154 }
2155
2156write_err:
e96d4605
MR		 2157 spi_nor_unlock_and_unprep_pe(nor, to, len);
2158
1d61dcb3 2159 return ret;
b199489d
HS		 2160}
2161
f10aa369 2162static int spi_nor_check(struct spi_nor *nor)
b199489d 2163{
b35b9a10 2164 if (!nor->dev ||
ac82229d 2165 (!nor->spimem && !nor->controller_ops) ||
45397787
TA		 2166 (!nor->spimem && nor->controller_ops &&
2167 (!nor->controller_ops->read ||
2168 !nor->controller_ops->write ||
2169 !nor->controller_ops->read_reg ||
2170 !nor->controller_ops->write_reg))) {
b199489d
HS		 2171 pr_err("spi-nor: please fill all the necessary fields!\n");
2172 return -EINVAL;
2173 }
2174
ac82229d
TA		 2175 if (nor->spimem && nor->controller_ops) {
2176 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");
2177 return -EINVAL;
2178 }
2179
b199489d
HS		 2180 return 0;
2181}
2182
fb27f198 2183void
cfc5604c
CP		 2184spi_nor_set_read_settings(struct spi_nor_read_command *read,
2185 u8 num_mode_clocks,
2186 u8 num_wait_states,
2187 u8 opcode,
2188 enum spi_nor_protocol proto)
2189{
2190 read->num_mode_clocks = num_mode_clocks;
2191 read->num_wait_states = num_wait_states;
2192 read->opcode = opcode;
2193 read->proto = proto;
2194}
2195
cb481b92
TA		 2196void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,
2197 enum spi_nor_protocol proto)
cfc5604c
CP		 2198{
2199 pp->opcode = opcode;
2200 pp->proto = proto;
2201}
2202
f10aa369
BB		 2203static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
2204{
2205 size_t i;
2206
2207 for (i = 0; i < size; i++)
2208 if (table[i][0] == (int)hwcaps)
2209 return table[i][1];
2210
2211 return -EINVAL;
2212}
2213
cb481b92 2214int spi_nor_hwcaps_read2cmd(u32 hwcaps)
f10aa369
BB		 2215{
2216 static const int hwcaps_read2cmd[][2] = {
2217 { SNOR_HWCAPS_READ, SNOR_CMD_READ },
2218 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
2219 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
2220 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
2221 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
2222 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
2223 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
2224 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
2225 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
2226 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
2227 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
2228 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
2229 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
2230 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
2231 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
0e30f472 2232 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
f10aa369
BB		 2233 };
2234
2235 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
2236 ARRAY_SIZE(hwcaps_read2cmd));
2237}
2238
d92e0dbc 2239int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
f10aa369
BB		 2240{
2241 static const int hwcaps_pp2cmd[][2] = {
2242 { SNOR_HWCAPS_PP, SNOR_CMD_PP },
2243 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
2244 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
2245 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
2246 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
2247 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
2248 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
0e30f472 2249 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
f10aa369
BB		 2250 };
2251
2252 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
2253 ARRAY_SIZE(hwcaps_pp2cmd));
2254}
2255
c76f5089
BB		 2256/**
2257 * spi_nor_spimem_check_op - check if the operation is supported
2258 * by controller
2259 *@nor: pointer to a 'struct spi_nor'
2260 *@op: pointer to op template to be checked
2261 *
39bdfb78 2262 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
c76f5089
BB		 2263 */
2264static int spi_nor_spimem_check_op(struct spi_nor *nor,
2265 struct spi_mem_op *op)
2266{
2267 /*
2268 * First test with 4 address bytes. The opcode itself might
2269 * be a 3B addressing opcode but we don't care, because
2270 * SPI controller implementation should not check the opcode,
2271 * but just the sequence.
2272 */
2273 op->addr.nbytes = 4;
2274 if (!spi_mem_supports_op(nor->spimem, op)) {
eb726c32 2275 if (nor->params->size > SZ_16M)
39bdfb78 2276 return -EOPNOTSUPP;
c76f5089
BB		 2277
2278 /* If flash size <= 16MB, 3 address bytes are sufficient */
2279 op->addr.nbytes = 3;
2280 if (!spi_mem_supports_op(nor->spimem, op))
39bdfb78 2281 return -EOPNOTSUPP;
c76f5089
BB		 2282 }
2283
2284 return 0;
2285}
2286
2287/**
2288 * spi_nor_spimem_check_readop - check if the read op is supported
2289 * by controller
2290 *@nor: pointer to a 'struct spi_nor'
2291 *@read: pointer to op template to be checked
2292 *
39bdfb78 2293 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
c76f5089
BB		 2294 */
2295static int spi_nor_spimem_check_readop(struct spi_nor *nor,
2296 const struct spi_nor_read_command *read)
2297{
c0abb861 2298 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);
c76f5089 2299
0e30f472
PY		 2300 spi_nor_spimem_setup_op(nor, &op, read->proto);
2301
2302 /* convert the dummy cycles to the number of bytes */
fdc20370
AKC		 2303 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
2304 op.dummy.buswidth / 8;
0e30f472
PY		 2305 if (spi_nor_protocol_is_dtr(nor->read_proto))
2306 op.dummy.nbytes *= 2;
c76f5089
BB		 2307
2308 return spi_nor_spimem_check_op(nor, &op);
2309}
2310
2311/**
2312 * spi_nor_spimem_check_pp - check if the page program op is supported
2313 * by controller
2314 *@nor: pointer to a 'struct spi_nor'
2315 *@pp: pointer to op template to be checked
2316 *
39bdfb78 2317 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.
c76f5089
BB		 2318 */
2319static int spi_nor_spimem_check_pp(struct spi_nor *nor,
2320 const struct spi_nor_pp_command *pp)
2321{
c0abb861 2322 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);
c76f5089 2323
0e30f472 2324 spi_nor_spimem_setup_op(nor, &op, pp->proto);
c76f5089
BB		 2325
2326 return spi_nor_spimem_check_op(nor, &op);
2327}
2328
2329/**
2330 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol
2331 * based on SPI controller capabilities
2332 * @nor: pointer to a 'struct spi_nor'
c76f5089
BB		 2333 * @hwcaps: pointer to resulting capabilities after adjusting
2334 * according to controller and flash's capability
2335 */
2336static void
1e35a567 2337spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
c76f5089 2338{
829ec640 2339 struct spi_nor_flash_parameter *params = nor->params;
c76f5089
BB		 2340 unsigned int cap;
2341
c76f5089
BB		 2342 /* X-X-X modes are not supported yet, mask them all. */
2343 *hwcaps &= ~SNOR_HWCAPS_X_X_X;
2344
0e30f472
PY		 2345 /*
2346 * If the reset line is broken, we do not want to enter a stateful
2347 * mode.
2348 */
2349 if (nor->flags & SNOR_F_BROKEN_RESET)
2350 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
2351
c76f5089
BB		 2352 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
2353 int rdidx, ppidx;
2354
2355 if (!(*hwcaps & BIT(cap)))
2356 continue;
2357
2358 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
2359 if (rdidx >= 0 &&
2360 spi_nor_spimem_check_readop(nor, &params->reads[rdidx]))
2361 *hwcaps &= ~BIT(cap);
2362
2363 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
2364 if (ppidx < 0)
2365 continue;
2366
2367 if (spi_nor_spimem_check_pp(nor,
2368 &params->page_programs[ppidx]))
2369 *hwcaps &= ~BIT(cap);
2370 }
2371}
2372
5390a8df
TA		 2373/**
2374 * spi_nor_set_erase_type() - set a SPI NOR erase type
2375 * @erase: pointer to a structure that describes a SPI NOR erase type
2376 * @size: the size of the sector/block erased by the erase type
2377 * @opcode: the SPI command op code to erase the sector/block
2378 */
cb481b92
TA		 2379void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,
2380 u8 opcode)
5390a8df
TA		 2381{
2382 erase->size = size;
2383 erase->opcode = opcode;
2384 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */
2385 erase->size_shift = ffs(erase->size) - 1;
2386 erase->size_mask = (1 << erase->size_shift) - 1;
2387}
2388
f0f0cfdc
LR		 2389/**
2390 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type
2391 * @erase: pointer to a structure that describes a SPI NOR erase type
2392 */
2393void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase)
2394{
2395 erase->size = 0;
2396}
2397
5390a8df
TA		 2398/**
2399 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map
2400 * @map: the erase map of the SPI NOR
2401 * @erase_mask: bitmask encoding erase types that can erase the entire
2402 * flash memory
2403 * @flash_size: the spi nor flash memory size
2404 */
cb481b92
TA		 2405void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,
2406 u8 erase_mask, u64 flash_size)
5390a8df 2407{
0e164238 2408 map->uniform_region.offset = 0;
5390a8df 2409 map->uniform_region.size = flash_size;
0e164238 2410 map->uniform_region.erase_mask = erase_mask;
5390a8df 2411 map->regions = &map->uniform_region;
df6e36ed 2412 map->n_regions = 1;
5390a8df
TA		 2413}
2414
cb481b92
TA		 2415int spi_nor_post_bfpt_fixups(struct spi_nor *nor,
2416 const struct sfdp_parameter_header *bfpt_header,
a580293a 2417 const struct sfdp_bfpt *bfpt)
2aaa5f7e 2418{
9ec4bbcb
BB		 2419 int ret;
2420
2421 if (nor->manufacturer && nor->manufacturer->fixups &&
2422 nor->manufacturer->fixups->post_bfpt) {
2423 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,
a580293a 2424 bfpt);
9ec4bbcb
BB		 2425 if (ret)
2426 return ret;
2427 }
2428
2aaa5f7e 2429 if (nor->info->fixups && nor->info->fixups->post_bfpt)
a580293a 2430 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);
2aaa5f7e
BB		 2431
2432 return 0;
2433}
2434
2d7ff858
TA		 2435static int spi_nor_select_read(struct spi_nor *nor,
2436 u32 shared_hwcaps)
2437{
2438 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
2439 const struct spi_nor_read_command *read;
2440
2441 if (best_match < 0)
2442 return -EINVAL;
2443
2444 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
2445 if (cmd < 0)
2446 return -EINVAL;
2447
829ec640 2448 read = &nor->params->reads[cmd];
2d7ff858
TA		 2449 nor->read_opcode = read->opcode;
2450 nor->read_proto = read->proto;
2451
2452 /*
1ac71ec0 2453 * In the SPI NOR framework, we don't need to make the difference
2d7ff858
TA		 2454 * between mode clock cycles and wait state clock cycles.
2455 * Indeed, the value of the mode clock cycles is used by a QSPI
2456 * flash memory to know whether it should enter or leave its 0-4-4
2457 * (Continuous Read / XIP) mode.
2458 * eXecution In Place is out of the scope of the mtd sub-system.
2459 * Hence we choose to merge both mode and wait state clock cycles
2460 * into the so called dummy clock cycles.
2461 */
2462 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
2463 return 0;
2464}
2465
2466static int spi_nor_select_pp(struct spi_nor *nor,
2467 u32 shared_hwcaps)
2468{
2469 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
2470 const struct spi_nor_pp_command *pp;
2471
2472 if (best_match < 0)
2473 return -EINVAL;
2474
2475 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
2476 if (cmd < 0)
2477 return -EINVAL;
2478
829ec640 2479 pp = &nor->params->page_programs[cmd];
2d7ff858
TA		 2480 nor->program_opcode = pp->opcode;
2481 nor->write_proto = pp->proto;
2482 return 0;
2483}
2484
2485/**
2486 * spi_nor_select_uniform_erase() - select optimum uniform erase type
2487 * @map: the erase map of the SPI NOR
2d7ff858
TA		 2488 *
2489 * Once the optimum uniform sector erase command is found, disable all the
2490 * other.
2491 *
2492 * Return: pointer to erase type on success, NULL otherwise.
2493 */
2494static const struct spi_nor_erase_type *
9b6bb07e 2495spi_nor_select_uniform_erase(struct spi_nor_erase_map *map)
2d7ff858
TA		 2496{
2497 const struct spi_nor_erase_type *tested_erase, *erase = NULL;
2498 int i;
0e164238 2499 u8 uniform_erase_type = map->uniform_region.erase_mask;
2d7ff858 2500
9b6bb07e
MW		 2501 /*
2502 * Search for the biggest erase size, except for when compiled
2503 * to use 4k erases.
2504 */
2d7ff858
TA		 2505 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2506 if (!(uniform_erase_type & BIT(i)))
2507 continue;
2508
2509 tested_erase = &map->erase_type[i];
2510
39eece67
MW		 2511 /* Skip masked erase types. */
2512 if (!tested_erase->size)
2513 continue;
2514
2d7ff858 2515 /*
9b6bb07e 2516 * If the current erase size is the 4k one, stop here,
2d7ff858
TA		 2517 * we have found the right uniform Sector Erase command.
2518 */
9b6bb07e
MW		 2519 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS) &&
2520 tested_erase->size == SZ_4K) {
2d7ff858
TA		 2521 erase = tested_erase;
2522 break;
2523 }
2524
2525 /*
c69942bd 2526 * Otherwise, the current erase size is still a valid candidate.
2d7ff858
TA		 2527 * Select the biggest valid candidate.
2528 */
2529 if (!erase && tested_erase->size)
2530 erase = tested_erase;
2531 /* keep iterating to find the wanted_size */
2532 }
2533
2534 if (!erase)
2535 return NULL;
2536
2537 /* Disable all other Sector Erase commands. */
0e164238 2538 map->uniform_region.erase_mask = BIT(erase - map->erase_type);
2d7ff858
TA		 2539 return erase;
2540}
2541
3a960339 2542static int spi_nor_select_erase(struct spi_nor *nor)
2d7ff858 2543{
829ec640 2544 struct spi_nor_erase_map *map = &nor->params->erase_map;
2d7ff858
TA		 2545 const struct spi_nor_erase_type *erase = NULL;
2546 struct mtd_info *mtd = &nor->mtd;
2547 int i;
2548
2549 /*
2550 * The previous implementation handling Sector Erase commands assumed
2551 * that the SPI flash memory has an uniform layout then used only one
2552 * of the supported erase sizes for all Sector Erase commands.
2553 * So to be backward compatible, the new implementation also tries to
2554 * manage the SPI flash memory as uniform with a single erase sector
2555 * size, when possible.
2556 */
2d7ff858 2557 if (spi_nor_has_uniform_erase(nor)) {
9b6bb07e 2558 erase = spi_nor_select_uniform_erase(map);
2d7ff858
TA		 2559 if (!erase)
2560 return -EINVAL;
2561 nor->erase_opcode = erase->opcode;
2562 mtd->erasesize = erase->size;
2563 return 0;
2564 }
2565
2566 /*
2567 * For non-uniform SPI flash memory, set mtd->erasesize to the
2568 * maximum erase sector size. No need to set nor->erase_opcode.
2569 */
2570 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
2571 if (map->erase_type[i].size) {
2572 erase = &map->erase_type[i];
2573 break;
2574 }
2575 }
2576
2577 if (!erase)
2578 return -EINVAL;
2579
2580 mtd->erasesize = erase->size;
2581 return 0;
2582}
2583
2584static int spi_nor_default_setup(struct spi_nor *nor,
2585 const struct spi_nor_hwcaps *hwcaps)
2586{
829ec640 2587 struct spi_nor_flash_parameter *params = nor->params;
2d7ff858
TA		 2588 u32 ignored_mask, shared_mask;
2589 int err;
2590
2591 /*
2592 * Keep only the hardware capabilities supported by both the SPI
2593 * controller and the SPI flash memory.
2594 */
2595 shared_mask = hwcaps->mask & params->hwcaps.mask;
2596
2597 if (nor->spimem) {
2598 /*
2599 * When called from spi_nor_probe(), all caps are set and we
2600 * need to discard some of them based on what the SPI
2601 * controller actually supports (using spi_mem_supports_op()).
2602 */
2603 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);
2604 } else {
2605 /*
2606 * SPI n-n-n protocols are not supported when the SPI
2607 * controller directly implements the spi_nor interface.
2608 * Yet another reason to switch to spi-mem.
2609 */
0e30f472 2610 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;
2d7ff858
TA		 2611 if (shared_mask & ignored_mask) {
2612 dev_dbg(nor->dev,
2613 "SPI n-n-n protocols are not supported.\n");
2614 shared_mask &= ~ignored_mask;
2615 }
2616 }
2617
2618 /* Select the (Fast) Read command. */
2619 err = spi_nor_select_read(nor, shared_mask);
2620 if (err) {
f633ebe4 2621 dev_dbg(nor->dev,
2d7ff858
TA		 2622 "can't select read settings supported by both the SPI controller and memory.\n");
2623 return err;
2624 }
2625
2626 /* Select the Page Program command. */
2627 err = spi_nor_select_pp(nor, shared_mask);
2628 if (err) {
f633ebe4 2629 dev_dbg(nor->dev,
2d7ff858
TA		 2630 "can't select write settings supported by both the SPI controller and memory.\n");
2631 return err;
2632 }
2633
2634 /* Select the Sector Erase command. */
3a960339 2635 err = spi_nor_select_erase(nor);
2d7ff858 2636 if (err) {
f633ebe4 2637 dev_dbg(nor->dev,
2d7ff858
TA		 2638 "can't select erase settings supported by both the SPI controller and memory.\n");
2639 return err;
2640 }
2641
2642 return 0;
2643}
2644
c452d498 2645static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
b7ed1a37 2646{
47c6f8a6
TA		 2647 if (nor->params->addr_nbytes) {
2648 nor->addr_nbytes = nor->params->addr_nbytes;
b7ed1a37
TA		 2649 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
2650 /*
2651 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
c452d498 2652 * in this protocol an odd addr_nbytes cannot be used because
b7ed1a37
TA		 2653 * then the address phase would only span a cycle and a half.
2654 * Half a cycle would be left over. We would then have to start
2655 * the dummy phase in the middle of a cycle and so too the data
2656 * phase, and we will end the transaction with half a cycle left
2657 * over.
2658 *
c452d498 2659 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to
b7ed1a37
TA		 2660 * avoid this situation.
2661 */
c452d498
TA		 2662 nor->addr_nbytes = 4;
2663 } else if (nor->info->addr_nbytes) {
2664 nor->addr_nbytes = nor->info->addr_nbytes;
b7ed1a37 2665 } else {
c452d498 2666 nor->addr_nbytes = 3;
b7ed1a37
TA		 2667 }
2668
c452d498 2669 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {
b7ed1a37 2670 /* enable 4-byte addressing if the device exceeds 16MiB */
c452d498 2671 nor->addr_nbytes = 4;
b7ed1a37
TA		 2672 }
2673
c452d498
TA		 2674 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) {
2675 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n",
2676 nor->addr_nbytes);
b7ed1a37
TA		 2677 return -EINVAL;
2678 }
2679
2680 /* Set 4byte opcodes when possible. */
c452d498 2681 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES &&
b7ed1a37
TA		 2682 !(nor->flags & SNOR_F_HAS_4BAIT))
2683 spi_nor_set_4byte_opcodes(nor);
2684
2685 return 0;
2686}
2687
2d7ff858
TA		 2688static int spi_nor_setup(struct spi_nor *nor,
2689 const struct spi_nor_hwcaps *hwcaps)
2690{
b7ed1a37 2691 int ret;
2d7ff858 2692
b44aa9ac 2693 if (nor->params->setup)
b7ed1a37 2694 ret = nor->params->setup(nor, hwcaps);
b44aa9ac
MW		 2695 else
2696 ret = spi_nor_default_setup(nor, hwcaps);
2697 if (ret)
2698 return ret;
b7ed1a37 2699
c452d498 2700 return spi_nor_set_addr_nbytes(nor);
2d7ff858
TA		 2701}
2702
ce0b6f3f
TA		 2703/**
2704 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and
22f2eaac 2705 * settings based on MFR register and ->default_init() hook.
d207b0b3 2706 * @nor: pointer to a 'struct spi_nor'.
ce0b6f3f
TA		 2707 */
2708static void spi_nor_manufacturer_init_params(struct spi_nor *nor)
2709{
9ec4bbcb
BB		 2710 if (nor->manufacturer && nor->manufacturer->fixups &&
2711 nor->manufacturer->fixups->default_init)
2712 nor->manufacturer->fixups->default_init(nor);
2713
ce0b6f3f
TA		 2714 if (nor->info->fixups && nor->info->fixups->default_init)
2715 nor->info->fixups->default_init(nor);
2716}
2717
1c1d8d98 2718/**
5dabf577
TA		 2719 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and
2720 * settings based on nor->info->sfdp_flags. This method should be called only by
2721 * flashes that do not define SFDP tables. If the flash supports SFDP but the
2722 * information is wrong and the settings from this function can not be retrieved
2723 * by parsing SFDP, one should instead use the fixup hooks and update the wrong
2724 * bits.
f4363e64 2725 * @nor: pointer to a 'struct spi_nor'.
1c1d8d98 2726 */
5dabf577 2727static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)
cfc5604c 2728{
829ec640 2729 struct spi_nor_flash_parameter *params = nor->params;
c4687217 2730 struct spi_nor_erase_map *map = &params->erase_map;
6dec24b1
MW		 2731 const struct flash_info *info = nor->info;
2732 const u8 no_sfdp_flags = info->no_sfdp_flags;
5390a8df
TA		 2733 u8 i, erase_mask;
2734
ec1c0e99 2735 if (no_sfdp_flags & SPI_NOR_DUAL_READ) {
cfc5604c
CP		 2736 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
2737 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
2738 0, 8, SPINOR_OP_READ_1_1_2,
2739 SNOR_PROTO_1_1_2);
2740 }
2741
ec1c0e99 2742 if (no_sfdp_flags & SPI_NOR_QUAD_READ) {
cfc5604c
CP		 2743 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
2744 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
2745 0, 8, SPINOR_OP_READ_1_1_4,
2746 SNOR_PROTO_1_1_4);
2747 }
2748
ec1c0e99 2749 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {
fcd44b64
YNG		 2750 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
2751 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
2752 0, 8, SPINOR_OP_READ_1_1_8,
2753 SNOR_PROTO_1_1_8);
2754 }
2755
ec1c0e99 2756 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {
0e30f472
PY		 2757 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
2758 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
2759 0, 20, SPINOR_OP_READ_FAST,
2760 SNOR_PROTO_8_8_8_DTR);
2761 }
2762
ec1c0e99 2763 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {
0e30f472
PY		 2764 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
2765 /*
2766 * Since xSPI Page Program opcode is backward compatible with
2767 * Legacy SPI, use Legacy SPI opcode there as well.
2768 */
2769 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
2770 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
2771 }
2772
5390a8df
TA		 2773 /*
2774 * Sector Erase settings. Sort Erase Types in ascending order, with the
2775 * smallest erase size starting at BIT(0).
2776 */
2777 erase_mask = 0;
2778 i = 0;
77d4ac6d 2779 if (no_sfdp_flags & SECT_4K) {
5390a8df
TA		 2780 erase_mask |= BIT(i);
2781 spi_nor_set_erase_type(&map->erase_type[i], 4096u,
2782 SPINOR_OP_BE_4K);
2783 i++;
2784 }
2785 erase_mask |= BIT(i);
6dec24b1
MW		 2786 spi_nor_set_erase_type(&map->erase_type[i],
2787 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE,
5390a8df
TA		 2788 SPINOR_OP_SE);
2789 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
1c1d8d98 2790}
5390a8df 2791
5429300d
TA		 2792/**
2793 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined
2794 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.
2795 * @nor: pointer to a 'struct spi_nor'
2796 */
2797static void spi_nor_init_flags(struct spi_nor *nor)
2798{
2799 struct device_node *np = spi_nor_get_flash_node(nor);
2800 const u16 flags = nor->info->flags;
2801
2802 if (of_property_read_bool(np, "broken-flash-reset"))
2803 nor->flags |= SNOR_F_BROKEN_RESET;
2804
18d7d01a
AKM		 2805 if (of_property_read_bool(np, "no-wp"))
2806 nor->flags |= SNOR_F_NO_WP;
2807
5429300d
TA		 2808 if (flags & SPI_NOR_SWP_IS_VOLATILE)
2809 nor->flags |= SNOR_F_SWP_IS_VOLATILE;
2810
2811 if (flags & SPI_NOR_HAS_LOCK)
2812 nor->flags |= SNOR_F_HAS_LOCK;
2813
2814 if (flags & SPI_NOR_HAS_TB) {
2815 nor->flags |= SNOR_F_HAS_SR_TB;
2816 if (flags & SPI_NOR_TB_SR_BIT6)
2817 nor->flags |= SNOR_F_HAS_SR_TB_BIT6;
2818 }
2819
2820 if (flags & SPI_NOR_4BIT_BP) {
2821 nor->flags |= SNOR_F_HAS_4BIT_BP;
2822 if (flags & SPI_NOR_BP3_SR_BIT6)
2823 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
2824 }
2825
9983e6da 2826 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&
74df43b3 2827 !nor->controller_ops)
4eddee70 2828 nor->flags |= SNOR_F_RWW;
5429300d
TA		 2829}
2830
a1ede1cc
TA		 2831/**
2832 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not
2833 * be discovered by SFDP for this particular flash because the SFDP table that
2834 * indicates this support is not defined in the flash. In case the table for
2835 * this support is defined but has wrong values, one should instead use a
2836 * post_sfdp() hook to set the SNOR_F equivalent flag.
2837 * @nor: pointer to a 'struct spi_nor'
2838 */
2839static void spi_nor_init_fixup_flags(struct spi_nor *nor)
2840{
2841 const u8 fixup_flags = nor->info->fixup_flags;
2842
2843 if (fixup_flags & SPI_NOR_4B_OPCODES)
2844 nor->flags |= SNOR_F_4B_OPCODES;
2845
2846 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)
2847 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
2848}
2849
dff97245
BB		 2850/**
2851 * spi_nor_late_init_params() - Late initialization of default flash parameters.
2852 * @nor: pointer to a 'struct spi_nor'
2853 *
dacc8cfe
TA		 2854 * Used to initialize flash parameters that are not declared in the JESD216
2855 * SFDP standard, or where SFDP tables are not defined at all.
2856 * Will replace the spi_nor_manufacturer_init_params() method.
dff97245 2857 */
d534fd97 2858static int spi_nor_late_init_params(struct spi_nor *nor)
dff97245 2859{
4e53ab0c 2860 struct spi_nor_flash_parameter *params = nor->params;
d534fd97 2861 int ret;
4e53ab0c 2862
dacc8cfe 2863 if (nor->manufacturer && nor->manufacturer->fixups &&
d534fd97
TK		 2864 nor->manufacturer->fixups->late_init) {
2865 ret = nor->manufacturer->fixups->late_init(nor);
2866 if (ret)
2867 return ret;
2868 }
dacc8cfe 2869
53919a96
TA		 2870 /* Needed by some flashes late_init hooks. */
2871 spi_nor_init_flags(nor);
2872
d534fd97
TK		 2873 if (nor->info->fixups && nor->info->fixups->late_init) {
2874 ret = nor->info->fixups->late_init(nor);
2875 if (ret)
2876 return ret;
2877 }
dacc8cfe 2878
96414231
TA		 2879 if (!nor->params->die_erase_opcode)
2880 nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;
2881
4e53ab0c
TA		 2882 /* Default method kept for backward compatibility. */
2883 if (!params->set_4byte_addr_mode)
2884 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;
2885
a1ede1cc 2886 spi_nor_init_fixup_flags(nor);
5429300d 2887
dff97245
BB		 2888 /*
2889 * NOR protection support. When locking_ops are not provided, we pick
2890 * the default ones.
2891 */
829ec640 2892 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)
c4c79510 2893 spi_nor_init_default_locking_ops(nor);
79a4db50 2894
9983e6da 2895 if (params->n_banks > 1)
c84b3925 2896 params->bank_size = div_u64(params->size, params->n_banks);
d534fd97
TK		 2897
2898 return 0;
dff97245
BB		 2899}
2900
5dabf577
TA		 2901/**
2902 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash
2903 * parameters and settings based on JESD216 SFDP standard.
2904 * @nor: pointer to a 'struct spi_nor'.
2905 *
2906 * The method has a roll-back mechanism: in case the SFDP parsing fails, the
2907 * legacy flash parameters and settings will be restored.
2908 */
2909static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
2910{
2911 struct spi_nor_flash_parameter sfdp_params;
2912
2913 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));
2914
2915 if (spi_nor_parse_sfdp(nor)) {
2916 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
5dabf577
TA		 2917 nor->flags &= ~SNOR_F_4B_OPCODES;
2918 }
2919}
2920
2921/**
2922 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash
2923 * parameters and settings.
2924 * @nor: pointer to a 'struct spi_nor'.
2925 *
2926 * The method assumes that flash doesn't support SFDP so it initializes flash
2927 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten
2928 * when parsing SFDP, if supported.
2929 */
2930static void spi_nor_init_params_deprecated(struct spi_nor *nor)
2931{
2932 spi_nor_no_sfdp_init_params(nor);
2933
2934 spi_nor_manufacturer_init_params(nor);
2935
2936 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |
2937 SPI_NOR_QUAD_READ |
2938 SPI_NOR_OCTAL_READ |
2939 SPI_NOR_OCTAL_DTR_READ))
2940 spi_nor_sfdp_init_params_deprecated(nor);
2941}
2942
2943/**
2944 * spi_nor_init_default_params() - Default initialization of flash parameters
2945 * and settings. Done for all flashes, regardless is they define SFDP tables
2946 * or not.
2947 * @nor: pointer to a 'struct spi_nor'.
2948 */
2949static void spi_nor_init_default_params(struct spi_nor *nor)
2950{
2951 struct spi_nor_flash_parameter *params = nor->params;
2952 const struct flash_info *info = nor->info;
2953 struct device_node *np = spi_nor_get_flash_node(nor);
2954
2955 params->quad_enable = spi_nor_sr2_bit1_quad_enable;
83e62ffa 2956 params->otp.org = info->otp;
5dabf577
TA		 2957
2958 /* Default to 16-bit Write Status (01h) Command */
2959 nor->flags |= SNOR_F_HAS_16BIT_SR;
2960
2961 /* Set SPI NOR sizes. */
2962 params->writesize = 1;
0554effe 2963 params->size = info->size;
4095f4d9 2964 params->bank_size = params->size;
d0cfd228 2965 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;
e255a791 2966 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;
5dabf577
TA		 2967
2968 if (!(info->flags & SPI_NOR_NO_FR)) {
2969 /* Default to Fast Read for DT and non-DT platform devices. */
2970 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
2971
2972 /* Mask out Fast Read if not requested at DT instantiation. */
2973 if (np && !of_property_read_bool(np, "m25p,fast-read"))
2974 params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
2975 }
2976
2977 /* (Fast) Read settings. */
2978 params->hwcaps.mask |= SNOR_HWCAPS_READ;
2979 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
2980 0, 0, SPINOR_OP_READ,
2981 SNOR_PROTO_1_1_1);
2982
2983 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
2984 spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
2985 0, 8, SPINOR_OP_READ_FAST,
2986 SNOR_PROTO_1_1_1);
2987 /* Page Program settings. */
2988 params->hwcaps.mask |= SNOR_HWCAPS_PP;
2989 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
2990 SPINOR_OP_PP, SNOR_PROTO_1_1_1);
1799cd85
SM		 2991
2992 if (info->flags & SPI_NOR_QUAD_PP) {
2993 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
2994 spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
2995 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
2996 }
5dabf577
TA		 2997}
2998
1c1d8d98
TA		 2999/**
3000 * spi_nor_init_params() - Initialize the flash's parameters and settings.
f4363e64 3001 * @nor: pointer to a 'struct spi_nor'.
1c1d8d98
TA		 3002 *
3003 * The flash parameters and settings are initialized based on a sequence of
3004 * calls that are ordered by priority:
3005 *
3006 * 1/ Default flash parameters initialization. The initializations are done
3007 * based on nor->info data:
3008 * spi_nor_info_init_params()
3009 *
3010 * which can be overwritten by:
3011 * 2/ Manufacturer flash parameters initialization. The initializations are
3012 * done based on MFR register, or when the decisions can not be done solely
3013 * based on MFR, by using specific flash_info tweeks, ->default_init():
3014 * spi_nor_manufacturer_init_params()
3015 *
3016 * which can be overwritten by:
3017 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and
3018 * should be more accurate that the above.
5dabf577 3019 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()
1c1d8d98
TA		 3020 *
3021 * Please note that there is a ->post_bfpt() fixup hook that can overwrite
3022 * the flash parameters and settings immediately after parsing the Basic
3023 * Flash Parameter Table.
5273cc6d
TA		 3024 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.
3025 * It is used to tweak various flash parameters when information provided
3026 * by the SFDP tables are wrong.
dff97245 3027 *
2b12ae1f 3028 * which can be overwritten by:
5273cc6d 3029 * 4/ Late flash parameters initialization, used to initialize flash
dacc8cfe
TA		 3030 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP
3031 * tables are not defined at all.
dff97245 3032 * spi_nor_late_init_params()
5dabf577
TA		 3033 *
3034 * Return: 0 on success, -errno otherwise.
1c1d8d98 3035 */
829ec640 3036static int spi_nor_init_params(struct spi_nor *nor)
1c1d8d98 3037{
5dabf577
TA		 3038 int ret;
3039
829ec640
TA		 3040 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);
3041 if (!nor->params)
3042 return -ENOMEM;
3043
5dabf577 3044 spi_nor_init_default_params(nor);
ce0b6f3f 3045
3ea3f0ac 3046 if (spi_nor_needs_sfdp(nor)) {
5dabf577
TA		 3047 ret = spi_nor_parse_sfdp(nor);
3048 if (ret) {
3049 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");
3050 return ret;
3051 }
3052 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {
3053 spi_nor_no_sfdp_init_params(nor);
3054 } else {
3055 spi_nor_init_params_deprecated(nor);
3056 }
dff97245 3057
d534fd97 3058 return spi_nor_late_init_params(nor);
cfc5604c
CP		 3059}
3060
d4996700 3061/** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O.
a33c89db
PY		 3062 * @nor: pointer to a 'struct spi_nor'
3063 * @enable: whether to enable or disable Octal DTR
3064 *
3065 * Return: 0 on success, -errno otherwise.
3066 */
d4996700 3067static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
a33c89db
PY		 3068{
3069 int ret;
3070
d4996700 3071 if (!nor->params->set_octal_dtr)
a33c89db
PY		 3072 return 0;
3073
3074 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
3075 nor->write_proto == SNOR_PROTO_8_8_8_DTR))
3076 return 0;
3077
3078 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))
3079 return 0;
3080
d4996700 3081 ret = nor->params->set_octal_dtr(nor, enable);
a33c89db
PY		 3082 if (ret)
3083 return ret;
3084
3085 if (enable)
3086 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
3087 else
3088 nor->reg_proto = SNOR_PROTO_1_1_1;
3089
3090 return 0;
3091}
3092
42f59947 3093/**
1afc0c89 3094 * spi_nor_quad_enable() - enable Quad I/O if needed.
42f59947
TA		 3095 * @nor: pointer to a 'struct spi_nor'
3096 *
3097 * Return: 0 on success, -errno otherwise.
3098 */
1afc0c89 3099static int spi_nor_quad_enable(struct spi_nor *nor)
42f59947 3100{
829ec640 3101 if (!nor->params->quad_enable)
42f59947
TA		 3102 return 0;
3103
3104 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
3105 spi_nor_get_protocol_width(nor->write_proto) == 4))
3106 return 0;
3107
1afc0c89 3108 return nor->params->quad_enable(nor);
42f59947
TA		 3109}
3110
b6094ac8
TA		 3111/**
3112 * spi_nor_set_4byte_addr_mode() - Set address mode.
3113 * @nor: pointer to a 'struct spi_nor'.
3114 * @enable: enable/disable 4 byte address mode.
3115 *
3116 * Return: 0 on success, -errno otherwise.
3117 */
3118int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)
3e0930f1 3119{
37513c56 3120 struct spi_nor_flash_parameter *params = nor->params;
b6094ac8
TA		 3121 int ret;
3122
53919a96
TA		 3123 if (enable) {
3124 /*
3125 * If the RESET# pin isn't hooked up properly, or the system
3126 * otherwise doesn't perform a reset command in the boot
3127 * sequence, it's impossible to 100% protect against unexpected
3128 * reboots (e.g., crashes). Warn the user (or hopefully, system
3129 * designer) that this is bad.
3130 */
3131 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
3132 "enabling reset hack; may not recover from unexpected reboots\n");
3133 }
3134
b6094ac8 3135 ret = params->set_4byte_addr_mode(nor, enable);
cff49d58 3136 if (ret && ret != -EOPNOTSUPP)
b6094ac8
TA		 3137 return ret;
3138
3139 if (enable) {
3140 params->addr_nbytes = 4;
3141 params->addr_mode_nbytes = 4;
3142 } else {
3143 params->addr_nbytes = 3;
3144 params->addr_mode_nbytes = 3;
3145 }
3146
3147 return 0;
3148}
3149
3e0930f1
TA		 3150static int spi_nor_init(struct spi_nor *nor)
3151{
3152 int err;
46dde01f 3153
d4996700 3154 err = spi_nor_set_octal_dtr(nor, true);
a33c89db
PY		 3155 if (err) {
3156 dev_dbg(nor->dev, "octal mode not supported\n");
3157 return err;
3158 }
3159
1afc0c89 3160 err = spi_nor_quad_enable(nor);
42f59947 3161 if (err) {
f633ebe4 3162 dev_dbg(nor->dev, "quad mode not supported\n");
42f59947 3163 return err;
cfc5604c
CP		 3164 }
3165
31ad3eff
MW		 3166 /*
3167 * Some SPI NOR flashes are write protected by default after a power-on
3168 * reset cycle, in order to avoid inadvertent writes during power-up.
3169 * Backward compatibility imposes to unlock the entire flash memory
3170 * array at power-up by default. Depending on the kernel configuration
3171 * (1) do nothing, (2) always unlock the entire flash array or (3)
3172 * unlock the entire flash array only when the software write
3173 * protection bits are volatile. The latter is indicated by
3174 * SNOR_F_SWP_IS_VOLATILE.
3175 */
3176 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||
3177 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&
3178 nor->flags & SNOR_F_SWP_IS_VOLATILE))
3179 spi_nor_try_unlock_all(nor);
3e0930f1 3180
c452d498 3181 if (nor->addr_nbytes == 4 &&
0e30f472 3182 nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
53919a96
TA		 3183 !(nor->flags & SNOR_F_4B_OPCODES))
3184 return spi_nor_set_4byte_addr_mode(nor, true);
46dde01f 3185
cfc5604c
CP		 3186 return 0;
3187}
3188
ccfb7cf1
PY		 3189/**
3190 * spi_nor_soft_reset() - Perform a software reset
3191 * @nor: pointer to 'struct spi_nor'
3192 *
3193 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets
3194 * the device to its power-on-reset state. This is useful when the software has
3195 * made some changes to device (volatile) registers and needs to reset it before
3196 * shutting down, for example.
3197 *
3198 * Not every flash supports this sequence. The same set of opcodes might be used
3199 * for some other operation on a flash that does not support this. Support for
3200 * this sequence can be discovered via SFDP in the BFPT table.
3201 *
3202 * Return: 0 on success, -errno otherwise.
3203 */
d73ee753
PY		 3204static void spi_nor_soft_reset(struct spi_nor *nor)
3205{
3206 struct spi_mem_op op;
3207 int ret;
3208
c0abb861 3209 op = (struct spi_mem_op)SPINOR_SRSTEN_OP;
d73ee753
PY		 3210
3211 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3212
3213 ret = spi_mem_exec_op(nor->spimem, &op);
3214 if (ret) {
7a030abc
CLKA		 3215 if (ret != -EOPNOTSUPP)
3216 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
d73ee753
PY		 3217 return;
3218 }
3219
c0abb861 3220 op = (struct spi_mem_op)SPINOR_SRST_OP;
d73ee753
PY		 3221
3222 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
3223
3224 ret = spi_mem_exec_op(nor->spimem, &op);
3225 if (ret) {
3226 dev_warn(nor->dev, "Software reset failed: %d\n", ret);
3227 return;
3228 }
3229
3230 /*
3231 * Software Reset is not instant, and the delay varies from flash to
3232 * flash. Looking at a few flashes, most range somewhere below 100
3233 * microseconds. So, sleep for a range of 200-400 us.
3234 */
3235 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);
3236}
3237
1b65c43f
PY		 3238/* mtd suspend handler */
3239static int spi_nor_suspend(struct mtd_info *mtd)
3240{
3241 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3242 int ret;
3243
3244 /* Disable octal DTR mode if we enabled it. */
d4996700 3245 ret = spi_nor_set_octal_dtr(nor, false);
1b65c43f
PY		 3246 if (ret)
3247 dev_err(nor->dev, "suspend() failed\n");
3248
3249 return ret;
3250}
3251
d6084fc8
KD		 3252/* mtd resume handler */
3253static void spi_nor_resume(struct mtd_info *mtd)
3254{
3255 struct spi_nor *nor = mtd_to_spi_nor(mtd);
3256 struct device *dev = nor->dev;
3257 int ret;
3258
3259 /* re-initialize the nor chip */
3260 ret = spi_nor_init(nor);
3261 if (ret)
3262 dev_err(dev, "resume() failed\n");
3263}
3264
be94215b
XC		 3265static int spi_nor_get_device(struct mtd_info *mtd)
3266{
3267 struct mtd_info *master = mtd_get_master(mtd);
3268 struct spi_nor *nor = mtd_to_spi_nor(master);
3269 struct device *dev;
3270
3271 if (nor->spimem)
3272 dev = nor->spimem->spi->controller->dev.parent;
3273 else
3274 dev = nor->dev;
3275
3276 if (!try_module_get(dev->driver->owner))
3277 return -ENODEV;
3278
3279 return 0;
3280}
3281
3282static void spi_nor_put_device(struct mtd_info *mtd)
3283{
3284 struct mtd_info *master = mtd_get_master(mtd);
3285 struct spi_nor *nor = mtd_to_spi_nor(master);
3286 struct device *dev;
3287
3288 if (nor->spimem)
3289 dev = nor->spimem->spi->controller->dev.parent;
3290 else
3291 dev = nor->dev;
3292
3293 module_put(dev->driver->owner);
3294}
3295
7fe1b00d 3296static void spi_nor_restore(struct spi_nor *nor)
8dee1d97 3297{
bb0e9c60
TA		 3298 int ret;
3299
8dee1d97 3300 /* restore the addressing mode */
c452d498 3301 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
bb0e9c60 3302 nor->flags & SNOR_F_BROKEN_RESET) {
b6094ac8 3303 ret = spi_nor_set_4byte_addr_mode(nor, false);
bb0e9c60
TA		 3304 if (ret)
3305 /*
3306 * Do not stop the execution in the hope that the flash
3307 * will default to the 3-byte address mode after the
3308 * software reset.
3309 */
3310 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);
3311 }
d73ee753
PY		 3312
3313 if (nor->flags & SNOR_F_SOFT_RESET)
3314 spi_nor_soft_reset(nor);
8dee1d97 3315}
8dee1d97 3316
b1145d6f
TA		 3317static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,
3318 const char *name)
f10aa369 3319{
9ec4bbcb 3320 unsigned int i, j;
f10aa369 3321
9ec4bbcb
BB		 3322 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {
3323 for (j = 0; j < manufacturers[i]->nparts; j++) {
3324 if (!strcmp(name, manufacturers[i]->parts[j].name)) {
3325 nor->manufacturer = manufacturers[i];
3326 return &manufacturers[i]->parts[j];
3327 }
3328 }
3329 }
3330
f10aa369
BB		 3331 return NULL;
3332}
3333
620df249
TA		 3334static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
3335 const char *name)
3336{
3337 const struct flash_info *info = NULL;
3338
3339 if (name)
b1145d6f 3340 info = spi_nor_match_name(nor, name);
620df249
TA		 3341 /* Try to auto-detect if chip name wasn't specified or not found */
3342 if (!info)
86b6b55f 3343 return spi_nor_detect(nor);
620df249
TA		 3344
3345 /*
3346 * If caller has specified name of flash model that can normally be
3347 * detected using JEDEC, let's verify it.
3348 */
2d7f3a08 3349 if (name && info->id) {
620df249
TA		 3350 const struct flash_info *jinfo;
3351
86b6b55f 3352 jinfo = spi_nor_detect(nor);
620df249
TA		 3353 if (IS_ERR(jinfo)) {
3354 return jinfo;
3355 } else if (jinfo != info) {
3356 /*
3357 * JEDEC knows better, so overwrite platform ID. We
3358 * can't trust partitions any longer, but we'll let
3359 * mtd apply them anyway, since some partitions may be
705c9ef8 3360 * marked read-only, and we don't want to loose that
620df249
TA		 3361 * information, even if it's not 100% accurate.
3362 */
3363 dev_warn(nor->dev, "found %s, expected %s\n",
3364 jinfo->name, info->name);
3365 info = jinfo;
3366 }
3367 }
3368
3369 return info;
3370}
3371
6a9eda34
TK		 3372static u32
3373spi_nor_get_region_erasesize(const struct spi_nor_erase_region *region,
3374 const struct spi_nor_erase_type *erase_type)
3375{
2842dc9b 3376 int i;
6a9eda34
TK		 3377
3378 if (region->overlaid)
3379 return region->size;
3380
3381 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
3382 if (region->erase_mask & BIT(i))
3383 return erase_type[i].size;
3384 }
3385
3386 return 0;
3387}
3388
3389static int spi_nor_set_mtd_eraseregions(struct spi_nor *nor)
3390{
3391 const struct spi_nor_erase_map *map = &nor->params->erase_map;
3392 const struct spi_nor_erase_region *region = map->regions;
3393 struct mtd_erase_region_info *mtd_region;
3394 struct mtd_info *mtd = &nor->mtd;
3395 u32 erasesize, i;
3396
3397 mtd_region = devm_kcalloc(nor->dev, map->n_regions, sizeof(*mtd_region),
3398 GFP_KERNEL);
3399 if (!mtd_region)
3400 return -ENOMEM;
3401
3402 for (i = 0; i < map->n_regions; i++) {
3403 erasesize = spi_nor_get_region_erasesize(&region[i],
3404 map->erase_type);
3405 if (!erasesize)
3406 return -EINVAL;
3407
3408 mtd_region[i].erasesize = erasesize;
c84b3925 3409 mtd_region[i].numblocks = div_u64(region[i].size, erasesize);
6a9eda34
TK		 3410 mtd_region[i].offset = region[i].offset;
3411 }
3412
3413 mtd->numeraseregions = map->n_regions;
3414 mtd->eraseregions = mtd_region;
3415
3416 return 0;
3417}
3418
3419static int spi_nor_set_mtd_info(struct spi_nor *nor)
ff67592c
TA		 3420{
3421 struct mtd_info *mtd = &nor->mtd;
3422 struct device *dev = nor->dev;
3423
3424 spi_nor_set_mtd_locking_ops(nor);
3425 spi_nor_set_mtd_otp_ops(nor);
3426
3427 mtd->dev.parent = dev;
3428 if (!mtd->name)
3429 mtd->name = dev_name(dev);
3430 mtd->type = MTD_NORFLASH;
3431 mtd->flags = MTD_CAP_NORFLASH;
9fd0945f
TK		 3432 /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */
3433 if (nor->flags & SNOR_F_ECC)
3434 mtd->flags &= ~MTD_BIT_WRITEABLE;
ff67592c
TA		 3435 if (nor->info->flags & SPI_NOR_NO_ERASE)
3436 mtd->flags |= MTD_NO_ERASE;
151c6b49
TA		 3437 else
3438 mtd->_erase = spi_nor_erase;
ff67592c
TA		 3439 mtd->writesize = nor->params->writesize;
3440 mtd->writebufsize = nor->params->page_size;
3441 mtd->size = nor->params->size;
ff67592c
TA		 3442 mtd->_read = spi_nor_read;
3443 /* Might be already set by some SST flashes. */
3444 if (!mtd->_write)
3445 mtd->_write = spi_nor_write;
3446 mtd->_suspend = spi_nor_suspend;
3447 mtd->_resume = spi_nor_resume;
3448 mtd->_get_device = spi_nor_get_device;
3449 mtd->_put_device = spi_nor_put_device;
6a9eda34
TK		 3450
3451 if (!spi_nor_has_uniform_erase(nor))
3452 return spi_nor_set_mtd_eraseregions(nor);
3453
3454 return 0;
ff67592c
TA		 3455}
3456
8f1ee9ef
SKP		 3457static int spi_nor_hw_reset(struct spi_nor *nor)
3458{
3459 struct gpio_desc *reset;
3460
3461 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW);
3462 if (IS_ERR_OR_NULL(reset))
3463 return PTR_ERR_OR_ZERO(reset);
3464
3465 /*
3466 * Experimental delay values by looking at different flash device
3467 * vendors datasheets.
3468 */
3469 usleep_range(1, 5);
3470 gpiod_set_value_cansleep(reset, 1);
3471 usleep_range(100, 150);
3472 gpiod_set_value_cansleep(reset, 0);
3473 usleep_range(1000, 1200);
3474
3475 return 0;
3476}
3477
cfc5604c
CP		 3478int spi_nor_scan(struct spi_nor *nor, const char *name,
3479 const struct spi_nor_hwcaps *hwcaps)
b199489d 3480{
620df249 3481 const struct flash_info *info;
b199489d 3482 struct device *dev = nor->dev;
b199489d 3483 int ret;
b199489d
HS		 3484
3485 ret = spi_nor_check(nor);
3486 if (ret)
3487 return ret;
3488
cfc5604c
CP		 3489 /* Reset SPI protocol for all commands. */
3490 nor->reg_proto = SNOR_PROTO_1_1_1;
3491 nor->read_proto = SNOR_PROTO_1_1_1;
3492 nor->write_proto = SNOR_PROTO_1_1_1;
3493
f173f26a
VR		 3494 /*
3495 * We need the bounce buffer early to read/write registers when going
3496 * through the spi-mem layer (buffers have to be DMA-able).
b35b9a10 3497 * For spi-mem drivers, we'll reallocate a new buffer if
5854d4a6 3498 * nor->params->page_size turns out to be greater than PAGE_SIZE (which
b35b9a10
BB		 3499 * shouldn't happen before long since NOR pages are usually less
3500 * than 1KB) after spi_nor_scan() returns.
f173f26a
VR		 3501 */
3502 nor->bouncebuf_size = PAGE_SIZE;
3503 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,
3504 GFP_KERNEL);
3505 if (!nor->bouncebuf)
3506 return -ENOMEM;
3507
8f1ee9ef
SKP		 3508 ret = spi_nor_hw_reset(nor);
3509 if (ret)
3510 return ret;
3511
620df249
TA		 3512 info = spi_nor_get_flash_info(nor, name);
3513 if (IS_ERR(info))
3514 return PTR_ERR(info);
b199489d 3515
b296379f
BB		 3516 nor->info = info;
3517
b199489d
HS		 3518 mutex_init(&nor->lock);
3519
1c1d8d98 3520 /* Init flash parameters based on flash_info struct and SFDP */
829ec640
TA		 3521 ret = spi_nor_init_params(nor);
3522 if (ret)
3523 return ret;
cfc5604c 3524
74df43b3
MR		 3525 if (spi_nor_use_parallel_locking(nor))
3526 init_waitqueue_head(&nor->rww.wait);
3527
cfc5604c
CP		 3528 /*
3529 * Configure the SPI memory:
3530 * - select op codes for (Fast) Read, Page Program and Sector Erase.
3531 * - set the number of dummy cycles (mode cycles + wait states).
3532 * - set the SPI protocols for register and memory accesses.
c452d498 3533 * - set the number of address bytes.
cfc5604c 3534 */
1e35a567 3535 ret = spi_nor_setup(nor, hwcaps);
cfc5604c
CP		 3536 if (ret)
3537 return ret;
b199489d 3538
46dde01f 3539 /* Send all the required SPI flash commands to initialize device */
46dde01f
KD		 3540 ret = spi_nor_init(nor);
3541 if (ret)
3542 return ret;
3543
ff67592c 3544 /* No mtd_info fields should be used up to this point. */
6a9eda34
TK		 3545 ret = spi_nor_set_mtd_info(nor);
3546 if (ret)
3547 return ret;
069089ac 3548
9fcb0999
TA		 3549 dev_dbg(dev, "Manufacturer and device ID: %*phN\n",
3550 SPI_NOR_MAX_ID_LEN, nor->id);
b199489d 3551
b199489d
HS		 3552 return 0;
3553}
b61834b0 3554EXPORT_SYMBOL_GPL(spi_nor_scan);
b199489d 3555
df5c2100
SS		 3556static int spi_nor_create_read_dirmap(struct spi_nor *nor)
3557{
3558 struct spi_mem_dirmap_info info = {
0e30f472 3559 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
c452d498 3560 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
0e30f472
PY		 3561 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
3562 SPI_MEM_OP_DATA_IN(0, NULL, 0)),
df5c2100 3563 .offset = 0,
eb726c32 3564 .length = nor->params->size,
df5c2100
SS		 3565 };
3566 struct spi_mem_op *op = &info.op_tmpl;
3567
0e30f472 3568 spi_nor_spimem_setup_op(nor, op, nor->read_proto);
df5c2100
SS		 3569
3570 /* convert the dummy cycles to the number of bytes */
3571 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;
0e30f472
PY		 3572 if (spi_nor_protocol_is_dtr(nor->read_proto))
3573 op->dummy.nbytes *= 2;
3574
3575 /*
3576 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3577 * of data bytes is non-zero, the data buswidth won't be set here. So,
3578 * do it explicitly.
3579 */
3580 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
df5c2100
SS		 3581
3582 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3583 &info);
3584 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);
3585}
3586
3587static int spi_nor_create_write_dirmap(struct spi_nor *nor)
3588{
3589 struct spi_mem_dirmap_info info = {
0e30f472 3590 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
c452d498 3591 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
df5c2100 3592 SPI_MEM_OP_NO_DUMMY,
0e30f472 3593 SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
df5c2100 3594 .offset = 0,
eb726c32 3595 .length = nor->params->size,
df5c2100
SS		 3596 };
3597 struct spi_mem_op *op = &info.op_tmpl;
3598
df5c2100
SS		 3599 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
3600 op->addr.nbytes = 0;
3601
0e30f472
PY		 3602 spi_nor_spimem_setup_op(nor, op, nor->write_proto);
3603
3604 /*
3605 * Since spi_nor_spimem_setup_op() only sets buswidth when the number
3606 * of data bytes is non-zero, the data buswidth won't be set here. So,
3607 * do it explicitly.
3608 */
3609 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
3610
df5c2100
SS		 3611 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,
3612 &info);
3613 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
3614}
3615
b35b9a10
BB		 3616static int spi_nor_probe(struct spi_mem *spimem)
3617{
3618 struct spi_device *spi = spimem->spi;
3619 struct flash_platform_data *data = dev_get_platdata(&spi->dev);
3620 struct spi_nor *nor;
c76f5089
BB		 3621 /*
3622 * Enable all caps by default. The core will mask them after
3623 * checking what's really supported using spi_mem_supports_op().
3624 */
3625 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };
b35b9a10
BB		 3626 char *flash_name;
3627 int ret;
3628
3629 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);
3630 if (!nor)
3631 return -ENOMEM;
3632
3633 nor->spimem = spimem;
3634 nor->dev = &spi->dev;
3635 spi_nor_set_flash_node(nor, spi->dev.of_node);
3636
3637 spi_mem_set_drvdata(spimem, nor);
3638
b35b9a10
BB		 3639 if (data && data->name)
3640 nor->mtd.name = data->name;
3641
3642 if (!nor->mtd.name)
3643 nor->mtd.name = spi_mem_get_name(spimem);
3644
3645 /*
3646 * For some (historical?) reason many platforms provide two different
3647 * names in flash_platform_data: "name" and "type". Quite often name is
3648 * set to "m25p80" and then "type" provides a real chip name.
3649 * If that's the case, respect "type" and ignore a "name".
3650 */
3651 if (data && data->type)
3652 flash_name = data->type;
3653 else if (!strcmp(spi->modalias, "spi-nor"))
3654 flash_name = NULL; /* auto-detect */
3655 else
3656 flash_name = spi->modalias;
3657
3658 ret = spi_nor_scan(nor, flash_name, &hwcaps);
3659 if (ret)
3660 return ret;
3661
0257be79
MW		 3662 spi_nor_debugfs_register(nor);
3663
b35b9a10
BB		 3664 /*
3665 * None of the existing parts have > 512B pages, but let's play safe
3666 * and add this logic so that if anyone ever adds support for such
3667 * a NOR we don't end up with buffer overflows.
3668 */
5854d4a6
TA		 3669 if (nor->params->page_size > PAGE_SIZE) {
3670 nor->bouncebuf_size = nor->params->page_size;
b35b9a10
BB		 3671 devm_kfree(nor->dev, nor->bouncebuf);
3672 nor->bouncebuf = devm_kmalloc(nor->dev,
3673 nor->bouncebuf_size,
3674 GFP_KERNEL);
3675 if (!nor->bouncebuf)
3676 return -ENOMEM;
3677 }
3678
df5c2100
SS		 3679 ret = spi_nor_create_read_dirmap(nor);
3680 if (ret)
3681 return ret;
3682
3683 ret = spi_nor_create_write_dirmap(nor);
3684 if (ret)
3685 return ret;
3686
b35b9a10
BB		 3687 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
3688 data ? data->nr_parts : 0);
3689}
3690
3691static int spi_nor_remove(struct spi_mem *spimem)
3692{
3693 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3694
3695 spi_nor_restore(nor);
3696
3697 /* Clean up MTD stuff. */
3698 return mtd_device_unregister(&nor->mtd);
3699}
3700
3701static void spi_nor_shutdown(struct spi_mem *spimem)
3702{
3703 struct spi_nor *nor = spi_mem_get_drvdata(spimem);
3704
3705 spi_nor_restore(nor);
3706}
3707
3708/*
3709 * Do NOT add to this array without reading the following:
3710 *
3711 * Historically, many flash devices are bound to this driver by their name. But
3712 * since most of these flash are compatible to some extent, and their
3713 * differences can often be differentiated by the JEDEC read-ID command, we
3714 * encourage new users to add support to the spi-nor library, and simply bind
3715 * against a generic string here (e.g., "jedec,spi-nor").
3716 *
e7ad9f59
FS		 3717 * Many flash names are kept here in this list to keep them available
3718 * as module aliases for existing platforms.
b35b9a10
BB		 3719 */
3720static const struct spi_device_id spi_nor_dev_ids[] = {
3721 /*
3722 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and
3723 * hack around the fact that the SPI core does not provide uevent
3724 * matching for .of_match_table
3725 */
3726 {"spi-nor"},
3727
3728 /*
3729 * Entries not used in DTs that should be safe to drop after replacing
3730 * them with "spi-nor" in platform data.
3731 */
3732 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
3733
3734 /*
3735 * Entries that were used in DTs without "jedec,spi-nor" fallback and
3736 * should be kept for backward compatibility.
3737 */
3738 {"at25df321a"}, {"at25df641"}, {"at26df081a"},
3739 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
3740 {"mx25l25635e"},{"mx66l51235l"},
3741 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
3742 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
3743 {"s25fl064k"},
3744 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
3745 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
3746 {"m25p64"}, {"m25p128"},
3747 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
3748 {"w25q80bl"}, {"w25q128"}, {"w25q256"},
3749
3750 /* Flashes that can't be detected using JEDEC */
3751 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
3752 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
3753 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
3754
3755 /* Everspin MRAMs (non-JEDEC) */
3756 { "mr25h128" }, /* 128 Kib, 40 MHz */
3757 { "mr25h256" }, /* 256 Kib, 40 MHz */
3758 { "mr25h10" }, /* 1 Mib, 40 MHz */
3759 { "mr25h40" }, /* 4 Mib, 40 MHz */
3760
3761 { },
3762};
3763MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);
3764
3765static const struct of_device_id spi_nor_of_table[] = {
3766 /*
3767 * Generic compatibility for SPI NOR that can be identified by the
3768 * JEDEC READ ID opcode (0x9F). Use this, if possible.
3769 */
3770 { .compatible = "jedec,spi-nor" },
3771 { /* sentinel */ },
3772};
3773MODULE_DEVICE_TABLE(of, spi_nor_of_table);
3774
3775/*
3776 * REVISIT: many of these chips have deep power-down modes, which
3777 * should clearly be entered on suspend() to minimize power use.
3778 * And also when they're otherwise idle...
3779 */
3780static struct spi_mem_driver spi_nor_driver = {
3781 .spidrv = {
3782 .driver = {
3783 .name = "spi-nor",
3784 .of_match_table = spi_nor_of_table,
36ac0228 3785 .dev_groups = spi_nor_sysfs_groups,
b35b9a10
BB		 3786 },
3787 .id_table = spi_nor_dev_ids,
3788 },
3789 .probe = spi_nor_probe,
3790 .remove = spi_nor_remove,
3791 .shutdown = spi_nor_shutdown,
3792};
ec738ca1
GKH		 3793
3794static int __init spi_nor_module_init(void)
3795{
3796 return spi_mem_driver_register(&spi_nor_driver);
3797}
3798module_init(spi_nor_module_init);
3799
3800static void __exit spi_nor_module_exit(void)
3801{
3802 spi_mem_driver_unregister(&spi_nor_driver);
3803 spi_nor_debugfs_shutdown();
3804}
3805module_exit(spi_nor_module_exit);
b35b9a10 3806
e9f3a2bc 3807MODULE_LICENSE("GPL v2");
b199489d
HS		 3808MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
3809MODULE_AUTHOR("Mike Lavender");
3810MODULE_DESCRIPTION("framework for SPI NOR");
Linux 6.x block layer and io_uring tree(s)