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Merge branch 'opp/fixes-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / mtd / spi-nor / atmel-quadspi.c
CommitLineData
161aaab8
CP		 1/*
2 * Driver for Atmel QSPI Controller
3 *
4 * Copyright (C) 2015 Atmel Corporation
5 *
6 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 *
20 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
21 */
22
23#include <linux/kernel.h>
24#include <linux/clk.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/interrupt.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/spi-nor.h>
33#include <linux/platform_data/atmel.h>
34#include <linux/of.h>
35
36#include <linux/io.h>
261b354c 37#include <linux/gpio/consumer.h>
161aaab8
CP		 38
39/* QSPI register offsets */
40#define QSPI_CR 0x0000 /* Control Register */
41#define QSPI_MR 0x0004 /* Mode Register */
42#define QSPI_RD 0x0008 /* Receive Data Register */
43#define QSPI_TD 0x000c /* Transmit Data Register */
44#define QSPI_SR 0x0010 /* Status Register */
45#define QSPI_IER 0x0014 /* Interrupt Enable Register */
46#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
47#define QSPI_IMR 0x001c /* Interrupt Mask Register */
48#define QSPI_SCR 0x0020 /* Serial Clock Register */
49
50#define QSPI_IAR 0x0030 /* Instruction Address Register */
51#define QSPI_ICR 0x0034 /* Instruction Code Register */
52#define QSPI_IFR 0x0038 /* Instruction Frame Register */
53
54#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
55#define QSPI_SKR 0x0044 /* Scrambling Key Register */
56
57#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
58#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
59
60#define QSPI_VERSION 0x00FC /* Version Register */
61
62
63/* Bitfields in QSPI_CR (Control Register) */
64#define QSPI_CR_QSPIEN BIT(0)
65#define QSPI_CR_QSPIDIS BIT(1)
66#define QSPI_CR_SWRST BIT(7)
67#define QSPI_CR_LASTXFER BIT(24)
68
69/* Bitfields in QSPI_MR (Mode Register) */
70#define QSPI_MR_SSM BIT(0)
71#define QSPI_MR_LLB BIT(1)
72#define QSPI_MR_WDRBT BIT(2)
73#define QSPI_MR_SMRM BIT(3)
74#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
75#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
76#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
77#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
78#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
79#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
80#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
81#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
82#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
83#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
84
85/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
86#define QSPI_SR_RDRF BIT(0)
87#define QSPI_SR_TDRE BIT(1)
88#define QSPI_SR_TXEMPTY BIT(2)
89#define QSPI_SR_OVRES BIT(3)
90#define QSPI_SR_CSR BIT(8)
91#define QSPI_SR_CSS BIT(9)
92#define QSPI_SR_INSTRE BIT(10)
93#define QSPI_SR_QSPIENS BIT(24)
94
95#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
96
97/* Bitfields in QSPI_SCR (Serial Clock Register) */
98#define QSPI_SCR_CPOL BIT(0)
99#define QSPI_SCR_CPHA BIT(1)
100#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
101#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
102#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
103#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
104
105/* Bitfields in QSPI_ICR (Instruction Code Register) */
106#define QSPI_ICR_INST_MASK GENMASK(7, 0)
107#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
108#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
109#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
110
111/* Bitfields in QSPI_IFR (Instruction Frame Register) */
112#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
113#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
114#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
115#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
116#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
117#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
118#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
119#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
120#define QSPI_IFR_INSTEN BIT(4)
121#define QSPI_IFR_ADDREN BIT(5)
122#define QSPI_IFR_OPTEN BIT(6)
123#define QSPI_IFR_DATAEN BIT(7)
124#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
125#define QSPI_IFR_OPTL_1BIT (0 << 8)
126#define QSPI_IFR_OPTL_2BIT (1 << 8)
127#define QSPI_IFR_OPTL_4BIT (2 << 8)
128#define QSPI_IFR_OPTL_8BIT (3 << 8)
129#define QSPI_IFR_ADDRL BIT(10)
130#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
131#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
132#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
133#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12)
134#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
135#define QSPI_IFR_CRM BIT(14)
136#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
137#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
138
139/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
140#define QSPI_SMR_SCREN BIT(0)
141#define QSPI_SMR_RVDIS BIT(1)
142
143/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
144#define QSPI_WPMR_WPEN BIT(0)
145#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
146#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
147
148/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
149#define QSPI_WPSR_WPVS BIT(0)
150#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
151#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
152
153
154struct atmel_qspi {
155 void __iomem *regs;
156 void __iomem *mem;
157 struct clk *clk;
158 struct platform_device *pdev;
159 u32 pending;
160
161 struct spi_nor nor;
162 u32 clk_rate;
163 struct completion cmd_completion;
164};
165
166struct atmel_qspi_command {
167 union {
168 struct {
169 u32 instruction:1;
170 u32 address:3;
171 u32 mode:1;
172 u32 dummy:1;
173 u32 data:1;
174 u32 reserved:25;
175 } bits;
176 u32 word;
177 } enable;
178 u8 instruction;
179 u8 mode;
180 u8 num_mode_cycles;
181 u8 num_dummy_cycles;
182 u32 address;
183
184 size_t buf_len;
185 const void *tx_buf;
186 void *rx_buf;
187};
188
189/* Register access functions */
190static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
191{
192 return readl_relaxed(aq->regs + reg);
193}
194
195static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
196{
197 writel_relaxed(value, aq->regs + reg);
198}
199
200static int atmel_qspi_run_transfer(struct atmel_qspi *aq,
201 const struct atmel_qspi_command *cmd)
202{
203 void __iomem *ahb_mem;
204
205 /* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */
206 ahb_mem = aq->mem;
207 if (cmd->enable.bits.address)
208 ahb_mem += cmd->address;
209 if (cmd->tx_buf)
210 _memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len);
211 else
212 _memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len);
213
214 return 0;
215}
216
217#ifdef DEBUG
218static void atmel_qspi_debug_command(struct atmel_qspi *aq,
219 const struct atmel_qspi_command *cmd,
220 u32 ifr)
221{
222 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
223 size_t len = 0;
224 int i;
225
226 if (cmd->enable.bits.instruction)
227 cmd_buf[len++] = cmd->instruction;
228
229 for (i = cmd->enable.bits.address-1; i >= 0; --i)
230 cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff;
231
232 if (cmd->enable.bits.mode)
233 cmd_buf[len++] = cmd->mode;
234
235 if (cmd->enable.bits.dummy) {
236 int num = cmd->num_dummy_cycles;
237
238 switch (ifr & QSPI_IFR_WIDTH_MASK) {
239 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
240 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
241 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
242 num >>= 3;
243 break;
244 case QSPI_IFR_WIDTH_DUAL_IO:
245 case QSPI_IFR_WIDTH_DUAL_CMD:
246 num >>= 2;
247 break;
248 case QSPI_IFR_WIDTH_QUAD_IO:
249 case QSPI_IFR_WIDTH_QUAD_CMD:
250 num >>= 1;
251 break;
252 default:
253 return;
254 }
255
256 for (i = 0; i < num; ++i)
257 cmd_buf[len++] = 0;
258 }
259
260 /* Dump the SPI command */
261 print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE,
262 32, 1, cmd_buf, len, false);
263
264#ifdef VERBOSE_DEBUG
265 /* If verbose debug is enabled, also dump the TX data */
266 if (cmd->enable.bits.data && cmd->tx_buf)
267 print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE,
268 32, 1, cmd->tx_buf, cmd->buf_len, false);
269#endif
270}
271#else
272#define atmel_qspi_debug_command(aq, cmd, ifr)
273#endif
274
275static int atmel_qspi_run_command(struct atmel_qspi *aq,
276 const struct atmel_qspi_command *cmd,
cfc5604c 277 u32 ifr_tfrtyp, enum spi_nor_protocol proto)
161aaab8
CP		 278{
279 u32 iar, icr, ifr, sr;
280 int err = 0;
281
282 iar = 0;
283 icr = 0;
cfc5604c
CP		 284 ifr = ifr_tfrtyp;
285
286 /* Set the SPI protocol */
287 switch (proto) {
288 case SNOR_PROTO_1_1_1:
289 ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
290 break;
291
292 case SNOR_PROTO_1_1_2:
293 ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT;
294 break;
295
296 case SNOR_PROTO_1_1_4:
297 ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT;
298 break;
299
300 case SNOR_PROTO_1_2_2:
301 ifr |= QSPI_IFR_WIDTH_DUAL_IO;
302 break;
303
304 case SNOR_PROTO_1_4_4:
305 ifr |= QSPI_IFR_WIDTH_QUAD_IO;
306 break;
307
308 case SNOR_PROTO_2_2_2:
309 ifr |= QSPI_IFR_WIDTH_DUAL_CMD;
310 break;
311
312 case SNOR_PROTO_4_4_4:
313 ifr |= QSPI_IFR_WIDTH_QUAD_CMD;
314 break;
315
316 default:
317 return -EINVAL;
318 }
161aaab8
CP		 319
320 /* Compute instruction parameters */
321 if (cmd->enable.bits.instruction) {
322 icr |= QSPI_ICR_INST(cmd->instruction);
323 ifr |= QSPI_IFR_INSTEN;
324 }
325
326 /* Compute address parameters */
327 switch (cmd->enable.bits.address) {
328 case 4:
329 ifr |= QSPI_IFR_ADDRL;
330 /* fall through to the 24bit (3 byte) address case. */
331 case 3:
332 iar = (cmd->enable.bits.data) ? 0 : cmd->address;
333 ifr |= QSPI_IFR_ADDREN;
334 break;
335 case 0:
336 break;
337 default:
338 return -EINVAL;
339 }
340
341 /* Compute option parameters */
342 if (cmd->enable.bits.mode && cmd->num_mode_cycles) {
343 u32 mode_cycle_bits, mode_bits;
344
345 icr |= QSPI_ICR_OPT(cmd->mode);
346 ifr |= QSPI_IFR_OPTEN;
347
348 switch (ifr & QSPI_IFR_WIDTH_MASK) {
349 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
350 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
351 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
352 mode_cycle_bits = 1;
353 break;
354 case QSPI_IFR_WIDTH_DUAL_IO:
355 case QSPI_IFR_WIDTH_DUAL_CMD:
356 mode_cycle_bits = 2;
357 break;
358 case QSPI_IFR_WIDTH_QUAD_IO:
359 case QSPI_IFR_WIDTH_QUAD_CMD:
360 mode_cycle_bits = 4;
361 break;
362 default:
363 return -EINVAL;
364 }
365
366 mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
367 switch (mode_bits) {
368 case 1:
369 ifr |= QSPI_IFR_OPTL_1BIT;
370 break;
371
372 case 2:
373 ifr |= QSPI_IFR_OPTL_2BIT;
374 break;
375
376 case 4:
377 ifr |= QSPI_IFR_OPTL_4BIT;
378 break;
379
380 case 8:
381 ifr |= QSPI_IFR_OPTL_8BIT;
382 break;
383
384 default:
385 return -EINVAL;
386 }
387 }
388
389 /* Set number of dummy cycles */
390 if (cmd->enable.bits.dummy)
391 ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
392
393 /* Set data enable */
394 if (cmd->enable.bits.data) {
395 ifr |= QSPI_IFR_DATAEN;
396
397 /* Special case for Continuous Read Mode */
398 if (!cmd->tx_buf && !cmd->rx_buf)
399 ifr |= QSPI_IFR_CRM;
400 }
401
402 /* Clear pending interrupts */
403 (void)qspi_readl(aq, QSPI_SR);
404
405 /* Set QSPI Instruction Frame registers */
406 atmel_qspi_debug_command(aq, cmd, ifr);
407 qspi_writel(aq, QSPI_IAR, iar);
408 qspi_writel(aq, QSPI_ICR, icr);
409 qspi_writel(aq, QSPI_IFR, ifr);
410
411 /* Skip to the final steps if there is no data */
412 if (!cmd->enable.bits.data)
413 goto no_data;
414
415 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
416 (void)qspi_readl(aq, QSPI_IFR);
417
418 /* Stop here for continuous read */
419 if (!cmd->tx_buf && !cmd->rx_buf)
420 return 0;
421 /* Send/Receive data */
422 err = atmel_qspi_run_transfer(aq, cmd);
423
424 /* Release the chip-select */
425 qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
426
427 if (err)
428 return err;
429
430#if defined(DEBUG) && defined(VERBOSE_DEBUG)
431 /*
432 * If verbose debug is enabled, also dump the RX data in addition to
433 * the SPI command previously dumped by atmel_qspi_debug_command()
434 */
435 if (cmd->rx_buf)
436 print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE,
437 32, 1, cmd->rx_buf, cmd->buf_len, false);
438#endif
439no_data:
440 /* Poll INSTRuction End status */
441 sr = qspi_readl(aq, QSPI_SR);
442 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
443 return err;
444
445 /* Wait for INSTRuction End interrupt */
446 reinit_completion(&aq->cmd_completion);
447 aq->pending = sr & QSPI_SR_CMD_COMPLETED;
448 qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
449 if (!wait_for_completion_timeout(&aq->cmd_completion,
450 msecs_to_jiffies(1000)))
451 err = -ETIMEDOUT;
452 qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
453
454 return err;
455}
456
457static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
458 u8 *buf, int len)
459{
460 struct atmel_qspi *aq = nor->priv;
461 struct atmel_qspi_command cmd;
462
463 memset(&cmd, 0, sizeof(cmd));
464 cmd.enable.bits.instruction = 1;
465 cmd.enable.bits.data = 1;
466 cmd.instruction = opcode;
467 cmd.rx_buf = buf;
468 cmd.buf_len = len;
469 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
cfc5604c 470 nor->reg_proto);
161aaab8
CP		 471}
472
473static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
474 u8 *buf, int len)
475{
476 struct atmel_qspi *aq = nor->priv;
477 struct atmel_qspi_command cmd;
478
479 memset(&cmd, 0, sizeof(cmd));
480 cmd.enable.bits.instruction = 1;
481 cmd.enable.bits.data = (buf != NULL && len > 0);
482 cmd.instruction = opcode;
483 cmd.tx_buf = buf;
484 cmd.buf_len = len;
485 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
cfc5604c 486 nor->reg_proto);
161aaab8
CP		 487}
488
489static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
490 const u_char *write_buf)
491{
492 struct atmel_qspi *aq = nor->priv;
493 struct atmel_qspi_command cmd;
494 ssize_t ret;
495
496 memset(&cmd, 0, sizeof(cmd));
497 cmd.enable.bits.instruction = 1;
498 cmd.enable.bits.address = nor->addr_width;
499 cmd.enable.bits.data = 1;
500 cmd.instruction = nor->program_opcode;
501 cmd.address = (u32)to;
502 cmd.tx_buf = write_buf;
503 cmd.buf_len = len;
504 ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
cfc5604c 505 nor->write_proto);
161aaab8
CP		 506 return (ret < 0) ? ret : len;
507}
508
509static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
510{
511 struct atmel_qspi *aq = nor->priv;
512 struct atmel_qspi_command cmd;
513
514 memset(&cmd, 0, sizeof(cmd));
515 cmd.enable.bits.instruction = 1;
516 cmd.enable.bits.address = nor->addr_width;
517 cmd.instruction = nor->erase_opcode;
518 cmd.address = (u32)offs;
519 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
cfc5604c 520 nor->reg_proto);
161aaab8
CP		 521}
522
523static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
524 u_char *read_buf)
525{
526 struct atmel_qspi *aq = nor->priv;
527 struct atmel_qspi_command cmd;
528 u8 num_mode_cycles, num_dummy_cycles;
161aaab8
CP		 529 ssize_t ret;
530
161aaab8
CP		 531 if (nor->read_dummy >= 2) {
532 num_mode_cycles = 2;
533 num_dummy_cycles = nor->read_dummy - 2;
534 } else {
535 num_mode_cycles = nor->read_dummy;
536 num_dummy_cycles = 0;
537 }
538
539 memset(&cmd, 0, sizeof(cmd));
540 cmd.enable.bits.instruction = 1;
541 cmd.enable.bits.address = nor->addr_width;
542 cmd.enable.bits.mode = (num_mode_cycles > 0);
543 cmd.enable.bits.dummy = (num_dummy_cycles > 0);
544 cmd.enable.bits.data = 1;
545 cmd.instruction = nor->read_opcode;
546 cmd.address = (u32)from;
547 cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */
548 cmd.num_mode_cycles = num_mode_cycles;
549 cmd.num_dummy_cycles = num_dummy_cycles;
550 cmd.rx_buf = read_buf;
551 cmd.buf_len = len;
552 ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
cfc5604c 553 nor->read_proto);
161aaab8
CP		 554 return (ret < 0) ? ret : len;
555}
556
557static int atmel_qspi_init(struct atmel_qspi *aq)
558{
559 unsigned long src_rate;
560 u32 mr, scr, scbr;
561
562 /* Reset the QSPI controller */
563 qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
564
565 /* Set the QSPI controller in Serial Memory Mode */
566 mr = QSPI_MR_NBBITS(8) | QSPI_MR_SSM;
567 qspi_writel(aq, QSPI_MR, mr);
568
569 src_rate = clk_get_rate(aq->clk);
570 if (!src_rate)
571 return -EINVAL;
572
573 /* Compute the QSPI baudrate */
574 scbr = DIV_ROUND_UP(src_rate, aq->clk_rate);
575 if (scbr > 0)
576 scbr--;
577 scr = QSPI_SCR_SCBR(scbr);
578 qspi_writel(aq, QSPI_SCR, scr);
579
580 /* Enable the QSPI controller */
581 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
582
583 return 0;
584}
585
586static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
587{
588 struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
589 u32 status, mask, pending;
590
591 status = qspi_readl(aq, QSPI_SR);
592 mask = qspi_readl(aq, QSPI_IMR);
593 pending = status & mask;
594
595 if (!pending)
596 return IRQ_NONE;
597
598 aq->pending |= pending;
599 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
600 complete(&aq->cmd_completion);
601
602 return IRQ_HANDLED;
603}
604
605static int atmel_qspi_probe(struct platform_device *pdev)
606{
cfc5604c
CP		 607 const struct spi_nor_hwcaps hwcaps = {
608 .mask = SNOR_HWCAPS_READ |
609 SNOR_HWCAPS_READ_FAST |
610 SNOR_HWCAPS_READ_1_1_2 |
611 SNOR_HWCAPS_READ_1_2_2 |
612 SNOR_HWCAPS_READ_2_2_2 |
613 SNOR_HWCAPS_READ_1_1_4 |
614 SNOR_HWCAPS_READ_1_4_4 |
615 SNOR_HWCAPS_READ_4_4_4 |
616 SNOR_HWCAPS_PP |
617 SNOR_HWCAPS_PP_1_1_4 |
618 SNOR_HWCAPS_PP_1_4_4 |
619 SNOR_HWCAPS_PP_4_4_4,
620 };
161aaab8
CP		 621 struct device_node *child, *np = pdev->dev.of_node;
622 struct atmel_qspi *aq;
623 struct resource *res;
624 struct spi_nor *nor;
625 struct mtd_info *mtd;
626 int irq, err = 0;
627
628 if (of_get_child_count(np) != 1)
629 return -ENODEV;
630 child = of_get_next_child(np, NULL);
631
632 aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
633 if (!aq) {
634 err = -ENOMEM;
635 goto exit;
636 }
637
638 platform_set_drvdata(pdev, aq);
639 init_completion(&aq->cmd_completion);
640 aq->pdev = pdev;
641
642 /* Map the registers */
643 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
644 aq->regs = devm_ioremap_resource(&pdev->dev, res);
645 if (IS_ERR(aq->regs)) {
646 dev_err(&pdev->dev, "missing registers\n");
647 err = PTR_ERR(aq->regs);
648 goto exit;
649 }
650
651 /* Map the AHB memory */
652 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
653 aq->mem = devm_ioremap_resource(&pdev->dev, res);
654 if (IS_ERR(aq->mem)) {
655 dev_err(&pdev->dev, "missing AHB memory\n");
656 err = PTR_ERR(aq->mem);
657 goto exit;
658 }
659
660 /* Get the peripheral clock */
661 aq->clk = devm_clk_get(&pdev->dev, NULL);
662 if (IS_ERR(aq->clk)) {
663 dev_err(&pdev->dev, "missing peripheral clock\n");
664 err = PTR_ERR(aq->clk);
665 goto exit;
666 }
667
668 /* Enable the peripheral clock */
669 err = clk_prepare_enable(aq->clk);
670 if (err) {
671 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
672 goto exit;
673 }
674
675 /* Request the IRQ */
676 irq = platform_get_irq(pdev, 0);
677 if (irq < 0) {
678 dev_err(&pdev->dev, "missing IRQ\n");
679 err = irq;
680 goto disable_clk;
681 }
682 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
683 0, dev_name(&pdev->dev), aq);
684 if (err)
685 goto disable_clk;
686
687 /* Setup the spi-nor */
688 nor = &aq->nor;
689 mtd = &nor->mtd;
690
691 nor->dev = &pdev->dev;
692 spi_nor_set_flash_node(nor, child);
693 nor->priv = aq;
694 mtd->priv = nor;
695
696 nor->read_reg = atmel_qspi_read_reg;
697 nor->write_reg = atmel_qspi_write_reg;
698 nor->read = atmel_qspi_read;
699 nor->write = atmel_qspi_write;
700 nor->erase = atmel_qspi_erase;
701
702 err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
703 if (err < 0)
704 goto disable_clk;
705
706 err = atmel_qspi_init(aq);
707 if (err)
708 goto disable_clk;
709
cfc5604c 710 err = spi_nor_scan(nor, NULL, &hwcaps);
161aaab8
CP		 711 if (err)
712 goto disable_clk;
713
714 err = mtd_device_register(mtd, NULL, 0);
715 if (err)
716 goto disable_clk;
717
718 of_node_put(child);
719
720 return 0;
721
722disable_clk:
723 clk_disable_unprepare(aq->clk);
724exit:
725 of_node_put(child);
726
727 return err;
728}
729
730static int atmel_qspi_remove(struct platform_device *pdev)
731{
732 struct atmel_qspi *aq = platform_get_drvdata(pdev);
733
734 mtd_device_unregister(&aq->nor.mtd);
735 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
736 clk_disable_unprepare(aq->clk);
737 return 0;
738}
739
de217c1c
CB		 740static int __maybe_unused atmel_qspi_suspend(struct device *dev)
741{
742 struct atmel_qspi *aq = dev_get_drvdata(dev);
743
744 clk_disable_unprepare(aq->clk);
745
746 return 0;
747}
748
749static int __maybe_unused atmel_qspi_resume(struct device *dev)
750{
751 struct atmel_qspi *aq = dev_get_drvdata(dev);
752
753 clk_prepare_enable(aq->clk);
754
755 return atmel_qspi_init(aq);
756}
757
758static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
759 atmel_qspi_resume);
161aaab8
CP		 760
761static const struct of_device_id atmel_qspi_dt_ids[] = {
762 { .compatible = "atmel,sama5d2-qspi" },
763 { /* sentinel */ }
764};
765
766MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
767
768static struct platform_driver atmel_qspi_driver = {
769 .driver = {
770 .name = "atmel_qspi",
771 .of_match_table = atmel_qspi_dt_ids,
de217c1c 772 .pm = &atmel_qspi_pm_ops,
161aaab8
CP		 773 },
774 .probe = atmel_qspi_probe,
775 .remove = atmel_qspi_remove,
776};
777module_platform_driver(atmel_qspi_driver);
778
779MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
780MODULE_DESCRIPTION("Atmel QSPI Controller driver");
781MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)