Commit | Line | Data |
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cd5f6346 KP |
1 | /* |
2 | * linux/drivers/mtd/onenand/onenand_base.c | |
3 | * | |
75384b0d | 4 | * Copyright (C) 2005-2007 Samsung Electronics |
cd5f6346 KP |
5 | * Kyungmin Park <kyungmin.park@samsung.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
015953d7 | 15 | #include <linux/sched.h> |
2c22120f | 16 | #include <linux/interrupt.h> |
015953d7 | 17 | #include <linux/jiffies.h> |
cd5f6346 KP |
18 | #include <linux/mtd/mtd.h> |
19 | #include <linux/mtd/onenand.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | ||
24 | /** | |
25 | * onenand_oob_64 - oob info for large (2KB) page | |
26 | */ | |
5bd34c09 | 27 | static struct nand_ecclayout onenand_oob_64 = { |
cd5f6346 KP |
28 | .eccbytes = 20, |
29 | .eccpos = { | |
30 | 8, 9, 10, 11, 12, | |
31 | 24, 25, 26, 27, 28, | |
32 | 40, 41, 42, 43, 44, | |
33 | 56, 57, 58, 59, 60, | |
34 | }, | |
35 | .oobfree = { | |
36 | {2, 3}, {14, 2}, {18, 3}, {30, 2}, | |
d9777f1c JL |
37 | {34, 3}, {46, 2}, {50, 3}, {62, 2} |
38 | } | |
cd5f6346 KP |
39 | }; |
40 | ||
41 | /** | |
42 | * onenand_oob_32 - oob info for middle (1KB) page | |
43 | */ | |
5bd34c09 | 44 | static struct nand_ecclayout onenand_oob_32 = { |
cd5f6346 KP |
45 | .eccbytes = 10, |
46 | .eccpos = { | |
47 | 8, 9, 10, 11, 12, | |
48 | 24, 25, 26, 27, 28, | |
49 | }, | |
50 | .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } | |
51 | }; | |
52 | ||
53 | static const unsigned char ffchars[] = { | |
54 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
55 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ | |
56 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
57 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ | |
58 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
59 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ | |
60 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
61 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ | |
62 | }; | |
63 | ||
64 | /** | |
65 | * onenand_readw - [OneNAND Interface] Read OneNAND register | |
66 | * @param addr address to read | |
67 | * | |
68 | * Read OneNAND register | |
69 | */ | |
70 | static unsigned short onenand_readw(void __iomem *addr) | |
71 | { | |
72 | return readw(addr); | |
73 | } | |
74 | ||
75 | /** | |
76 | * onenand_writew - [OneNAND Interface] Write OneNAND register with value | |
77 | * @param value value to write | |
78 | * @param addr address to write | |
79 | * | |
80 | * Write OneNAND register with value | |
81 | */ | |
82 | static void onenand_writew(unsigned short value, void __iomem *addr) | |
83 | { | |
84 | writew(value, addr); | |
85 | } | |
86 | ||
87 | /** | |
88 | * onenand_block_address - [DEFAULT] Get block address | |
83a36838 | 89 | * @param this onenand chip data structure |
cd5f6346 KP |
90 | * @param block the block |
91 | * @return translated block address if DDP, otherwise same | |
92 | * | |
93 | * Setup Start Address 1 Register (F100h) | |
94 | */ | |
83a36838 | 95 | static int onenand_block_address(struct onenand_chip *this, int block) |
cd5f6346 | 96 | { |
738d61f5 KP |
97 | /* Device Flash Core select, NAND Flash Block Address */ |
98 | if (block & this->density_mask) | |
99 | return ONENAND_DDP_CHIP1 | (block ^ this->density_mask); | |
cd5f6346 KP |
100 | |
101 | return block; | |
102 | } | |
103 | ||
104 | /** | |
105 | * onenand_bufferram_address - [DEFAULT] Get bufferram address | |
83a36838 | 106 | * @param this onenand chip data structure |
cd5f6346 KP |
107 | * @param block the block |
108 | * @return set DBS value if DDP, otherwise 0 | |
109 | * | |
110 | * Setup Start Address 2 Register (F101h) for DDP | |
111 | */ | |
83a36838 | 112 | static int onenand_bufferram_address(struct onenand_chip *this, int block) |
cd5f6346 | 113 | { |
738d61f5 KP |
114 | /* Device BufferRAM Select */ |
115 | if (block & this->density_mask) | |
116 | return ONENAND_DDP_CHIP1; | |
cd5f6346 | 117 | |
738d61f5 | 118 | return ONENAND_DDP_CHIP0; |
cd5f6346 KP |
119 | } |
120 | ||
121 | /** | |
122 | * onenand_page_address - [DEFAULT] Get page address | |
123 | * @param page the page address | |
124 | * @param sector the sector address | |
125 | * @return combined page and sector address | |
126 | * | |
127 | * Setup Start Address 8 Register (F107h) | |
128 | */ | |
129 | static int onenand_page_address(int page, int sector) | |
130 | { | |
131 | /* Flash Page Address, Flash Sector Address */ | |
132 | int fpa, fsa; | |
133 | ||
134 | fpa = page & ONENAND_FPA_MASK; | |
135 | fsa = sector & ONENAND_FSA_MASK; | |
136 | ||
137 | return ((fpa << ONENAND_FPA_SHIFT) | fsa); | |
138 | } | |
139 | ||
140 | /** | |
141 | * onenand_buffer_address - [DEFAULT] Get buffer address | |
142 | * @param dataram1 DataRAM index | |
143 | * @param sectors the sector address | |
144 | * @param count the number of sectors | |
145 | * @return the start buffer value | |
146 | * | |
147 | * Setup Start Buffer Register (F200h) | |
148 | */ | |
149 | static int onenand_buffer_address(int dataram1, int sectors, int count) | |
150 | { | |
151 | int bsa, bsc; | |
152 | ||
153 | /* BufferRAM Sector Address */ | |
154 | bsa = sectors & ONENAND_BSA_MASK; | |
155 | ||
156 | if (dataram1) | |
157 | bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ | |
158 | else | |
159 | bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ | |
160 | ||
161 | /* BufferRAM Sector Count */ | |
162 | bsc = count & ONENAND_BSC_MASK; | |
163 | ||
164 | return ((bsa << ONENAND_BSA_SHIFT) | bsc); | |
165 | } | |
166 | ||
167 | /** | |
168 | * onenand_command - [DEFAULT] Send command to OneNAND device | |
169 | * @param mtd MTD device structure | |
170 | * @param cmd the command to be sent | |
171 | * @param addr offset to read from or write to | |
172 | * @param len number of bytes to read or write | |
173 | * | |
174 | * Send command to OneNAND device. This function is used for middle/large page | |
175 | * devices (1KB/2KB Bytes per page) | |
176 | */ | |
177 | static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) | |
178 | { | |
179 | struct onenand_chip *this = mtd->priv; | |
493c6460 | 180 | int value, readcmd = 0, block_cmd = 0; |
cd5f6346 | 181 | int block, page; |
cd5f6346 KP |
182 | |
183 | /* Address translation */ | |
184 | switch (cmd) { | |
185 | case ONENAND_CMD_UNLOCK: | |
186 | case ONENAND_CMD_LOCK: | |
187 | case ONENAND_CMD_LOCK_TIGHT: | |
28b79ff9 | 188 | case ONENAND_CMD_UNLOCK_ALL: |
cd5f6346 KP |
189 | block = -1; |
190 | page = -1; | |
191 | break; | |
192 | ||
193 | case ONENAND_CMD_ERASE: | |
194 | case ONENAND_CMD_BUFFERRAM: | |
493c6460 KP |
195 | case ONENAND_CMD_OTP_ACCESS: |
196 | block_cmd = 1; | |
cd5f6346 KP |
197 | block = (int) (addr >> this->erase_shift); |
198 | page = -1; | |
199 | break; | |
200 | ||
201 | default: | |
202 | block = (int) (addr >> this->erase_shift); | |
203 | page = (int) (addr >> this->page_shift); | |
204 | page &= this->page_mask; | |
205 | break; | |
206 | } | |
207 | ||
208 | /* NOTE: The setting order of the registers is very important! */ | |
209 | if (cmd == ONENAND_CMD_BUFFERRAM) { | |
210 | /* Select DataRAM for DDP */ | |
83a36838 | 211 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
212 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
213 | ||
214 | /* Switch to the next data buffer */ | |
215 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | if (block != -1) { | |
221 | /* Write 'DFS, FBA' of Flash */ | |
83a36838 | 222 | value = onenand_block_address(this, block); |
cd5f6346 | 223 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); |
3cecf69e | 224 | |
75287070 | 225 | if (block_cmd) { |
3cecf69e KP |
226 | /* Select DataRAM for DDP */ |
227 | value = onenand_bufferram_address(this, block); | |
228 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
229 | } | |
cd5f6346 KP |
230 | } |
231 | ||
232 | if (page != -1) { | |
60d84f97 KP |
233 | /* Now we use page size operation */ |
234 | int sectors = 4, count = 4; | |
cd5f6346 KP |
235 | int dataram; |
236 | ||
237 | switch (cmd) { | |
238 | case ONENAND_CMD_READ: | |
239 | case ONENAND_CMD_READOOB: | |
240 | dataram = ONENAND_SET_NEXT_BUFFERRAM(this); | |
241 | readcmd = 1; | |
242 | break; | |
243 | ||
244 | default: | |
245 | dataram = ONENAND_CURRENT_BUFFERRAM(this); | |
246 | break; | |
247 | } | |
248 | ||
249 | /* Write 'FPA, FSA' of Flash */ | |
250 | value = onenand_page_address(page, sectors); | |
251 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); | |
252 | ||
253 | /* Write 'BSA, BSC' of DataRAM */ | |
254 | value = onenand_buffer_address(dataram, sectors, count); | |
255 | this->write_word(value, this->base + ONENAND_REG_START_BUFFER); | |
d5c5e78a | 256 | |
cd5f6346 KP |
257 | if (readcmd) { |
258 | /* Select DataRAM for DDP */ | |
83a36838 | 259 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
260 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
261 | } | |
262 | } | |
263 | ||
264 | /* Interrupt clear */ | |
265 | this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); | |
266 | ||
267 | /* Write command */ | |
268 | this->write_word(cmd, this->base + ONENAND_REG_COMMAND); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /** | |
274 | * onenand_wait - [DEFAULT] wait until the command is done | |
275 | * @param mtd MTD device structure | |
276 | * @param state state to select the max. timeout value | |
277 | * | |
278 | * Wait for command done. This applies to all OneNAND command | |
279 | * Read can take up to 30us, erase up to 2ms and program up to 350us | |
280 | * according to general OneNAND specs | |
281 | */ | |
282 | static int onenand_wait(struct mtd_info *mtd, int state) | |
283 | { | |
284 | struct onenand_chip * this = mtd->priv; | |
285 | unsigned long timeout; | |
286 | unsigned int flags = ONENAND_INT_MASTER; | |
287 | unsigned int interrupt = 0; | |
2fd32d4a | 288 | unsigned int ctrl; |
cd5f6346 KP |
289 | |
290 | /* The 20 msec is enough */ | |
291 | timeout = jiffies + msecs_to_jiffies(20); | |
292 | while (time_before(jiffies, timeout)) { | |
293 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
294 | ||
295 | if (interrupt & flags) | |
296 | break; | |
297 | ||
298 | if (state != FL_READING) | |
299 | cond_resched(); | |
300 | } | |
301 | /* To get correct interrupt status in timeout case */ | |
302 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
303 | ||
304 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
305 | ||
306 | if (ctrl & ONENAND_CTRL_ERROR) { | |
cdc00130 | 307 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x\n", ctrl); |
f6272487 KP |
308 | if (ctrl & ONENAND_CTRL_LOCK) |
309 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error.\n"); | |
310 | return ctrl; | |
cd5f6346 KP |
311 | } |
312 | ||
313 | if (interrupt & ONENAND_INT_READ) { | |
2fd32d4a | 314 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); |
f4f91ac3 | 315 | if (ecc) { |
cdc00130 | 316 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x\n", ecc); |
b3c9f8bf | 317 | if (ecc & ONENAND_ECC_2BIT_ALL) { |
f4f91ac3 | 318 | mtd->ecc_stats.failed++; |
b3c9f8bf KP |
319 | return ecc; |
320 | } else if (ecc & ONENAND_ECC_1BIT_ALL) | |
f4f91ac3 | 321 | mtd->ecc_stats.corrected++; |
cd5f6346 | 322 | } |
9d032801 AH |
323 | } else if (state == FL_READING) { |
324 | printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
325 | return -EIO; | |
cd5f6346 KP |
326 | } |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
2c22120f KP |
331 | /* |
332 | * onenand_interrupt - [DEFAULT] onenand interrupt handler | |
333 | * @param irq onenand interrupt number | |
334 | * @param dev_id interrupt data | |
335 | * | |
336 | * complete the work | |
337 | */ | |
338 | static irqreturn_t onenand_interrupt(int irq, void *data) | |
339 | { | |
340 | struct onenand_chip *this = (struct onenand_chip *) data; | |
341 | ||
342 | /* To handle shared interrupt */ | |
343 | if (!this->complete.done) | |
344 | complete(&this->complete); | |
345 | ||
346 | return IRQ_HANDLED; | |
347 | } | |
348 | ||
349 | /* | |
350 | * onenand_interrupt_wait - [DEFAULT] wait until the command is done | |
351 | * @param mtd MTD device structure | |
352 | * @param state state to select the max. timeout value | |
353 | * | |
354 | * Wait for command done. | |
355 | */ | |
356 | static int onenand_interrupt_wait(struct mtd_info *mtd, int state) | |
357 | { | |
358 | struct onenand_chip *this = mtd->priv; | |
359 | ||
2c22120f KP |
360 | wait_for_completion(&this->complete); |
361 | ||
362 | return onenand_wait(mtd, state); | |
363 | } | |
364 | ||
365 | /* | |
366 | * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait | |
367 | * @param mtd MTD device structure | |
368 | * @param state state to select the max. timeout value | |
369 | * | |
370 | * Try interrupt based wait (It is used one-time) | |
371 | */ | |
372 | static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state) | |
373 | { | |
374 | struct onenand_chip *this = mtd->priv; | |
375 | unsigned long remain, timeout; | |
376 | ||
377 | /* We use interrupt wait first */ | |
378 | this->wait = onenand_interrupt_wait; | |
379 | ||
2c22120f KP |
380 | timeout = msecs_to_jiffies(100); |
381 | remain = wait_for_completion_timeout(&this->complete, timeout); | |
382 | if (!remain) { | |
383 | printk(KERN_INFO "OneNAND: There's no interrupt. " | |
384 | "We use the normal wait\n"); | |
385 | ||
386 | /* Release the irq */ | |
387 | free_irq(this->irq, this); | |
c9ac5977 | 388 | |
2c22120f KP |
389 | this->wait = onenand_wait; |
390 | } | |
391 | ||
392 | return onenand_wait(mtd, state); | |
393 | } | |
394 | ||
395 | /* | |
396 | * onenand_setup_wait - [OneNAND Interface] setup onenand wait method | |
397 | * @param mtd MTD device structure | |
398 | * | |
399 | * There's two method to wait onenand work | |
400 | * 1. polling - read interrupt status register | |
401 | * 2. interrupt - use the kernel interrupt method | |
402 | */ | |
403 | static void onenand_setup_wait(struct mtd_info *mtd) | |
404 | { | |
405 | struct onenand_chip *this = mtd->priv; | |
406 | int syscfg; | |
407 | ||
408 | init_completion(&this->complete); | |
409 | ||
410 | if (this->irq <= 0) { | |
411 | this->wait = onenand_wait; | |
412 | return; | |
413 | } | |
414 | ||
415 | if (request_irq(this->irq, &onenand_interrupt, | |
416 | IRQF_SHARED, "onenand", this)) { | |
417 | /* If we can't get irq, use the normal wait */ | |
418 | this->wait = onenand_wait; | |
419 | return; | |
420 | } | |
421 | ||
422 | /* Enable interrupt */ | |
423 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
424 | syscfg |= ONENAND_SYS_CFG1_IOBE; | |
425 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
426 | ||
427 | this->wait = onenand_try_interrupt_wait; | |
428 | } | |
429 | ||
cd5f6346 KP |
430 | /** |
431 | * onenand_bufferram_offset - [DEFAULT] BufferRAM offset | |
432 | * @param mtd MTD data structure | |
433 | * @param area BufferRAM area | |
434 | * @return offset given area | |
435 | * | |
436 | * Return BufferRAM offset given area | |
437 | */ | |
438 | static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) | |
439 | { | |
440 | struct onenand_chip *this = mtd->priv; | |
441 | ||
442 | if (ONENAND_CURRENT_BUFFERRAM(this)) { | |
443 | if (area == ONENAND_DATARAM) | |
28318776 | 444 | return mtd->writesize; |
cd5f6346 KP |
445 | if (area == ONENAND_SPARERAM) |
446 | return mtd->oobsize; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area | |
454 | * @param mtd MTD data structure | |
455 | * @param area BufferRAM area | |
456 | * @param buffer the databuffer to put/get data | |
457 | * @param offset offset to read from or write to | |
458 | * @param count number of bytes to read/write | |
459 | * | |
460 | * Read the BufferRAM area | |
461 | */ | |
462 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
463 | unsigned char *buffer, int offset, size_t count) | |
464 | { | |
465 | struct onenand_chip *this = mtd->priv; | |
466 | void __iomem *bufferram; | |
467 | ||
468 | bufferram = this->base + area; | |
469 | ||
470 | bufferram += onenand_bufferram_offset(mtd, area); | |
471 | ||
9c01f87d KP |
472 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
473 | unsigned short word; | |
474 | ||
475 | /* Align with word(16-bit) size */ | |
476 | count--; | |
477 | ||
478 | /* Read word and save byte */ | |
479 | word = this->read_word(bufferram + offset + count); | |
480 | buffer[count] = (word & 0xff); | |
481 | } | |
482 | ||
cd5f6346 KP |
483 | memcpy(buffer, bufferram + offset, count); |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
52b0eea7 KP |
488 | /** |
489 | * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode | |
490 | * @param mtd MTD data structure | |
491 | * @param area BufferRAM area | |
492 | * @param buffer the databuffer to put/get data | |
493 | * @param offset offset to read from or write to | |
494 | * @param count number of bytes to read/write | |
495 | * | |
496 | * Read the BufferRAM area with Sync. Burst Mode | |
497 | */ | |
498 | static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, | |
499 | unsigned char *buffer, int offset, size_t count) | |
500 | { | |
501 | struct onenand_chip *this = mtd->priv; | |
502 | void __iomem *bufferram; | |
503 | ||
504 | bufferram = this->base + area; | |
505 | ||
506 | bufferram += onenand_bufferram_offset(mtd, area); | |
507 | ||
508 | this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); | |
509 | ||
9c01f87d KP |
510 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
511 | unsigned short word; | |
512 | ||
513 | /* Align with word(16-bit) size */ | |
514 | count--; | |
515 | ||
516 | /* Read word and save byte */ | |
517 | word = this->read_word(bufferram + offset + count); | |
518 | buffer[count] = (word & 0xff); | |
519 | } | |
520 | ||
52b0eea7 KP |
521 | memcpy(buffer, bufferram + offset, count); |
522 | ||
523 | this->mmcontrol(mtd, 0); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
cd5f6346 KP |
528 | /** |
529 | * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area | |
530 | * @param mtd MTD data structure | |
531 | * @param area BufferRAM area | |
532 | * @param buffer the databuffer to put/get data | |
533 | * @param offset offset to read from or write to | |
534 | * @param count number of bytes to read/write | |
535 | * | |
536 | * Write the BufferRAM area | |
537 | */ | |
538 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
539 | const unsigned char *buffer, int offset, size_t count) | |
540 | { | |
541 | struct onenand_chip *this = mtd->priv; | |
542 | void __iomem *bufferram; | |
543 | ||
544 | bufferram = this->base + area; | |
545 | ||
546 | bufferram += onenand_bufferram_offset(mtd, area); | |
547 | ||
9c01f87d KP |
548 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
549 | unsigned short word; | |
550 | int byte_offset; | |
551 | ||
552 | /* Align with word(16-bit) size */ | |
553 | count--; | |
554 | ||
555 | /* Calculate byte access offset */ | |
556 | byte_offset = offset + count; | |
557 | ||
558 | /* Read word and save byte */ | |
559 | word = this->read_word(bufferram + byte_offset); | |
560 | word = (word & ~0xff) | buffer[count]; | |
561 | this->write_word(word, bufferram + byte_offset); | |
562 | } | |
563 | ||
cd5f6346 KP |
564 | memcpy(bufferram + offset, buffer, count); |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | /** | |
570 | * onenand_check_bufferram - [GENERIC] Check BufferRAM information | |
571 | * @param mtd MTD data structure | |
572 | * @param addr address to check | |
d5c5e78a | 573 | * @return 1 if there are valid data, otherwise 0 |
cd5f6346 KP |
574 | * |
575 | * Check bufferram if there is data we required | |
576 | */ | |
577 | static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) | |
578 | { | |
579 | struct onenand_chip *this = mtd->priv; | |
580 | int block, page; | |
581 | int i; | |
d5c5e78a | 582 | |
cd5f6346 | 583 | block = (int) (addr >> this->erase_shift); |
75384b0d | 584 | page = (int) (addr >> this->page_shift) & this->page_mask; |
cd5f6346 KP |
585 | |
586 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
587 | ||
588 | /* Is there valid data? */ | |
589 | if (this->bufferram[i].block == block && | |
590 | this->bufferram[i].page == page && | |
591 | this->bufferram[i].valid) | |
592 | return 1; | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | /** | |
598 | * onenand_update_bufferram - [GENERIC] Update BufferRAM information | |
599 | * @param mtd MTD data structure | |
600 | * @param addr address to update | |
601 | * @param valid valid flag | |
602 | * | |
603 | * Update BufferRAM information | |
604 | */ | |
605 | static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, | |
606 | int valid) | |
607 | { | |
608 | struct onenand_chip *this = mtd->priv; | |
609 | int block, page; | |
610 | int i; | |
d5c5e78a | 611 | |
cd5f6346 | 612 | block = (int) (addr >> this->erase_shift); |
75384b0d | 613 | page = (int) (addr >> this->page_shift) & this->page_mask; |
cd5f6346 KP |
614 | |
615 | /* Invalidate BufferRAM */ | |
616 | for (i = 0; i < MAX_BUFFERRAM; i++) { | |
617 | if (this->bufferram[i].block == block && | |
618 | this->bufferram[i].page == page) | |
619 | this->bufferram[i].valid = 0; | |
620 | } | |
621 | ||
622 | /* Update BufferRAM */ | |
623 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
624 | this->bufferram[i].block = block; | |
625 | this->bufferram[i].page = page; | |
626 | this->bufferram[i].valid = valid; | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | /** | |
632 | * onenand_get_device - [GENERIC] Get chip for selected access | |
633 | * @param mtd MTD device structure | |
634 | * @param new_state the state which is requested | |
635 | * | |
636 | * Get the device and lock it for exclusive access | |
637 | */ | |
a41371eb | 638 | static int onenand_get_device(struct mtd_info *mtd, int new_state) |
cd5f6346 KP |
639 | { |
640 | struct onenand_chip *this = mtd->priv; | |
641 | DECLARE_WAITQUEUE(wait, current); | |
642 | ||
643 | /* | |
644 | * Grab the lock and see if the device is available | |
645 | */ | |
646 | while (1) { | |
647 | spin_lock(&this->chip_lock); | |
648 | if (this->state == FL_READY) { | |
649 | this->state = new_state; | |
650 | spin_unlock(&this->chip_lock); | |
651 | break; | |
652 | } | |
a41371eb KP |
653 | if (new_state == FL_PM_SUSPENDED) { |
654 | spin_unlock(&this->chip_lock); | |
655 | return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; | |
656 | } | |
cd5f6346 KP |
657 | set_current_state(TASK_UNINTERRUPTIBLE); |
658 | add_wait_queue(&this->wq, &wait); | |
659 | spin_unlock(&this->chip_lock); | |
660 | schedule(); | |
661 | remove_wait_queue(&this->wq, &wait); | |
662 | } | |
a41371eb KP |
663 | |
664 | return 0; | |
cd5f6346 KP |
665 | } |
666 | ||
667 | /** | |
668 | * onenand_release_device - [GENERIC] release chip | |
669 | * @param mtd MTD device structure | |
670 | * | |
671 | * Deselect, release chip lock and wake up anyone waiting on the device | |
672 | */ | |
673 | static void onenand_release_device(struct mtd_info *mtd) | |
674 | { | |
675 | struct onenand_chip *this = mtd->priv; | |
676 | ||
677 | /* Release the chip */ | |
678 | spin_lock(&this->chip_lock); | |
679 | this->state = FL_READY; | |
680 | wake_up(&this->wq); | |
681 | spin_unlock(&this->chip_lock); | |
682 | } | |
683 | ||
684 | /** | |
9223a456 | 685 | * onenand_read - [MTD Interface] Read data from flash |
cd5f6346 KP |
686 | * @param mtd MTD device structure |
687 | * @param from offset to read from | |
688 | * @param len number of bytes to read | |
689 | * @param retlen pointer to variable to store the number of read bytes | |
690 | * @param buf the databuffer to put data | |
cd5f6346 | 691 | * |
9223a456 TG |
692 | * Read with ecc |
693 | */ | |
694 | static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
695 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
696 | { |
697 | struct onenand_chip *this = mtd->priv; | |
f4f91ac3 | 698 | struct mtd_ecc_stats stats; |
cd5f6346 KP |
699 | int read = 0, column; |
700 | int thislen; | |
0fc2ccea | 701 | int ret = 0, boundary = 0; |
cd5f6346 | 702 | |
9223a456 | 703 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); |
cd5f6346 KP |
704 | |
705 | /* Do not allow reads past end of device */ | |
706 | if ((from + len) > mtd->size) { | |
9223a456 | 707 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read: Attempt read beyond end of device\n"); |
cd5f6346 KP |
708 | *retlen = 0; |
709 | return -EINVAL; | |
710 | } | |
711 | ||
712 | /* Grab the lock and see if the device is available */ | |
713 | onenand_get_device(mtd, FL_READING); | |
714 | ||
f4f91ac3 | 715 | stats = mtd->ecc_stats; |
61a7e198 | 716 | |
a8de85d5 AH |
717 | /* Read-while-load method */ |
718 | ||
719 | /* Do first load to bufferRAM */ | |
720 | if (read < len) { | |
721 | if (!onenand_check_bufferram(mtd, from)) { | |
722 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
723 | ret = this->wait(mtd, FL_READING); | |
724 | onenand_update_bufferram(mtd, from, !ret); | |
725 | } | |
726 | } | |
727 | ||
728 | thislen = min_t(int, mtd->writesize, len - read); | |
729 | column = from & (mtd->writesize - 1); | |
730 | if (column + thislen > mtd->writesize) | |
731 | thislen = mtd->writesize - column; | |
732 | ||
733 | while (!ret) { | |
734 | /* If there is more to load then start next load */ | |
735 | from += thislen; | |
736 | if (read + thislen < len) { | |
737 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
0fc2ccea AH |
738 | /* |
739 | * Chip boundary handling in DDP | |
740 | * Now we issued chip 1 read and pointed chip 1 | |
741 | * bufferam so we have to point chip 0 bufferam. | |
742 | */ | |
738d61f5 KP |
743 | if (ONENAND_IS_DDP(this) && |
744 | unlikely(from == (this->chipsize >> 1))) { | |
745 | this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); | |
0fc2ccea AH |
746 | boundary = 1; |
747 | } else | |
748 | boundary = 0; | |
a8de85d5 AH |
749 | ONENAND_SET_PREV_BUFFERRAM(this); |
750 | } | |
751 | /* While load is going, read from last bufferRAM */ | |
752 | this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); | |
753 | /* See if we are done */ | |
754 | read += thislen; | |
755 | if (read == len) | |
756 | break; | |
757 | /* Set up for next read from bufferRAM */ | |
0fc2ccea | 758 | if (unlikely(boundary)) |
738d61f5 | 759 | this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); |
a8de85d5 AH |
760 | ONENAND_SET_NEXT_BUFFERRAM(this); |
761 | buf += thislen; | |
762 | thislen = min_t(int, mtd->writesize, len - read); | |
763 | column = 0; | |
764 | cond_resched(); | |
765 | /* Now wait for load */ | |
766 | ret = this->wait(mtd, FL_READING); | |
767 | onenand_update_bufferram(mtd, from, !ret); | |
768 | } | |
cd5f6346 | 769 | |
cd5f6346 KP |
770 | /* Deselect and wake up anyone waiting on the device */ |
771 | onenand_release_device(mtd); | |
772 | ||
773 | /* | |
774 | * Return success, if no ECC failures, else -EBADMSG | |
775 | * fs driver will take care of that, because | |
776 | * retlen == desired len and result == -EBADMSG | |
777 | */ | |
778 | *retlen = read; | |
f4f91ac3 KP |
779 | |
780 | if (mtd->ecc_stats.failed - stats.failed) | |
781 | return -EBADMSG; | |
782 | ||
a8de85d5 AH |
783 | if (ret) |
784 | return ret; | |
785 | ||
f4f91ac3 | 786 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; |
cd5f6346 KP |
787 | } |
788 | ||
cd5f6346 | 789 | /** |
8593fbc6 | 790 | * onenand_do_read_oob - [MTD Interface] OneNAND read out-of-band |
cd5f6346 KP |
791 | * @param mtd MTD device structure |
792 | * @param from offset to read from | |
793 | * @param len number of bytes to read | |
794 | * @param retlen pointer to variable to store the number of read bytes | |
795 | * @param buf the databuffer to put data | |
796 | * | |
797 | * OneNAND read out-of-band data from the spare area | |
798 | */ | |
8593fbc6 TG |
799 | int onenand_do_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
800 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
801 | { |
802 | struct onenand_chip *this = mtd->priv; | |
803 | int read = 0, thislen, column; | |
804 | int ret = 0; | |
805 | ||
806 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); | |
807 | ||
808 | /* Initialize return length value */ | |
809 | *retlen = 0; | |
810 | ||
811 | /* Do not allow reads past end of device */ | |
812 | if (unlikely((from + len) > mtd->size)) { | |
813 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n"); | |
814 | return -EINVAL; | |
815 | } | |
816 | ||
817 | /* Grab the lock and see if the device is available */ | |
818 | onenand_get_device(mtd, FL_READING); | |
819 | ||
820 | column = from & (mtd->oobsize - 1); | |
821 | ||
822 | while (read < len) { | |
61a7e198 AB |
823 | cond_resched(); |
824 | ||
cd5f6346 KP |
825 | thislen = mtd->oobsize - column; |
826 | thislen = min_t(int, thislen, len); | |
827 | ||
828 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
829 | ||
830 | onenand_update_bufferram(mtd, from, 0); | |
831 | ||
832 | ret = this->wait(mtd, FL_READING); | |
833 | /* First copy data and check return value for ECC handling */ | |
834 | ||
835 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
836 | ||
f6272487 KP |
837 | if (ret) { |
838 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = 0x%x\n", ret); | |
839 | goto out; | |
840 | } | |
841 | ||
cd5f6346 KP |
842 | read += thislen; |
843 | ||
844 | if (read == len) | |
845 | break; | |
846 | ||
cd5f6346 KP |
847 | buf += thislen; |
848 | ||
849 | /* Read more? */ | |
850 | if (read < len) { | |
851 | /* Page size */ | |
28318776 | 852 | from += mtd->writesize; |
cd5f6346 KP |
853 | column = 0; |
854 | } | |
855 | } | |
856 | ||
857 | out: | |
858 | /* Deselect and wake up anyone waiting on the device */ | |
859 | onenand_release_device(mtd); | |
860 | ||
861 | *retlen = read; | |
862 | return ret; | |
863 | } | |
864 | ||
8593fbc6 TG |
865 | /** |
866 | * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band | |
867 | * @mtd: MTD device structure | |
868 | * @from: offset to read from | |
869 | * @ops: oob operation description structure | |
870 | */ | |
871 | static int onenand_read_oob(struct mtd_info *mtd, loff_t from, | |
872 | struct mtd_oob_ops *ops) | |
873 | { | |
874 | BUG_ON(ops->mode != MTD_OOB_PLACE); | |
875 | ||
66a1e421 KP |
876 | return onenand_do_read_oob(mtd, from + ops->ooboffs, ops->ooblen, |
877 | &ops->oobretlen, ops->oobbuf); | |
8593fbc6 TG |
878 | } |
879 | ||
cd5f6346 | 880 | #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE |
8e6ec690 KP |
881 | /** |
882 | * onenand_verify_oob - [GENERIC] verify the oob contents after a write | |
883 | * @param mtd MTD device structure | |
884 | * @param buf the databuffer to verify | |
885 | * @param to offset to read from | |
886 | * @param len number of bytes to read and compare | |
887 | * | |
888 | */ | |
889 | static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, int len) | |
890 | { | |
891 | struct onenand_chip *this = mtd->priv; | |
892 | char *readp = this->page_buf; | |
893 | int column = to & (mtd->oobsize - 1); | |
894 | int status, i; | |
895 | ||
896 | this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); | |
897 | onenand_update_bufferram(mtd, to, 0); | |
898 | status = this->wait(mtd, FL_READING); | |
899 | if (status) | |
900 | return status; | |
901 | ||
902 | this->read_bufferram(mtd, ONENAND_SPARERAM, readp, column, len); | |
903 | ||
904 | for(i = 0; i < len; i++) | |
905 | if (buf[i] != 0xFF && buf[i] != readp[i]) | |
906 | return -EBADMSG; | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
cd5f6346 KP |
911 | /** |
912 | * onenand_verify_page - [GENERIC] verify the chip contents after a write | |
913 | * @param mtd MTD device structure | |
914 | * @param buf the databuffer to verify | |
cd5f6346 KP |
915 | * |
916 | * Check DataRAM area directly | |
917 | */ | |
d36d63d4 | 918 | static int onenand_verify_page(struct mtd_info *mtd, u_char *buf, loff_t addr) |
cd5f6346 KP |
919 | { |
920 | struct onenand_chip *this = mtd->priv; | |
921 | void __iomem *dataram0, *dataram1; | |
922 | int ret = 0; | |
923 | ||
60d84f97 KP |
924 | /* In partial page write, just skip it */ |
925 | if ((addr & (mtd->writesize - 1)) != 0) | |
926 | return 0; | |
927 | ||
28318776 | 928 | this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); |
cd5f6346 KP |
929 | |
930 | ret = this->wait(mtd, FL_READING); | |
931 | if (ret) | |
932 | return ret; | |
933 | ||
934 | onenand_update_bufferram(mtd, addr, 1); | |
935 | ||
936 | /* Check, if the two dataram areas are same */ | |
937 | dataram0 = this->base + ONENAND_DATARAM; | |
28318776 | 938 | dataram1 = dataram0 + mtd->writesize; |
cd5f6346 | 939 | |
28318776 | 940 | if (memcmp(dataram0, dataram1, mtd->writesize)) |
cd5f6346 | 941 | return -EBADMSG; |
d5c5e78a | 942 | |
cd5f6346 KP |
943 | return 0; |
944 | } | |
945 | #else | |
946 | #define onenand_verify_page(...) (0) | |
8e6ec690 | 947 | #define onenand_verify_oob(...) (0) |
cd5f6346 KP |
948 | #endif |
949 | ||
60d84f97 | 950 | #define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) |
cd5f6346 KP |
951 | |
952 | /** | |
9223a456 | 953 | * onenand_write - [MTD Interface] write buffer to FLASH |
cd5f6346 KP |
954 | * @param mtd MTD device structure |
955 | * @param to offset to write to | |
956 | * @param len number of bytes to write | |
957 | * @param retlen pointer to variable to store the number of written bytes | |
958 | * @param buf the data to write | |
cd5f6346 | 959 | * |
9223a456 | 960 | * Write with ECC |
cd5f6346 | 961 | */ |
9223a456 TG |
962 | static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, |
963 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
964 | { |
965 | struct onenand_chip *this = mtd->priv; | |
966 | int written = 0; | |
967 | int ret = 0; | |
60d84f97 | 968 | int column, subpage; |
cd5f6346 | 969 | |
9223a456 | 970 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); |
cd5f6346 KP |
971 | |
972 | /* Initialize retlen, in case of early exit */ | |
973 | *retlen = 0; | |
974 | ||
975 | /* Do not allow writes past end of device */ | |
976 | if (unlikely((to + len) > mtd->size)) { | |
9223a456 | 977 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt write to past end of device\n"); |
cd5f6346 KP |
978 | return -EINVAL; |
979 | } | |
980 | ||
981 | /* Reject writes, which are not page aligned */ | |
982 | if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { | |
9223a456 | 983 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt to write not page aligned data\n"); |
cd5f6346 KP |
984 | return -EINVAL; |
985 | } | |
986 | ||
60d84f97 KP |
987 | column = to & (mtd->writesize - 1); |
988 | subpage = column || (len & (mtd->writesize - 1)); | |
989 | ||
cd5f6346 KP |
990 | /* Grab the lock and see if the device is available */ |
991 | onenand_get_device(mtd, FL_WRITING); | |
992 | ||
993 | /* Loop until all data write */ | |
994 | while (written < len) { | |
60d84f97 KP |
995 | int bytes = mtd->writesize; |
996 | int thislen = min_t(int, bytes, len - written); | |
997 | u_char *wbuf = (u_char *) buf; | |
998 | ||
61a7e198 AB |
999 | cond_resched(); |
1000 | ||
60d84f97 KP |
1001 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, bytes); |
1002 | ||
1003 | /* Partial page write */ | |
1004 | if (subpage) { | |
1005 | bytes = min_t(int, bytes - column, (int) len); | |
1006 | memset(this->page_buf, 0xff, mtd->writesize); | |
1007 | memcpy(this->page_buf + column, buf, bytes); | |
1008 | wbuf = this->page_buf; | |
1009 | /* Even though partial write, we need page size */ | |
1010 | thislen = mtd->writesize; | |
1011 | } | |
cd5f6346 | 1012 | |
60d84f97 | 1013 | this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, thislen); |
cd5f6346 KP |
1014 | this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); |
1015 | ||
28318776 | 1016 | this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); |
cd5f6346 | 1017 | |
60d84f97 KP |
1018 | /* In partial page write we don't update bufferram */ |
1019 | onenand_update_bufferram(mtd, to, !subpage); | |
cd5f6346 KP |
1020 | |
1021 | ret = this->wait(mtd, FL_WRITING); | |
1022 | if (ret) { | |
9223a456 | 1023 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: write filaed %d\n", ret); |
60d84f97 | 1024 | break; |
cd5f6346 KP |
1025 | } |
1026 | ||
cd5f6346 | 1027 | /* Only check verify write turn on */ |
60d84f97 | 1028 | ret = onenand_verify_page(mtd, (u_char *) wbuf, to); |
cd5f6346 | 1029 | if (ret) { |
9223a456 | 1030 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: verify failed %d\n", ret); |
60d84f97 | 1031 | break; |
cd5f6346 KP |
1032 | } |
1033 | ||
60d84f97 KP |
1034 | written += thislen; |
1035 | ||
cd5f6346 KP |
1036 | if (written == len) |
1037 | break; | |
1038 | ||
60d84f97 | 1039 | column = 0; |
cd5f6346 KP |
1040 | to += thislen; |
1041 | buf += thislen; | |
1042 | } | |
1043 | ||
cd5f6346 KP |
1044 | /* Deselect and wake up anyone waiting on the device */ |
1045 | onenand_release_device(mtd); | |
1046 | ||
1047 | *retlen = written; | |
d5c5e78a | 1048 | |
cd5f6346 KP |
1049 | return ret; |
1050 | } | |
1051 | ||
cd5f6346 | 1052 | /** |
8593fbc6 | 1053 | * onenand_do_write_oob - [Internal] OneNAND write out-of-band |
cd5f6346 KP |
1054 | * @param mtd MTD device structure |
1055 | * @param to offset to write to | |
1056 | * @param len number of bytes to write | |
1057 | * @param retlen pointer to variable to store the number of written bytes | |
1058 | * @param buf the data to write | |
1059 | * | |
1060 | * OneNAND write out-of-band | |
1061 | */ | |
8593fbc6 TG |
1062 | static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
1063 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
1064 | { |
1065 | struct onenand_chip *this = mtd->priv; | |
8e6ec690 | 1066 | int column, ret = 0; |
cd5f6346 KP |
1067 | int written = 0; |
1068 | ||
1069 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); | |
1070 | ||
1071 | /* Initialize retlen, in case of early exit */ | |
1072 | *retlen = 0; | |
1073 | ||
1074 | /* Do not allow writes past end of device */ | |
1075 | if (unlikely((to + len) > mtd->size)) { | |
1076 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n"); | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | ||
1080 | /* Grab the lock and see if the device is available */ | |
1081 | onenand_get_device(mtd, FL_WRITING); | |
1082 | ||
1083 | /* Loop until all data write */ | |
1084 | while (written < len) { | |
1085 | int thislen = min_t(int, mtd->oobsize, len - written); | |
1086 | ||
61a7e198 AB |
1087 | cond_resched(); |
1088 | ||
cd5f6346 KP |
1089 | column = to & (mtd->oobsize - 1); |
1090 | ||
1091 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); | |
1092 | ||
34c10609 KP |
1093 | /* We send data to spare ram with oobsize |
1094 | * to prevent byte access */ | |
1095 | memset(this->page_buf, 0xff, mtd->oobsize); | |
1096 | memcpy(this->page_buf + column, buf, thislen); | |
1097 | this->write_bufferram(mtd, ONENAND_SPARERAM, this->page_buf, 0, mtd->oobsize); | |
cd5f6346 KP |
1098 | |
1099 | this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); | |
1100 | ||
1101 | onenand_update_bufferram(mtd, to, 0); | |
1102 | ||
8e6ec690 KP |
1103 | ret = this->wait(mtd, FL_WRITING); |
1104 | if (ret) { | |
1105 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: write filaed %d\n", ret); | |
1106 | goto out; | |
1107 | } | |
1108 | ||
1109 | ret = onenand_verify_oob(mtd, buf, to, thislen); | |
1110 | if (ret) { | |
1111 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: verify failed %d\n", ret); | |
cd5f6346 | 1112 | goto out; |
8e6ec690 | 1113 | } |
cd5f6346 KP |
1114 | |
1115 | written += thislen; | |
1116 | ||
1117 | if (written == len) | |
1118 | break; | |
1119 | ||
1120 | to += thislen; | |
1121 | buf += thislen; | |
1122 | } | |
1123 | ||
1124 | out: | |
1125 | /* Deselect and wake up anyone waiting on the device */ | |
1126 | onenand_release_device(mtd); | |
1127 | ||
1128 | *retlen = written; | |
d5c5e78a | 1129 | |
8e6ec690 | 1130 | return ret; |
cd5f6346 KP |
1131 | } |
1132 | ||
8593fbc6 TG |
1133 | /** |
1134 | * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1135 | * @mtd: MTD device structure | |
1136 | * @from: offset to read from | |
1137 | * @ops: oob operation description structure | |
1138 | */ | |
1139 | static int onenand_write_oob(struct mtd_info *mtd, loff_t to, | |
1140 | struct mtd_oob_ops *ops) | |
1141 | { | |
1142 | BUG_ON(ops->mode != MTD_OOB_PLACE); | |
1143 | ||
66a1e421 KP |
1144 | return onenand_do_write_oob(mtd, to + ops->ooboffs, ops->ooblen, |
1145 | &ops->oobretlen, ops->oobbuf); | |
8593fbc6 TG |
1146 | } |
1147 | ||
cdc00130 KP |
1148 | /** |
1149 | * onenand_block_checkbad - [GENERIC] Check if a block is marked bad | |
1150 | * @param mtd MTD device structure | |
1151 | * @param ofs offset from device start | |
1152 | * @param getchip 0, if the chip is already selected | |
1153 | * @param allowbbt 1, if its allowed to access the bbt area | |
1154 | * | |
1155 | * Check, if the block is bad. Either by reading the bad block table or | |
1156 | * calling of the scan function. | |
1157 | */ | |
1158 | static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) | |
1159 | { | |
1160 | struct onenand_chip *this = mtd->priv; | |
1161 | struct bbm_info *bbm = this->bbm; | |
1162 | ||
1163 | /* Return info from the table */ | |
1164 | return bbm->isbad_bbt(mtd, ofs, allowbbt); | |
1165 | } | |
1166 | ||
cd5f6346 KP |
1167 | /** |
1168 | * onenand_erase - [MTD Interface] erase block(s) | |
1169 | * @param mtd MTD device structure | |
1170 | * @param instr erase instruction | |
1171 | * | |
1172 | * Erase one ore more blocks | |
1173 | */ | |
1174 | static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) | |
1175 | { | |
1176 | struct onenand_chip *this = mtd->priv; | |
1177 | unsigned int block_size; | |
1178 | loff_t addr; | |
1179 | int len; | |
1180 | int ret = 0; | |
1181 | ||
1182 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); | |
1183 | ||
1184 | block_size = (1 << this->erase_shift); | |
1185 | ||
1186 | /* Start address must align on block boundary */ | |
1187 | if (unlikely(instr->addr & (block_size - 1))) { | |
1188 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); | |
1189 | return -EINVAL; | |
1190 | } | |
1191 | ||
1192 | /* Length must align on block boundary */ | |
1193 | if (unlikely(instr->len & (block_size - 1))) { | |
1194 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n"); | |
1195 | return -EINVAL; | |
1196 | } | |
1197 | ||
1198 | /* Do not allow erase past end of device */ | |
1199 | if (unlikely((instr->len + instr->addr) > mtd->size)) { | |
1200 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n"); | |
1201 | return -EINVAL; | |
1202 | } | |
1203 | ||
1204 | instr->fail_addr = 0xffffffff; | |
1205 | ||
1206 | /* Grab the lock and see if the device is available */ | |
1207 | onenand_get_device(mtd, FL_ERASING); | |
1208 | ||
1209 | /* Loop throught the pages */ | |
1210 | len = instr->len; | |
1211 | addr = instr->addr; | |
1212 | ||
1213 | instr->state = MTD_ERASING; | |
1214 | ||
1215 | while (len) { | |
61a7e198 | 1216 | cond_resched(); |
cd5f6346 | 1217 | |
cdc00130 KP |
1218 | /* Check if we have a bad block, we do not erase bad blocks */ |
1219 | if (onenand_block_checkbad(mtd, addr, 0, 0)) { | |
1220 | printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); | |
1221 | instr->state = MTD_ERASE_FAILED; | |
1222 | goto erase_exit; | |
1223 | } | |
cd5f6346 KP |
1224 | |
1225 | this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); | |
1226 | ||
1227 | ret = this->wait(mtd, FL_ERASING); | |
1228 | /* Check, if it is write protected */ | |
1229 | if (ret) { | |
f6272487 | 1230 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); |
cd5f6346 KP |
1231 | instr->state = MTD_ERASE_FAILED; |
1232 | instr->fail_addr = addr; | |
1233 | goto erase_exit; | |
1234 | } | |
1235 | ||
1236 | len -= block_size; | |
1237 | addr += block_size; | |
1238 | } | |
1239 | ||
1240 | instr->state = MTD_ERASE_DONE; | |
1241 | ||
1242 | erase_exit: | |
1243 | ||
1244 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1245 | /* Do call back function */ | |
1246 | if (!ret) | |
1247 | mtd_erase_callback(instr); | |
1248 | ||
1249 | /* Deselect and wake up anyone waiting on the device */ | |
1250 | onenand_release_device(mtd); | |
1251 | ||
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | /** | |
1256 | * onenand_sync - [MTD Interface] sync | |
1257 | * @param mtd MTD device structure | |
1258 | * | |
1259 | * Sync is actually a wait for chip ready function | |
1260 | */ | |
1261 | static void onenand_sync(struct mtd_info *mtd) | |
1262 | { | |
1263 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); | |
1264 | ||
1265 | /* Grab the lock and see if the device is available */ | |
1266 | onenand_get_device(mtd, FL_SYNCING); | |
1267 | ||
1268 | /* Release it and go back */ | |
1269 | onenand_release_device(mtd); | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad | |
1274 | * @param mtd MTD device structure | |
1275 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1276 | * |
1277 | * Check whether the block is bad | |
cd5f6346 KP |
1278 | */ |
1279 | static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) | |
1280 | { | |
cdc00130 KP |
1281 | /* Check for invalid offset */ |
1282 | if (ofs > mtd->size) | |
1283 | return -EINVAL; | |
1284 | ||
1285 | return onenand_block_checkbad(mtd, ofs, 1, 0); | |
1286 | } | |
1287 | ||
1288 | /** | |
1289 | * onenand_default_block_markbad - [DEFAULT] mark a block bad | |
1290 | * @param mtd MTD device structure | |
1291 | * @param ofs offset from device start | |
1292 | * | |
1293 | * This is the default implementation, which can be overridden by | |
1294 | * a hardware specific driver. | |
1295 | */ | |
1296 | static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1297 | { | |
1298 | struct onenand_chip *this = mtd->priv; | |
1299 | struct bbm_info *bbm = this->bbm; | |
1300 | u_char buf[2] = {0, 0}; | |
1301 | size_t retlen; | |
1302 | int block; | |
1303 | ||
1304 | /* Get block number */ | |
1305 | block = ((int) ofs) >> bbm->bbt_erase_shift; | |
1306 | if (bbm->bbt) | |
1307 | bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1308 | ||
1309 | /* We write two bytes, so we dont have to mess with 16 bit access */ | |
1310 | ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); | |
8593fbc6 | 1311 | return onenand_do_write_oob(mtd, ofs , 2, &retlen, buf); |
cd5f6346 KP |
1312 | } |
1313 | ||
1314 | /** | |
1315 | * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad | |
1316 | * @param mtd MTD device structure | |
1317 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1318 | * |
1319 | * Mark the block as bad | |
cd5f6346 KP |
1320 | */ |
1321 | static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1322 | { | |
cdc00130 KP |
1323 | struct onenand_chip *this = mtd->priv; |
1324 | int ret; | |
1325 | ||
1326 | ret = onenand_block_isbad(mtd, ofs); | |
1327 | if (ret) { | |
1328 | /* If it was bad already, return success and do nothing */ | |
1329 | if (ret > 0) | |
1330 | return 0; | |
1331 | return ret; | |
1332 | } | |
1333 | ||
1334 | return this->block_markbad(mtd, ofs); | |
cd5f6346 KP |
1335 | } |
1336 | ||
1337 | /** | |
08f782b6 | 1338 | * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) |
cd5f6346 KP |
1339 | * @param mtd MTD device structure |
1340 | * @param ofs offset relative to mtd start | |
08f782b6 | 1341 | * @param len number of bytes to lock or unlock |
cd5f6346 | 1342 | * |
08f782b6 | 1343 | * Lock or unlock one or more blocks |
cd5f6346 | 1344 | */ |
08f782b6 | 1345 | static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) |
cd5f6346 KP |
1346 | { |
1347 | struct onenand_chip *this = mtd->priv; | |
1348 | int start, end, block, value, status; | |
08f782b6 | 1349 | int wp_status_mask; |
cd5f6346 KP |
1350 | |
1351 | start = ofs >> this->erase_shift; | |
1352 | end = len >> this->erase_shift; | |
1353 | ||
08f782b6 KP |
1354 | if (cmd == ONENAND_CMD_LOCK) |
1355 | wp_status_mask = ONENAND_WP_LS; | |
1356 | else | |
1357 | wp_status_mask = ONENAND_WP_US; | |
1358 | ||
cd5f6346 | 1359 | /* Continuous lock scheme */ |
28b79ff9 | 1360 | if (this->options & ONENAND_HAS_CONT_LOCK) { |
cd5f6346 KP |
1361 | /* Set start block address */ |
1362 | this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1363 | /* Set end block address */ | |
28b79ff9 | 1364 | this->write_word(start + end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); |
08f782b6 KP |
1365 | /* Write lock command */ |
1366 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1367 | |
1368 | /* There's no return value */ | |
08f782b6 | 1369 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1370 | |
1371 | /* Sanity check */ | |
1372 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1373 | & ONENAND_CTRL_ONGO) | |
1374 | continue; | |
1375 | ||
1376 | /* Check lock status */ | |
1377 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1378 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1379 | printk(KERN_ERR "wp status = 0x%x\n", status); |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | /* Block lock scheme */ | |
28b79ff9 | 1385 | for (block = start; block < start + end; block++) { |
20ba89a3 KP |
1386 | /* Set block address */ |
1387 | value = onenand_block_address(this, block); | |
1388 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1389 | /* Select DataRAM for DDP */ | |
1390 | value = onenand_bufferram_address(this, block); | |
1391 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
cd5f6346 KP |
1392 | /* Set start block address */ |
1393 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
08f782b6 KP |
1394 | /* Write lock command */ |
1395 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1396 | |
1397 | /* There's no return value */ | |
08f782b6 | 1398 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1399 | |
1400 | /* Sanity check */ | |
1401 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1402 | & ONENAND_CTRL_ONGO) | |
1403 | continue; | |
1404 | ||
cd5f6346 KP |
1405 | /* Check lock status */ |
1406 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1407 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1408 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); |
1409 | } | |
d5c5e78a | 1410 | |
cd5f6346 KP |
1411 | return 0; |
1412 | } | |
1413 | ||
08f782b6 KP |
1414 | /** |
1415 | * onenand_lock - [MTD Interface] Lock block(s) | |
1416 | * @param mtd MTD device structure | |
1417 | * @param ofs offset relative to mtd start | |
1418 | * @param len number of bytes to unlock | |
1419 | * | |
1420 | * Lock one or more blocks | |
1421 | */ | |
1422 | static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1423 | { | |
1424 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); | |
1425 | } | |
1426 | ||
08f782b6 KP |
1427 | /** |
1428 | * onenand_unlock - [MTD Interface] Unlock block(s) | |
1429 | * @param mtd MTD device structure | |
1430 | * @param ofs offset relative to mtd start | |
1431 | * @param len number of bytes to unlock | |
1432 | * | |
1433 | * Unlock one or more blocks | |
1434 | */ | |
1435 | static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1436 | { | |
1437 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); | |
1438 | } | |
1439 | ||
28b79ff9 KP |
1440 | /** |
1441 | * onenand_check_lock_status - [OneNAND Interface] Check lock status | |
1442 | * @param this onenand chip data structure | |
1443 | * | |
1444 | * Check lock status | |
1445 | */ | |
1446 | static void onenand_check_lock_status(struct onenand_chip *this) | |
1447 | { | |
1448 | unsigned int value, block, status; | |
1449 | unsigned int end; | |
1450 | ||
1451 | end = this->chipsize >> this->erase_shift; | |
1452 | for (block = 0; block < end; block++) { | |
1453 | /* Set block address */ | |
1454 | value = onenand_block_address(this, block); | |
1455 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1456 | /* Select DataRAM for DDP */ | |
1457 | value = onenand_bufferram_address(this, block); | |
1458 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
1459 | /* Set start block address */ | |
1460 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1461 | ||
1462 | /* Check lock status */ | |
1463 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1464 | if (!(status & ONENAND_WP_US)) | |
1465 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * onenand_unlock_all - [OneNAND Interface] unlock all blocks | |
1471 | * @param mtd MTD device structure | |
1472 | * | |
1473 | * Unlock all blocks | |
1474 | */ | |
1475 | static int onenand_unlock_all(struct mtd_info *mtd) | |
1476 | { | |
1477 | struct onenand_chip *this = mtd->priv; | |
1478 | ||
1479 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
10b7a2bd KP |
1480 | /* Set start block address */ |
1481 | this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
28b79ff9 KP |
1482 | /* Write unlock command */ |
1483 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
1484 | ||
1485 | /* There's no return value */ | |
08f782b6 | 1486 | this->wait(mtd, FL_LOCKING); |
28b79ff9 KP |
1487 | |
1488 | /* Sanity check */ | |
1489 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1490 | & ONENAND_CTRL_ONGO) | |
1491 | continue; | |
1492 | ||
1493 | /* Workaround for all block unlock in DDP */ | |
738d61f5 | 1494 | if (ONENAND_IS_DDP(this)) { |
28b79ff9 | 1495 | /* 1st block on another chip */ |
10b7a2bd KP |
1496 | loff_t ofs = this->chipsize >> 1; |
1497 | size_t len = mtd->erasesize; | |
28b79ff9 KP |
1498 | |
1499 | onenand_unlock(mtd, ofs, len); | |
1500 | } | |
1501 | ||
1502 | onenand_check_lock_status(this); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
08f782b6 | 1507 | onenand_unlock(mtd, 0x0, this->chipsize); |
28b79ff9 KP |
1508 | |
1509 | return 0; | |
1510 | } | |
1511 | ||
493c6460 KP |
1512 | #ifdef CONFIG_MTD_ONENAND_OTP |
1513 | ||
1514 | /* Interal OTP operation */ | |
1515 | typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, | |
1516 | size_t *retlen, u_char *buf); | |
1517 | ||
1518 | /** | |
1519 | * do_otp_read - [DEFAULT] Read OTP block area | |
1520 | * @param mtd MTD device structure | |
1521 | * @param from The offset to read | |
1522 | * @param len number of bytes to read | |
1523 | * @param retlen pointer to variable to store the number of readbytes | |
1524 | * @param buf the databuffer to put/get data | |
1525 | * | |
1526 | * Read OTP block area. | |
1527 | */ | |
1528 | static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1529 | size_t *retlen, u_char *buf) | |
1530 | { | |
1531 | struct onenand_chip *this = mtd->priv; | |
1532 | int ret; | |
1533 | ||
1534 | /* Enter OTP access mode */ | |
1535 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1536 | this->wait(mtd, FL_OTPING); | |
1537 | ||
1538 | ret = mtd->read(mtd, from, len, retlen, buf); | |
1539 | ||
1540 | /* Exit OTP access mode */ | |
1541 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1542 | this->wait(mtd, FL_RESETING); | |
1543 | ||
1544 | return ret; | |
1545 | } | |
1546 | ||
1547 | /** | |
1548 | * do_otp_write - [DEFAULT] Write OTP block area | |
1549 | * @param mtd MTD device structure | |
1550 | * @param from The offset to write | |
1551 | * @param len number of bytes to write | |
1552 | * @param retlen pointer to variable to store the number of write bytes | |
1553 | * @param buf the databuffer to put/get data | |
1554 | * | |
1555 | * Write OTP block area. | |
1556 | */ | |
1557 | static int do_otp_write(struct mtd_info *mtd, loff_t from, size_t len, | |
1558 | size_t *retlen, u_char *buf) | |
1559 | { | |
1560 | struct onenand_chip *this = mtd->priv; | |
1561 | unsigned char *pbuf = buf; | |
1562 | int ret; | |
1563 | ||
1564 | /* Force buffer page aligned */ | |
28318776 | 1565 | if (len < mtd->writesize) { |
493c6460 | 1566 | memcpy(this->page_buf, buf, len); |
28318776 | 1567 | memset(this->page_buf + len, 0xff, mtd->writesize - len); |
493c6460 | 1568 | pbuf = this->page_buf; |
28318776 | 1569 | len = mtd->writesize; |
493c6460 KP |
1570 | } |
1571 | ||
1572 | /* Enter OTP access mode */ | |
1573 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1574 | this->wait(mtd, FL_OTPING); | |
1575 | ||
1576 | ret = mtd->write(mtd, from, len, retlen, pbuf); | |
1577 | ||
1578 | /* Exit OTP access mode */ | |
1579 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1580 | this->wait(mtd, FL_RESETING); | |
1581 | ||
1582 | return ret; | |
1583 | } | |
1584 | ||
1585 | /** | |
1586 | * do_otp_lock - [DEFAULT] Lock OTP block area | |
1587 | * @param mtd MTD device structure | |
1588 | * @param from The offset to lock | |
1589 | * @param len number of bytes to lock | |
1590 | * @param retlen pointer to variable to store the number of lock bytes | |
1591 | * @param buf the databuffer to put/get data | |
1592 | * | |
1593 | * Lock OTP block area. | |
1594 | */ | |
1595 | static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, | |
1596 | size_t *retlen, u_char *buf) | |
1597 | { | |
1598 | struct onenand_chip *this = mtd->priv; | |
1599 | int ret; | |
1600 | ||
1601 | /* Enter OTP access mode */ | |
1602 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1603 | this->wait(mtd, FL_OTPING); | |
1604 | ||
8593fbc6 | 1605 | ret = onenand_do_write_oob(mtd, from, len, retlen, buf); |
493c6460 KP |
1606 | |
1607 | /* Exit OTP access mode */ | |
1608 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1609 | this->wait(mtd, FL_RESETING); | |
1610 | ||
1611 | return ret; | |
1612 | } | |
1613 | ||
1614 | /** | |
1615 | * onenand_otp_walk - [DEFAULT] Handle OTP operation | |
1616 | * @param mtd MTD device structure | |
1617 | * @param from The offset to read/write | |
1618 | * @param len number of bytes to read/write | |
1619 | * @param retlen pointer to variable to store the number of read bytes | |
1620 | * @param buf the databuffer to put/get data | |
1621 | * @param action do given action | |
1622 | * @param mode specify user and factory | |
1623 | * | |
1624 | * Handle OTP operation. | |
1625 | */ | |
1626 | static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, | |
1627 | size_t *retlen, u_char *buf, | |
1628 | otp_op_t action, int mode) | |
1629 | { | |
1630 | struct onenand_chip *this = mtd->priv; | |
1631 | int otp_pages; | |
1632 | int density; | |
1633 | int ret = 0; | |
1634 | ||
1635 | *retlen = 0; | |
1636 | ||
1637 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1638 | if (density < ONENAND_DEVICE_DENSITY_512Mb) | |
1639 | otp_pages = 20; | |
1640 | else | |
1641 | otp_pages = 10; | |
1642 | ||
1643 | if (mode == MTD_OTP_FACTORY) { | |
28318776 | 1644 | from += mtd->writesize * otp_pages; |
493c6460 KP |
1645 | otp_pages = 64 - otp_pages; |
1646 | } | |
1647 | ||
1648 | /* Check User/Factory boundary */ | |
28318776 | 1649 | if (((mtd->writesize * otp_pages) - (from + len)) < 0) |
493c6460 KP |
1650 | return 0; |
1651 | ||
1652 | while (len > 0 && otp_pages > 0) { | |
1653 | if (!action) { /* OTP Info functions */ | |
1654 | struct otp_info *otpinfo; | |
1655 | ||
1656 | len -= sizeof(struct otp_info); | |
1657 | if (len <= 0) | |
1658 | return -ENOSPC; | |
1659 | ||
1660 | otpinfo = (struct otp_info *) buf; | |
1661 | otpinfo->start = from; | |
28318776 | 1662 | otpinfo->length = mtd->writesize; |
493c6460 KP |
1663 | otpinfo->locked = 0; |
1664 | ||
28318776 | 1665 | from += mtd->writesize; |
493c6460 KP |
1666 | buf += sizeof(struct otp_info); |
1667 | *retlen += sizeof(struct otp_info); | |
1668 | } else { | |
1669 | size_t tmp_retlen; | |
1670 | int size = len; | |
1671 | ||
1672 | ret = action(mtd, from, len, &tmp_retlen, buf); | |
1673 | ||
1674 | buf += size; | |
1675 | len -= size; | |
1676 | *retlen += size; | |
1677 | ||
1678 | if (ret < 0) | |
1679 | return ret; | |
1680 | } | |
1681 | otp_pages--; | |
1682 | } | |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | /** | |
1688 | * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info | |
1689 | * @param mtd MTD device structure | |
1690 | * @param buf the databuffer to put/get data | |
1691 | * @param len number of bytes to read | |
1692 | * | |
1693 | * Read factory OTP info. | |
1694 | */ | |
1695 | static int onenand_get_fact_prot_info(struct mtd_info *mtd, | |
1696 | struct otp_info *buf, size_t len) | |
1697 | { | |
1698 | size_t retlen; | |
1699 | int ret; | |
1700 | ||
1701 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY); | |
1702 | ||
1703 | return ret ? : retlen; | |
1704 | } | |
1705 | ||
1706 | /** | |
1707 | * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area | |
1708 | * @param mtd MTD device structure | |
1709 | * @param from The offset to read | |
1710 | * @param len number of bytes to read | |
1711 | * @param retlen pointer to variable to store the number of read bytes | |
1712 | * @param buf the databuffer to put/get data | |
1713 | * | |
1714 | * Read factory OTP area. | |
1715 | */ | |
1716 | static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | |
1717 | size_t len, size_t *retlen, u_char *buf) | |
1718 | { | |
1719 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY); | |
1720 | } | |
1721 | ||
1722 | /** | |
1723 | * onenand_get_user_prot_info - [MTD Interface] Read user OTP info | |
1724 | * @param mtd MTD device structure | |
1725 | * @param buf the databuffer to put/get data | |
1726 | * @param len number of bytes to read | |
1727 | * | |
1728 | * Read user OTP info. | |
1729 | */ | |
1730 | static int onenand_get_user_prot_info(struct mtd_info *mtd, | |
1731 | struct otp_info *buf, size_t len) | |
1732 | { | |
1733 | size_t retlen; | |
1734 | int ret; | |
1735 | ||
1736 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER); | |
1737 | ||
1738 | return ret ? : retlen; | |
1739 | } | |
1740 | ||
1741 | /** | |
1742 | * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area | |
1743 | * @param mtd MTD device structure | |
1744 | * @param from The offset to read | |
1745 | * @param len number of bytes to read | |
1746 | * @param retlen pointer to variable to store the number of read bytes | |
1747 | * @param buf the databuffer to put/get data | |
1748 | * | |
1749 | * Read user OTP area. | |
1750 | */ | |
1751 | static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1752 | size_t len, size_t *retlen, u_char *buf) | |
1753 | { | |
1754 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER); | |
1755 | } | |
1756 | ||
1757 | /** | |
1758 | * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area | |
1759 | * @param mtd MTD device structure | |
1760 | * @param from The offset to write | |
1761 | * @param len number of bytes to write | |
1762 | * @param retlen pointer to variable to store the number of write bytes | |
1763 | * @param buf the databuffer to put/get data | |
1764 | * | |
1765 | * Write user OTP area. | |
1766 | */ | |
1767 | static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1768 | size_t len, size_t *retlen, u_char *buf) | |
1769 | { | |
1770 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER); | |
1771 | } | |
1772 | ||
1773 | /** | |
1774 | * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area | |
1775 | * @param mtd MTD device structure | |
1776 | * @param from The offset to lock | |
1777 | * @param len number of bytes to unlock | |
1778 | * | |
1779 | * Write lock mark on spare area in page 0 in OTP block | |
1780 | */ | |
1781 | static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1782 | size_t len) | |
1783 | { | |
1784 | unsigned char oob_buf[64]; | |
1785 | size_t retlen; | |
1786 | int ret; | |
1787 | ||
1788 | memset(oob_buf, 0xff, mtd->oobsize); | |
1789 | /* | |
1790 | * Note: OTP lock operation | |
1791 | * OTP block : 0xXXFC | |
1792 | * 1st block : 0xXXF3 (If chip support) | |
1793 | * Both : 0xXXF0 (If chip support) | |
1794 | */ | |
1795 | oob_buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC; | |
1796 | ||
1797 | /* | |
1798 | * Write lock mark to 8th word of sector0 of page0 of the spare0. | |
1799 | * We write 16 bytes spare area instead of 2 bytes. | |
1800 | */ | |
1801 | from = 0; | |
1802 | len = 16; | |
1803 | ||
1804 | ret = onenand_otp_walk(mtd, from, len, &retlen, oob_buf, do_otp_lock, MTD_OTP_USER); | |
1805 | ||
1806 | return ret ? : retlen; | |
1807 | } | |
1808 | #endif /* CONFIG_MTD_ONENAND_OTP */ | |
1809 | ||
28b79ff9 | 1810 | /** |
75384b0d | 1811 | * onenand_check_features - Check and set OneNAND features |
28b79ff9 KP |
1812 | * @param mtd MTD data structure |
1813 | * | |
75384b0d KP |
1814 | * Check and set OneNAND features |
1815 | * - lock scheme | |
28b79ff9 | 1816 | */ |
75384b0d | 1817 | static void onenand_check_features(struct mtd_info *mtd) |
28b79ff9 KP |
1818 | { |
1819 | struct onenand_chip *this = mtd->priv; | |
1820 | unsigned int density, process; | |
1821 | ||
1822 | /* Lock scheme depends on density and process */ | |
1823 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1824 | process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; | |
1825 | ||
1826 | /* Lock scheme */ | |
1827 | if (density >= ONENAND_DEVICE_DENSITY_1Gb) { | |
1828 | /* A-Die has all block unlock */ | |
1829 | if (process) { | |
1830 | printk(KERN_DEBUG "Chip support all block unlock\n"); | |
1831 | this->options |= ONENAND_HAS_UNLOCK_ALL; | |
1832 | } | |
1833 | } else { | |
1834 | /* Some OneNAND has continues lock scheme */ | |
1835 | if (!process) { | |
1836 | printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); | |
1837 | this->options |= ONENAND_HAS_CONT_LOCK; | |
1838 | } | |
1839 | } | |
1840 | } | |
1841 | ||
cd5f6346 KP |
1842 | /** |
1843 | * onenand_print_device_info - Print device ID | |
1844 | * @param device device ID | |
1845 | * | |
1846 | * Print device ID | |
1847 | */ | |
28b79ff9 | 1848 | static void onenand_print_device_info(int device, int version) |
cd5f6346 KP |
1849 | { |
1850 | int vcc, demuxed, ddp, density; | |
1851 | ||
1852 | vcc = device & ONENAND_DEVICE_VCC_MASK; | |
1853 | demuxed = device & ONENAND_DEVICE_IS_DEMUX; | |
1854 | ddp = device & ONENAND_DEVICE_IS_DDP; | |
1855 | density = device >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1856 | printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", | |
1857 | demuxed ? "" : "Muxed ", | |
1858 | ddp ? "(DDP)" : "", | |
1859 | (16 << density), | |
1860 | vcc ? "2.65/3.3" : "1.8", | |
1861 | device); | |
28b79ff9 | 1862 | printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); |
cd5f6346 KP |
1863 | } |
1864 | ||
1865 | static const struct onenand_manufacturers onenand_manuf_ids[] = { | |
1866 | {ONENAND_MFR_SAMSUNG, "Samsung"}, | |
cd5f6346 KP |
1867 | }; |
1868 | ||
1869 | /** | |
1870 | * onenand_check_maf - Check manufacturer ID | |
1871 | * @param manuf manufacturer ID | |
1872 | * | |
1873 | * Check manufacturer ID | |
1874 | */ | |
1875 | static int onenand_check_maf(int manuf) | |
1876 | { | |
37b1cc39 KP |
1877 | int size = ARRAY_SIZE(onenand_manuf_ids); |
1878 | char *name; | |
cd5f6346 KP |
1879 | int i; |
1880 | ||
37b1cc39 | 1881 | for (i = 0; i < size; i++) |
cd5f6346 KP |
1882 | if (manuf == onenand_manuf_ids[i].id) |
1883 | break; | |
cd5f6346 | 1884 | |
37b1cc39 KP |
1885 | if (i < size) |
1886 | name = onenand_manuf_ids[i].name; | |
1887 | else | |
1888 | name = "Unknown"; | |
1889 | ||
1890 | printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); | |
cd5f6346 | 1891 | |
37b1cc39 | 1892 | return (i == size); |
cd5f6346 KP |
1893 | } |
1894 | ||
1895 | /** | |
1896 | * onenand_probe - [OneNAND Interface] Probe the OneNAND device | |
1897 | * @param mtd MTD device structure | |
1898 | * | |
1899 | * OneNAND detection method: | |
1900 | * Compare the the values from command with ones from register | |
1901 | */ | |
1902 | static int onenand_probe(struct mtd_info *mtd) | |
1903 | { | |
1904 | struct onenand_chip *this = mtd->priv; | |
28b79ff9 | 1905 | int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; |
cd5f6346 | 1906 | int density; |
47e777e0 KP |
1907 | int syscfg; |
1908 | ||
1909 | /* Save system configuration 1 */ | |
1910 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
1911 | /* Clear Sync. Burst Read mode to read BootRAM */ | |
1912 | this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); | |
cd5f6346 KP |
1913 | |
1914 | /* Send the command for reading device ID from BootRAM */ | |
1915 | this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); | |
1916 | ||
1917 | /* Read manufacturer and device IDs from BootRAM */ | |
1918 | bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); | |
1919 | bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); | |
1920 | ||
47e777e0 KP |
1921 | /* Reset OneNAND to read default register values */ |
1922 | this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); | |
1923 | /* Wait reset */ | |
1924 | this->wait(mtd, FL_RESETING); | |
1925 | ||
1926 | /* Restore system configuration 1 */ | |
1927 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
1928 | ||
cd5f6346 KP |
1929 | /* Check manufacturer ID */ |
1930 | if (onenand_check_maf(bram_maf_id)) | |
1931 | return -ENXIO; | |
1932 | ||
cd5f6346 KP |
1933 | /* Read manufacturer and device IDs from Register */ |
1934 | maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); | |
1935 | dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); | |
f4f91ac3 | 1936 | ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); |
cd5f6346 KP |
1937 | |
1938 | /* Check OneNAND device */ | |
1939 | if (maf_id != bram_maf_id || dev_id != bram_dev_id) | |
1940 | return -ENXIO; | |
1941 | ||
1942 | /* Flash device information */ | |
28b79ff9 | 1943 | onenand_print_device_info(dev_id, ver_id); |
cd5f6346 | 1944 | this->device_id = dev_id; |
28b79ff9 | 1945 | this->version_id = ver_id; |
cd5f6346 KP |
1946 | |
1947 | density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1948 | this->chipsize = (16 << density) << 20; | |
83a36838 | 1949 | /* Set density mask. it is used for DDP */ |
738d61f5 KP |
1950 | if (ONENAND_IS_DDP(this)) |
1951 | this->density_mask = (1 << (density + 6)); | |
1952 | else | |
1953 | this->density_mask = 0; | |
cd5f6346 KP |
1954 | |
1955 | /* OneNAND page size & block size */ | |
1956 | /* The data buffer size is equal to page size */ | |
28318776 JE |
1957 | mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); |
1958 | mtd->oobsize = mtd->writesize >> 5; | |
cd5f6346 | 1959 | /* Pagers per block is always 64 in OneNAND */ |
28318776 | 1960 | mtd->erasesize = mtd->writesize << 6; |
cd5f6346 KP |
1961 | |
1962 | this->erase_shift = ffs(mtd->erasesize) - 1; | |
28318776 | 1963 | this->page_shift = ffs(mtd->writesize) - 1; |
cd5f6346 | 1964 | this->ppb_shift = (this->erase_shift - this->page_shift); |
28318776 | 1965 | this->page_mask = (mtd->erasesize / mtd->writesize) - 1; |
cd5f6346 KP |
1966 | |
1967 | /* REVIST: Multichip handling */ | |
1968 | ||
1969 | mtd->size = this->chipsize; | |
1970 | ||
75384b0d KP |
1971 | /* Check OneNAND features */ |
1972 | onenand_check_features(mtd); | |
d5c5e78a | 1973 | |
cd5f6346 KP |
1974 | return 0; |
1975 | } | |
1976 | ||
a41371eb KP |
1977 | /** |
1978 | * onenand_suspend - [MTD Interface] Suspend the OneNAND flash | |
1979 | * @param mtd MTD device structure | |
1980 | */ | |
1981 | static int onenand_suspend(struct mtd_info *mtd) | |
1982 | { | |
1983 | return onenand_get_device(mtd, FL_PM_SUSPENDED); | |
1984 | } | |
1985 | ||
1986 | /** | |
1987 | * onenand_resume - [MTD Interface] Resume the OneNAND flash | |
1988 | * @param mtd MTD device structure | |
1989 | */ | |
1990 | static void onenand_resume(struct mtd_info *mtd) | |
1991 | { | |
1992 | struct onenand_chip *this = mtd->priv; | |
1993 | ||
1994 | if (this->state == FL_PM_SUSPENDED) | |
1995 | onenand_release_device(mtd); | |
1996 | else | |
1997 | printk(KERN_ERR "resume() called for the chip which is not" | |
1998 | "in suspended state\n"); | |
1999 | } | |
2000 | ||
cd5f6346 KP |
2001 | /** |
2002 | * onenand_scan - [OneNAND Interface] Scan for the OneNAND device | |
2003 | * @param mtd MTD device structure | |
2004 | * @param maxchips Number of chips to scan for | |
2005 | * | |
2006 | * This fills out all the not initialized function pointers | |
2007 | * with the defaults. | |
2008 | * The flash ID is read and the mtd/chip structures are | |
2009 | * filled with the appropriate values. | |
2010 | */ | |
2011 | int onenand_scan(struct mtd_info *mtd, int maxchips) | |
2012 | { | |
2013 | struct onenand_chip *this = mtd->priv; | |
2014 | ||
2015 | if (!this->read_word) | |
2016 | this->read_word = onenand_readw; | |
2017 | if (!this->write_word) | |
2018 | this->write_word = onenand_writew; | |
2019 | ||
2020 | if (!this->command) | |
2021 | this->command = onenand_command; | |
2022 | if (!this->wait) | |
2c22120f | 2023 | onenand_setup_wait(mtd); |
cd5f6346 KP |
2024 | |
2025 | if (!this->read_bufferram) | |
2026 | this->read_bufferram = onenand_read_bufferram; | |
2027 | if (!this->write_bufferram) | |
2028 | this->write_bufferram = onenand_write_bufferram; | |
2029 | ||
cdc00130 KP |
2030 | if (!this->block_markbad) |
2031 | this->block_markbad = onenand_default_block_markbad; | |
2032 | if (!this->scan_bbt) | |
2033 | this->scan_bbt = onenand_default_bbt; | |
2034 | ||
cd5f6346 KP |
2035 | if (onenand_probe(mtd)) |
2036 | return -ENXIO; | |
2037 | ||
52b0eea7 KP |
2038 | /* Set Sync. Burst Read after probing */ |
2039 | if (this->mmcontrol) { | |
2040 | printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); | |
2041 | this->read_bufferram = onenand_sync_read_bufferram; | |
2042 | } | |
2043 | ||
532a37cf KP |
2044 | /* Allocate buffers, if necessary */ |
2045 | if (!this->page_buf) { | |
2046 | size_t len; | |
28318776 | 2047 | len = mtd->writesize + mtd->oobsize; |
532a37cf KP |
2048 | this->page_buf = kmalloc(len, GFP_KERNEL); |
2049 | if (!this->page_buf) { | |
2050 | printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); | |
2051 | return -ENOMEM; | |
2052 | } | |
2053 | this->options |= ONENAND_PAGEBUF_ALLOC; | |
2054 | } | |
2055 | ||
cd5f6346 KP |
2056 | this->state = FL_READY; |
2057 | init_waitqueue_head(&this->wq); | |
2058 | spin_lock_init(&this->chip_lock); | |
2059 | ||
60d84f97 KP |
2060 | /* |
2061 | * Allow subpage writes up to oobsize. | |
2062 | */ | |
cd5f6346 KP |
2063 | switch (mtd->oobsize) { |
2064 | case 64: | |
5bd34c09 | 2065 | this->ecclayout = &onenand_oob_64; |
60d84f97 | 2066 | mtd->subpage_sft = 2; |
cd5f6346 KP |
2067 | break; |
2068 | ||
2069 | case 32: | |
5bd34c09 | 2070 | this->ecclayout = &onenand_oob_32; |
60d84f97 | 2071 | mtd->subpage_sft = 1; |
cd5f6346 KP |
2072 | break; |
2073 | ||
2074 | default: | |
2075 | printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", | |
2076 | mtd->oobsize); | |
60d84f97 | 2077 | mtd->subpage_sft = 0; |
cd5f6346 | 2078 | /* To prevent kernel oops */ |
5bd34c09 | 2079 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
2080 | break; |
2081 | } | |
2082 | ||
60d84f97 | 2083 | this->subpagesize = mtd->writesize >> mtd->subpage_sft; |
5bd34c09 | 2084 | mtd->ecclayout = this->ecclayout; |
d5c5e78a | 2085 | |
cd5f6346 KP |
2086 | /* Fill in remaining MTD driver data */ |
2087 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2088 | mtd->flags = MTD_CAP_NANDFLASH; |
cd5f6346 KP |
2089 | mtd->ecctype = MTD_ECC_SW; |
2090 | mtd->erase = onenand_erase; | |
2091 | mtd->point = NULL; | |
2092 | mtd->unpoint = NULL; | |
2093 | mtd->read = onenand_read; | |
2094 | mtd->write = onenand_write; | |
cd5f6346 KP |
2095 | mtd->read_oob = onenand_read_oob; |
2096 | mtd->write_oob = onenand_write_oob; | |
493c6460 KP |
2097 | #ifdef CONFIG_MTD_ONENAND_OTP |
2098 | mtd->get_fact_prot_info = onenand_get_fact_prot_info; | |
2099 | mtd->read_fact_prot_reg = onenand_read_fact_prot_reg; | |
2100 | mtd->get_user_prot_info = onenand_get_user_prot_info; | |
2101 | mtd->read_user_prot_reg = onenand_read_user_prot_reg; | |
2102 | mtd->write_user_prot_reg = onenand_write_user_prot_reg; | |
2103 | mtd->lock_user_prot_reg = onenand_lock_user_prot_reg; | |
2104 | #endif | |
cd5f6346 | 2105 | mtd->sync = onenand_sync; |
08f782b6 | 2106 | mtd->lock = onenand_lock; |
cd5f6346 | 2107 | mtd->unlock = onenand_unlock; |
a41371eb KP |
2108 | mtd->suspend = onenand_suspend; |
2109 | mtd->resume = onenand_resume; | |
cd5f6346 KP |
2110 | mtd->block_isbad = onenand_block_isbad; |
2111 | mtd->block_markbad = onenand_block_markbad; | |
2112 | mtd->owner = THIS_MODULE; | |
2113 | ||
2114 | /* Unlock whole block */ | |
28b79ff9 | 2115 | onenand_unlock_all(mtd); |
cd5f6346 | 2116 | |
cdc00130 | 2117 | return this->scan_bbt(mtd); |
cd5f6346 KP |
2118 | } |
2119 | ||
2120 | /** | |
2121 | * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device | |
2122 | * @param mtd MTD device structure | |
2123 | */ | |
2124 | void onenand_release(struct mtd_info *mtd) | |
2125 | { | |
532a37cf KP |
2126 | struct onenand_chip *this = mtd->priv; |
2127 | ||
cd5f6346 KP |
2128 | #ifdef CONFIG_MTD_PARTITIONS |
2129 | /* Deregister partitions */ | |
2130 | del_mtd_partitions (mtd); | |
2131 | #endif | |
2132 | /* Deregister the device */ | |
2133 | del_mtd_device (mtd); | |
532a37cf KP |
2134 | |
2135 | /* Free bad block table memory, if allocated */ | |
f00b0046 AH |
2136 | if (this->bbm) { |
2137 | struct bbm_info *bbm = this->bbm; | |
2138 | kfree(bbm->bbt); | |
532a37cf | 2139 | kfree(this->bbm); |
f00b0046 | 2140 | } |
532a37cf KP |
2141 | /* Buffer allocated by onenand_scan */ |
2142 | if (this->options & ONENAND_PAGEBUF_ALLOC) | |
2143 | kfree(this->page_buf); | |
cd5f6346 KP |
2144 | } |
2145 | ||
2146 | EXPORT_SYMBOL_GPL(onenand_scan); | |
2147 | EXPORT_SYMBOL_GPL(onenand_release); | |
2148 | ||
2149 | MODULE_LICENSE("GPL"); | |
2150 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
2151 | MODULE_DESCRIPTION("Generic OneNAND flash driver code"); |