Commit | Line | Data |
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cd5f6346 KP |
1 | /* |
2 | * linux/drivers/mtd/onenand/onenand_base.c | |
3 | * | |
75384b0d | 4 | * Copyright (C) 2005-2007 Samsung Electronics |
cd5f6346 KP |
5 | * Kyungmin Park <kyungmin.park@samsung.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
015953d7 | 15 | #include <linux/sched.h> |
2c22120f | 16 | #include <linux/interrupt.h> |
015953d7 | 17 | #include <linux/jiffies.h> |
cd5f6346 KP |
18 | #include <linux/mtd/mtd.h> |
19 | #include <linux/mtd/onenand.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | ||
24 | /** | |
25 | * onenand_oob_64 - oob info for large (2KB) page | |
26 | */ | |
5bd34c09 | 27 | static struct nand_ecclayout onenand_oob_64 = { |
cd5f6346 KP |
28 | .eccbytes = 20, |
29 | .eccpos = { | |
30 | 8, 9, 10, 11, 12, | |
31 | 24, 25, 26, 27, 28, | |
32 | 40, 41, 42, 43, 44, | |
33 | 56, 57, 58, 59, 60, | |
34 | }, | |
35 | .oobfree = { | |
36 | {2, 3}, {14, 2}, {18, 3}, {30, 2}, | |
d9777f1c JL |
37 | {34, 3}, {46, 2}, {50, 3}, {62, 2} |
38 | } | |
cd5f6346 KP |
39 | }; |
40 | ||
41 | /** | |
42 | * onenand_oob_32 - oob info for middle (1KB) page | |
43 | */ | |
5bd34c09 | 44 | static struct nand_ecclayout onenand_oob_32 = { |
cd5f6346 KP |
45 | .eccbytes = 10, |
46 | .eccpos = { | |
47 | 8, 9, 10, 11, 12, | |
48 | 24, 25, 26, 27, 28, | |
49 | }, | |
50 | .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } | |
51 | }; | |
52 | ||
53 | static const unsigned char ffchars[] = { | |
54 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
55 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ | |
56 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
57 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ | |
58 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
59 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ | |
60 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
61 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ | |
62 | }; | |
63 | ||
64 | /** | |
65 | * onenand_readw - [OneNAND Interface] Read OneNAND register | |
66 | * @param addr address to read | |
67 | * | |
68 | * Read OneNAND register | |
69 | */ | |
70 | static unsigned short onenand_readw(void __iomem *addr) | |
71 | { | |
72 | return readw(addr); | |
73 | } | |
74 | ||
75 | /** | |
76 | * onenand_writew - [OneNAND Interface] Write OneNAND register with value | |
77 | * @param value value to write | |
78 | * @param addr address to write | |
79 | * | |
80 | * Write OneNAND register with value | |
81 | */ | |
82 | static void onenand_writew(unsigned short value, void __iomem *addr) | |
83 | { | |
84 | writew(value, addr); | |
85 | } | |
86 | ||
87 | /** | |
88 | * onenand_block_address - [DEFAULT] Get block address | |
83a36838 | 89 | * @param this onenand chip data structure |
cd5f6346 KP |
90 | * @param block the block |
91 | * @return translated block address if DDP, otherwise same | |
92 | * | |
93 | * Setup Start Address 1 Register (F100h) | |
94 | */ | |
83a36838 | 95 | static int onenand_block_address(struct onenand_chip *this, int block) |
cd5f6346 | 96 | { |
738d61f5 KP |
97 | /* Device Flash Core select, NAND Flash Block Address */ |
98 | if (block & this->density_mask) | |
99 | return ONENAND_DDP_CHIP1 | (block ^ this->density_mask); | |
cd5f6346 KP |
100 | |
101 | return block; | |
102 | } | |
103 | ||
104 | /** | |
105 | * onenand_bufferram_address - [DEFAULT] Get bufferram address | |
83a36838 | 106 | * @param this onenand chip data structure |
cd5f6346 KP |
107 | * @param block the block |
108 | * @return set DBS value if DDP, otherwise 0 | |
109 | * | |
110 | * Setup Start Address 2 Register (F101h) for DDP | |
111 | */ | |
83a36838 | 112 | static int onenand_bufferram_address(struct onenand_chip *this, int block) |
cd5f6346 | 113 | { |
738d61f5 KP |
114 | /* Device BufferRAM Select */ |
115 | if (block & this->density_mask) | |
116 | return ONENAND_DDP_CHIP1; | |
cd5f6346 | 117 | |
738d61f5 | 118 | return ONENAND_DDP_CHIP0; |
cd5f6346 KP |
119 | } |
120 | ||
121 | /** | |
122 | * onenand_page_address - [DEFAULT] Get page address | |
123 | * @param page the page address | |
124 | * @param sector the sector address | |
125 | * @return combined page and sector address | |
126 | * | |
127 | * Setup Start Address 8 Register (F107h) | |
128 | */ | |
129 | static int onenand_page_address(int page, int sector) | |
130 | { | |
131 | /* Flash Page Address, Flash Sector Address */ | |
132 | int fpa, fsa; | |
133 | ||
134 | fpa = page & ONENAND_FPA_MASK; | |
135 | fsa = sector & ONENAND_FSA_MASK; | |
136 | ||
137 | return ((fpa << ONENAND_FPA_SHIFT) | fsa); | |
138 | } | |
139 | ||
140 | /** | |
141 | * onenand_buffer_address - [DEFAULT] Get buffer address | |
142 | * @param dataram1 DataRAM index | |
143 | * @param sectors the sector address | |
144 | * @param count the number of sectors | |
145 | * @return the start buffer value | |
146 | * | |
147 | * Setup Start Buffer Register (F200h) | |
148 | */ | |
149 | static int onenand_buffer_address(int dataram1, int sectors, int count) | |
150 | { | |
151 | int bsa, bsc; | |
152 | ||
153 | /* BufferRAM Sector Address */ | |
154 | bsa = sectors & ONENAND_BSA_MASK; | |
155 | ||
156 | if (dataram1) | |
157 | bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ | |
158 | else | |
159 | bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ | |
160 | ||
161 | /* BufferRAM Sector Count */ | |
162 | bsc = count & ONENAND_BSC_MASK; | |
163 | ||
164 | return ((bsa << ONENAND_BSA_SHIFT) | bsc); | |
165 | } | |
166 | ||
167 | /** | |
168 | * onenand_command - [DEFAULT] Send command to OneNAND device | |
169 | * @param mtd MTD device structure | |
170 | * @param cmd the command to be sent | |
171 | * @param addr offset to read from or write to | |
172 | * @param len number of bytes to read or write | |
173 | * | |
174 | * Send command to OneNAND device. This function is used for middle/large page | |
175 | * devices (1KB/2KB Bytes per page) | |
176 | */ | |
177 | static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) | |
178 | { | |
179 | struct onenand_chip *this = mtd->priv; | |
493c6460 | 180 | int value, readcmd = 0, block_cmd = 0; |
cd5f6346 | 181 | int block, page; |
cd5f6346 KP |
182 | |
183 | /* Address translation */ | |
184 | switch (cmd) { | |
185 | case ONENAND_CMD_UNLOCK: | |
186 | case ONENAND_CMD_LOCK: | |
187 | case ONENAND_CMD_LOCK_TIGHT: | |
28b79ff9 | 188 | case ONENAND_CMD_UNLOCK_ALL: |
cd5f6346 KP |
189 | block = -1; |
190 | page = -1; | |
191 | break; | |
192 | ||
193 | case ONENAND_CMD_ERASE: | |
194 | case ONENAND_CMD_BUFFERRAM: | |
493c6460 KP |
195 | case ONENAND_CMD_OTP_ACCESS: |
196 | block_cmd = 1; | |
cd5f6346 KP |
197 | block = (int) (addr >> this->erase_shift); |
198 | page = -1; | |
199 | break; | |
200 | ||
201 | default: | |
202 | block = (int) (addr >> this->erase_shift); | |
203 | page = (int) (addr >> this->page_shift); | |
204 | page &= this->page_mask; | |
205 | break; | |
206 | } | |
207 | ||
208 | /* NOTE: The setting order of the registers is very important! */ | |
209 | if (cmd == ONENAND_CMD_BUFFERRAM) { | |
210 | /* Select DataRAM for DDP */ | |
83a36838 | 211 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
212 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
213 | ||
214 | /* Switch to the next data buffer */ | |
215 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | if (block != -1) { | |
221 | /* Write 'DFS, FBA' of Flash */ | |
83a36838 | 222 | value = onenand_block_address(this, block); |
cd5f6346 | 223 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); |
3cecf69e | 224 | |
75287070 | 225 | if (block_cmd) { |
3cecf69e KP |
226 | /* Select DataRAM for DDP */ |
227 | value = onenand_bufferram_address(this, block); | |
228 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
229 | } | |
cd5f6346 KP |
230 | } |
231 | ||
232 | if (page != -1) { | |
60d84f97 KP |
233 | /* Now we use page size operation */ |
234 | int sectors = 4, count = 4; | |
cd5f6346 KP |
235 | int dataram; |
236 | ||
237 | switch (cmd) { | |
238 | case ONENAND_CMD_READ: | |
239 | case ONENAND_CMD_READOOB: | |
240 | dataram = ONENAND_SET_NEXT_BUFFERRAM(this); | |
241 | readcmd = 1; | |
242 | break; | |
243 | ||
244 | default: | |
245 | dataram = ONENAND_CURRENT_BUFFERRAM(this); | |
246 | break; | |
247 | } | |
248 | ||
249 | /* Write 'FPA, FSA' of Flash */ | |
250 | value = onenand_page_address(page, sectors); | |
251 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); | |
252 | ||
253 | /* Write 'BSA, BSC' of DataRAM */ | |
254 | value = onenand_buffer_address(dataram, sectors, count); | |
255 | this->write_word(value, this->base + ONENAND_REG_START_BUFFER); | |
d5c5e78a | 256 | |
cd5f6346 KP |
257 | if (readcmd) { |
258 | /* Select DataRAM for DDP */ | |
83a36838 | 259 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
260 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
261 | } | |
262 | } | |
263 | ||
264 | /* Interrupt clear */ | |
265 | this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); | |
266 | ||
267 | /* Write command */ | |
268 | this->write_word(cmd, this->base + ONENAND_REG_COMMAND); | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /** | |
274 | * onenand_wait - [DEFAULT] wait until the command is done | |
275 | * @param mtd MTD device structure | |
276 | * @param state state to select the max. timeout value | |
277 | * | |
278 | * Wait for command done. This applies to all OneNAND command | |
279 | * Read can take up to 30us, erase up to 2ms and program up to 350us | |
280 | * according to general OneNAND specs | |
281 | */ | |
282 | static int onenand_wait(struct mtd_info *mtd, int state) | |
283 | { | |
284 | struct onenand_chip * this = mtd->priv; | |
285 | unsigned long timeout; | |
286 | unsigned int flags = ONENAND_INT_MASTER; | |
287 | unsigned int interrupt = 0; | |
2fd32d4a | 288 | unsigned int ctrl; |
cd5f6346 KP |
289 | |
290 | /* The 20 msec is enough */ | |
291 | timeout = jiffies + msecs_to_jiffies(20); | |
292 | while (time_before(jiffies, timeout)) { | |
293 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
294 | ||
295 | if (interrupt & flags) | |
296 | break; | |
297 | ||
298 | if (state != FL_READING) | |
299 | cond_resched(); | |
300 | } | |
301 | /* To get correct interrupt status in timeout case */ | |
302 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
303 | ||
304 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
305 | ||
306 | if (ctrl & ONENAND_CTRL_ERROR) { | |
cdc00130 | 307 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x\n", ctrl); |
f6272487 KP |
308 | if (ctrl & ONENAND_CTRL_LOCK) |
309 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error.\n"); | |
310 | return ctrl; | |
cd5f6346 KP |
311 | } |
312 | ||
313 | if (interrupt & ONENAND_INT_READ) { | |
2fd32d4a | 314 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); |
f4f91ac3 | 315 | if (ecc) { |
cdc00130 | 316 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x\n", ecc); |
b3c9f8bf | 317 | if (ecc & ONENAND_ECC_2BIT_ALL) { |
f4f91ac3 | 318 | mtd->ecc_stats.failed++; |
b3c9f8bf KP |
319 | return ecc; |
320 | } else if (ecc & ONENAND_ECC_1BIT_ALL) | |
f4f91ac3 | 321 | mtd->ecc_stats.corrected++; |
cd5f6346 | 322 | } |
9d032801 AH |
323 | } else if (state == FL_READING) { |
324 | printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
325 | return -EIO; | |
cd5f6346 KP |
326 | } |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
2c22120f KP |
331 | /* |
332 | * onenand_interrupt - [DEFAULT] onenand interrupt handler | |
333 | * @param irq onenand interrupt number | |
334 | * @param dev_id interrupt data | |
335 | * | |
336 | * complete the work | |
337 | */ | |
338 | static irqreturn_t onenand_interrupt(int irq, void *data) | |
339 | { | |
340 | struct onenand_chip *this = (struct onenand_chip *) data; | |
341 | ||
342 | /* To handle shared interrupt */ | |
343 | if (!this->complete.done) | |
344 | complete(&this->complete); | |
345 | ||
346 | return IRQ_HANDLED; | |
347 | } | |
348 | ||
349 | /* | |
350 | * onenand_interrupt_wait - [DEFAULT] wait until the command is done | |
351 | * @param mtd MTD device structure | |
352 | * @param state state to select the max. timeout value | |
353 | * | |
354 | * Wait for command done. | |
355 | */ | |
356 | static int onenand_interrupt_wait(struct mtd_info *mtd, int state) | |
357 | { | |
358 | struct onenand_chip *this = mtd->priv; | |
359 | ||
2c22120f KP |
360 | wait_for_completion(&this->complete); |
361 | ||
362 | return onenand_wait(mtd, state); | |
363 | } | |
364 | ||
365 | /* | |
366 | * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait | |
367 | * @param mtd MTD device structure | |
368 | * @param state state to select the max. timeout value | |
369 | * | |
370 | * Try interrupt based wait (It is used one-time) | |
371 | */ | |
372 | static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state) | |
373 | { | |
374 | struct onenand_chip *this = mtd->priv; | |
375 | unsigned long remain, timeout; | |
376 | ||
377 | /* We use interrupt wait first */ | |
378 | this->wait = onenand_interrupt_wait; | |
379 | ||
2c22120f KP |
380 | timeout = msecs_to_jiffies(100); |
381 | remain = wait_for_completion_timeout(&this->complete, timeout); | |
382 | if (!remain) { | |
383 | printk(KERN_INFO "OneNAND: There's no interrupt. " | |
384 | "We use the normal wait\n"); | |
385 | ||
386 | /* Release the irq */ | |
387 | free_irq(this->irq, this); | |
c9ac5977 | 388 | |
2c22120f KP |
389 | this->wait = onenand_wait; |
390 | } | |
391 | ||
392 | return onenand_wait(mtd, state); | |
393 | } | |
394 | ||
395 | /* | |
396 | * onenand_setup_wait - [OneNAND Interface] setup onenand wait method | |
397 | * @param mtd MTD device structure | |
398 | * | |
399 | * There's two method to wait onenand work | |
400 | * 1. polling - read interrupt status register | |
401 | * 2. interrupt - use the kernel interrupt method | |
402 | */ | |
403 | static void onenand_setup_wait(struct mtd_info *mtd) | |
404 | { | |
405 | struct onenand_chip *this = mtd->priv; | |
406 | int syscfg; | |
407 | ||
408 | init_completion(&this->complete); | |
409 | ||
410 | if (this->irq <= 0) { | |
411 | this->wait = onenand_wait; | |
412 | return; | |
413 | } | |
414 | ||
415 | if (request_irq(this->irq, &onenand_interrupt, | |
416 | IRQF_SHARED, "onenand", this)) { | |
417 | /* If we can't get irq, use the normal wait */ | |
418 | this->wait = onenand_wait; | |
419 | return; | |
420 | } | |
421 | ||
422 | /* Enable interrupt */ | |
423 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
424 | syscfg |= ONENAND_SYS_CFG1_IOBE; | |
425 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
426 | ||
427 | this->wait = onenand_try_interrupt_wait; | |
428 | } | |
429 | ||
cd5f6346 KP |
430 | /** |
431 | * onenand_bufferram_offset - [DEFAULT] BufferRAM offset | |
432 | * @param mtd MTD data structure | |
433 | * @param area BufferRAM area | |
434 | * @return offset given area | |
435 | * | |
436 | * Return BufferRAM offset given area | |
437 | */ | |
438 | static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) | |
439 | { | |
440 | struct onenand_chip *this = mtd->priv; | |
441 | ||
442 | if (ONENAND_CURRENT_BUFFERRAM(this)) { | |
443 | if (area == ONENAND_DATARAM) | |
28318776 | 444 | return mtd->writesize; |
cd5f6346 KP |
445 | if (area == ONENAND_SPARERAM) |
446 | return mtd->oobsize; | |
447 | } | |
448 | ||
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area | |
454 | * @param mtd MTD data structure | |
455 | * @param area BufferRAM area | |
456 | * @param buffer the databuffer to put/get data | |
457 | * @param offset offset to read from or write to | |
458 | * @param count number of bytes to read/write | |
459 | * | |
460 | * Read the BufferRAM area | |
461 | */ | |
462 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
463 | unsigned char *buffer, int offset, size_t count) | |
464 | { | |
465 | struct onenand_chip *this = mtd->priv; | |
466 | void __iomem *bufferram; | |
467 | ||
468 | bufferram = this->base + area; | |
469 | ||
470 | bufferram += onenand_bufferram_offset(mtd, area); | |
471 | ||
9c01f87d KP |
472 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
473 | unsigned short word; | |
474 | ||
475 | /* Align with word(16-bit) size */ | |
476 | count--; | |
477 | ||
478 | /* Read word and save byte */ | |
479 | word = this->read_word(bufferram + offset + count); | |
480 | buffer[count] = (word & 0xff); | |
481 | } | |
482 | ||
cd5f6346 KP |
483 | memcpy(buffer, bufferram + offset, count); |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
52b0eea7 KP |
488 | /** |
489 | * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode | |
490 | * @param mtd MTD data structure | |
491 | * @param area BufferRAM area | |
492 | * @param buffer the databuffer to put/get data | |
493 | * @param offset offset to read from or write to | |
494 | * @param count number of bytes to read/write | |
495 | * | |
496 | * Read the BufferRAM area with Sync. Burst Mode | |
497 | */ | |
498 | static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, | |
499 | unsigned char *buffer, int offset, size_t count) | |
500 | { | |
501 | struct onenand_chip *this = mtd->priv; | |
502 | void __iomem *bufferram; | |
503 | ||
504 | bufferram = this->base + area; | |
505 | ||
506 | bufferram += onenand_bufferram_offset(mtd, area); | |
507 | ||
508 | this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); | |
509 | ||
9c01f87d KP |
510 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
511 | unsigned short word; | |
512 | ||
513 | /* Align with word(16-bit) size */ | |
514 | count--; | |
515 | ||
516 | /* Read word and save byte */ | |
517 | word = this->read_word(bufferram + offset + count); | |
518 | buffer[count] = (word & 0xff); | |
519 | } | |
520 | ||
52b0eea7 KP |
521 | memcpy(buffer, bufferram + offset, count); |
522 | ||
523 | this->mmcontrol(mtd, 0); | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
cd5f6346 KP |
528 | /** |
529 | * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area | |
530 | * @param mtd MTD data structure | |
531 | * @param area BufferRAM area | |
532 | * @param buffer the databuffer to put/get data | |
533 | * @param offset offset to read from or write to | |
534 | * @param count number of bytes to read/write | |
535 | * | |
536 | * Write the BufferRAM area | |
537 | */ | |
538 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
539 | const unsigned char *buffer, int offset, size_t count) | |
540 | { | |
541 | struct onenand_chip *this = mtd->priv; | |
542 | void __iomem *bufferram; | |
543 | ||
544 | bufferram = this->base + area; | |
545 | ||
546 | bufferram += onenand_bufferram_offset(mtd, area); | |
547 | ||
9c01f87d KP |
548 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
549 | unsigned short word; | |
550 | int byte_offset; | |
551 | ||
552 | /* Align with word(16-bit) size */ | |
553 | count--; | |
554 | ||
555 | /* Calculate byte access offset */ | |
556 | byte_offset = offset + count; | |
557 | ||
558 | /* Read word and save byte */ | |
559 | word = this->read_word(bufferram + byte_offset); | |
560 | word = (word & ~0xff) | buffer[count]; | |
561 | this->write_word(word, bufferram + byte_offset); | |
562 | } | |
563 | ||
cd5f6346 KP |
564 | memcpy(bufferram + offset, buffer, count); |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | /** | |
570 | * onenand_check_bufferram - [GENERIC] Check BufferRAM information | |
571 | * @param mtd MTD data structure | |
572 | * @param addr address to check | |
d5c5e78a | 573 | * @return 1 if there are valid data, otherwise 0 |
cd5f6346 KP |
574 | * |
575 | * Check bufferram if there is data we required | |
576 | */ | |
577 | static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) | |
578 | { | |
579 | struct onenand_chip *this = mtd->priv; | |
580 | int block, page; | |
581 | int i; | |
d5c5e78a | 582 | |
cd5f6346 | 583 | block = (int) (addr >> this->erase_shift); |
75384b0d | 584 | page = (int) (addr >> this->page_shift) & this->page_mask; |
cd5f6346 KP |
585 | |
586 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
587 | ||
588 | /* Is there valid data? */ | |
589 | if (this->bufferram[i].block == block && | |
590 | this->bufferram[i].page == page && | |
591 | this->bufferram[i].valid) | |
592 | return 1; | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | /** | |
598 | * onenand_update_bufferram - [GENERIC] Update BufferRAM information | |
599 | * @param mtd MTD data structure | |
600 | * @param addr address to update | |
601 | * @param valid valid flag | |
602 | * | |
603 | * Update BufferRAM information | |
604 | */ | |
605 | static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, | |
606 | int valid) | |
607 | { | |
608 | struct onenand_chip *this = mtd->priv; | |
609 | int block, page; | |
610 | int i; | |
d5c5e78a | 611 | |
cd5f6346 | 612 | block = (int) (addr >> this->erase_shift); |
75384b0d | 613 | page = (int) (addr >> this->page_shift) & this->page_mask; |
cd5f6346 KP |
614 | |
615 | /* Invalidate BufferRAM */ | |
616 | for (i = 0; i < MAX_BUFFERRAM; i++) { | |
617 | if (this->bufferram[i].block == block && | |
618 | this->bufferram[i].page == page) | |
619 | this->bufferram[i].valid = 0; | |
620 | } | |
621 | ||
622 | /* Update BufferRAM */ | |
623 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
624 | this->bufferram[i].block = block; | |
625 | this->bufferram[i].page = page; | |
626 | this->bufferram[i].valid = valid; | |
627 | ||
628 | return 0; | |
629 | } | |
630 | ||
631 | /** | |
632 | * onenand_get_device - [GENERIC] Get chip for selected access | |
633 | * @param mtd MTD device structure | |
634 | * @param new_state the state which is requested | |
635 | * | |
636 | * Get the device and lock it for exclusive access | |
637 | */ | |
a41371eb | 638 | static int onenand_get_device(struct mtd_info *mtd, int new_state) |
cd5f6346 KP |
639 | { |
640 | struct onenand_chip *this = mtd->priv; | |
641 | DECLARE_WAITQUEUE(wait, current); | |
642 | ||
643 | /* | |
644 | * Grab the lock and see if the device is available | |
645 | */ | |
646 | while (1) { | |
647 | spin_lock(&this->chip_lock); | |
648 | if (this->state == FL_READY) { | |
649 | this->state = new_state; | |
650 | spin_unlock(&this->chip_lock); | |
651 | break; | |
652 | } | |
a41371eb KP |
653 | if (new_state == FL_PM_SUSPENDED) { |
654 | spin_unlock(&this->chip_lock); | |
655 | return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; | |
656 | } | |
cd5f6346 KP |
657 | set_current_state(TASK_UNINTERRUPTIBLE); |
658 | add_wait_queue(&this->wq, &wait); | |
659 | spin_unlock(&this->chip_lock); | |
660 | schedule(); | |
661 | remove_wait_queue(&this->wq, &wait); | |
662 | } | |
a41371eb KP |
663 | |
664 | return 0; | |
cd5f6346 KP |
665 | } |
666 | ||
667 | /** | |
668 | * onenand_release_device - [GENERIC] release chip | |
669 | * @param mtd MTD device structure | |
670 | * | |
671 | * Deselect, release chip lock and wake up anyone waiting on the device | |
672 | */ | |
673 | static void onenand_release_device(struct mtd_info *mtd) | |
674 | { | |
675 | struct onenand_chip *this = mtd->priv; | |
676 | ||
677 | /* Release the chip */ | |
678 | spin_lock(&this->chip_lock); | |
679 | this->state = FL_READY; | |
680 | wake_up(&this->wq); | |
681 | spin_unlock(&this->chip_lock); | |
682 | } | |
683 | ||
684 | /** | |
9223a456 | 685 | * onenand_read - [MTD Interface] Read data from flash |
cd5f6346 KP |
686 | * @param mtd MTD device structure |
687 | * @param from offset to read from | |
688 | * @param len number of bytes to read | |
689 | * @param retlen pointer to variable to store the number of read bytes | |
690 | * @param buf the databuffer to put data | |
cd5f6346 | 691 | * |
9223a456 TG |
692 | * Read with ecc |
693 | */ | |
694 | static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
695 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
696 | { |
697 | struct onenand_chip *this = mtd->priv; | |
f4f91ac3 | 698 | struct mtd_ecc_stats stats; |
cd5f6346 KP |
699 | int read = 0, column; |
700 | int thislen; | |
0fc2ccea | 701 | int ret = 0, boundary = 0; |
cd5f6346 | 702 | |
9223a456 | 703 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); |
cd5f6346 KP |
704 | |
705 | /* Do not allow reads past end of device */ | |
706 | if ((from + len) > mtd->size) { | |
9223a456 | 707 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read: Attempt read beyond end of device\n"); |
cd5f6346 KP |
708 | *retlen = 0; |
709 | return -EINVAL; | |
710 | } | |
711 | ||
712 | /* Grab the lock and see if the device is available */ | |
713 | onenand_get_device(mtd, FL_READING); | |
714 | ||
f4f91ac3 | 715 | stats = mtd->ecc_stats; |
61a7e198 | 716 | |
a8de85d5 AH |
717 | /* Read-while-load method */ |
718 | ||
719 | /* Do first load to bufferRAM */ | |
720 | if (read < len) { | |
721 | if (!onenand_check_bufferram(mtd, from)) { | |
722 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
723 | ret = this->wait(mtd, FL_READING); | |
724 | onenand_update_bufferram(mtd, from, !ret); | |
725 | } | |
726 | } | |
727 | ||
728 | thislen = min_t(int, mtd->writesize, len - read); | |
729 | column = from & (mtd->writesize - 1); | |
730 | if (column + thislen > mtd->writesize) | |
731 | thislen = mtd->writesize - column; | |
732 | ||
733 | while (!ret) { | |
734 | /* If there is more to load then start next load */ | |
735 | from += thislen; | |
736 | if (read + thislen < len) { | |
737 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
0fc2ccea AH |
738 | /* |
739 | * Chip boundary handling in DDP | |
740 | * Now we issued chip 1 read and pointed chip 1 | |
741 | * bufferam so we have to point chip 0 bufferam. | |
742 | */ | |
738d61f5 KP |
743 | if (ONENAND_IS_DDP(this) && |
744 | unlikely(from == (this->chipsize >> 1))) { | |
745 | this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); | |
0fc2ccea AH |
746 | boundary = 1; |
747 | } else | |
748 | boundary = 0; | |
a8de85d5 AH |
749 | ONENAND_SET_PREV_BUFFERRAM(this); |
750 | } | |
751 | /* While load is going, read from last bufferRAM */ | |
752 | this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); | |
753 | /* See if we are done */ | |
754 | read += thislen; | |
755 | if (read == len) | |
756 | break; | |
757 | /* Set up for next read from bufferRAM */ | |
0fc2ccea | 758 | if (unlikely(boundary)) |
738d61f5 | 759 | this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); |
a8de85d5 AH |
760 | ONENAND_SET_NEXT_BUFFERRAM(this); |
761 | buf += thislen; | |
762 | thislen = min_t(int, mtd->writesize, len - read); | |
763 | column = 0; | |
764 | cond_resched(); | |
765 | /* Now wait for load */ | |
766 | ret = this->wait(mtd, FL_READING); | |
767 | onenand_update_bufferram(mtd, from, !ret); | |
768 | } | |
cd5f6346 | 769 | |
cd5f6346 KP |
770 | /* Deselect and wake up anyone waiting on the device */ |
771 | onenand_release_device(mtd); | |
772 | ||
773 | /* | |
774 | * Return success, if no ECC failures, else -EBADMSG | |
775 | * fs driver will take care of that, because | |
776 | * retlen == desired len and result == -EBADMSG | |
777 | */ | |
778 | *retlen = read; | |
f4f91ac3 KP |
779 | |
780 | if (mtd->ecc_stats.failed - stats.failed) | |
781 | return -EBADMSG; | |
782 | ||
a8de85d5 AH |
783 | if (ret) |
784 | return ret; | |
785 | ||
f4f91ac3 | 786 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; |
cd5f6346 KP |
787 | } |
788 | ||
a5e7c7b4 AH |
789 | /** |
790 | * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer | |
791 | * @param mtd MTD device structure | |
792 | * @param buf destination address | |
793 | * @param column oob offset to read from | |
794 | * @param thislen oob length to read | |
795 | */ | |
796 | static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column, | |
797 | int thislen) | |
798 | { | |
799 | struct onenand_chip *this = mtd->priv; | |
800 | struct nand_oobfree *free; | |
801 | int readcol = column; | |
802 | int readend = column + thislen; | |
803 | int lastgap = 0; | |
804 | uint8_t *oob_buf = this->page_buf + mtd->writesize; | |
805 | ||
806 | for (free = this->ecclayout->oobfree; free->length; ++free) { | |
807 | if (readcol >= lastgap) | |
808 | readcol += free->offset - lastgap; | |
809 | if (readend >= lastgap) | |
810 | readend += free->offset - lastgap; | |
811 | lastgap = free->offset + free->length; | |
812 | } | |
4f4fad27 | 813 | this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); |
a5e7c7b4 AH |
814 | for (free = this->ecclayout->oobfree; free->length; ++free) { |
815 | int free_end = free->offset + free->length; | |
816 | if (free->offset < readend && free_end > readcol) { | |
817 | int st = max_t(int,free->offset,readcol); | |
818 | int ed = min_t(int,free_end,readend); | |
819 | int n = ed - st; | |
820 | memcpy(buf, oob_buf + st, n); | |
821 | buf += n; | |
822 | } | |
823 | } | |
824 | return 0; | |
825 | } | |
826 | ||
cd5f6346 | 827 | /** |
8593fbc6 | 828 | * onenand_do_read_oob - [MTD Interface] OneNAND read out-of-band |
cd5f6346 KP |
829 | * @param mtd MTD device structure |
830 | * @param from offset to read from | |
831 | * @param len number of bytes to read | |
832 | * @param retlen pointer to variable to store the number of read bytes | |
833 | * @param buf the databuffer to put data | |
a5e7c7b4 | 834 | * @param mode operation mode |
cd5f6346 KP |
835 | * |
836 | * OneNAND read out-of-band data from the spare area | |
837 | */ | |
8593fbc6 | 838 | int onenand_do_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
a5e7c7b4 | 839 | size_t *retlen, u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
840 | { |
841 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 842 | int read = 0, thislen, column, oobsize; |
cd5f6346 KP |
843 | int ret = 0; |
844 | ||
845 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); | |
846 | ||
847 | /* Initialize return length value */ | |
848 | *retlen = 0; | |
849 | ||
a5e7c7b4 AH |
850 | if (mode == MTD_OOB_AUTO) |
851 | oobsize = this->ecclayout->oobavail; | |
852 | else | |
853 | oobsize = mtd->oobsize; | |
854 | ||
855 | column = from & (mtd->oobsize - 1); | |
856 | ||
857 | if (unlikely(column >= oobsize)) { | |
858 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempted to start read outside oob\n"); | |
859 | return -EINVAL; | |
860 | } | |
861 | ||
cd5f6346 | 862 | /* Do not allow reads past end of device */ |
a5e7c7b4 AH |
863 | if (unlikely(from >= mtd->size || |
864 | column + len > ((mtd->size >> this->page_shift) - | |
865 | (from >> this->page_shift)) * oobsize)) { | |
866 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempted to read beyond end of device\n"); | |
cd5f6346 KP |
867 | return -EINVAL; |
868 | } | |
869 | ||
870 | /* Grab the lock and see if the device is available */ | |
871 | onenand_get_device(mtd, FL_READING); | |
872 | ||
cd5f6346 | 873 | while (read < len) { |
61a7e198 AB |
874 | cond_resched(); |
875 | ||
a5e7c7b4 | 876 | thislen = oobsize - column; |
cd5f6346 KP |
877 | thislen = min_t(int, thislen, len); |
878 | ||
879 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
880 | ||
881 | onenand_update_bufferram(mtd, from, 0); | |
882 | ||
883 | ret = this->wait(mtd, FL_READING); | |
884 | /* First copy data and check return value for ECC handling */ | |
885 | ||
a5e7c7b4 AH |
886 | if (mode == MTD_OOB_AUTO) |
887 | onenand_transfer_auto_oob(mtd, buf, column, thislen); | |
888 | else | |
889 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
cd5f6346 | 890 | |
f6272487 KP |
891 | if (ret) { |
892 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = 0x%x\n", ret); | |
893 | goto out; | |
894 | } | |
895 | ||
cd5f6346 KP |
896 | read += thislen; |
897 | ||
898 | if (read == len) | |
899 | break; | |
900 | ||
cd5f6346 KP |
901 | buf += thislen; |
902 | ||
903 | /* Read more? */ | |
904 | if (read < len) { | |
905 | /* Page size */ | |
28318776 | 906 | from += mtd->writesize; |
cd5f6346 KP |
907 | column = 0; |
908 | } | |
909 | } | |
910 | ||
911 | out: | |
912 | /* Deselect and wake up anyone waiting on the device */ | |
913 | onenand_release_device(mtd); | |
914 | ||
915 | *retlen = read; | |
916 | return ret; | |
917 | } | |
918 | ||
8593fbc6 TG |
919 | /** |
920 | * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band | |
921 | * @mtd: MTD device structure | |
922 | * @from: offset to read from | |
923 | * @ops: oob operation description structure | |
924 | */ | |
925 | static int onenand_read_oob(struct mtd_info *mtd, loff_t from, | |
926 | struct mtd_oob_ops *ops) | |
927 | { | |
4f4fad27 | 928 | switch (ops->mode) { |
a5e7c7b4 AH |
929 | case MTD_OOB_PLACE: |
930 | case MTD_OOB_AUTO: | |
931 | break; | |
932 | case MTD_OOB_RAW: | |
4f4fad27 | 933 | /* Not implemented yet */ |
a5e7c7b4 AH |
934 | default: |
935 | return -EINVAL; | |
936 | } | |
66a1e421 | 937 | return onenand_do_read_oob(mtd, from + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 938 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
939 | } |
940 | ||
cd5f6346 | 941 | #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE |
8e6ec690 KP |
942 | /** |
943 | * onenand_verify_oob - [GENERIC] verify the oob contents after a write | |
944 | * @param mtd MTD device structure | |
945 | * @param buf the databuffer to verify | |
946 | * @param to offset to read from | |
8e6ec690 KP |
947 | * |
948 | */ | |
a5e7c7b4 | 949 | static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to) |
8e6ec690 KP |
950 | { |
951 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 952 | char *readp = this->page_buf + mtd->writesize; |
8e6ec690 KP |
953 | int status, i; |
954 | ||
955 | this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); | |
956 | onenand_update_bufferram(mtd, to, 0); | |
957 | status = this->wait(mtd, FL_READING); | |
958 | if (status) | |
959 | return status; | |
960 | ||
a5e7c7b4 AH |
961 | this->read_bufferram(mtd, ONENAND_SPARERAM, readp, 0, mtd->oobsize); |
962 | for(i = 0; i < mtd->oobsize; i++) | |
8e6ec690 KP |
963 | if (buf[i] != 0xFF && buf[i] != readp[i]) |
964 | return -EBADMSG; | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
cd5f6346 | 969 | /** |
8b29c0b6 AH |
970 | * onenand_verify - [GENERIC] verify the chip contents after a write |
971 | * @param mtd MTD device structure | |
972 | * @param buf the databuffer to verify | |
973 | * @param addr offset to read from | |
974 | * @param len number of bytes to read and compare | |
cd5f6346 | 975 | * |
cd5f6346 | 976 | */ |
8b29c0b6 | 977 | static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len) |
cd5f6346 KP |
978 | { |
979 | struct onenand_chip *this = mtd->priv; | |
8b29c0b6 | 980 | void __iomem *dataram; |
cd5f6346 | 981 | int ret = 0; |
8b29c0b6 | 982 | int thislen, column; |
cd5f6346 | 983 | |
8b29c0b6 AH |
984 | while (len != 0) { |
985 | thislen = min_t(int, mtd->writesize, len); | |
986 | column = addr & (mtd->writesize - 1); | |
987 | if (column + thislen > mtd->writesize) | |
988 | thislen = mtd->writesize - column; | |
60d84f97 | 989 | |
8b29c0b6 | 990 | this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); |
cd5f6346 | 991 | |
8b29c0b6 AH |
992 | onenand_update_bufferram(mtd, addr, 0); |
993 | ||
994 | ret = this->wait(mtd, FL_READING); | |
995 | if (ret) | |
996 | return ret; | |
cd5f6346 | 997 | |
8b29c0b6 | 998 | onenand_update_bufferram(mtd, addr, 1); |
cd5f6346 | 999 | |
8b29c0b6 AH |
1000 | dataram = this->base + ONENAND_DATARAM; |
1001 | dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM); | |
cd5f6346 | 1002 | |
8b29c0b6 AH |
1003 | if (memcmp(buf, dataram + column, thislen)) |
1004 | return -EBADMSG; | |
1005 | ||
1006 | len -= thislen; | |
1007 | buf += thislen; | |
1008 | addr += thislen; | |
1009 | } | |
d5c5e78a | 1010 | |
cd5f6346 KP |
1011 | return 0; |
1012 | } | |
1013 | #else | |
8b29c0b6 | 1014 | #define onenand_verify(...) (0) |
8e6ec690 | 1015 | #define onenand_verify_oob(...) (0) |
cd5f6346 KP |
1016 | #endif |
1017 | ||
60d84f97 | 1018 | #define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) |
cd5f6346 KP |
1019 | |
1020 | /** | |
9223a456 | 1021 | * onenand_write - [MTD Interface] write buffer to FLASH |
cd5f6346 KP |
1022 | * @param mtd MTD device structure |
1023 | * @param to offset to write to | |
1024 | * @param len number of bytes to write | |
1025 | * @param retlen pointer to variable to store the number of written bytes | |
1026 | * @param buf the data to write | |
cd5f6346 | 1027 | * |
9223a456 | 1028 | * Write with ECC |
cd5f6346 | 1029 | */ |
9223a456 TG |
1030 | static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1031 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
1032 | { |
1033 | struct onenand_chip *this = mtd->priv; | |
1034 | int written = 0; | |
1035 | int ret = 0; | |
60d84f97 | 1036 | int column, subpage; |
cd5f6346 | 1037 | |
9223a456 | 1038 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); |
cd5f6346 KP |
1039 | |
1040 | /* Initialize retlen, in case of early exit */ | |
1041 | *retlen = 0; | |
1042 | ||
1043 | /* Do not allow writes past end of device */ | |
1044 | if (unlikely((to + len) > mtd->size)) { | |
9223a456 | 1045 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt write to past end of device\n"); |
cd5f6346 KP |
1046 | return -EINVAL; |
1047 | } | |
1048 | ||
1049 | /* Reject writes, which are not page aligned */ | |
1050 | if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { | |
9223a456 | 1051 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt to write not page aligned data\n"); |
cd5f6346 KP |
1052 | return -EINVAL; |
1053 | } | |
1054 | ||
60d84f97 KP |
1055 | column = to & (mtd->writesize - 1); |
1056 | subpage = column || (len & (mtd->writesize - 1)); | |
1057 | ||
cd5f6346 KP |
1058 | /* Grab the lock and see if the device is available */ |
1059 | onenand_get_device(mtd, FL_WRITING); | |
1060 | ||
1061 | /* Loop until all data write */ | |
1062 | while (written < len) { | |
60d84f97 KP |
1063 | int bytes = mtd->writesize; |
1064 | int thislen = min_t(int, bytes, len - written); | |
1065 | u_char *wbuf = (u_char *) buf; | |
1066 | ||
61a7e198 AB |
1067 | cond_resched(); |
1068 | ||
60d84f97 KP |
1069 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, bytes); |
1070 | ||
1071 | /* Partial page write */ | |
1072 | if (subpage) { | |
1073 | bytes = min_t(int, bytes - column, (int) len); | |
1074 | memset(this->page_buf, 0xff, mtd->writesize); | |
1075 | memcpy(this->page_buf + column, buf, bytes); | |
1076 | wbuf = this->page_buf; | |
1077 | /* Even though partial write, we need page size */ | |
1078 | thislen = mtd->writesize; | |
1079 | } | |
cd5f6346 | 1080 | |
60d84f97 | 1081 | this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, thislen); |
cd5f6346 KP |
1082 | this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); |
1083 | ||
28318776 | 1084 | this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); |
cd5f6346 | 1085 | |
60d84f97 KP |
1086 | /* In partial page write we don't update bufferram */ |
1087 | onenand_update_bufferram(mtd, to, !subpage); | |
cd5f6346 KP |
1088 | |
1089 | ret = this->wait(mtd, FL_WRITING); | |
1090 | if (ret) { | |
9223a456 | 1091 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: write filaed %d\n", ret); |
60d84f97 | 1092 | break; |
cd5f6346 KP |
1093 | } |
1094 | ||
cd5f6346 | 1095 | /* Only check verify write turn on */ |
8b29c0b6 | 1096 | ret = onenand_verify(mtd, (u_char *) wbuf, to, thislen); |
cd5f6346 | 1097 | if (ret) { |
9223a456 | 1098 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: verify failed %d\n", ret); |
60d84f97 | 1099 | break; |
cd5f6346 KP |
1100 | } |
1101 | ||
60d84f97 KP |
1102 | written += thislen; |
1103 | ||
cd5f6346 KP |
1104 | if (written == len) |
1105 | break; | |
1106 | ||
60d84f97 | 1107 | column = 0; |
cd5f6346 KP |
1108 | to += thislen; |
1109 | buf += thislen; | |
1110 | } | |
1111 | ||
cd5f6346 KP |
1112 | /* Deselect and wake up anyone waiting on the device */ |
1113 | onenand_release_device(mtd); | |
1114 | ||
1115 | *retlen = written; | |
d5c5e78a | 1116 | |
cd5f6346 KP |
1117 | return ret; |
1118 | } | |
1119 | ||
a5e7c7b4 AH |
1120 | /** |
1121 | * onenand_fill_auto_oob - [Internal] oob auto-placement transfer | |
1122 | * @param mtd MTD device structure | |
1123 | * @param oob_buf oob buffer | |
1124 | * @param buf source address | |
1125 | * @param column oob offset to write to | |
1126 | * @param thislen oob length to write | |
1127 | */ | |
1128 | static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, | |
1129 | const u_char *buf, int column, int thislen) | |
1130 | { | |
1131 | struct onenand_chip *this = mtd->priv; | |
1132 | struct nand_oobfree *free; | |
1133 | int writecol = column; | |
1134 | int writeend = column + thislen; | |
1135 | int lastgap = 0; | |
1136 | ||
1137 | for (free = this->ecclayout->oobfree; free->length; ++free) { | |
1138 | if (writecol >= lastgap) | |
1139 | writecol += free->offset - lastgap; | |
1140 | if (writeend >= lastgap) | |
1141 | writeend += free->offset - lastgap; | |
1142 | lastgap = free->offset + free->length; | |
1143 | } | |
a5e7c7b4 AH |
1144 | for (free = this->ecclayout->oobfree; free->length; ++free) { |
1145 | int free_end = free->offset + free->length; | |
1146 | if (free->offset < writeend && free_end > writecol) { | |
1147 | int st = max_t(int,free->offset,writecol); | |
1148 | int ed = min_t(int,free_end,writeend); | |
1149 | int n = ed - st; | |
1150 | memcpy(oob_buf + st, buf, n); | |
1151 | buf += n; | |
1152 | } | |
1153 | } | |
1154 | return 0; | |
1155 | } | |
1156 | ||
cd5f6346 | 1157 | /** |
8593fbc6 | 1158 | * onenand_do_write_oob - [Internal] OneNAND write out-of-band |
cd5f6346 KP |
1159 | * @param mtd MTD device structure |
1160 | * @param to offset to write to | |
1161 | * @param len number of bytes to write | |
1162 | * @param retlen pointer to variable to store the number of written bytes | |
1163 | * @param buf the data to write | |
a5e7c7b4 | 1164 | * @param mode operation mode |
cd5f6346 KP |
1165 | * |
1166 | * OneNAND write out-of-band | |
1167 | */ | |
8593fbc6 | 1168 | static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
a5e7c7b4 | 1169 | size_t *retlen, const u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
1170 | { |
1171 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 1172 | int column, ret = 0, oobsize; |
cd5f6346 KP |
1173 | int written = 0; |
1174 | ||
1175 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); | |
1176 | ||
1177 | /* Initialize retlen, in case of early exit */ | |
1178 | *retlen = 0; | |
1179 | ||
a5e7c7b4 AH |
1180 | if (mode == MTD_OOB_AUTO) |
1181 | oobsize = this->ecclayout->oobavail; | |
1182 | else | |
1183 | oobsize = mtd->oobsize; | |
1184 | ||
1185 | column = to & (mtd->oobsize - 1); | |
1186 | ||
1187 | if (unlikely(column >= oobsize)) { | |
1188 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempted to start write outside oob\n"); | |
1189 | return -EINVAL; | |
1190 | } | |
1191 | ||
1192 | /* Do not allow reads past end of device */ | |
1193 | if (unlikely(to >= mtd->size || | |
1194 | column + len > ((mtd->size >> this->page_shift) - | |
1195 | (to >> this->page_shift)) * oobsize)) { | |
1196 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempted to write past end of device\n"); | |
cd5f6346 KP |
1197 | return -EINVAL; |
1198 | } | |
1199 | ||
1200 | /* Grab the lock and see if the device is available */ | |
1201 | onenand_get_device(mtd, FL_WRITING); | |
1202 | ||
1203 | /* Loop until all data write */ | |
1204 | while (written < len) { | |
a5e7c7b4 | 1205 | int thislen = min_t(int, oobsize, len - written); |
cd5f6346 | 1206 | |
61a7e198 AB |
1207 | cond_resched(); |
1208 | ||
cd5f6346 KP |
1209 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); |
1210 | ||
34c10609 KP |
1211 | /* We send data to spare ram with oobsize |
1212 | * to prevent byte access */ | |
1213 | memset(this->page_buf, 0xff, mtd->oobsize); | |
a5e7c7b4 AH |
1214 | if (mode == MTD_OOB_AUTO) |
1215 | onenand_fill_auto_oob(mtd, this->page_buf, buf, column, thislen); | |
1216 | else | |
1217 | memcpy(this->page_buf + column, buf, thislen); | |
34c10609 | 1218 | this->write_bufferram(mtd, ONENAND_SPARERAM, this->page_buf, 0, mtd->oobsize); |
cd5f6346 KP |
1219 | |
1220 | this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); | |
1221 | ||
1222 | onenand_update_bufferram(mtd, to, 0); | |
1223 | ||
8e6ec690 KP |
1224 | ret = this->wait(mtd, FL_WRITING); |
1225 | if (ret) { | |
a5e7c7b4 | 1226 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: write failed %d\n", ret); |
8e6ec690 KP |
1227 | goto out; |
1228 | } | |
1229 | ||
a5e7c7b4 | 1230 | ret = onenand_verify_oob(mtd, this->page_buf, to); |
8e6ec690 KP |
1231 | if (ret) { |
1232 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: verify failed %d\n", ret); | |
cd5f6346 | 1233 | goto out; |
8e6ec690 | 1234 | } |
cd5f6346 KP |
1235 | |
1236 | written += thislen; | |
1237 | ||
1238 | if (written == len) | |
1239 | break; | |
1240 | ||
a5e7c7b4 | 1241 | to += mtd->writesize; |
cd5f6346 | 1242 | buf += thislen; |
a5e7c7b4 | 1243 | column = 0; |
cd5f6346 KP |
1244 | } |
1245 | ||
1246 | out: | |
1247 | /* Deselect and wake up anyone waiting on the device */ | |
1248 | onenand_release_device(mtd); | |
1249 | ||
1250 | *retlen = written; | |
d5c5e78a | 1251 | |
8e6ec690 | 1252 | return ret; |
cd5f6346 KP |
1253 | } |
1254 | ||
8593fbc6 TG |
1255 | /** |
1256 | * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1257 | * @mtd: MTD device structure | |
1258 | * @from: offset to read from | |
1259 | * @ops: oob operation description structure | |
1260 | */ | |
1261 | static int onenand_write_oob(struct mtd_info *mtd, loff_t to, | |
1262 | struct mtd_oob_ops *ops) | |
1263 | { | |
4f4fad27 | 1264 | switch (ops->mode) { |
a5e7c7b4 AH |
1265 | case MTD_OOB_PLACE: |
1266 | case MTD_OOB_AUTO: | |
1267 | break; | |
1268 | case MTD_OOB_RAW: | |
4f4fad27 | 1269 | /* Not implemented yet */ |
a5e7c7b4 AH |
1270 | default: |
1271 | return -EINVAL; | |
1272 | } | |
66a1e421 | 1273 | return onenand_do_write_oob(mtd, to + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 1274 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
1275 | } |
1276 | ||
cdc00130 KP |
1277 | /** |
1278 | * onenand_block_checkbad - [GENERIC] Check if a block is marked bad | |
1279 | * @param mtd MTD device structure | |
1280 | * @param ofs offset from device start | |
1281 | * @param getchip 0, if the chip is already selected | |
1282 | * @param allowbbt 1, if its allowed to access the bbt area | |
1283 | * | |
1284 | * Check, if the block is bad. Either by reading the bad block table or | |
1285 | * calling of the scan function. | |
1286 | */ | |
1287 | static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) | |
1288 | { | |
1289 | struct onenand_chip *this = mtd->priv; | |
1290 | struct bbm_info *bbm = this->bbm; | |
1291 | ||
1292 | /* Return info from the table */ | |
1293 | return bbm->isbad_bbt(mtd, ofs, allowbbt); | |
1294 | } | |
1295 | ||
cd5f6346 KP |
1296 | /** |
1297 | * onenand_erase - [MTD Interface] erase block(s) | |
1298 | * @param mtd MTD device structure | |
1299 | * @param instr erase instruction | |
1300 | * | |
1301 | * Erase one ore more blocks | |
1302 | */ | |
1303 | static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) | |
1304 | { | |
1305 | struct onenand_chip *this = mtd->priv; | |
1306 | unsigned int block_size; | |
1307 | loff_t addr; | |
1308 | int len; | |
1309 | int ret = 0; | |
1310 | ||
1311 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); | |
1312 | ||
1313 | block_size = (1 << this->erase_shift); | |
1314 | ||
1315 | /* Start address must align on block boundary */ | |
1316 | if (unlikely(instr->addr & (block_size - 1))) { | |
1317 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); | |
1318 | return -EINVAL; | |
1319 | } | |
1320 | ||
1321 | /* Length must align on block boundary */ | |
1322 | if (unlikely(instr->len & (block_size - 1))) { | |
1323 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n"); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
1327 | /* Do not allow erase past end of device */ | |
1328 | if (unlikely((instr->len + instr->addr) > mtd->size)) { | |
1329 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n"); | |
1330 | return -EINVAL; | |
1331 | } | |
1332 | ||
1333 | instr->fail_addr = 0xffffffff; | |
1334 | ||
1335 | /* Grab the lock and see if the device is available */ | |
1336 | onenand_get_device(mtd, FL_ERASING); | |
1337 | ||
1338 | /* Loop throught the pages */ | |
1339 | len = instr->len; | |
1340 | addr = instr->addr; | |
1341 | ||
1342 | instr->state = MTD_ERASING; | |
1343 | ||
1344 | while (len) { | |
61a7e198 | 1345 | cond_resched(); |
cd5f6346 | 1346 | |
cdc00130 KP |
1347 | /* Check if we have a bad block, we do not erase bad blocks */ |
1348 | if (onenand_block_checkbad(mtd, addr, 0, 0)) { | |
1349 | printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); | |
1350 | instr->state = MTD_ERASE_FAILED; | |
1351 | goto erase_exit; | |
1352 | } | |
cd5f6346 KP |
1353 | |
1354 | this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); | |
1355 | ||
1356 | ret = this->wait(mtd, FL_ERASING); | |
1357 | /* Check, if it is write protected */ | |
1358 | if (ret) { | |
f6272487 | 1359 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); |
cd5f6346 KP |
1360 | instr->state = MTD_ERASE_FAILED; |
1361 | instr->fail_addr = addr; | |
1362 | goto erase_exit; | |
1363 | } | |
1364 | ||
1365 | len -= block_size; | |
1366 | addr += block_size; | |
1367 | } | |
1368 | ||
1369 | instr->state = MTD_ERASE_DONE; | |
1370 | ||
1371 | erase_exit: | |
1372 | ||
1373 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1374 | /* Do call back function */ | |
1375 | if (!ret) | |
1376 | mtd_erase_callback(instr); | |
1377 | ||
1378 | /* Deselect and wake up anyone waiting on the device */ | |
1379 | onenand_release_device(mtd); | |
1380 | ||
1381 | return ret; | |
1382 | } | |
1383 | ||
1384 | /** | |
1385 | * onenand_sync - [MTD Interface] sync | |
1386 | * @param mtd MTD device structure | |
1387 | * | |
1388 | * Sync is actually a wait for chip ready function | |
1389 | */ | |
1390 | static void onenand_sync(struct mtd_info *mtd) | |
1391 | { | |
1392 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); | |
1393 | ||
1394 | /* Grab the lock and see if the device is available */ | |
1395 | onenand_get_device(mtd, FL_SYNCING); | |
1396 | ||
1397 | /* Release it and go back */ | |
1398 | onenand_release_device(mtd); | |
1399 | } | |
1400 | ||
1401 | /** | |
1402 | * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad | |
1403 | * @param mtd MTD device structure | |
1404 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1405 | * |
1406 | * Check whether the block is bad | |
cd5f6346 KP |
1407 | */ |
1408 | static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) | |
1409 | { | |
cdc00130 KP |
1410 | /* Check for invalid offset */ |
1411 | if (ofs > mtd->size) | |
1412 | return -EINVAL; | |
1413 | ||
1414 | return onenand_block_checkbad(mtd, ofs, 1, 0); | |
1415 | } | |
1416 | ||
1417 | /** | |
1418 | * onenand_default_block_markbad - [DEFAULT] mark a block bad | |
1419 | * @param mtd MTD device structure | |
1420 | * @param ofs offset from device start | |
1421 | * | |
1422 | * This is the default implementation, which can be overridden by | |
1423 | * a hardware specific driver. | |
1424 | */ | |
1425 | static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1426 | { | |
1427 | struct onenand_chip *this = mtd->priv; | |
1428 | struct bbm_info *bbm = this->bbm; | |
1429 | u_char buf[2] = {0, 0}; | |
1430 | size_t retlen; | |
1431 | int block; | |
1432 | ||
1433 | /* Get block number */ | |
1434 | block = ((int) ofs) >> bbm->bbt_erase_shift; | |
1435 | if (bbm->bbt) | |
1436 | bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1437 | ||
1438 | /* We write two bytes, so we dont have to mess with 16 bit access */ | |
1439 | ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); | |
a5e7c7b4 | 1440 | return onenand_do_write_oob(mtd, ofs , 2, &retlen, buf, MTD_OOB_PLACE); |
cd5f6346 KP |
1441 | } |
1442 | ||
1443 | /** | |
1444 | * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad | |
1445 | * @param mtd MTD device structure | |
1446 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1447 | * |
1448 | * Mark the block as bad | |
cd5f6346 KP |
1449 | */ |
1450 | static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1451 | { | |
cdc00130 KP |
1452 | struct onenand_chip *this = mtd->priv; |
1453 | int ret; | |
1454 | ||
1455 | ret = onenand_block_isbad(mtd, ofs); | |
1456 | if (ret) { | |
1457 | /* If it was bad already, return success and do nothing */ | |
1458 | if (ret > 0) | |
1459 | return 0; | |
1460 | return ret; | |
1461 | } | |
1462 | ||
1463 | return this->block_markbad(mtd, ofs); | |
cd5f6346 KP |
1464 | } |
1465 | ||
1466 | /** | |
08f782b6 | 1467 | * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) |
cd5f6346 KP |
1468 | * @param mtd MTD device structure |
1469 | * @param ofs offset relative to mtd start | |
08f782b6 | 1470 | * @param len number of bytes to lock or unlock |
cd5f6346 | 1471 | * |
08f782b6 | 1472 | * Lock or unlock one or more blocks |
cd5f6346 | 1473 | */ |
08f782b6 | 1474 | static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) |
cd5f6346 KP |
1475 | { |
1476 | struct onenand_chip *this = mtd->priv; | |
1477 | int start, end, block, value, status; | |
08f782b6 | 1478 | int wp_status_mask; |
cd5f6346 KP |
1479 | |
1480 | start = ofs >> this->erase_shift; | |
1481 | end = len >> this->erase_shift; | |
1482 | ||
08f782b6 KP |
1483 | if (cmd == ONENAND_CMD_LOCK) |
1484 | wp_status_mask = ONENAND_WP_LS; | |
1485 | else | |
1486 | wp_status_mask = ONENAND_WP_US; | |
1487 | ||
cd5f6346 | 1488 | /* Continuous lock scheme */ |
28b79ff9 | 1489 | if (this->options & ONENAND_HAS_CONT_LOCK) { |
cd5f6346 KP |
1490 | /* Set start block address */ |
1491 | this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1492 | /* Set end block address */ | |
28b79ff9 | 1493 | this->write_word(start + end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); |
08f782b6 KP |
1494 | /* Write lock command */ |
1495 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1496 | |
1497 | /* There's no return value */ | |
08f782b6 | 1498 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1499 | |
1500 | /* Sanity check */ | |
1501 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1502 | & ONENAND_CTRL_ONGO) | |
1503 | continue; | |
1504 | ||
1505 | /* Check lock status */ | |
1506 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1507 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1508 | printk(KERN_ERR "wp status = 0x%x\n", status); |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | /* Block lock scheme */ | |
28b79ff9 | 1514 | for (block = start; block < start + end; block++) { |
20ba89a3 KP |
1515 | /* Set block address */ |
1516 | value = onenand_block_address(this, block); | |
1517 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1518 | /* Select DataRAM for DDP */ | |
1519 | value = onenand_bufferram_address(this, block); | |
1520 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
cd5f6346 KP |
1521 | /* Set start block address */ |
1522 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
08f782b6 KP |
1523 | /* Write lock command */ |
1524 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1525 | |
1526 | /* There's no return value */ | |
08f782b6 | 1527 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1528 | |
1529 | /* Sanity check */ | |
1530 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1531 | & ONENAND_CTRL_ONGO) | |
1532 | continue; | |
1533 | ||
cd5f6346 KP |
1534 | /* Check lock status */ |
1535 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1536 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1537 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); |
1538 | } | |
d5c5e78a | 1539 | |
cd5f6346 KP |
1540 | return 0; |
1541 | } | |
1542 | ||
08f782b6 KP |
1543 | /** |
1544 | * onenand_lock - [MTD Interface] Lock block(s) | |
1545 | * @param mtd MTD device structure | |
1546 | * @param ofs offset relative to mtd start | |
1547 | * @param len number of bytes to unlock | |
1548 | * | |
1549 | * Lock one or more blocks | |
1550 | */ | |
1551 | static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1552 | { | |
1553 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); | |
1554 | } | |
1555 | ||
08f782b6 KP |
1556 | /** |
1557 | * onenand_unlock - [MTD Interface] Unlock block(s) | |
1558 | * @param mtd MTD device structure | |
1559 | * @param ofs offset relative to mtd start | |
1560 | * @param len number of bytes to unlock | |
1561 | * | |
1562 | * Unlock one or more blocks | |
1563 | */ | |
1564 | static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1565 | { | |
1566 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); | |
1567 | } | |
1568 | ||
28b79ff9 KP |
1569 | /** |
1570 | * onenand_check_lock_status - [OneNAND Interface] Check lock status | |
1571 | * @param this onenand chip data structure | |
1572 | * | |
1573 | * Check lock status | |
1574 | */ | |
1575 | static void onenand_check_lock_status(struct onenand_chip *this) | |
1576 | { | |
1577 | unsigned int value, block, status; | |
1578 | unsigned int end; | |
1579 | ||
1580 | end = this->chipsize >> this->erase_shift; | |
1581 | for (block = 0; block < end; block++) { | |
1582 | /* Set block address */ | |
1583 | value = onenand_block_address(this, block); | |
1584 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1585 | /* Select DataRAM for DDP */ | |
1586 | value = onenand_bufferram_address(this, block); | |
1587 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
1588 | /* Set start block address */ | |
1589 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1590 | ||
1591 | /* Check lock status */ | |
1592 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1593 | if (!(status & ONENAND_WP_US)) | |
1594 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | /** | |
1599 | * onenand_unlock_all - [OneNAND Interface] unlock all blocks | |
1600 | * @param mtd MTD device structure | |
1601 | * | |
1602 | * Unlock all blocks | |
1603 | */ | |
1604 | static int onenand_unlock_all(struct mtd_info *mtd) | |
1605 | { | |
1606 | struct onenand_chip *this = mtd->priv; | |
1607 | ||
1608 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
10b7a2bd KP |
1609 | /* Set start block address */ |
1610 | this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
28b79ff9 KP |
1611 | /* Write unlock command */ |
1612 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
1613 | ||
1614 | /* There's no return value */ | |
08f782b6 | 1615 | this->wait(mtd, FL_LOCKING); |
28b79ff9 KP |
1616 | |
1617 | /* Sanity check */ | |
1618 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1619 | & ONENAND_CTRL_ONGO) | |
1620 | continue; | |
1621 | ||
1622 | /* Workaround for all block unlock in DDP */ | |
738d61f5 | 1623 | if (ONENAND_IS_DDP(this)) { |
28b79ff9 | 1624 | /* 1st block on another chip */ |
10b7a2bd KP |
1625 | loff_t ofs = this->chipsize >> 1; |
1626 | size_t len = mtd->erasesize; | |
28b79ff9 KP |
1627 | |
1628 | onenand_unlock(mtd, ofs, len); | |
1629 | } | |
1630 | ||
1631 | onenand_check_lock_status(this); | |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
08f782b6 | 1636 | onenand_unlock(mtd, 0x0, this->chipsize); |
28b79ff9 KP |
1637 | |
1638 | return 0; | |
1639 | } | |
1640 | ||
493c6460 KP |
1641 | #ifdef CONFIG_MTD_ONENAND_OTP |
1642 | ||
1643 | /* Interal OTP operation */ | |
1644 | typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, | |
1645 | size_t *retlen, u_char *buf); | |
1646 | ||
1647 | /** | |
1648 | * do_otp_read - [DEFAULT] Read OTP block area | |
1649 | * @param mtd MTD device structure | |
1650 | * @param from The offset to read | |
1651 | * @param len number of bytes to read | |
1652 | * @param retlen pointer to variable to store the number of readbytes | |
1653 | * @param buf the databuffer to put/get data | |
1654 | * | |
1655 | * Read OTP block area. | |
1656 | */ | |
1657 | static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1658 | size_t *retlen, u_char *buf) | |
1659 | { | |
1660 | struct onenand_chip *this = mtd->priv; | |
1661 | int ret; | |
1662 | ||
1663 | /* Enter OTP access mode */ | |
1664 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1665 | this->wait(mtd, FL_OTPING); | |
1666 | ||
1667 | ret = mtd->read(mtd, from, len, retlen, buf); | |
1668 | ||
1669 | /* Exit OTP access mode */ | |
1670 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1671 | this->wait(mtd, FL_RESETING); | |
1672 | ||
1673 | return ret; | |
1674 | } | |
1675 | ||
1676 | /** | |
1677 | * do_otp_write - [DEFAULT] Write OTP block area | |
1678 | * @param mtd MTD device structure | |
1679 | * @param from The offset to write | |
1680 | * @param len number of bytes to write | |
1681 | * @param retlen pointer to variable to store the number of write bytes | |
1682 | * @param buf the databuffer to put/get data | |
1683 | * | |
1684 | * Write OTP block area. | |
1685 | */ | |
1686 | static int do_otp_write(struct mtd_info *mtd, loff_t from, size_t len, | |
1687 | size_t *retlen, u_char *buf) | |
1688 | { | |
1689 | struct onenand_chip *this = mtd->priv; | |
1690 | unsigned char *pbuf = buf; | |
1691 | int ret; | |
1692 | ||
1693 | /* Force buffer page aligned */ | |
28318776 | 1694 | if (len < mtd->writesize) { |
493c6460 | 1695 | memcpy(this->page_buf, buf, len); |
28318776 | 1696 | memset(this->page_buf + len, 0xff, mtd->writesize - len); |
493c6460 | 1697 | pbuf = this->page_buf; |
28318776 | 1698 | len = mtd->writesize; |
493c6460 KP |
1699 | } |
1700 | ||
1701 | /* Enter OTP access mode */ | |
1702 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1703 | this->wait(mtd, FL_OTPING); | |
1704 | ||
1705 | ret = mtd->write(mtd, from, len, retlen, pbuf); | |
1706 | ||
1707 | /* Exit OTP access mode */ | |
1708 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1709 | this->wait(mtd, FL_RESETING); | |
1710 | ||
1711 | return ret; | |
1712 | } | |
1713 | ||
1714 | /** | |
1715 | * do_otp_lock - [DEFAULT] Lock OTP block area | |
1716 | * @param mtd MTD device structure | |
1717 | * @param from The offset to lock | |
1718 | * @param len number of bytes to lock | |
1719 | * @param retlen pointer to variable to store the number of lock bytes | |
1720 | * @param buf the databuffer to put/get data | |
1721 | * | |
1722 | * Lock OTP block area. | |
1723 | */ | |
1724 | static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, | |
1725 | size_t *retlen, u_char *buf) | |
1726 | { | |
1727 | struct onenand_chip *this = mtd->priv; | |
1728 | int ret; | |
1729 | ||
1730 | /* Enter OTP access mode */ | |
1731 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1732 | this->wait(mtd, FL_OTPING); | |
1733 | ||
a5e7c7b4 | 1734 | ret = onenand_do_write_oob(mtd, from, len, retlen, buf, MTD_OOB_PLACE); |
493c6460 KP |
1735 | |
1736 | /* Exit OTP access mode */ | |
1737 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1738 | this->wait(mtd, FL_RESETING); | |
1739 | ||
1740 | return ret; | |
1741 | } | |
1742 | ||
1743 | /** | |
1744 | * onenand_otp_walk - [DEFAULT] Handle OTP operation | |
1745 | * @param mtd MTD device structure | |
1746 | * @param from The offset to read/write | |
1747 | * @param len number of bytes to read/write | |
1748 | * @param retlen pointer to variable to store the number of read bytes | |
1749 | * @param buf the databuffer to put/get data | |
1750 | * @param action do given action | |
1751 | * @param mode specify user and factory | |
1752 | * | |
1753 | * Handle OTP operation. | |
1754 | */ | |
1755 | static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, | |
1756 | size_t *retlen, u_char *buf, | |
1757 | otp_op_t action, int mode) | |
1758 | { | |
1759 | struct onenand_chip *this = mtd->priv; | |
1760 | int otp_pages; | |
1761 | int density; | |
1762 | int ret = 0; | |
1763 | ||
1764 | *retlen = 0; | |
1765 | ||
1766 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1767 | if (density < ONENAND_DEVICE_DENSITY_512Mb) | |
1768 | otp_pages = 20; | |
1769 | else | |
1770 | otp_pages = 10; | |
1771 | ||
1772 | if (mode == MTD_OTP_FACTORY) { | |
28318776 | 1773 | from += mtd->writesize * otp_pages; |
493c6460 KP |
1774 | otp_pages = 64 - otp_pages; |
1775 | } | |
1776 | ||
1777 | /* Check User/Factory boundary */ | |
28318776 | 1778 | if (((mtd->writesize * otp_pages) - (from + len)) < 0) |
493c6460 KP |
1779 | return 0; |
1780 | ||
1781 | while (len > 0 && otp_pages > 0) { | |
1782 | if (!action) { /* OTP Info functions */ | |
1783 | struct otp_info *otpinfo; | |
1784 | ||
1785 | len -= sizeof(struct otp_info); | |
1786 | if (len <= 0) | |
1787 | return -ENOSPC; | |
1788 | ||
1789 | otpinfo = (struct otp_info *) buf; | |
1790 | otpinfo->start = from; | |
28318776 | 1791 | otpinfo->length = mtd->writesize; |
493c6460 KP |
1792 | otpinfo->locked = 0; |
1793 | ||
28318776 | 1794 | from += mtd->writesize; |
493c6460 KP |
1795 | buf += sizeof(struct otp_info); |
1796 | *retlen += sizeof(struct otp_info); | |
1797 | } else { | |
1798 | size_t tmp_retlen; | |
1799 | int size = len; | |
1800 | ||
1801 | ret = action(mtd, from, len, &tmp_retlen, buf); | |
1802 | ||
1803 | buf += size; | |
1804 | len -= size; | |
1805 | *retlen += size; | |
1806 | ||
1807 | if (ret < 0) | |
1808 | return ret; | |
1809 | } | |
1810 | otp_pages--; | |
1811 | } | |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | ||
1816 | /** | |
1817 | * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info | |
1818 | * @param mtd MTD device structure | |
1819 | * @param buf the databuffer to put/get data | |
1820 | * @param len number of bytes to read | |
1821 | * | |
1822 | * Read factory OTP info. | |
1823 | */ | |
1824 | static int onenand_get_fact_prot_info(struct mtd_info *mtd, | |
1825 | struct otp_info *buf, size_t len) | |
1826 | { | |
1827 | size_t retlen; | |
1828 | int ret; | |
1829 | ||
1830 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY); | |
1831 | ||
1832 | return ret ? : retlen; | |
1833 | } | |
1834 | ||
1835 | /** | |
1836 | * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area | |
1837 | * @param mtd MTD device structure | |
1838 | * @param from The offset to read | |
1839 | * @param len number of bytes to read | |
1840 | * @param retlen pointer to variable to store the number of read bytes | |
1841 | * @param buf the databuffer to put/get data | |
1842 | * | |
1843 | * Read factory OTP area. | |
1844 | */ | |
1845 | static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | |
1846 | size_t len, size_t *retlen, u_char *buf) | |
1847 | { | |
1848 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY); | |
1849 | } | |
1850 | ||
1851 | /** | |
1852 | * onenand_get_user_prot_info - [MTD Interface] Read user OTP info | |
1853 | * @param mtd MTD device structure | |
1854 | * @param buf the databuffer to put/get data | |
1855 | * @param len number of bytes to read | |
1856 | * | |
1857 | * Read user OTP info. | |
1858 | */ | |
1859 | static int onenand_get_user_prot_info(struct mtd_info *mtd, | |
1860 | struct otp_info *buf, size_t len) | |
1861 | { | |
1862 | size_t retlen; | |
1863 | int ret; | |
1864 | ||
1865 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER); | |
1866 | ||
1867 | return ret ? : retlen; | |
1868 | } | |
1869 | ||
1870 | /** | |
1871 | * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area | |
1872 | * @param mtd MTD device structure | |
1873 | * @param from The offset to read | |
1874 | * @param len number of bytes to read | |
1875 | * @param retlen pointer to variable to store the number of read bytes | |
1876 | * @param buf the databuffer to put/get data | |
1877 | * | |
1878 | * Read user OTP area. | |
1879 | */ | |
1880 | static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1881 | size_t len, size_t *retlen, u_char *buf) | |
1882 | { | |
1883 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER); | |
1884 | } | |
1885 | ||
1886 | /** | |
1887 | * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area | |
1888 | * @param mtd MTD device structure | |
1889 | * @param from The offset to write | |
1890 | * @param len number of bytes to write | |
1891 | * @param retlen pointer to variable to store the number of write bytes | |
1892 | * @param buf the databuffer to put/get data | |
1893 | * | |
1894 | * Write user OTP area. | |
1895 | */ | |
1896 | static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1897 | size_t len, size_t *retlen, u_char *buf) | |
1898 | { | |
1899 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER); | |
1900 | } | |
1901 | ||
1902 | /** | |
1903 | * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area | |
1904 | * @param mtd MTD device structure | |
1905 | * @param from The offset to lock | |
1906 | * @param len number of bytes to unlock | |
1907 | * | |
1908 | * Write lock mark on spare area in page 0 in OTP block | |
1909 | */ | |
1910 | static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1911 | size_t len) | |
1912 | { | |
1913 | unsigned char oob_buf[64]; | |
1914 | size_t retlen; | |
1915 | int ret; | |
1916 | ||
1917 | memset(oob_buf, 0xff, mtd->oobsize); | |
1918 | /* | |
1919 | * Note: OTP lock operation | |
1920 | * OTP block : 0xXXFC | |
1921 | * 1st block : 0xXXF3 (If chip support) | |
1922 | * Both : 0xXXF0 (If chip support) | |
1923 | */ | |
1924 | oob_buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC; | |
1925 | ||
1926 | /* | |
1927 | * Write lock mark to 8th word of sector0 of page0 of the spare0. | |
1928 | * We write 16 bytes spare area instead of 2 bytes. | |
1929 | */ | |
1930 | from = 0; | |
1931 | len = 16; | |
1932 | ||
1933 | ret = onenand_otp_walk(mtd, from, len, &retlen, oob_buf, do_otp_lock, MTD_OTP_USER); | |
1934 | ||
1935 | return ret ? : retlen; | |
1936 | } | |
1937 | #endif /* CONFIG_MTD_ONENAND_OTP */ | |
1938 | ||
28b79ff9 | 1939 | /** |
75384b0d | 1940 | * onenand_check_features - Check and set OneNAND features |
28b79ff9 KP |
1941 | * @param mtd MTD data structure |
1942 | * | |
75384b0d KP |
1943 | * Check and set OneNAND features |
1944 | * - lock scheme | |
28b79ff9 | 1945 | */ |
75384b0d | 1946 | static void onenand_check_features(struct mtd_info *mtd) |
28b79ff9 KP |
1947 | { |
1948 | struct onenand_chip *this = mtd->priv; | |
1949 | unsigned int density, process; | |
1950 | ||
1951 | /* Lock scheme depends on density and process */ | |
1952 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1953 | process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; | |
1954 | ||
1955 | /* Lock scheme */ | |
1956 | if (density >= ONENAND_DEVICE_DENSITY_1Gb) { | |
1957 | /* A-Die has all block unlock */ | |
1958 | if (process) { | |
1959 | printk(KERN_DEBUG "Chip support all block unlock\n"); | |
1960 | this->options |= ONENAND_HAS_UNLOCK_ALL; | |
1961 | } | |
1962 | } else { | |
1963 | /* Some OneNAND has continues lock scheme */ | |
1964 | if (!process) { | |
1965 | printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); | |
1966 | this->options |= ONENAND_HAS_CONT_LOCK; | |
1967 | } | |
1968 | } | |
1969 | } | |
1970 | ||
cd5f6346 KP |
1971 | /** |
1972 | * onenand_print_device_info - Print device ID | |
1973 | * @param device device ID | |
1974 | * | |
1975 | * Print device ID | |
1976 | */ | |
28b79ff9 | 1977 | static void onenand_print_device_info(int device, int version) |
cd5f6346 KP |
1978 | { |
1979 | int vcc, demuxed, ddp, density; | |
1980 | ||
1981 | vcc = device & ONENAND_DEVICE_VCC_MASK; | |
1982 | demuxed = device & ONENAND_DEVICE_IS_DEMUX; | |
1983 | ddp = device & ONENAND_DEVICE_IS_DDP; | |
1984 | density = device >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1985 | printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", | |
1986 | demuxed ? "" : "Muxed ", | |
1987 | ddp ? "(DDP)" : "", | |
1988 | (16 << density), | |
1989 | vcc ? "2.65/3.3" : "1.8", | |
1990 | device); | |
28b79ff9 | 1991 | printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); |
cd5f6346 KP |
1992 | } |
1993 | ||
1994 | static const struct onenand_manufacturers onenand_manuf_ids[] = { | |
1995 | {ONENAND_MFR_SAMSUNG, "Samsung"}, | |
cd5f6346 KP |
1996 | }; |
1997 | ||
1998 | /** | |
1999 | * onenand_check_maf - Check manufacturer ID | |
2000 | * @param manuf manufacturer ID | |
2001 | * | |
2002 | * Check manufacturer ID | |
2003 | */ | |
2004 | static int onenand_check_maf(int manuf) | |
2005 | { | |
37b1cc39 KP |
2006 | int size = ARRAY_SIZE(onenand_manuf_ids); |
2007 | char *name; | |
cd5f6346 KP |
2008 | int i; |
2009 | ||
37b1cc39 | 2010 | for (i = 0; i < size; i++) |
cd5f6346 KP |
2011 | if (manuf == onenand_manuf_ids[i].id) |
2012 | break; | |
cd5f6346 | 2013 | |
37b1cc39 KP |
2014 | if (i < size) |
2015 | name = onenand_manuf_ids[i].name; | |
2016 | else | |
2017 | name = "Unknown"; | |
2018 | ||
2019 | printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); | |
cd5f6346 | 2020 | |
37b1cc39 | 2021 | return (i == size); |
cd5f6346 KP |
2022 | } |
2023 | ||
2024 | /** | |
2025 | * onenand_probe - [OneNAND Interface] Probe the OneNAND device | |
2026 | * @param mtd MTD device structure | |
2027 | * | |
2028 | * OneNAND detection method: | |
2029 | * Compare the the values from command with ones from register | |
2030 | */ | |
2031 | static int onenand_probe(struct mtd_info *mtd) | |
2032 | { | |
2033 | struct onenand_chip *this = mtd->priv; | |
28b79ff9 | 2034 | int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; |
cd5f6346 | 2035 | int density; |
47e777e0 KP |
2036 | int syscfg; |
2037 | ||
2038 | /* Save system configuration 1 */ | |
2039 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
2040 | /* Clear Sync. Burst Read mode to read BootRAM */ | |
2041 | this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); | |
cd5f6346 KP |
2042 | |
2043 | /* Send the command for reading device ID from BootRAM */ | |
2044 | this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); | |
2045 | ||
2046 | /* Read manufacturer and device IDs from BootRAM */ | |
2047 | bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); | |
2048 | bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); | |
2049 | ||
47e777e0 KP |
2050 | /* Reset OneNAND to read default register values */ |
2051 | this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); | |
2052 | /* Wait reset */ | |
2053 | this->wait(mtd, FL_RESETING); | |
2054 | ||
2055 | /* Restore system configuration 1 */ | |
2056 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
2057 | ||
cd5f6346 KP |
2058 | /* Check manufacturer ID */ |
2059 | if (onenand_check_maf(bram_maf_id)) | |
2060 | return -ENXIO; | |
2061 | ||
cd5f6346 KP |
2062 | /* Read manufacturer and device IDs from Register */ |
2063 | maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); | |
2064 | dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); | |
f4f91ac3 | 2065 | ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); |
cd5f6346 KP |
2066 | |
2067 | /* Check OneNAND device */ | |
2068 | if (maf_id != bram_maf_id || dev_id != bram_dev_id) | |
2069 | return -ENXIO; | |
2070 | ||
2071 | /* Flash device information */ | |
28b79ff9 | 2072 | onenand_print_device_info(dev_id, ver_id); |
cd5f6346 | 2073 | this->device_id = dev_id; |
28b79ff9 | 2074 | this->version_id = ver_id; |
cd5f6346 KP |
2075 | |
2076 | density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2077 | this->chipsize = (16 << density) << 20; | |
83a36838 | 2078 | /* Set density mask. it is used for DDP */ |
738d61f5 KP |
2079 | if (ONENAND_IS_DDP(this)) |
2080 | this->density_mask = (1 << (density + 6)); | |
2081 | else | |
2082 | this->density_mask = 0; | |
cd5f6346 KP |
2083 | |
2084 | /* OneNAND page size & block size */ | |
2085 | /* The data buffer size is equal to page size */ | |
28318776 JE |
2086 | mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); |
2087 | mtd->oobsize = mtd->writesize >> 5; | |
9bfbc9b2 | 2088 | /* Pages per a block are always 64 in OneNAND */ |
28318776 | 2089 | mtd->erasesize = mtd->writesize << 6; |
cd5f6346 KP |
2090 | |
2091 | this->erase_shift = ffs(mtd->erasesize) - 1; | |
28318776 | 2092 | this->page_shift = ffs(mtd->writesize) - 1; |
9bfbc9b2 | 2093 | this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1; |
cd5f6346 KP |
2094 | |
2095 | /* REVIST: Multichip handling */ | |
2096 | ||
2097 | mtd->size = this->chipsize; | |
2098 | ||
75384b0d KP |
2099 | /* Check OneNAND features */ |
2100 | onenand_check_features(mtd); | |
d5c5e78a | 2101 | |
cd5f6346 KP |
2102 | return 0; |
2103 | } | |
2104 | ||
a41371eb KP |
2105 | /** |
2106 | * onenand_suspend - [MTD Interface] Suspend the OneNAND flash | |
2107 | * @param mtd MTD device structure | |
2108 | */ | |
2109 | static int onenand_suspend(struct mtd_info *mtd) | |
2110 | { | |
2111 | return onenand_get_device(mtd, FL_PM_SUSPENDED); | |
2112 | } | |
2113 | ||
2114 | /** | |
2115 | * onenand_resume - [MTD Interface] Resume the OneNAND flash | |
2116 | * @param mtd MTD device structure | |
2117 | */ | |
2118 | static void onenand_resume(struct mtd_info *mtd) | |
2119 | { | |
2120 | struct onenand_chip *this = mtd->priv; | |
2121 | ||
2122 | if (this->state == FL_PM_SUSPENDED) | |
2123 | onenand_release_device(mtd); | |
2124 | else | |
2125 | printk(KERN_ERR "resume() called for the chip which is not" | |
2126 | "in suspended state\n"); | |
2127 | } | |
2128 | ||
cd5f6346 KP |
2129 | /** |
2130 | * onenand_scan - [OneNAND Interface] Scan for the OneNAND device | |
2131 | * @param mtd MTD device structure | |
2132 | * @param maxchips Number of chips to scan for | |
2133 | * | |
2134 | * This fills out all the not initialized function pointers | |
2135 | * with the defaults. | |
2136 | * The flash ID is read and the mtd/chip structures are | |
2137 | * filled with the appropriate values. | |
2138 | */ | |
2139 | int onenand_scan(struct mtd_info *mtd, int maxchips) | |
2140 | { | |
a5e7c7b4 | 2141 | int i; |
cd5f6346 KP |
2142 | struct onenand_chip *this = mtd->priv; |
2143 | ||
2144 | if (!this->read_word) | |
2145 | this->read_word = onenand_readw; | |
2146 | if (!this->write_word) | |
2147 | this->write_word = onenand_writew; | |
2148 | ||
2149 | if (!this->command) | |
2150 | this->command = onenand_command; | |
2151 | if (!this->wait) | |
2c22120f | 2152 | onenand_setup_wait(mtd); |
cd5f6346 KP |
2153 | |
2154 | if (!this->read_bufferram) | |
2155 | this->read_bufferram = onenand_read_bufferram; | |
2156 | if (!this->write_bufferram) | |
2157 | this->write_bufferram = onenand_write_bufferram; | |
2158 | ||
cdc00130 KP |
2159 | if (!this->block_markbad) |
2160 | this->block_markbad = onenand_default_block_markbad; | |
2161 | if (!this->scan_bbt) | |
2162 | this->scan_bbt = onenand_default_bbt; | |
2163 | ||
cd5f6346 KP |
2164 | if (onenand_probe(mtd)) |
2165 | return -ENXIO; | |
2166 | ||
52b0eea7 KP |
2167 | /* Set Sync. Burst Read after probing */ |
2168 | if (this->mmcontrol) { | |
2169 | printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); | |
2170 | this->read_bufferram = onenand_sync_read_bufferram; | |
2171 | } | |
2172 | ||
532a37cf KP |
2173 | /* Allocate buffers, if necessary */ |
2174 | if (!this->page_buf) { | |
2175 | size_t len; | |
28318776 | 2176 | len = mtd->writesize + mtd->oobsize; |
532a37cf KP |
2177 | this->page_buf = kmalloc(len, GFP_KERNEL); |
2178 | if (!this->page_buf) { | |
2179 | printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); | |
2180 | return -ENOMEM; | |
2181 | } | |
2182 | this->options |= ONENAND_PAGEBUF_ALLOC; | |
2183 | } | |
2184 | ||
cd5f6346 KP |
2185 | this->state = FL_READY; |
2186 | init_waitqueue_head(&this->wq); | |
2187 | spin_lock_init(&this->chip_lock); | |
2188 | ||
60d84f97 KP |
2189 | /* |
2190 | * Allow subpage writes up to oobsize. | |
2191 | */ | |
cd5f6346 KP |
2192 | switch (mtd->oobsize) { |
2193 | case 64: | |
5bd34c09 | 2194 | this->ecclayout = &onenand_oob_64; |
60d84f97 | 2195 | mtd->subpage_sft = 2; |
cd5f6346 KP |
2196 | break; |
2197 | ||
2198 | case 32: | |
5bd34c09 | 2199 | this->ecclayout = &onenand_oob_32; |
60d84f97 | 2200 | mtd->subpage_sft = 1; |
cd5f6346 KP |
2201 | break; |
2202 | ||
2203 | default: | |
2204 | printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", | |
2205 | mtd->oobsize); | |
60d84f97 | 2206 | mtd->subpage_sft = 0; |
cd5f6346 | 2207 | /* To prevent kernel oops */ |
5bd34c09 | 2208 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
2209 | break; |
2210 | } | |
2211 | ||
60d84f97 | 2212 | this->subpagesize = mtd->writesize >> mtd->subpage_sft; |
a5e7c7b4 AH |
2213 | |
2214 | /* | |
2215 | * The number of bytes available for a client to place data into | |
2216 | * the out of band area | |
2217 | */ | |
2218 | this->ecclayout->oobavail = 0; | |
2219 | for (i = 0; this->ecclayout->oobfree[i].length; i++) | |
2220 | this->ecclayout->oobavail += | |
2221 | this->ecclayout->oobfree[i].length; | |
2222 | ||
5bd34c09 | 2223 | mtd->ecclayout = this->ecclayout; |
d5c5e78a | 2224 | |
cd5f6346 KP |
2225 | /* Fill in remaining MTD driver data */ |
2226 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2227 | mtd->flags = MTD_CAP_NANDFLASH; |
cd5f6346 KP |
2228 | mtd->ecctype = MTD_ECC_SW; |
2229 | mtd->erase = onenand_erase; | |
2230 | mtd->point = NULL; | |
2231 | mtd->unpoint = NULL; | |
2232 | mtd->read = onenand_read; | |
2233 | mtd->write = onenand_write; | |
cd5f6346 KP |
2234 | mtd->read_oob = onenand_read_oob; |
2235 | mtd->write_oob = onenand_write_oob; | |
493c6460 KP |
2236 | #ifdef CONFIG_MTD_ONENAND_OTP |
2237 | mtd->get_fact_prot_info = onenand_get_fact_prot_info; | |
2238 | mtd->read_fact_prot_reg = onenand_read_fact_prot_reg; | |
2239 | mtd->get_user_prot_info = onenand_get_user_prot_info; | |
2240 | mtd->read_user_prot_reg = onenand_read_user_prot_reg; | |
2241 | mtd->write_user_prot_reg = onenand_write_user_prot_reg; | |
2242 | mtd->lock_user_prot_reg = onenand_lock_user_prot_reg; | |
2243 | #endif | |
cd5f6346 | 2244 | mtd->sync = onenand_sync; |
08f782b6 | 2245 | mtd->lock = onenand_lock; |
cd5f6346 | 2246 | mtd->unlock = onenand_unlock; |
a41371eb KP |
2247 | mtd->suspend = onenand_suspend; |
2248 | mtd->resume = onenand_resume; | |
cd5f6346 KP |
2249 | mtd->block_isbad = onenand_block_isbad; |
2250 | mtd->block_markbad = onenand_block_markbad; | |
2251 | mtd->owner = THIS_MODULE; | |
2252 | ||
2253 | /* Unlock whole block */ | |
28b79ff9 | 2254 | onenand_unlock_all(mtd); |
cd5f6346 | 2255 | |
cdc00130 | 2256 | return this->scan_bbt(mtd); |
cd5f6346 KP |
2257 | } |
2258 | ||
2259 | /** | |
2260 | * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device | |
2261 | * @param mtd MTD device structure | |
2262 | */ | |
2263 | void onenand_release(struct mtd_info *mtd) | |
2264 | { | |
532a37cf KP |
2265 | struct onenand_chip *this = mtd->priv; |
2266 | ||
cd5f6346 KP |
2267 | #ifdef CONFIG_MTD_PARTITIONS |
2268 | /* Deregister partitions */ | |
2269 | del_mtd_partitions (mtd); | |
2270 | #endif | |
2271 | /* Deregister the device */ | |
2272 | del_mtd_device (mtd); | |
532a37cf KP |
2273 | |
2274 | /* Free bad block table memory, if allocated */ | |
f00b0046 AH |
2275 | if (this->bbm) { |
2276 | struct bbm_info *bbm = this->bbm; | |
2277 | kfree(bbm->bbt); | |
532a37cf | 2278 | kfree(this->bbm); |
f00b0046 | 2279 | } |
532a37cf KP |
2280 | /* Buffer allocated by onenand_scan */ |
2281 | if (this->options & ONENAND_PAGEBUF_ALLOC) | |
2282 | kfree(this->page_buf); | |
cd5f6346 KP |
2283 | } |
2284 | ||
2285 | EXPORT_SYMBOL_GPL(onenand_scan); | |
2286 | EXPORT_SYMBOL_GPL(onenand_release); | |
2287 | ||
2288 | MODULE_LICENSE("GPL"); | |
2289 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
2290 | MODULE_DESCRIPTION("Generic OneNAND flash driver code"); |