[linux-block.git] / drivers / mtd / onenand / omap2.c

/*
 *  linux/drivers/mtd/onenand/omap2.c
 *
 *  OneNAND driver for OMAP2 / OMAP3
 *
 *  Copyright © 2005-2006 Nokia Corporation
 *
 *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
 *  IRQ and DMA support written by Timo Teras
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; see the file COPYING. If not, write to the Free Software
 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 */

#include <linux/device.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/gpio.h>

#include <asm/mach/flash.h>
#include <linux/platform_data/mtd-onenand-omap2.h>

#define DRIVER_NAME "omap2-onenand"

#define ONENAND_BUFRAM_SIZE	(1024 * 5)

struct omap2_onenand {
	struct platform_device *pdev;
	int gpmc_cs;
	unsigned long phys_base;
	unsigned int mem_size;
	int gpio_irq;
	struct mtd_info mtd;
	struct onenand_chip onenand;
	struct completion irq_done;
	struct completion dma_done;
	struct dma_chan *dma_chan;
	int freq;
	int (*setup)(void __iomem *base, int *freq_ptr);
};

static void omap2_onenand_dma_complete_func(void *completion)
{
	complete(completion);
}

static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
{
	struct omap2_onenand *c = dev_id;

	complete(&c->irq_done);

	return IRQ_HANDLED;
}

static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
{
	return readw(c->onenand.base + reg);
}

static inline void write_reg(struct omap2_onenand *c, unsigned short value,
			     int reg)
{
	writew(value, c->onenand.base + reg);
}

static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
{
	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
	       msg, state, ctrl, intr);
}

static void wait_warn(char *msg, int state, unsigned int ctrl,
		      unsigned int intr)
{
	printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
	       "intr 0x%04x\n", msg, state, ctrl, intr);
}

static int omap2_onenand_wait(struct mtd_info *mtd, int state)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	unsigned int intr = 0;
	unsigned int ctrl, ctrl_mask;
	unsigned long timeout;
	u32 syscfg;

	if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
	    state == FL_VERIFYING_ERASE) {
		int i = 21;
		unsigned int intr_flags = ONENAND_INT_MASTER;

		switch (state) {
		case FL_RESETING:
			intr_flags |= ONENAND_INT_RESET;
			break;
		case FL_PREPARING_ERASE:
			intr_flags |= ONENAND_INT_ERASE;
			break;
		case FL_VERIFYING_ERASE:
			i = 101;
			break;
		}

		while (--i) {
			udelay(1);
			intr = read_reg(c, ONENAND_REG_INTERRUPT);
			if (intr & ONENAND_INT_MASTER)
				break;
		}
		ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
		if (ctrl & ONENAND_CTRL_ERROR) {
			wait_err("controller error", state, ctrl, intr);
			return -EIO;
		}
		if ((intr & intr_flags) == intr_flags)
			return 0;
		/* Continue in wait for interrupt branch */
	}

	if (state != FL_READING) {
		int result;

		/* Turn interrupts on */
		syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
			syscfg |= ONENAND_SYS_CFG1_IOBE;
			write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
			/* Add a delay to let GPIO settle */
			syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		}

		reinit_completion(&c->irq_done);
		if (c->gpio_irq) {
			result = gpio_get_value(c->gpio_irq);
			if (result == -1) {
				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
				intr = read_reg(c, ONENAND_REG_INTERRUPT);
				wait_err("gpio error", state, ctrl, intr);
				return -EIO;
			}
		} else
			result = 0;
		if (result == 0) {
			int retry_cnt = 0;
retry:
			if (!wait_for_completion_io_timeout(&c->irq_done,
						msecs_to_jiffies(20))) {
				/* Timeout after 20ms */
				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
				if (ctrl & ONENAND_CTRL_ONGO &&
				    !this->ongoing) {
					/*
					 * The operation seems to be still going
					 * so give it some more time.
					 */
					retry_cnt += 1;
					if (retry_cnt < 3)
						goto retry;
					intr = read_reg(c,
							ONENAND_REG_INTERRUPT);
					wait_err("timeout", state, ctrl, intr);
					return -EIO;
				}
				intr = read_reg(c, ONENAND_REG_INTERRUPT);
				if ((intr & ONENAND_INT_MASTER) == 0)
					wait_warn("timeout", state, ctrl, intr);
			}
		}
	} else {
		int retry_cnt = 0;

		/* Turn interrupts off */
		syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
		syscfg &= ~ONENAND_SYS_CFG1_IOBE;
		write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);

		timeout = jiffies + msecs_to_jiffies(20);
		while (1) {
			if (time_before(jiffies, timeout)) {
				intr = read_reg(c, ONENAND_REG_INTERRUPT);
				if (intr & ONENAND_INT_MASTER)
					break;
			} else {
				/* Timeout after 20ms */
				ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
				if (ctrl & ONENAND_CTRL_ONGO) {
					/*
					 * The operation seems to be still going
					 * so give it some more time.
					 */
					retry_cnt += 1;
					if (retry_cnt < 3) {
						timeout = jiffies +
							  msecs_to_jiffies(20);
						continue;
					}
				}
				break;
			}
		}
	}

	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);

	if (intr & ONENAND_INT_READ) {
		int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);

		if (ecc) {
			unsigned int addr1, addr8;

			addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
			addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
			if (ecc & ONENAND_ECC_2BIT_ALL) {
				printk(KERN_ERR "onenand_wait: ECC error = "
				       "0x%04x, addr1 %#x, addr8 %#x\n",
				       ecc, addr1, addr8);
				mtd->ecc_stats.failed++;
				return -EBADMSG;
			} else if (ecc & ONENAND_ECC_1BIT_ALL) {
				printk(KERN_NOTICE "onenand_wait: correctable "
				       "ECC error = 0x%04x, addr1 %#x, "
				       "addr8 %#x\n", ecc, addr1, addr8);
				mtd->ecc_stats.corrected++;
			}
		}
	} else if (state == FL_READING) {
		wait_err("timeout", state, ctrl, intr);
		return -EIO;
	}

	if (ctrl & ONENAND_CTRL_ERROR) {
		wait_err("controller error", state, ctrl, intr);
		if (ctrl & ONENAND_CTRL_LOCK)
			printk(KERN_ERR "onenand_wait: "
					"Device is write protected!!!\n");
		return -EIO;
	}

	ctrl_mask = 0xFE9F;
	if (this->ongoing)
		ctrl_mask &= ~0x8000;

	if (ctrl & ctrl_mask)
		wait_warn("unexpected controller status", state, ctrl, intr);

	return 0;
}

static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
{
	struct onenand_chip *this = mtd->priv;

	if (ONENAND_CURRENT_BUFFERRAM(this)) {
		if (area == ONENAND_DATARAM)
			return this->writesize;
		if (area == ONENAND_SPARERAM)
			return mtd->oobsize;
	}

	return 0;
}

static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
					     dma_addr_t src, dma_addr_t dst,
					     size_t count)
{
	struct dma_async_tx_descriptor *tx;
	dma_cookie_t cookie;

	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
	if (!tx) {
		dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
		return -EIO;
	}

	reinit_completion(&c->dma_done);

	tx->callback = omap2_onenand_dma_complete_func;
	tx->callback_param = &c->dma_done;

	cookie = tx->tx_submit(tx);
	if (dma_submit_error(cookie)) {
		dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
		return -EIO;
	}

	dma_async_issue_pending(c->dma_chan);

	if (!wait_for_completion_io_timeout(&c->dma_done,
					    msecs_to_jiffies(20))) {
		dmaengine_terminate_sync(c->dma_chan);
		return -ETIMEDOUT;
	}

	return 0;
}

static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
					unsigned char *buffer, int offset,
					size_t count)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	dma_addr_t dma_src, dma_dst;
	int bram_offset;
	void *buf = (void *)buffer;
	size_t xtra;
	int ret;

	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
		goto out_copy;

	/* panic_write() may be in an interrupt context */
	if (in_interrupt() || oops_in_progress)
		goto out_copy;

	if (buf >= high_memory) {
		struct page *p1;

		if (((size_t)buf & PAGE_MASK) !=
		    ((size_t)(buf + count - 1) & PAGE_MASK))
			goto out_copy;
		p1 = vmalloc_to_page(buf);
		if (!p1)
			goto out_copy;
		buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
	}

	xtra = count & 3;
	if (xtra) {
		count -= xtra;
		memcpy(buf + count, this->base + bram_offset + count, xtra);
	}

	dma_src = c->phys_base + bram_offset;
	dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
	if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
		dev_err(&c->pdev->dev,
			"Couldn't DMA map a %d byte buffer\n",
			count);
		goto out_copy;
	}

	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);

	if (ret) {
		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
		goto out_copy;
	}

	return 0;

out_copy:
	memcpy(buf, this->base + bram_offset, count);
	return 0;
}

static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
					 const unsigned char *buffer,
					 int offset, size_t count)
{
	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	struct onenand_chip *this = mtd->priv;
	dma_addr_t dma_src, dma_dst;
	int bram_offset;
	void *buf = (void *)buffer;
	int ret;

	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
		goto out_copy;

	/* panic_write() may be in an interrupt context */
	if (in_interrupt() || oops_in_progress)
		goto out_copy;

	if (buf >= high_memory) {
		struct page *p1;

		if (((size_t)buf & PAGE_MASK) !=
		    ((size_t)(buf + count - 1) & PAGE_MASK))
			goto out_copy;
		p1 = vmalloc_to_page(buf);
		if (!p1)
			goto out_copy;
		buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
	}

	dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
	dma_dst = c->phys_base + bram_offset;
	if (dma_mapping_error(&c->pdev->dev, dma_src)) {
		dev_err(&c->pdev->dev,
			"Couldn't DMA map a %d byte buffer\n",
			count);
		return -1;
	}

	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);

	if (ret) {
		dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
		goto out_copy;
	}

	return 0;

out_copy:
	memcpy(this->base + bram_offset, buf, count);
	return 0;
}

static struct platform_driver omap2_onenand_driver;

static void omap2_onenand_shutdown(struct platform_device *pdev)
{
	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);

	/* With certain content in the buffer RAM, the OMAP boot ROM code
	 * can recognize the flash chip incorrectly. Zero it out before
	 * soft reset.
	 */
	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
}

static int omap2_onenand_probe(struct platform_device *pdev)
{
	struct omap_onenand_platform_data *pdata;
	struct omap2_onenand *c;
	struct onenand_chip *this;
	int r;
	struct resource *res;

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata == NULL) {
		dev_err(&pdev->dev, "platform data missing\n");
		return -ENODEV;
	}

	c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
	if (!c)
		return -ENOMEM;

	init_completion(&c->irq_done);
	init_completion(&c->dma_done);
	c->gpmc_cs = pdata->cs;
	c->gpio_irq = pdata->gpio_irq;
	if (pdata->dma_channel < 0) {
		/* if -1, don't use DMA */
		c->gpio_irq = 0;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		r = -EINVAL;
		dev_err(&pdev->dev, "error getting memory resource\n");
		goto err_kfree;
	}

	c->phys_base = res->start;
	c->mem_size = resource_size(res);

	if (request_mem_region(c->phys_base, c->mem_size,
			       pdev->dev.driver->name) == NULL) {
		dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
						c->phys_base, c->mem_size);
		r = -EBUSY;
		goto err_kfree;
	}
	c->onenand.base = ioremap(c->phys_base, c->mem_size);
	if (c->onenand.base == NULL) {
		r = -ENOMEM;
		goto err_release_mem_region;
	}

	if (pdata->onenand_setup != NULL) {
		r = pdata->onenand_setup(c->onenand.base, &c->freq);
		if (r < 0) {
			dev_err(&pdev->dev, "Onenand platform setup failed: "
				"%d\n", r);
			goto err_iounmap;
		}
		c->setup = pdata->onenand_setup;
	}

	if (c->gpio_irq) {
		if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
			dev_err(&pdev->dev,  "Failed to request GPIO%d for "
				"OneNAND\n", c->gpio_irq);
			goto err_iounmap;
	}
	gpio_direction_input(c->gpio_irq);

	if ((r = request_irq(gpio_to_irq(c->gpio_irq),
			     omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
			     pdev->dev.driver->name, c)) < 0)
		goto err_release_gpio;
	}

	if (pdata->dma_channel >= 0) {
		dma_cap_mask_t mask;

		dma_cap_zero(mask);
		dma_cap_set(DMA_MEMCPY, mask);

		c->dma_chan = dma_request_channel(mask, NULL, NULL);
		if (!c->dma_chan)
			dev_info(&pdev->dev,
				 "failed to allocate DMA for OneNAND, "
				 "using PIO instead\n");
	}

	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
		 "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
		 c->onenand.base, c->freq);

	c->pdev = pdev;
	c->mtd.priv = &c->onenand;

	c->mtd.dev.parent = &pdev->dev;
	mtd_set_of_node(&c->mtd, pdata->of_node);

	this = &c->onenand;
	if (c->dma_chan) {
		this->wait = omap2_onenand_wait;
		this->read_bufferram = omap2_onenand_read_bufferram;
		this->write_bufferram = omap2_onenand_write_bufferram;
	}

	if ((r = onenand_scan(&c->mtd, 1)) < 0)
		goto err_release_dma;

	r = mtd_device_register(&c->mtd, NULL, 0);
	if (r)
		goto err_release_onenand;

	platform_set_drvdata(pdev, c);

	return 0;

err_release_onenand:
	onenand_release(&c->mtd);
err_release_dma:
	if (c->dma_chan)
		dma_release_channel(c->dma_chan);
	if (c->gpio_irq)
		free_irq(gpio_to_irq(c->gpio_irq), c);
err_release_gpio:
	if (c->gpio_irq)
		gpio_free(c->gpio_irq);
err_iounmap:
	iounmap(c->onenand.base);
err_release_mem_region:
	release_mem_region(c->phys_base, c->mem_size);
err_kfree:
	kfree(c);

	return r;
}

static int omap2_onenand_remove(struct platform_device *pdev)
{
	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);

	onenand_release(&c->mtd);
	if (c->dma_chan)
		dma_release_channel(c->dma_chan);
	omap2_onenand_shutdown(pdev);
	if (c->gpio_irq) {
		free_irq(gpio_to_irq(c->gpio_irq), c);
		gpio_free(c->gpio_irq);
	}
	iounmap(c->onenand.base);
	release_mem_region(c->phys_base, c->mem_size);
	kfree(c);

	return 0;
}

static struct platform_driver omap2_onenand_driver = {
	.probe		= omap2_onenand_probe,
	.remove		= omap2_onenand_remove,
	.shutdown	= omap2_onenand_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

module_platform_driver(omap2_onenand_driver);

MODULE_ALIAS("platform:" DRIVER_NAME);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");
Commit	Line	Data
36cd4fb5 AH	1	/*
	2	* linux/drivers/mtd/onenand/omap2.c
	3	*
	4	* OneNAND driver for OMAP2 / OMAP3
	5	*
	6	* Copyright © 2005-2006 Nokia Corporation
	7	*
	8	* Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
	9	* IRQ and DMA support written by Timo Teras
	10	*
	11	* This program is free software; you can redistribute it and/or modify it
	12	* under the terms of the GNU General Public License version 2 as published by
	13	* the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope that it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	18	* more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along with
	21	* this program; see the file COPYING. If not, write to the Free Software
	22	* Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	23	*
	24	*/
	25
	26	#include <linux/device.h>
	27	#include <linux/module.h>
36cd4fb5 AH	28	#include <linux/mtd/mtd.h>
	29	#include <linux/mtd/onenand.h>
	30	#include <linux/mtd/partitions.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/interrupt.h>
	33	#include <linux/delay.h>
cbbd6956	34	#include <linux/dma-mapping.h>
3ed6a4d1	35	#include <linux/dmaengine.h>
cbbd6956	36	#include <linux/io.h>
5a0e3ad6	37	#include <linux/slab.h>
288e6eaa	38	#include <linux/gpio.h>
36cd4fb5	39
36cd4fb5	40	#include <asm/mach/flash.h>
2203747c	41	#include <linux/platform_data/mtd-onenand-omap2.h>
36cd4fb5	42
36cd4fb5 AH	43	#define DRIVER_NAME "omap2-onenand"
36cd4fb5 AH	44
36cd4fb5 AH	45	#define ONENAND_BUFRAM_SIZE (1024 * 5)
	46
	47	struct omap2_onenand {
	48	struct platform_device *pdev;
	49	int gpmc_cs;
	50	unsigned long phys_base;
d65ccb6d	51	unsigned int mem_size;
36cd4fb5 AH	52	int gpio_irq;
36cd4fb5 AH	53	struct mtd_info mtd;
36cd4fb5 AH	54	struct onenand_chip onenand;
	55	struct completion irq_done;
	56	struct completion dma_done;
3ed6a4d1	57	struct dma_chan *dma_chan;
36cd4fb5	58	int freq;
3ad2d861	59	int (setup)(void __iomem base, int *freq_ptr);
36cd4fb5 AH	60	};
36cd4fb5 AH	61
3ed6a4d1	62	static void omap2_onenand_dma_complete_func(void *completion)
36cd4fb5	63	{
3ed6a4d1	64	complete(completion);
36cd4fb5 AH	65	}
	66
	67	static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
	68	{
	69	struct omap2_onenand *c = dev_id;
	70
	71	complete(&c->irq_done);
	72
	73	return IRQ_HANDLED;
	74	}
	75
	76	static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
	77	{
	78	return readw(c->onenand.base + reg);
	79	}
	80
	81	static inline void write_reg(struct omap2_onenand *c, unsigned short value,
	82	int reg)
	83	{
	84	writew(value, c->onenand.base + reg);
	85	}
	86
	87	static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
	88	{
	89	printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
	90	msg, state, ctrl, intr);
	91	}
	92
	93	static void wait_warn(char *msg, int state, unsigned int ctrl,
	94	unsigned int intr)
	95	{
	96	printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
	97	"intr 0x%04x\n", msg, state, ctrl, intr);
	98	}
	99
	100	static int omap2_onenand_wait(struct mtd_info *mtd, int state)
	101	{
	102	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
d19d7b46	103	struct onenand_chip *this = mtd->priv;
36cd4fb5	104	unsigned int intr = 0;
d19d7b46	105	unsigned int ctrl, ctrl_mask;
36cd4fb5 AH	106	unsigned long timeout;
	107	u32 syscfg;
	108
72073027 MK	109	if (state == FL_RESETING \|\| state == FL_PREPARING_ERASE \|\|
	110	state == FL_VERIFYING_ERASE) {
	111	int i = 21;
	112	unsigned int intr_flags = ONENAND_INT_MASTER;
	113
	114	switch (state) {
	115	case FL_RESETING:
	116	intr_flags \|= ONENAND_INT_RESET;
	117	break;
	118	case FL_PREPARING_ERASE:
	119	intr_flags \|= ONENAND_INT_ERASE;
	120	break;
	121	case FL_VERIFYING_ERASE:
	122	i = 101;
	123	break;
	124	}
36cd4fb5	125
72073027	126	while (--i) {
36cd4fb5 AH	127	udelay(1);
	128	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	129	if (intr & ONENAND_INT_MASTER)
	130	break;
	131	}
	132	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	133	if (ctrl & ONENAND_CTRL_ERROR) {
	134	wait_err("controller error", state, ctrl, intr);
	135	return -EIO;
	136	}
c497dd55 RT	137	if ((intr & intr_flags) == intr_flags)
	138	return 0;
	139	/* Continue in wait for interrupt branch */
36cd4fb5 AH	140	}
	141
	142	if (state != FL_READING) {
	143	int result;
	144
	145	/* Turn interrupts on */
	146	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
782b7a36 AH	147	if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
	148	syscfg \|= ONENAND_SYS_CFG1_IOBE;
	149	write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
f5229331 LM	150	/* Add a delay to let GPIO settle */
f5229331 LM	151	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
782b7a36	152	}
36cd4fb5	153
16735d02	154	reinit_completion(&c->irq_done);
36cd4fb5	155	if (c->gpio_irq) {
0b84b5ca	156	result = gpio_get_value(c->gpio_irq);
36cd4fb5 AH	157	if (result == -1) {
	158	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	159	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	160	wait_err("gpio error", state, ctrl, intr);
	161	return -EIO;
	162	}
	163	} else
	164	result = 0;
	165	if (result == 0) {
	166	int retry_cnt = 0;
	167	retry:
d1205688 LM	168	if (!wait_for_completion_io_timeout(&c->irq_done,
d1205688 LM	169	msecs_to_jiffies(20))) {
36cd4fb5 AH	170	/* Timeout after 20ms */
36cd4fb5 AH	171	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
d19d7b46 RT	172	if (ctrl & ONENAND_CTRL_ONGO &&
d19d7b46 RT	173	!this->ongoing) {
36cd4fb5 AH	174	/*
	175	* The operation seems to be still going
	176	* so give it some more time.
	177	*/
	178	retry_cnt += 1;
	179	if (retry_cnt < 3)
	180	goto retry;
	181	intr = read_reg(c,
	182	ONENAND_REG_INTERRUPT);
	183	wait_err("timeout", state, ctrl, intr);
	184	return -EIO;
	185	}
	186	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	187	if ((intr & ONENAND_INT_MASTER) == 0)
	188	wait_warn("timeout", state, ctrl, intr);
	189	}
	190	}
	191	} else {
8afbc114 AH	192	int retry_cnt = 0;
8afbc114 AH	193
36cd4fb5 AH	194	/* Turn interrupts off */
	195	syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
	196	syscfg &= ~ONENAND_SYS_CFG1_IOBE;
	197	write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
	198
	199	timeout = jiffies + msecs_to_jiffies(20);
8afbc114 AH	200	while (1) {
	201	if (time_before(jiffies, timeout)) {
	202	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	203	if (intr & ONENAND_INT_MASTER)
	204	break;
	205	} else {
	206	/* Timeout after 20ms */
	207	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	208	if (ctrl & ONENAND_CTRL_ONGO) {
	209	/*
	210	* The operation seems to be still going
	211	* so give it some more time.
	212	*/
	213	retry_cnt += 1;
	214	if (retry_cnt < 3) {
	215	timeout = jiffies +
	216	msecs_to_jiffies(20);
	217	continue;
	218	}
	219	}
36cd4fb5	220	break;
8afbc114	221	}
36cd4fb5 AH	222	}
	223	}
	224
	225	intr = read_reg(c, ONENAND_REG_INTERRUPT);
	226	ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
	227
	228	if (intr & ONENAND_INT_READ) {
	229	int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
	230
	231	if (ecc) {
	232	unsigned int addr1, addr8;
	233
	234	addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
	235	addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
	236	if (ecc & ONENAND_ECC_2BIT_ALL) {
	237	printk(KERN_ERR "onenand_wait: ECC error = "
	238	"0x%04x, addr1 %#x, addr8 %#x\n",
	239	ecc, addr1, addr8);
	240	mtd->ecc_stats.failed++;
	241	return -EBADMSG;
	242	} else if (ecc & ONENAND_ECC_1BIT_ALL) {
	243	printk(KERN_NOTICE "onenand_wait: correctable "
	244	"ECC error = 0x%04x, addr1 %#x, "
	245	"addr8 %#x\n", ecc, addr1, addr8);
	246	mtd->ecc_stats.corrected++;
	247	}
	248	}
	249	} else if (state == FL_READING) {
	250	wait_err("timeout", state, ctrl, intr);
	251	return -EIO;
	252	}
	253
	254	if (ctrl & ONENAND_CTRL_ERROR) {
	255	wait_err("controller error", state, ctrl, intr);
	256	if (ctrl & ONENAND_CTRL_LOCK)
	257	printk(KERN_ERR "onenand_wait: "
	258	"Device is write protected!!!\n");
	259	return -EIO;
	260	}
	261
d19d7b46 RT	262	ctrl_mask = 0xFE9F;
	263	if (this->ongoing)
	264	ctrl_mask &= ~0x8000;
	265
	266	if (ctrl & ctrl_mask)
36cd4fb5 AH	267	wait_warn("unexpected controller status", state, ctrl, intr);
	268
	269	return 0;
	270	}
	271
	272	static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
	273	{
	274	struct onenand_chip *this = mtd->priv;
	275
	276	if (ONENAND_CURRENT_BUFFERRAM(this)) {
	277	if (area == ONENAND_DATARAM)
00acf4a8	278	return this->writesize;
36cd4fb5 AH	279	if (area == ONENAND_SPARERAM)
	280	return mtd->oobsize;
	281	}
	282
	283	return 0;
	284	}
	285
36213116 PU	286	static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
	287	dma_addr_t src, dma_addr_t dst,
	288	size_t count)
	289	{
3ed6a4d1 PU	290	struct dma_async_tx_descriptor *tx;
3ed6a4d1 PU	291	dma_cookie_t cookie;
36213116	292
3ed6a4d1 PU	293	tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
	294	if (!tx) {
	295	dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
	296	return -EIO;
	297	}
36213116 PU	298
36213116 PU	299	reinit_completion(&c->dma_done);
3ed6a4d1 PU	300
	301	tx->callback = omap2_onenand_dma_complete_func;
	302	tx->callback_param = &c->dma_done;
	303
	304	cookie = tx->tx_submit(tx);
	305	if (dma_submit_error(cookie)) {
	306	dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
	307	return -EIO;
	308	}
	309
	310	dma_async_issue_pending(c->dma_chan);
	311
36213116 PU	312	if (!wait_for_completion_io_timeout(&c->dma_done,
36213116 PU	313	msecs_to_jiffies(20))) {
3ed6a4d1	314	dmaengine_terminate_sync(c->dma_chan);
36213116 PU	315	return -ETIMEDOUT;
	316	}
	317
	318	return 0;
	319	}
	320
fb25070a	321	static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
36cd4fb5 AH	322	unsigned char *buffer, int offset,
	323	size_t count)
	324	{
	325	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	326	struct onenand_chip *this = mtd->priv;
	327	dma_addr_t dma_src, dma_dst;
	328	int bram_offset;
36cd4fb5 AH	329	void buf = (void )buffer;
36cd4fb5 AH	330	size_t xtra;
36213116	331	int ret;
36cd4fb5 AH	332
	333	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	334	if (bram_offset & 3 \|\| (size_t)buf & 3 \|\| count < 384)
	335	goto out_copy;
	336
a29f280b	337	/* panic_write() may be in an interrupt context */
932f5d21	338	if (in_interrupt() \|\| oops_in_progress)
a29f280b AH	339	goto out_copy;
a29f280b AH	340
36cd4fb5 AH	341	if (buf >= high_memory) {
	342	struct page *p1;
	343
	344	if (((size_t)buf & PAGE_MASK) !=
	345	((size_t)(buf + count - 1) & PAGE_MASK))
	346	goto out_copy;
	347	p1 = vmalloc_to_page(buf);
	348	if (!p1)
	349	goto out_copy;
	350	buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
	351	}
	352
	353	xtra = count & 3;
	354	if (xtra) {
	355	count -= xtra;
	356	memcpy(buf + count, this->base + bram_offset + count, xtra);
	357	}
	358
	359	dma_src = c->phys_base + bram_offset;
	360	dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
	361	if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
	362	dev_err(&c->pdev->dev,
	363	"Couldn't DMA map a %d byte buffer\n",
	364	count);
	365	goto out_copy;
	366	}
	367
36213116	368	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
36cd4fb5 AH	369	dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
36cd4fb5 AH	370
36213116	371	if (ret) {
36cd4fb5 AH	372	dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
	373	goto out_copy;
	374	}
	375
	376	return 0;
	377
	378	out_copy:
	379	memcpy(buf, this->base + bram_offset, count);
	380	return 0;
	381	}
	382
fb25070a	383	static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
36cd4fb5 AH	384	const unsigned char *buffer,
	385	int offset, size_t count)
	386	{
	387	struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
	388	struct onenand_chip *this = mtd->priv;
	389	dma_addr_t dma_src, dma_dst;
	390	int bram_offset;
36cd4fb5	391	void buf = (void )buffer;
36213116	392	int ret;
36cd4fb5 AH	393
	394	bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
	395	if (bram_offset & 3 \|\| (size_t)buf & 3 \|\| count < 384)
	396	goto out_copy;
	397
	398	/* panic_write() may be in an interrupt context */
932f5d21	399	if (in_interrupt() \|\| oops_in_progress)
36cd4fb5 AH	400	goto out_copy;
	401
	402	if (buf >= high_memory) {
	403	struct page *p1;
	404
	405	if (((size_t)buf & PAGE_MASK) !=
	406	((size_t)(buf + count - 1) & PAGE_MASK))
	407	goto out_copy;
	408	p1 = vmalloc_to_page(buf);
	409	if (!p1)
	410	goto out_copy;
	411	buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
	412	}
	413
	414	dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
	415	dma_dst = c->phys_base + bram_offset;
4a70b7d3	416	if (dma_mapping_error(&c->pdev->dev, dma_src)) {
36cd4fb5 AH	417	dev_err(&c->pdev->dev,
	418	"Couldn't DMA map a %d byte buffer\n",
	419	count);
	420	return -1;
	421	}
	422
36213116	423	ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
4a70b7d3	424	dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
36cd4fb5	425
36213116	426	if (ret) {
36cd4fb5 AH	427	dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
	428	goto out_copy;
	429	}
	430
	431	return 0;
	432
	433	out_copy:
	434	memcpy(this->base + bram_offset, buf, count);
	435	return 0;
	436	}
	437
36cd4fb5 AH	438	static struct platform_driver omap2_onenand_driver;
36cd4fb5 AH	439
d3412dbd	440	static void omap2_onenand_shutdown(struct platform_device *pdev)
36cd4fb5 AH	441	{
	442	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
	443
	444	/* With certain content in the buffer RAM, the OMAP boot ROM code
	445	* can recognize the flash chip incorrectly. Zero it out before
	446	* soft reset.
	447	*/
	448	memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
	449	}
	450
06f25510	451	static int omap2_onenand_probe(struct platform_device *pdev)
36cd4fb5 AH	452	{
	453	struct omap_onenand_platform_data *pdata;
	454	struct omap2_onenand *c;
c93ff6bf	455	struct onenand_chip *this;
36cd4fb5	456	int r;
d65ccb6d	457	struct resource *res;
36cd4fb5	458
e09f7f99	459	pdata = dev_get_platdata(&pdev->dev);
36cd4fb5 AH	460	if (pdata == NULL) {
	461	dev_err(&pdev->dev, "platform data missing\n");
	462	return -ENODEV;
	463	}
	464
	465	c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
	466	if (!c)
	467	return -ENOMEM;
	468
	469	init_completion(&c->irq_done);
	470	init_completion(&c->dma_done);
	471	c->gpmc_cs = pdata->cs;
	472	c->gpio_irq = pdata->gpio_irq;
3ed6a4d1	473	if (pdata->dma_channel < 0) {
36cd4fb5 AH	474	/* if -1, don't use DMA */
	475	c->gpio_irq = 0;
	476	}
	477
d65ccb6d AM	478	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	479	if (res == NULL) {
	480	r = -EINVAL;
	481	dev_err(&pdev->dev, "error getting memory resource\n");
36cd4fb5 AH	482	goto err_kfree;
	483	}
	484
d65ccb6d AM	485	c->phys_base = res->start;
	486	c->mem_size = resource_size(res);
	487
	488	if (request_mem_region(c->phys_base, c->mem_size,
36cd4fb5	489	pdev->dev.driver->name) == NULL) {
d65ccb6d AM	490	dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
d65ccb6d AM	491	c->phys_base, c->mem_size);
36cd4fb5	492	r = -EBUSY;
d65ccb6d	493	goto err_kfree;
36cd4fb5	494	}
d65ccb6d	495	c->onenand.base = ioremap(c->phys_base, c->mem_size);
36cd4fb5 AH	496	if (c->onenand.base == NULL) {
	497	r = -ENOMEM;
	498	goto err_release_mem_region;
	499	}
	500
	501	if (pdata->onenand_setup != NULL) {
3ad2d861	502	r = pdata->onenand_setup(c->onenand.base, &c->freq);
36cd4fb5 AH	503	if (r < 0) {
	504	dev_err(&pdev->dev, "Onenand platform setup failed: "
	505	"%d\n", r);
	506	goto err_iounmap;
	507	}
	508	c->setup = pdata->onenand_setup;
	509	}
	510
	511	if (c->gpio_irq) {
73069e38	512	if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
36cd4fb5 AH	513	dev_err(&pdev->dev, "Failed to request GPIO%d for "
	514	"OneNAND\n", c->gpio_irq);
	515	goto err_iounmap;
	516	}
40e3925b	517	gpio_direction_input(c->gpio_irq);
36cd4fb5	518
15f74b03	519	if ((r = request_irq(gpio_to_irq(c->gpio_irq),
36cd4fb5 AH	520	omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
	521	pdev->dev.driver->name, c)) < 0)
	522	goto err_release_gpio;
	523	}
	524
3ed6a4d1 PU	525	if (pdata->dma_channel >= 0) {
	526	dma_cap_mask_t mask;
	527
	528	dma_cap_zero(mask);
	529	dma_cap_set(DMA_MEMCPY, mask);
	530
	531	c->dma_chan = dma_request_channel(mask, NULL, NULL);
	532	if (!c->dma_chan)
36cd4fb5 AH	533	dev_info(&pdev->dev,
	534	"failed to allocate DMA for OneNAND, "
	535	"using PIO instead\n");
36cd4fb5 AH	536	}
	537
	538	dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
3ad2d861 AH	539	"base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
3ad2d861 AH	540	c->onenand.base, c->freq);
36cd4fb5 AH	541
36cd4fb5 AH	542	c->pdev = pdev;
36cd4fb5	543	c->mtd.priv = &c->onenand;
36cd4fb5	544
87f39f04	545	c->mtd.dev.parent = &pdev->dev;
004b5e60	546	mtd_set_of_node(&c->mtd, pdata->of_node);
87f39f04	547
c93ff6bf	548	this = &c->onenand;
3ed6a4d1	549	if (c->dma_chan) {
36cd4fb5	550	this->wait = omap2_onenand_wait;
fb25070a LM	551	this->read_bufferram = omap2_onenand_read_bufferram;
fb25070a LM	552	this->write_bufferram = omap2_onenand_write_bufferram;
36cd4fb5 AH	553	}
	554
	555	if ((r = onenand_scan(&c->mtd, 1)) < 0)
e6854e02	556	goto err_release_dma;
36cd4fb5	557
fafc0b3a	558	r = mtd_device_register(&c->mtd, NULL, 0);
263a8c86	559	if (r)
36cd4fb5 AH	560	goto err_release_onenand;
	561
	562	platform_set_drvdata(pdev, c);
	563
	564	return 0;
	565
	566	err_release_onenand:
	567	onenand_release(&c->mtd);
	568	err_release_dma:
3ed6a4d1 PU	569	if (c->dma_chan)
3ed6a4d1 PU	570	dma_release_channel(c->dma_chan);
36cd4fb5	571	if (c->gpio_irq)
15f74b03	572	free_irq(gpio_to_irq(c->gpio_irq), c);
36cd4fb5 AH	573	err_release_gpio:
36cd4fb5 AH	574	if (c->gpio_irq)
73069e38	575	gpio_free(c->gpio_irq);
36cd4fb5 AH	576	err_iounmap:
	577	iounmap(c->onenand.base);
	578	err_release_mem_region:
d65ccb6d	579	release_mem_region(c->phys_base, c->mem_size);
36cd4fb5 AH	580	err_kfree:
	581	kfree(c);
	582
	583	return r;
	584	}
	585
810b7e06	586	static int omap2_onenand_remove(struct platform_device *pdev)
36cd4fb5 AH	587	{
	588	struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
	589
36cd4fb5	590	onenand_release(&c->mtd);
3ed6a4d1 PU	591	if (c->dma_chan)
3ed6a4d1 PU	592	dma_release_channel(c->dma_chan);
36cd4fb5	593	omap2_onenand_shutdown(pdev);
36cd4fb5	594	if (c->gpio_irq) {
15f74b03	595	free_irq(gpio_to_irq(c->gpio_irq), c);
73069e38	596	gpio_free(c->gpio_irq);
36cd4fb5 AH	597	}
36cd4fb5 AH	598	iounmap(c->onenand.base);
d65ccb6d	599	release_mem_region(c->phys_base, c->mem_size);
36cd4fb5 AH	600	kfree(c);
	601
	602	return 0;
	603	}
	604
	605	static struct platform_driver omap2_onenand_driver = {
	606	.probe = omap2_onenand_probe,
5153b88c	607	.remove = omap2_onenand_remove,
36cd4fb5 AH	608	.shutdown = omap2_onenand_shutdown,
	609	.driver = {
	610	.name = DRIVER_NAME,
36cd4fb5 AH	611	},
	612	};
	613
cdb6404c	614	module_platform_driver(omap2_onenand_driver);
36cd4fb5	615
c804c733	616	MODULE_ALIAS("platform:" DRIVER_NAME);
36cd4fb5 AH	617	MODULE_LICENSE("GPL");
	618	MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
	619	MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");