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99f2b107 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
6 | * Copyright © 2012 John Crispin <blogic@openwrt.org> | |
02436675 | 7 | * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de> |
99f2b107 JC |
8 | */ |
9 | ||
10 | #include <linux/mtd/nand.h> | |
11 | #include <linux/of_gpio.h> | |
12 | #include <linux/of_platform.h> | |
13 | ||
14 | #include <lantiq_soc.h> | |
15 | ||
16 | /* nand registers */ | |
17 | #define EBU_ADDSEL1 0x24 | |
18 | #define EBU_NAND_CON 0xB0 | |
19 | #define EBU_NAND_WAIT 0xB4 | |
3d8cec22 HM |
20 | #define NAND_WAIT_RD BIT(0) /* NAND flash status output */ |
21 | #define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */ | |
99f2b107 JC |
22 | #define EBU_NAND_ECC0 0xB8 |
23 | #define EBU_NAND_ECC_AC 0xBC | |
24 | ||
3d8cec22 HM |
25 | /* |
26 | * nand commands | |
27 | * The pins of the NAND chip are selected based on the address bits of the | |
28 | * "register" read and write. There are no special registers, but an | |
29 | * address range and the lower address bits are used to activate the | |
30 | * correct line. For example when the bit (1 << 2) is set in the address | |
31 | * the ALE pin will be activated. | |
32 | */ | |
33 | #define NAND_CMD_ALE BIT(2) /* address latch enable */ | |
34 | #define NAND_CMD_CLE BIT(3) /* command latch enable */ | |
35 | #define NAND_CMD_CS BIT(4) /* chip select */ | |
36 | #define NAND_CMD_SE BIT(5) /* spare area access latch */ | |
37 | #define NAND_CMD_WP BIT(6) /* write protect */ | |
99f2b107 JC |
38 | #define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) |
39 | #define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) | |
40 | #define NAND_WRITE_DATA (NAND_CMD_CS) | |
41 | #define NAND_READ_DATA (NAND_CMD_CS) | |
99f2b107 JC |
42 | |
43 | /* we need to tel the ebu which addr we mapped the nand to */ | |
44 | #define ADDSEL1_MASK(x) (x << 4) | |
45 | #define ADDSEL1_REGEN 1 | |
46 | ||
47 | /* we need to tell the EBU that we have nand attached and set it up properly */ | |
48 | #define BUSCON1_SETUP (1 << 22) | |
49 | #define BUSCON1_BCGEN_RES (0x3 << 12) | |
50 | #define BUSCON1_WAITWRC2 (2 << 8) | |
51 | #define BUSCON1_WAITRDC2 (2 << 6) | |
52 | #define BUSCON1_HOLDC1 (1 << 4) | |
53 | #define BUSCON1_RECOVC1 (1 << 2) | |
54 | #define BUSCON1_CMULT4 1 | |
55 | ||
56 | #define NAND_CON_CE (1 << 20) | |
57 | #define NAND_CON_OUT_CS1 (1 << 10) | |
58 | #define NAND_CON_IN_CS1 (1 << 8) | |
59 | #define NAND_CON_PRE_P (1 << 7) | |
60 | #define NAND_CON_WP_P (1 << 6) | |
61 | #define NAND_CON_SE_P (1 << 5) | |
62 | #define NAND_CON_CS_P (1 << 4) | |
63 | #define NAND_CON_CSMUX (1 << 1) | |
64 | #define NAND_CON_NANDM 1 | |
65 | ||
02436675 HM |
66 | struct xway_nand_data { |
67 | struct nand_chip chip; | |
e7e1f7be | 68 | unsigned long csflags; |
37987ba4 | 69 | void __iomem *nandaddr; |
02436675 HM |
70 | }; |
71 | ||
ddbed9c2 HM |
72 | static u8 xway_readb(struct mtd_info *mtd, int op) |
73 | { | |
74 | struct nand_chip *chip = mtd_to_nand(mtd); | |
37987ba4 | 75 | struct xway_nand_data *data = nand_get_controller_data(chip); |
ddbed9c2 | 76 | |
37987ba4 | 77 | return readb(data->nandaddr + op); |
ddbed9c2 HM |
78 | } |
79 | ||
80 | static void xway_writeb(struct mtd_info *mtd, int op, u8 value) | |
81 | { | |
82 | struct nand_chip *chip = mtd_to_nand(mtd); | |
37987ba4 | 83 | struct xway_nand_data *data = nand_get_controller_data(chip); |
ddbed9c2 | 84 | |
37987ba4 | 85 | writeb(value, data->nandaddr + op); |
ddbed9c2 HM |
86 | } |
87 | ||
e7e1f7be | 88 | static void xway_select_chip(struct mtd_info *mtd, int select) |
99f2b107 | 89 | { |
e7e1f7be JC |
90 | struct nand_chip *chip = mtd_to_nand(mtd); |
91 | struct xway_nand_data *data = nand_get_controller_data(chip); | |
99f2b107 | 92 | |
e7e1f7be | 93 | switch (select) { |
99f2b107 JC |
94 | case -1: |
95 | ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); | |
96 | ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); | |
e7e1f7be | 97 | spin_unlock_irqrestore(&ebu_lock, data->csflags); |
99f2b107 JC |
98 | break; |
99 | case 0: | |
e7e1f7be | 100 | spin_lock_irqsave(&ebu_lock, data->csflags); |
99f2b107 JC |
101 | ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); |
102 | ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); | |
103 | break; | |
104 | default: | |
105 | BUG(); | |
106 | } | |
107 | } | |
108 | ||
109 | static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
110 | { | |
f45eb7b5 JC |
111 | if (cmd == NAND_CMD_NONE) |
112 | return; | |
99f2b107 | 113 | |
f45eb7b5 | 114 | if (ctrl & NAND_CLE) |
ddbed9c2 | 115 | xway_writeb(mtd, NAND_WRITE_CMD, cmd); |
f45eb7b5 | 116 | else if (ctrl & NAND_ALE) |
ddbed9c2 | 117 | xway_writeb(mtd, NAND_WRITE_ADDR, cmd); |
f45eb7b5 JC |
118 | |
119 | while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) | |
120 | ; | |
99f2b107 JC |
121 | } |
122 | ||
123 | static int xway_dev_ready(struct mtd_info *mtd) | |
124 | { | |
125 | return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; | |
126 | } | |
127 | ||
128 | static unsigned char xway_read_byte(struct mtd_info *mtd) | |
129 | { | |
ddbed9c2 | 130 | return xway_readb(mtd, NAND_READ_DATA); |
99f2b107 JC |
131 | } |
132 | ||
250d45eb HM |
133 | static void xway_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
134 | { | |
135 | int i; | |
136 | ||
137 | for (i = 0; i < len; i++) | |
138 | buf[i] = xway_readb(mtd, NAND_WRITE_DATA); | |
139 | } | |
140 | ||
141 | static void xway_write_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < len; i++) | |
146 | xway_writeb(mtd, NAND_WRITE_DATA, buf[i]); | |
147 | } | |
148 | ||
02436675 HM |
149 | /* |
150 | * Probe for the NAND device. | |
151 | */ | |
99f2b107 JC |
152 | static int xway_nand_probe(struct platform_device *pdev) |
153 | { | |
02436675 HM |
154 | struct xway_nand_data *data; |
155 | struct mtd_info *mtd; | |
156 | struct resource *res; | |
157 | int err; | |
02436675 | 158 | u32 cs; |
99f2b107 JC |
159 | u32 cs_flag = 0; |
160 | ||
02436675 HM |
161 | /* Allocate memory for the device structure (and zero it) */ |
162 | data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), | |
163 | GFP_KERNEL); | |
164 | if (!data) | |
165 | return -ENOMEM; | |
166 | ||
167 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
37987ba4 HM |
168 | data->nandaddr = devm_ioremap_resource(&pdev->dev, res); |
169 | if (IS_ERR(data->nandaddr)) | |
170 | return PTR_ERR(data->nandaddr); | |
02436675 HM |
171 | |
172 | nand_set_flash_node(&data->chip, pdev->dev.of_node); | |
173 | mtd = nand_to_mtd(&data->chip); | |
174 | mtd->dev.parent = &pdev->dev; | |
175 | ||
02436675 HM |
176 | data->chip.cmd_ctrl = xway_cmd_ctrl; |
177 | data->chip.dev_ready = xway_dev_ready; | |
178 | data->chip.select_chip = xway_select_chip; | |
250d45eb HM |
179 | data->chip.write_buf = xway_write_buf; |
180 | data->chip.read_buf = xway_read_buf; | |
02436675 HM |
181 | data->chip.read_byte = xway_read_byte; |
182 | data->chip.chip_delay = 30; | |
183 | ||
184 | data->chip.ecc.mode = NAND_ECC_SOFT; | |
185 | data->chip.ecc.algo = NAND_ECC_HAMMING; | |
186 | ||
187 | platform_set_drvdata(pdev, data); | |
188 | nand_set_controller_data(&data->chip, data); | |
189 | ||
99f2b107 | 190 | /* load our CS from the DT. Either we find a valid 1 or default to 0 */ |
02436675 HM |
191 | err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs); |
192 | if (!err && cs == 1) | |
99f2b107 JC |
193 | cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; |
194 | ||
195 | /* setup the EBU to run in NAND mode on our base addr */ | |
37987ba4 HM |
196 | ltq_ebu_w32(CPHYSADDR(data->nandaddr) |
197 | | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); | |
99f2b107 JC |
198 | |
199 | ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 | |
37987ba4 HM |
200 | | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 |
201 | | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); | |
99f2b107 JC |
202 | |
203 | ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P | |
37987ba4 HM |
204 | | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P |
205 | | cs_flag, EBU_NAND_CON); | |
99f2b107 | 206 | |
02436675 HM |
207 | /* Scan to find existence of the device */ |
208 | err = nand_scan(mtd, 1); | |
209 | if (err) | |
210 | return err; | |
99f2b107 | 211 | |
02436675 HM |
212 | err = mtd_device_register(mtd, NULL, 0); |
213 | if (err) | |
214 | nand_release(mtd); | |
215 | ||
216 | return err; | |
217 | } | |
99f2b107 JC |
218 | |
219 | /* | |
02436675 | 220 | * Remove a NAND device. |
99f2b107 | 221 | */ |
02436675 | 222 | static int xway_nand_remove(struct platform_device *pdev) |
99f2b107 | 223 | { |
02436675 HM |
224 | struct xway_nand_data *data = platform_get_drvdata(pdev); |
225 | ||
226 | nand_release(nand_to_mtd(&data->chip)); | |
227 | ||
99f2b107 JC |
228 | return 0; |
229 | } | |
230 | ||
02436675 HM |
231 | static const struct of_device_id xway_nand_match[] = { |
232 | { .compatible = "lantiq,nand-xway" }, | |
233 | {}, | |
234 | }; | |
235 | MODULE_DEVICE_TABLE(of, xway_nand_match); | |
236 | ||
237 | static struct platform_driver xway_nand_driver = { | |
238 | .probe = xway_nand_probe, | |
239 | .remove = xway_nand_remove, | |
240 | .driver = { | |
241 | .name = "lantiq,nand-xway", | |
242 | .of_match_table = xway_nand_match, | |
243 | }, | |
244 | }; | |
245 | ||
246 | module_platform_driver(xway_nand_driver); | |
247 | ||
248 | MODULE_LICENSE("GPL"); |