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456930d8 SA |
1 | /* |
2 | * Copyright 2009-2015 Freescale Semiconductor, Inc. and others | |
3 | * | |
4 | * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. | |
5 | * Jason ported to M54418TWR and MVFA5 (VF610). | |
6 | * Authors: Stefan Agner <stefan.agner@toradex.com> | |
7 | * Bill Pringlemeir <bpringlemeir@nbsps.com> | |
8 | * Shaohui Xie <b21989@freescale.com> | |
9 | * Jason Jin <Jason.jin@freescale.com> | |
10 | * | |
11 | * Based on original driver mpc5121_nfc.c. | |
12 | * | |
13 | * This is free software; you can redistribute it and/or modify it | |
14 | * under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * Limitations: | |
19 | * - Untested on MPC5125 and M54418. | |
20 | * - DMA and pipelining not used. | |
21 | * - 2K pages or less. | |
049f4250 SA |
22 | * - HW ECC: Only 2K page with 64+ OOB. |
23 | * - HW ECC: Only 24 and 32-bit error correction implemented. | |
456930d8 SA |
24 | */ |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/bitops.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/mtd/mtd.h> | |
34 | #include <linux/mtd/nand.h> | |
35 | #include <linux/mtd/partitions.h> | |
456930d8 | 36 | #include <linux/of_device.h> |
039353c8 | 37 | #include <linux/pinctrl/consumer.h> |
456930d8 SA |
38 | #include <linux/platform_device.h> |
39 | #include <linux/slab.h> | |
40 | ||
41 | #define DRV_NAME "vf610_nfc" | |
42 | ||
43 | /* Register Offsets */ | |
44 | #define NFC_FLASH_CMD1 0x3F00 | |
45 | #define NFC_FLASH_CMD2 0x3F04 | |
46 | #define NFC_COL_ADDR 0x3F08 | |
47 | #define NFC_ROW_ADDR 0x3F0c | |
48 | #define NFC_ROW_ADDR_INC 0x3F14 | |
49 | #define NFC_FLASH_STATUS1 0x3F18 | |
50 | #define NFC_FLASH_STATUS2 0x3F1c | |
51 | #define NFC_CACHE_SWAP 0x3F28 | |
52 | #define NFC_SECTOR_SIZE 0x3F2c | |
53 | #define NFC_FLASH_CONFIG 0x3F30 | |
54 | #define NFC_IRQ_STATUS 0x3F38 | |
55 | ||
56 | /* Addresses for NFC MAIN RAM BUFFER areas */ | |
57 | #define NFC_MAIN_AREA(n) ((n) * 0x1000) | |
58 | ||
59 | #define PAGE_2K 0x0800 | |
60 | #define OOB_64 0x0040 | |
61 | #define OOB_MAX 0x0100 | |
62 | ||
63 | /* | |
64 | * NFC_CMD2[CODE] values. See section: | |
65 | * - 31.4.7 Flash Command Code Description, Vybrid manual | |
66 | * - 23.8.6 Flash Command Sequencer, MPC5125 manual | |
67 | * | |
68 | * Briefly these are bitmasks of controller cycles. | |
69 | */ | |
70 | #define READ_PAGE_CMD_CODE 0x7EE0 | |
71 | #define READ_ONFI_PARAM_CMD_CODE 0x4860 | |
72 | #define PROGRAM_PAGE_CMD_CODE 0x7FC0 | |
73 | #define ERASE_CMD_CODE 0x4EC0 | |
74 | #define READ_ID_CMD_CODE 0x4804 | |
75 | #define RESET_CMD_CODE 0x4040 | |
76 | #define STATUS_READ_CMD_CODE 0x4068 | |
77 | ||
78 | /* NFC ECC mode define */ | |
79 | #define ECC_BYPASS 0 | |
049f4250 SA |
80 | #define ECC_45_BYTE 6 |
81 | #define ECC_60_BYTE 7 | |
456930d8 SA |
82 | |
83 | /*** Register Mask and bit definitions */ | |
84 | ||
85 | /* NFC_FLASH_CMD1 Field */ | |
86 | #define CMD_BYTE2_MASK 0xFF000000 | |
87 | #define CMD_BYTE2_SHIFT 24 | |
88 | ||
89 | /* NFC_FLASH_CM2 Field */ | |
90 | #define CMD_BYTE1_MASK 0xFF000000 | |
91 | #define CMD_BYTE1_SHIFT 24 | |
92 | #define CMD_CODE_MASK 0x00FFFF00 | |
93 | #define CMD_CODE_SHIFT 8 | |
94 | #define BUFNO_MASK 0x00000006 | |
95 | #define BUFNO_SHIFT 1 | |
96 | #define START_BIT BIT(0) | |
97 | ||
98 | /* NFC_COL_ADDR Field */ | |
99 | #define COL_ADDR_MASK 0x0000FFFF | |
100 | #define COL_ADDR_SHIFT 0 | |
101 | ||
102 | /* NFC_ROW_ADDR Field */ | |
103 | #define ROW_ADDR_MASK 0x00FFFFFF | |
104 | #define ROW_ADDR_SHIFT 0 | |
105 | #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 | |
106 | #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 | |
107 | #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 | |
108 | #define ROW_ADDR_CHIP_SEL_SHIFT 24 | |
109 | ||
110 | /* NFC_FLASH_STATUS2 Field */ | |
111 | #define STATUS_BYTE1_MASK 0x000000FF | |
112 | ||
113 | /* NFC_FLASH_CONFIG Field */ | |
114 | #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 | |
115 | #define CONFIG_ECC_SRAM_ADDR_SHIFT 22 | |
116 | #define CONFIG_ECC_SRAM_REQ_BIT BIT(21) | |
117 | #define CONFIG_DMA_REQ_BIT BIT(20) | |
118 | #define CONFIG_ECC_MODE_MASK 0x000E0000 | |
119 | #define CONFIG_ECC_MODE_SHIFT 17 | |
120 | #define CONFIG_FAST_FLASH_BIT BIT(16) | |
121 | #define CONFIG_16BIT BIT(7) | |
122 | #define CONFIG_BOOT_MODE_BIT BIT(6) | |
123 | #define CONFIG_ADDR_AUTO_INCR_BIT BIT(5) | |
124 | #define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4) | |
125 | #define CONFIG_PAGE_CNT_MASK 0xF | |
126 | #define CONFIG_PAGE_CNT_SHIFT 0 | |
127 | ||
128 | /* NFC_IRQ_STATUS Field */ | |
129 | #define IDLE_IRQ_BIT BIT(29) | |
130 | #define IDLE_EN_BIT BIT(20) | |
131 | #define CMD_DONE_CLEAR_BIT BIT(18) | |
132 | #define IDLE_CLEAR_BIT BIT(17) | |
133 | ||
049f4250 SA |
134 | /* |
135 | * ECC status - seems to consume 8 bytes (double word). The documented | |
136 | * status byte is located in the lowest byte of the second word (which is | |
137 | * the 4th or 7th byte depending on endianness). | |
138 | * Calculate an offset to store the ECC status at the end of the buffer. | |
139 | */ | |
140 | #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8) | |
141 | ||
142 | #define ECC_STATUS 0x4 | |
143 | #define ECC_STATUS_MASK 0x80 | |
144 | #define ECC_STATUS_ERR_COUNT 0x3F | |
145 | ||
456930d8 SA |
146 | enum vf610_nfc_alt_buf { |
147 | ALT_BUF_DATA = 0, | |
148 | ALT_BUF_ID = 1, | |
149 | ALT_BUF_STAT = 2, | |
150 | ALT_BUF_ONFI = 3, | |
151 | }; | |
152 | ||
153 | enum vf610_nfc_variant { | |
154 | NFC_VFC610 = 1, | |
155 | }; | |
156 | ||
157 | struct vf610_nfc { | |
456930d8 SA |
158 | struct nand_chip chip; |
159 | struct device *dev; | |
160 | void __iomem *regs; | |
161 | struct completion cmd_done; | |
162 | uint buf_offset; | |
163 | int write_sz; | |
164 | /* Status and ID are in alternate locations. */ | |
165 | enum vf610_nfc_alt_buf alt_buf; | |
166 | enum vf610_nfc_variant variant; | |
167 | struct clk *clk; | |
049f4250 SA |
168 | bool use_hw_ecc; |
169 | u32 ecc_mode; | |
456930d8 SA |
170 | }; |
171 | ||
960823a2 BB |
172 | static inline struct vf610_nfc *mtd_to_nfc(struct mtd_info *mtd) |
173 | { | |
174 | return container_of(mtd_to_nand(mtd), struct vf610_nfc, chip); | |
175 | } | |
456930d8 SA |
176 | |
177 | static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) | |
178 | { | |
179 | return readl(nfc->regs + reg); | |
180 | } | |
181 | ||
182 | static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) | |
183 | { | |
184 | writel(val, nfc->regs + reg); | |
185 | } | |
186 | ||
187 | static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) | |
188 | { | |
189 | vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); | |
190 | } | |
191 | ||
192 | static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) | |
193 | { | |
194 | vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); | |
195 | } | |
196 | ||
197 | static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, | |
198 | u32 mask, u32 shift, u32 val) | |
199 | { | |
200 | vf610_nfc_write(nfc, reg, | |
201 | (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); | |
202 | } | |
203 | ||
204 | static inline void vf610_nfc_memcpy(void *dst, const void __iomem *src, | |
205 | size_t n) | |
206 | { | |
207 | /* | |
208 | * Use this accessor for the internal SRAM buffers. On the ARM | |
209 | * Freescale Vybrid SoC it's known that the driver can treat | |
210 | * the SRAM buffer as if it's memory. Other platform might need | |
211 | * to treat the buffers differently. | |
212 | * | |
213 | * For the time being, use memcpy | |
214 | */ | |
215 | memcpy(dst, src, n); | |
216 | } | |
217 | ||
218 | /* Clear flags for upcoming command */ | |
219 | static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) | |
220 | { | |
221 | u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS); | |
222 | ||
223 | tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; | |
224 | vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); | |
225 | } | |
226 | ||
227 | static void vf610_nfc_done(struct vf610_nfc *nfc) | |
228 | { | |
229 | unsigned long timeout = msecs_to_jiffies(100); | |
230 | ||
231 | /* | |
232 | * Barrier is needed after this write. This write need | |
233 | * to be done before reading the next register the first | |
234 | * time. | |
235 | * vf610_nfc_set implicates such a barrier by using writel | |
236 | * to write to the register. | |
237 | */ | |
238 | vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); | |
239 | vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT); | |
240 | ||
241 | if (!wait_for_completion_timeout(&nfc->cmd_done, timeout)) | |
242 | dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n"); | |
243 | ||
244 | vf610_nfc_clear_status(nfc); | |
245 | } | |
246 | ||
247 | static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col) | |
248 | { | |
249 | u32 flash_id; | |
250 | ||
251 | if (col < 4) { | |
252 | flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1); | |
253 | flash_id >>= (3 - col) * 8; | |
254 | } else { | |
255 | flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2); | |
256 | flash_id >>= 24; | |
257 | } | |
258 | ||
259 | return flash_id & 0xff; | |
260 | } | |
261 | ||
262 | static u8 vf610_nfc_get_status(struct vf610_nfc *nfc) | |
263 | { | |
264 | return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; | |
265 | } | |
266 | ||
267 | static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1, | |
268 | u32 cmd_code) | |
269 | { | |
270 | u32 tmp; | |
271 | ||
272 | vf610_nfc_clear_status(nfc); | |
273 | ||
274 | tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2); | |
275 | tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); | |
276 | tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; | |
277 | tmp |= cmd_code << CMD_CODE_SHIFT; | |
278 | vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp); | |
279 | } | |
280 | ||
281 | static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1, | |
282 | u32 cmd_byte2, u32 cmd_code) | |
283 | { | |
284 | u32 tmp; | |
285 | ||
286 | vf610_nfc_send_command(nfc, cmd_byte1, cmd_code); | |
287 | ||
288 | tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1); | |
289 | tmp &= ~CMD_BYTE2_MASK; | |
290 | tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; | |
291 | vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp); | |
292 | } | |
293 | ||
294 | static irqreturn_t vf610_nfc_irq(int irq, void *data) | |
295 | { | |
296 | struct mtd_info *mtd = data; | |
297 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
298 | ||
299 | vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); | |
300 | complete(&nfc->cmd_done); | |
301 | ||
302 | return IRQ_HANDLED; | |
303 | } | |
304 | ||
305 | static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) | |
306 | { | |
307 | if (column != -1) { | |
308 | if (nfc->chip.options & NAND_BUSWIDTH_16) | |
309 | column = column / 2; | |
310 | vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK, | |
311 | COL_ADDR_SHIFT, column); | |
312 | } | |
313 | if (page != -1) | |
314 | vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, | |
315 | ROW_ADDR_SHIFT, page); | |
316 | } | |
317 | ||
049f4250 SA |
318 | static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode) |
319 | { | |
320 | vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, | |
321 | CONFIG_ECC_MODE_MASK, | |
322 | CONFIG_ECC_MODE_SHIFT, ecc_mode); | |
323 | } | |
324 | ||
456930d8 SA |
325 | static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) |
326 | { | |
327 | vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); | |
328 | } | |
329 | ||
330 | static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, | |
331 | int column, int page) | |
332 | { | |
333 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
334 | int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; | |
335 | ||
336 | nfc->buf_offset = max(column, 0); | |
337 | nfc->alt_buf = ALT_BUF_DATA; | |
338 | ||
339 | switch (command) { | |
340 | case NAND_CMD_SEQIN: | |
341 | /* Use valid column/page from preread... */ | |
342 | vf610_nfc_addr_cycle(nfc, column, page); | |
049f4250 SA |
343 | nfc->buf_offset = 0; |
344 | ||
456930d8 SA |
345 | /* |
346 | * SEQIN => data => PAGEPROG sequence is done by the controller | |
347 | * hence we do not need to issue the command here... | |
348 | */ | |
349 | return; | |
350 | case NAND_CMD_PAGEPROG: | |
351 | trfr_sz += nfc->write_sz; | |
352 | vf610_nfc_transfer_size(nfc, trfr_sz); | |
353 | vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, | |
354 | command, PROGRAM_PAGE_CMD_CODE); | |
049f4250 SA |
355 | if (nfc->use_hw_ecc) |
356 | vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); | |
357 | else | |
358 | vf610_nfc_ecc_mode(nfc, ECC_BYPASS); | |
456930d8 SA |
359 | break; |
360 | ||
361 | case NAND_CMD_RESET: | |
362 | vf610_nfc_transfer_size(nfc, 0); | |
363 | vf610_nfc_send_command(nfc, command, RESET_CMD_CODE); | |
364 | break; | |
365 | ||
366 | case NAND_CMD_READOOB: | |
367 | trfr_sz += mtd->oobsize; | |
368 | column = mtd->writesize; | |
369 | vf610_nfc_transfer_size(nfc, trfr_sz); | |
370 | vf610_nfc_send_commands(nfc, NAND_CMD_READ0, | |
371 | NAND_CMD_READSTART, READ_PAGE_CMD_CODE); | |
372 | vf610_nfc_addr_cycle(nfc, column, page); | |
049f4250 | 373 | vf610_nfc_ecc_mode(nfc, ECC_BYPASS); |
456930d8 SA |
374 | break; |
375 | ||
376 | case NAND_CMD_READ0: | |
377 | trfr_sz += mtd->writesize + mtd->oobsize; | |
378 | vf610_nfc_transfer_size(nfc, trfr_sz); | |
379 | vf610_nfc_send_commands(nfc, NAND_CMD_READ0, | |
380 | NAND_CMD_READSTART, READ_PAGE_CMD_CODE); | |
381 | vf610_nfc_addr_cycle(nfc, column, page); | |
049f4250 | 382 | vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); |
456930d8 SA |
383 | break; |
384 | ||
385 | case NAND_CMD_PARAM: | |
386 | nfc->alt_buf = ALT_BUF_ONFI; | |
387 | trfr_sz = 3 * sizeof(struct nand_onfi_params); | |
388 | vf610_nfc_transfer_size(nfc, trfr_sz); | |
389 | vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); | |
390 | vf610_nfc_addr_cycle(nfc, -1, column); | |
049f4250 | 391 | vf610_nfc_ecc_mode(nfc, ECC_BYPASS); |
456930d8 SA |
392 | break; |
393 | ||
394 | case NAND_CMD_ERASE1: | |
395 | vf610_nfc_transfer_size(nfc, 0); | |
396 | vf610_nfc_send_commands(nfc, command, | |
397 | NAND_CMD_ERASE2, ERASE_CMD_CODE); | |
398 | vf610_nfc_addr_cycle(nfc, column, page); | |
399 | break; | |
400 | ||
401 | case NAND_CMD_READID: | |
402 | nfc->alt_buf = ALT_BUF_ID; | |
403 | nfc->buf_offset = 0; | |
404 | vf610_nfc_transfer_size(nfc, 0); | |
405 | vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE); | |
406 | vf610_nfc_addr_cycle(nfc, -1, column); | |
407 | break; | |
408 | ||
409 | case NAND_CMD_STATUS: | |
410 | nfc->alt_buf = ALT_BUF_STAT; | |
411 | vf610_nfc_transfer_size(nfc, 0); | |
412 | vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE); | |
413 | break; | |
414 | default: | |
415 | return; | |
416 | } | |
417 | ||
418 | vf610_nfc_done(nfc); | |
419 | ||
049f4250 | 420 | nfc->use_hw_ecc = false; |
456930d8 SA |
421 | nfc->write_sz = 0; |
422 | } | |
423 | ||
424 | static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
425 | { | |
426 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
427 | uint c = nfc->buf_offset; | |
428 | ||
429 | /* Alternate buffers are only supported through read_byte */ | |
430 | WARN_ON(nfc->alt_buf); | |
431 | ||
432 | vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); | |
433 | ||
434 | nfc->buf_offset += len; | |
435 | } | |
436 | ||
437 | static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, | |
438 | int len) | |
439 | { | |
440 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
441 | uint c = nfc->buf_offset; | |
442 | uint l; | |
443 | ||
444 | l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); | |
445 | vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); | |
446 | ||
447 | nfc->write_sz += l; | |
448 | nfc->buf_offset += l; | |
449 | } | |
450 | ||
451 | static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) | |
452 | { | |
453 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
454 | u8 tmp; | |
455 | uint c = nfc->buf_offset; | |
456 | ||
457 | switch (nfc->alt_buf) { | |
458 | case ALT_BUF_ID: | |
459 | tmp = vf610_nfc_get_id(nfc, c); | |
460 | break; | |
461 | case ALT_BUF_STAT: | |
462 | tmp = vf610_nfc_get_status(nfc); | |
463 | break; | |
464 | #ifdef __LITTLE_ENDIAN | |
465 | case ALT_BUF_ONFI: | |
466 | /* Reverse byte since the controller uses big endianness */ | |
467 | c = nfc->buf_offset ^ 0x3; | |
468 | /* fall-through */ | |
469 | #endif | |
470 | default: | |
471 | tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); | |
472 | break; | |
473 | } | |
474 | nfc->buf_offset++; | |
475 | return tmp; | |
476 | } | |
477 | ||
478 | static u16 vf610_nfc_read_word(struct mtd_info *mtd) | |
479 | { | |
480 | u16 tmp; | |
481 | ||
482 | vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); | |
483 | return tmp; | |
484 | } | |
485 | ||
486 | /* If not provided, upper layers apply a fixed delay. */ | |
487 | static int vf610_nfc_dev_ready(struct mtd_info *mtd) | |
488 | { | |
489 | /* NFC handles R/B internally; always ready. */ | |
490 | return 1; | |
491 | } | |
492 | ||
493 | /* | |
494 | * This function supports Vybrid only (MPC5125 would have full RB and four CS) | |
495 | */ | |
496 | static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) | |
497 | { | |
498 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
499 | u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR); | |
500 | ||
501 | /* Vybrid only (MPC5125 would have full RB and four CS) */ | |
502 | if (nfc->variant != NFC_VFC610) | |
503 | return; | |
504 | ||
505 | tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); | |
506 | ||
507 | if (chip >= 0) { | |
508 | tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; | |
509 | tmp |= BIT(chip) << ROW_ADDR_CHIP_SEL_SHIFT; | |
510 | } | |
511 | ||
512 | vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp); | |
513 | } | |
514 | ||
049f4250 SA |
515 | /* Count the number of 0's in buff up to max_bits */ |
516 | static inline int count_written_bits(uint8_t *buff, int size, int max_bits) | |
517 | { | |
518 | uint32_t *buff32 = (uint32_t *)buff; | |
519 | int k, written_bits = 0; | |
520 | ||
521 | for (k = 0; k < (size / 4); k++) { | |
522 | written_bits += hweight32(~buff32[k]); | |
523 | if (unlikely(written_bits > max_bits)) | |
524 | break; | |
525 | } | |
526 | ||
527 | return written_bits; | |
528 | } | |
529 | ||
530 | static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat, | |
531 | uint8_t *oob, int page) | |
532 | { | |
533 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
534 | u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS; | |
535 | u8 ecc_status; | |
536 | u8 ecc_count; | |
049f4250 SA |
537 | int flips_threshold = nfc->chip.ecc.strength / 2; |
538 | ||
539 | ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff; | |
540 | ecc_count = ecc_status & ECC_STATUS_ERR_COUNT; | |
541 | ||
542 | if (!(ecc_status & ECC_STATUS_MASK)) | |
543 | return ecc_count; | |
544 | ||
545 | /* Read OOB without ECC unit enabled */ | |
546 | vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page); | |
547 | vf610_nfc_read_buf(mtd, oob, mtd->oobsize); | |
548 | ||
549 | /* | |
550 | * On an erased page, bit count (including OOB) should be zero or | |
551 | * at least less then half of the ECC strength. | |
552 | */ | |
48c25cf4 BN |
553 | return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob, |
554 | mtd->oobsize, NULL, 0, | |
555 | flips_threshold); | |
049f4250 SA |
556 | } |
557 | ||
558 | static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
559 | uint8_t *buf, int oob_required, int page) | |
560 | { | |
561 | int eccsize = chip->ecc.size; | |
562 | int stat; | |
563 | ||
564 | vf610_nfc_read_buf(mtd, buf, eccsize); | |
565 | if (oob_required) | |
566 | vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
567 | ||
568 | stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page); | |
569 | ||
570 | if (stat < 0) { | |
571 | mtd->ecc_stats.failed++; | |
572 | return 0; | |
573 | } else { | |
574 | mtd->ecc_stats.corrected += stat; | |
575 | return stat; | |
576 | } | |
577 | } | |
578 | ||
579 | static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
45aaeff9 | 580 | const uint8_t *buf, int oob_required, int page) |
049f4250 SA |
581 | { |
582 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
583 | ||
584 | vf610_nfc_write_buf(mtd, buf, mtd->writesize); | |
585 | if (oob_required) | |
586 | vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
587 | ||
588 | /* Always write whole page including OOB due to HW ECC */ | |
589 | nfc->use_hw_ecc = true; | |
590 | nfc->write_sz = mtd->writesize + mtd->oobsize; | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
456930d8 SA |
595 | static const struct of_device_id vf610_nfc_dt_ids[] = { |
596 | { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 }, | |
597 | { /* sentinel */ } | |
598 | }; | |
599 | MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids); | |
600 | ||
601 | static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc) | |
602 | { | |
603 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); | |
604 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); | |
605 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); | |
606 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); | |
607 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); | |
608 | vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); | |
609 | ||
610 | /* Disable virtual pages, only one elementary transfer unit */ | |
611 | vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, | |
612 | CONFIG_PAGE_CNT_SHIFT, 1); | |
613 | } | |
614 | ||
615 | static void vf610_nfc_init_controller(struct vf610_nfc *nfc) | |
616 | { | |
617 | if (nfc->chip.options & NAND_BUSWIDTH_16) | |
618 | vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); | |
619 | else | |
620 | vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); | |
049f4250 SA |
621 | |
622 | if (nfc->chip.ecc.mode == NAND_ECC_HW) { | |
623 | /* Set ECC status offset in SRAM */ | |
624 | vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, | |
625 | CONFIG_ECC_SRAM_ADDR_MASK, | |
626 | CONFIG_ECC_SRAM_ADDR_SHIFT, | |
627 | ECC_SRAM_ADDR >> 3); | |
628 | ||
629 | /* Enable ECC status in SRAM */ | |
630 | vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); | |
631 | } | |
456930d8 SA |
632 | } |
633 | ||
634 | static int vf610_nfc_probe(struct platform_device *pdev) | |
635 | { | |
636 | struct vf610_nfc *nfc; | |
637 | struct resource *res; | |
638 | struct mtd_info *mtd; | |
639 | struct nand_chip *chip; | |
640 | struct device_node *child; | |
641 | const struct of_device_id *of_id; | |
642 | int err; | |
643 | int irq; | |
644 | ||
645 | nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); | |
646 | if (!nfc) | |
647 | return -ENOMEM; | |
648 | ||
649 | nfc->dev = &pdev->dev; | |
456930d8 | 650 | chip = &nfc->chip; |
960823a2 | 651 | mtd = nand_to_mtd(chip); |
456930d8 | 652 | |
456930d8 SA |
653 | mtd->owner = THIS_MODULE; |
654 | mtd->dev.parent = nfc->dev; | |
655 | mtd->name = DRV_NAME; | |
656 | ||
657 | irq = platform_get_irq(pdev, 0); | |
658 | if (irq <= 0) | |
659 | return -EINVAL; | |
660 | ||
661 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
662 | nfc->regs = devm_ioremap_resource(nfc->dev, res); | |
663 | if (IS_ERR(nfc->regs)) | |
664 | return PTR_ERR(nfc->regs); | |
665 | ||
666 | nfc->clk = devm_clk_get(&pdev->dev, NULL); | |
667 | if (IS_ERR(nfc->clk)) | |
668 | return PTR_ERR(nfc->clk); | |
669 | ||
670 | err = clk_prepare_enable(nfc->clk); | |
671 | if (err) { | |
672 | dev_err(nfc->dev, "Unable to enable clock!\n"); | |
673 | return err; | |
674 | } | |
675 | ||
676 | of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev); | |
677 | nfc->variant = (enum vf610_nfc_variant)of_id->data; | |
678 | ||
679 | for_each_available_child_of_node(nfc->dev->of_node, child) { | |
680 | if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) { | |
681 | ||
44ec23c9 | 682 | if (nand_get_flash_node(chip)) { |
456930d8 SA |
683 | dev_err(nfc->dev, |
684 | "Only one NAND chip supported!\n"); | |
685 | err = -EINVAL; | |
686 | goto error; | |
687 | } | |
688 | ||
63752199 | 689 | nand_set_flash_node(chip, child); |
456930d8 SA |
690 | } |
691 | } | |
692 | ||
44ec23c9 | 693 | if (!nand_get_flash_node(chip)) { |
456930d8 SA |
694 | dev_err(nfc->dev, "NAND chip sub-node missing!\n"); |
695 | err = -ENODEV; | |
696 | goto err_clk; | |
697 | } | |
698 | ||
699 | chip->dev_ready = vf610_nfc_dev_ready; | |
700 | chip->cmdfunc = vf610_nfc_command; | |
701 | chip->read_byte = vf610_nfc_read_byte; | |
702 | chip->read_word = vf610_nfc_read_word; | |
703 | chip->read_buf = vf610_nfc_read_buf; | |
704 | chip->write_buf = vf610_nfc_write_buf; | |
705 | chip->select_chip = vf610_nfc_select_chip; | |
706 | ||
707 | chip->options |= NAND_NO_SUBPAGE_WRITE; | |
708 | ||
709 | init_completion(&nfc->cmd_done); | |
710 | ||
711 | err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd); | |
712 | if (err) { | |
713 | dev_err(nfc->dev, "Error requesting IRQ!\n"); | |
714 | goto error; | |
715 | } | |
716 | ||
717 | vf610_nfc_preinit_controller(nfc); | |
718 | ||
719 | /* first scan to find the device and get the page size */ | |
720 | if (nand_scan_ident(mtd, 1, NULL)) { | |
721 | err = -ENXIO; | |
722 | goto error; | |
723 | } | |
724 | ||
725 | vf610_nfc_init_controller(nfc); | |
726 | ||
727 | /* Bad block options. */ | |
728 | if (chip->bbt_options & NAND_BBT_USE_FLASH) | |
729 | chip->bbt_options |= NAND_BBT_NO_OOB; | |
730 | ||
731 | /* Single buffer only, max 256 OOB minus ECC status */ | |
732 | if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) { | |
733 | dev_err(nfc->dev, "Unsupported flash page size\n"); | |
734 | err = -ENXIO; | |
735 | goto error; | |
736 | } | |
737 | ||
049f4250 SA |
738 | if (chip->ecc.mode == NAND_ECC_HW) { |
739 | if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { | |
740 | dev_err(nfc->dev, "Unsupported flash with hwecc\n"); | |
741 | err = -ENXIO; | |
742 | goto error; | |
743 | } | |
744 | ||
745 | if (chip->ecc.size != mtd->writesize) { | |
746 | dev_err(nfc->dev, "Step size needs to be page size\n"); | |
747 | err = -ENXIO; | |
748 | goto error; | |
749 | } | |
750 | ||
751 | /* Only 64 byte ECC layouts known */ | |
752 | if (mtd->oobsize > 64) | |
753 | mtd->oobsize = 64; | |
754 | ||
3cf32d18 BB |
755 | /* |
756 | * mtd->ecclayout is not specified here because we're using the | |
757 | * default large page ECC layout defined in NAND core. | |
758 | */ | |
049f4250 SA |
759 | if (chip->ecc.strength == 32) { |
760 | nfc->ecc_mode = ECC_60_BYTE; | |
761 | chip->ecc.bytes = 60; | |
049f4250 SA |
762 | } else if (chip->ecc.strength == 24) { |
763 | nfc->ecc_mode = ECC_45_BYTE; | |
764 | chip->ecc.bytes = 45; | |
049f4250 SA |
765 | } else { |
766 | dev_err(nfc->dev, "Unsupported ECC strength\n"); | |
767 | err = -ENXIO; | |
768 | goto error; | |
769 | } | |
770 | ||
049f4250 SA |
771 | chip->ecc.read_page = vf610_nfc_read_page; |
772 | chip->ecc.write_page = vf610_nfc_write_page; | |
773 | ||
774 | chip->ecc.size = PAGE_2K; | |
775 | } | |
776 | ||
456930d8 SA |
777 | /* second phase scan */ |
778 | if (nand_scan_tail(mtd)) { | |
779 | err = -ENXIO; | |
780 | goto error; | |
781 | } | |
782 | ||
783 | platform_set_drvdata(pdev, mtd); | |
784 | ||
785 | /* Register device in MTD */ | |
a61ae81a | 786 | return mtd_device_register(mtd, NULL, 0); |
456930d8 SA |
787 | |
788 | error: | |
44ec23c9 | 789 | of_node_put(nand_get_flash_node(chip)); |
456930d8 SA |
790 | err_clk: |
791 | clk_disable_unprepare(nfc->clk); | |
792 | return err; | |
793 | } | |
794 | ||
795 | static int vf610_nfc_remove(struct platform_device *pdev) | |
796 | { | |
797 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
798 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
799 | ||
800 | nand_release(mtd); | |
801 | clk_disable_unprepare(nfc->clk); | |
802 | return 0; | |
803 | } | |
804 | ||
805 | #ifdef CONFIG_PM_SLEEP | |
806 | static int vf610_nfc_suspend(struct device *dev) | |
807 | { | |
808 | struct mtd_info *mtd = dev_get_drvdata(dev); | |
809 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
810 | ||
811 | clk_disable_unprepare(nfc->clk); | |
812 | return 0; | |
813 | } | |
814 | ||
815 | static int vf610_nfc_resume(struct device *dev) | |
816 | { | |
817 | struct mtd_info *mtd = dev_get_drvdata(dev); | |
818 | struct vf610_nfc *nfc = mtd_to_nfc(mtd); | |
819 | ||
820 | pinctrl_pm_select_default_state(dev); | |
821 | ||
822 | clk_prepare_enable(nfc->clk); | |
823 | ||
824 | vf610_nfc_preinit_controller(nfc); | |
825 | vf610_nfc_init_controller(nfc); | |
826 | return 0; | |
827 | } | |
828 | #endif | |
829 | ||
830 | static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume); | |
831 | ||
832 | static struct platform_driver vf610_nfc_driver = { | |
833 | .driver = { | |
834 | .name = DRV_NAME, | |
835 | .of_match_table = vf610_nfc_dt_ids, | |
836 | .pm = &vf610_nfc_pm_ops, | |
837 | }, | |
838 | .probe = vf610_nfc_probe, | |
839 | .remove = vf610_nfc_remove, | |
840 | }; | |
841 | ||
842 | module_platform_driver(vf610_nfc_driver); | |
843 | ||
844 | MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); | |
845 | MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver"); | |
846 | MODULE_LICENSE("GPL"); |